Hbm pure hardware layer-by-layer power supply control and self-healing system

Abstract

The application discloses a kind of HBM pure hardware layer-by-layer power supply control unit, by pure hardware circuit composition, does not include any programmable logic device.The power supply of each layer DRAM chip in HBM stack is controlled by independent power gate control unit, and pure hardware power supply arbitrator monitors each layer voltage in real time, and compares with the voltage threshold value solidified in one-time nonvolatile memory.When detecting that the voltage of a layer is abnormal and exceeds the threshold value, the output voltage of the corresponding power rail is automatically fine-tuned and compensated by hardware, and the compensation range is constrained by the upper and lower limits solidified in one-time nonvolatile memory;If compensation is invalid, trigger the protective power-off of the layer.The application solves the problem that single point failure of existing HBM power supply scheme leads to the failure of the whole chip, realizes layer-by-layer independent power supply control and fault self-recovery, and significantly improves the reliability of HBM.

Description

Technical Field

[0001] This invention relates to the field of semiconductor storage technology, and in particular to a power supply management and self-healing system for high-bandwidth memory. Background Technology

[0002] High-bandwidth memory (HBM) employs a three-dimensional stacked structure, connecting DRAM chips across layers via through-silicon vias (TSVs). Existing HBM power supply solutions typically use a uniform power supply, with all DRAM chips sharing the same power rail. This approach has the following drawbacks: 1. High risk of single point of failure: If a short circuit occurs in a DRAM chip layer, it will cause the voltage of the entire power rail to drop, and the entire HBM chip will fail.

[0003] 2. Low power supply efficiency: Different layers of DRAM chips have different workloads and require different power supply voltages. A uniform power supply method cannot dynamically adjust the power supply voltage according to the actual load of each layer, resulting in low power supply efficiency and high power consumption.

[0004] 3. Slow fault response: Existing power supply solutions mainly use software control. The power management chip sends voltage data to the processor, which then runs the control algorithm and sends adjustment commands. This method suffers from high latency and poor reliability, making it unable to respond quickly to voltage anomalies and easily leading to data loss or chip damage. Technical issues

[0005] The technical problem this invention aims to solve is that existing HBM power supply solutions have the risk of single-point failure, where a failure in one layer can cause the entire chip to fail; they have low power supply efficiency and high power consumption; they have slow fault response and cannot quickly handle voltage anomalies; and they are susceptible to power supply glitches and latch-up effects. Solution

[0006] To address the aforementioned technical problems, this invention provides a pure hardware layer-by-layer power supply management unit for HBM, composed entirely of hardware circuitry and containing no programmable logic devices. The power supply to each DRAM chip layer in the HBM stack is controlled by an independent power gating unit. A pure hardware power supply arbiter monitors the voltage of each layer in real time and compares it with the voltage thresholds fixed to the one-time non-volatile memory. When a layer's voltage is detected to abnormally exceed the threshold, the hardware automatically fine-tunes the output voltage of the corresponding power rail for compensation, with the compensation range constrained by the upper and lower limits fixed to the one-time non-volatile memory. If compensation is ineffective, a protective power-off is triggered for that layer. It does not include any adaptive power supply management algorithms based on real-time signal quality feedback.

[0007] Furthermore, if the compensation fails, a protective power outage is triggered on that layer, while the backup layer is activated and the task migration is performed.

[0008] Furthermore, it also includes an independent power monitoring circuit that directly monitors the voltage of the power input pin without relying on the power good signal from the external power management chip; when the independent monitoring circuit detects an abnormal voltage, it will trigger a protection action even if the external power management chip reports normal.

[0009] Furthermore, it also includes a voltage glitch detector, which adopts an asynchronous multi-sampling rate design. Multiple independent voltage glitch detectors are deployed to operate at different, uncorrelated sampling frequencies. As long as any detector detects that the slope of the rising or falling edge of the power supply voltage exceeds the one-time non-volatile memory hardening threshold, a local reset is immediately triggered and the parameters are reloaded.

[0010] Furthermore, it also includes a latch-up effect detection circuit, which monitors the rate of change of power supply current in real time for each power domain and immediately cuts off the power domain when it exceeds the one-time non-volatile memory solidification threshold; it also includes a global overcurrent protection circuit, which triggers a chip-level emergency shutdown when the total current exceeds the threshold; all input / output pins and power domains adopt a dual-well isolation and substrate contact process.

[0011] Furthermore, it also includes a power supply ripple spectrum analysis circuit, which analyzes the spectrum characteristics of the power supply ripple in real time. When an abnormal ripple pattern is detected, a safety alarm is triggered and the circuit switches to a high-intensity filtering mode.

[0012] Furthermore, all analog circuits employ differential input and common-mode rejection circuits; it also includes an analog circuit reading verification circuit that compares the readings of multiple analog circuits with the same function, and triggers an alarm when the difference exceeds a threshold.

[0013] Furthermore, it also includes a hardware Trojan detection circuit, which deploys multiple ring oscillators inside the chip to monitor changes in circuit delay and triggers a security lockout when abnormal delay is detected.

[0014] Furthermore, it also includes a physically unclonable function module that uses random differences in the chip manufacturing process to generate a unique key, which is used to encrypt all one-time non-volatile memory parameters. Beneficial effects

[0015] The present invention has the following beneficial effects: 1. High reliability and no single point of failure: Employing a layer-by-layer independent power supply architecture, when a DRAM chip in one layer fails, only the power supply to that layer is affected, preventing the entire chip from failing. The faulty layer can be isolated, and the backup layer can be activated, achieving automatic self-healing.

[0016] 2. High power supply efficiency: The power supply voltage can be dynamically adjusted according to the actual load of each DRAM chip layer, which improves power supply efficiency and reduces power consumption.

[0017] 3. Fast response speed: All control logic is implemented by pure hardware circuits. Voltage anomaly detection and compensation are completed in nanoseconds, which can quickly respond to voltage anomalies and effectively prevent data loss and chip damage.

[0018] 4. Strong resistance to attacks: All control parameters and logic are fixed at the factory and cannot be modified during operation, which can effectively resist various software and physical attacks.

[0019] 5. Good compatibility: It can be directly integrated into existing HBM products without modifying the existing physical structure and interfaces, ensuring good compatibility. Detailed Implementation

[0020] The present invention will now be described in detail with reference to specific embodiments.

[0021] The HBM pure hardware layer-by-layer power supply control unit disclosed in this invention is integrated into the logic substrate chip of the HBM stack and connected to the DRAM chips of each layer of the HBM stack through through-silicon vias. The entire system is composed of pure hardware circuits and does not contain any processors, microcontrollers or programmable logic devices. All control logic is implemented through combinational logic circuits and sequential logic circuits.

[0022] The one-time non-volatile memory uses a fuse-type one-time programmable memory. All control parameters and safety thresholds are fixed by blowing the fuse once at the factory and cannot be modified during operation. After programming, the programming power path and global address lines are permanently cut off, making it physically impossible to perform any further programming operations.

[0023] Each layer of DRAM chips in the HBM stack has an independent power gating unit deployed within the logic substrate chip. Each power gating unit includes a power metal-oxide-semiconductor transistor, voltage monitoring circuitry, and current monitoring circuitry.

[0024] The pure hardware power supply arbiter receives voltage and current monitoring data sent by the power gating units at each layer and compares it with the voltage and current thresholds stored in a one-time non-volatile memory.

[0025] When a voltage anomaly is detected on a certain level, the power supply arbiter first sends a compensation signal to the voltage compensation controller. The voltage compensation controller adjusts the output voltage of the corresponding power rail, with the compensation range constrained by upper and lower limits fixed in a one-time non-volatile memory to prevent over-compensation from causing other problems.

[0026] If the voltage cannot be restored to the normal range within the compensation range, the power supply arbitrator determines that an unrecoverable fault has occurred in that layer, sends a power-off signal to the power gating unit of that layer, activates the power gating unit of the backup layer, and initiates the atomic migration process to migrate the data of the faulty layer to the backup layer.

[0027] An independent power supply monitoring circuit is directly connected to the power input pin to monitor the input voltage in real time. When the input voltage is abnormal, the protection mechanism is triggered even if the external power management chip reports that the power supply is good.

[0028] The voltage glitch detector consists of multiple independent sampling circuits, each sampling the power supply voltage at a different frequency. If any sampling circuit detects that the rising or falling edge slope of the voltage exceeds a threshold, a local reset is immediately triggered, reloading all parameters.

[0029] The latch-up detection circuit monitors the rate of current change in each power domain in real time. When the rate of current change exceeds a threshold, the power supply to that power domain is immediately cut off. The global overcurrent protection circuit monitors the total current, and when the total current exceeds a threshold, it triggers a chip-level emergency shutdown.

[0030] The power supply ripple spectrum analysis circuit performs a Fast Fourier Transform on the power supply voltage to analyze the spectral characteristics of the ripple. When an abnormal spectral pattern is detected, a safety alarm is triggered, and the circuit switches to a high-intensity filtering mode.

[0031] The hardware trojan detection circuit deploys multiple ring oscillators of varying lengths inside the chip. A hardware trojan alters the circuit's delay, causing changes in the frequency of the ring oscillators. By comparing the frequency changes of each ring oscillator, the presence of a hardware trojan can be detected.

[0032] The physically unclonable function module employs a physically unclonable function based on static random access memory (SRAM), generating a unique key using the random initial state of the SRAM cell upon power-on. Each time power is applied, the physically unclonable function module automatically generates a key used to decrypt parameters in the one-time non-volatile memory.

[0033] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A HBM pure hardware layer-by-layer power supply management unit, characterized in that, It consists of pure hardware circuits and does not contain any programmable logic devices; the power supply of each DRAM chip in the HBM stack is controlled by an independent power gating unit. The pure hardware power supply arbiter monitors the voltage of each layer in real time and compares it with the voltage threshold fixed by the one-time non-volatile memory. When the voltage of a certain layer is detected to be abnormally exceeding the threshold, the hardware automatically fine-tunes the output voltage of the corresponding power rail for compensation. The compensation range is constrained by the upper and lower limits fixed by the one-time non-volatile memory. If the compensation is ineffective, the protective power-off of that layer is triggered. It does not contain any adaptive power management algorithms based on real-time signal quality feedback.

2. The power provisioning management unit of claim 1, wherein, If the compensation fails, a protective power outage is triggered on that layer, while the backup layer is activated and the task migration is performed.

3. The power provisioning management unit of claim 1, wherein, It also includes an independent power monitoring circuit that directly monitors the voltage of the power input pin without relying on the power good signal from an external power management chip. When the independent monitoring circuit detects an abnormal voltage, it will trigger a protection action even if the external power management chip reports that it is normal.

4. The power provisioning management unit of claim 1, wherein, It also includes a voltage glitch detector, which adopts an asynchronous multi-sampling rate design. Multiple independent voltage glitch detectors are deployed to work at different and uncorrelated sampling frequencies. As long as any detector detects that the slope of the rising or falling edge of the power supply voltage exceeds the one-time non-volatile memory solidification threshold, a local reset is immediately triggered and the parameters are reloaded.

5. The power supply control unit according to claim 1, characterized in that, It also includes a latch-up detection circuit that monitors the rate of change of power current in each power domain in real time and immediately cuts off the power domain when it exceeds the one-time non-volatile memory solidification threshold; it also includes a global overcurrent protection circuit that triggers a chip-level emergency shutdown when the total current exceeds the threshold. All input / output pins and power domains employ dual-well isolation and substrate contact technology.

6. The power provisioning management unit of claim 1, wherein, It also includes a power supply ripple spectrum analysis circuit, which analyzes the spectrum characteristics of the power supply ripple in real time. When an abnormal ripple pattern is detected, a safety alarm is triggered and the circuit switches to a high-intensity filtering mode.

7. The power provisioning management unit of claim 1, wherein, All analog circuits employ differential input and common-mode rejection circuitry; an analog circuit reading verification circuit is also included, which compares the readings of multiple analog circuits with the same function, and triggers an alarm when the difference exceeds a threshold.

8. The power provisioning management unit of claim 1, wherein, It also includes a hardware Trojan detection circuit, which deploys multiple ring oscillators inside the chip to monitor changes in circuit delay and triggers a security lockout when abnormal delay is detected.

9. The power provisioning management unit of claim 1, wherein, It also includes a physically unclonable function module that uses random differences in the chip manufacturing process to generate a unique key, which is used to encrypt all one-time non-volatile memory parameters.

10. A method for layer-by-layer power supply control and self-healing in HBM, characterized in that, The power supply control unit according to any one of claims 1 to 9 includes the following steps: real-time monitoring of the power supply voltage of each layer of DRAM through an independent power gating unit for each layer; comparing the monitored voltage value with the threshold value of the one-time non-volatile memory; automatically fine-tuning the power rail output voltage within the compensation range when the threshold value is exceeded; and triggering the protective power-off of the layer when the compensation is ineffective.