Power control circuit

Abstract

A power control circuit for a storage system including a controller communicating with a host, the power control circuit including: a sequencer; a first terminal connected to a first power circuit; and a second terminal connected to a second power circuit, wherein the sequencer is configured to: detect the interruption of external power supply, disconnect the first power circuit from the sequencer via the first terminal without waiting for a request from the controller, and disconnect the second power circuit from the sequencer via the second terminal in response to the request from the controller, the storage system including a first semiconductor memory as non-volatile memory, a second semiconductor memory as volatile memory, and an energy storage device.

Description

[0001] This application is a divisional application of Chinese patent application filed on February 28, 2022, with application number 202210205958.9 and entitled "Storage System, Control Method and Power Control Circuit". Cross-reference to related applications

[0002] This application claims priority to Japanese Patent Application No. 2021-113533, filed on July 8, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] In summary, the implementation methods described herein relate to storage systems, control methods, and power control circuits. Background Technology

[0004] The storage system is connected to the host and operates when powered by an external power source. When the external power supply is interrupted without prior notice, the storage system needs to store data in a non-volatile manner. Therefore, an energy storage device capable of storing backup power is installed on the storage system, serving as a substitute for power from the external source. During a power outage, the storage system can use the backup power to store data in a non-volatile manner.

[0005] As the storage capacity of a storage system increases, so does the amount of data that needs to be stored. Consequently, the required backup power also increases. To increase backup power, one could consider increasing the number of energy storage devices installed on the storage system. However, to reduce the cost of the storage system or to miniaturize it, it is desirable to reduce the number of energy storage devices installed. Summary of the Invention

[0006] The embodiments provide a storage system, control method, and power control circuit that can appropriately control the power consumed during data processing in a non-volatile manner during a power outage.

[0007] One implementation provides: A power control circuit for a storage system including a controller communicating with a host, the power control circuit comprising: Sequencer; The first terminal is connected to the first power supply circuit; and The second terminal is connected to the second power supply circuit. The sequencer is configured as follows: Upon detecting the disconnection of external power supply, without waiting for a request from the controller, the first power circuit is disconnected from the sequencer via the first terminal, and in response to the request from the controller, the second power circuit is disconnected from the sequencer via the second terminal. The storage system includes a first semiconductor memory as a non-volatile memory, a second semiconductor memory as a volatile memory, and an energy storage device.

[0008] In addition, one implementation provides: A power control circuit for a storage system including a controller communicating with a host, the power control circuit comprising: Sequencer; The first terminal is connected to the first power supply circuit; The second terminal is connected to the second power supply circuit; and The third terminal is connected to an external power source. The sequencer is configured as follows: The system detects the disconnection of the external power supply at the third terminal, disconnects the first power circuit from the sequencer via the first terminal without waiting for a request from the controller, and disconnects the second power circuit from the sequencer via the second terminal in response to the request from the controller. The storage system includes a first semiconductor memory as a non-volatile memory, a second semiconductor memory as a volatile memory, and an energy storage device.

[0009] In addition, one implementation provides: A storage system, comprising: As the first memory for non-volatile memory; As a secondary memory for volatile memory; Controller; A power control circuit, based on a first power supplied from at least an external power source, controls the application of a first voltage to the first memory, the second memory, and the controller; and The energy storage device supplies a second power to the power control circuit during the period when the first power from the external power source is cut off. During the period when the first power supplied from the external power source is cut off, The power control circuit controls the application of a second voltage based on the second power supplied from the energy storage device to the first memory, the second memory, and the controller. The controller reads data from the second memory and sends the data to the first memory; After the data is written to the first memory, the power control circuit controls the application of the second voltage to the first memory to stop; and After the data is read from the second memory and before the data is written to the first memory, the power control circuit controls the application of the second voltage to the second memory to stop.

[0010] In addition, one implementation provides: A method for controlling a storage system, the storage system comprising a first memory as non-volatile memory, a second memory as volatile memory, and an energy storage device. The method includes: During the period when the first power supply from the external power source is cut off A second voltage based on the second power supplied from the energy storage device is applied to the first memory and the second memory; After reading data from the second memory and before the writing of the data to the first memory is complete, the application of the second voltage to the second memory is stopped; and After the data has been written to the first memory, the application of the second voltage to the first memory is stopped.

[0011] In addition, one implementation provides: A power control circuit for a storage system including a controller, comprising: Sequencer; The first terminal is connected to the first power supply circuit; and The second terminal is connected to the second power supply circuit. The sequencer is configured as follows: The system detects the disconnection of external power supply, disconnects the first power circuit from the sequencer via the first terminal without waiting for a request from the controller, and disconnects the second power circuit from the sequencer via the second terminal in response to the request from the controller. Attached Figure Description

[0012] Figure 1 This is a block diagram schematically illustrating a portion of the structure of an information processing system including a storage system according to the first embodiment.

[0013] Figure 2 This is a block diagram illustrating the power supply structure of the storage system according to the first embodiment.

[0014] Figure 3 This is a flowchart illustrating power control in the power failure protection (PLP) process of a storage system according to a first embodiment.

[0015] Figure 4AThis is a diagram showing a table in a storage system according to the first embodiment for managing the process of stopping the application of voltage.

[0016] Figure 4B This is a block diagram showing the connections between multiple terminals and multiple power supply circuits according to the first embodiment.

[0017] Figure 5 This is a timing diagram illustrating the power control in the PLP processing within the storage system according to the first embodiment.

[0018] Figure 6 This is a block diagram illustrating the power supply structure of the storage system according to the second embodiment; and Figure 7 This is a flowchart illustrating power control in the power failure protection (PLP) process of a storage system according to the second embodiment. Detailed Implementation

[0019] The embodiments provide a storage system, control method, and power control circuit that can appropriately control the power consumed during data processing in a non-volatile manner during a power outage.

[0020] Typically, according to one embodiment, a storage system includes: a non-volatile first memory; a volatile second memory; a controller; a power control circuit that controls, based on a first power supplied from at least an external power source, that applies a first voltage to the first memory, the second memory, and the controller; and an energy storage device capable of providing a second power to the power control circuit during a period when the first power from the external power source is interrupted. During the period when the first power supplied from the external power source is interrupted, the power control circuit controls, that a second voltage based on the second power supplied from the energy storage device is applied to the first memory, the second memory, and the controller; the controller reads data from the second memory; after reading the data and before the writing of the data to the first memory is completed, the power control circuit controls, that the application of the second voltage to the second memory is stopped; the controller sends the data to the first memory; and after the data is written to the first memory, the power control circuit controls, that the application of the second voltage to the second memory is stopped.

[0021] In the following text, implementation methods of the present disclosure will be described.

[0022] In this specification, several expressions are given for several elements. These expressions are merely illustrative, and other expressions may be given for these elements.

[0023] The accompanying drawings are schematic, and the relationships between thickness and planar dimensions, layer thickness ratios, etc., may differ from reality. The relationships and scales between dimensions depicted in different drawings may differ in some parts.

[0024] (First Implementation) Reference Figure 1 The description includes the basic configuration of the information processing system of the storage system according to the first embodiment.

[0025] The information processing system 3 includes a storage system 1, a host 2, and an external power supply 10.

[0026] Host 2 can be a storage server that stores large amounts of diverse data in storage system 1, or it can be a personal computer. Multiple storage systems 1 can be connected to host 2.

[0027] External power supply 10 is a power supply located outside the storage system 1, and is a device that provides power to the storage system 1. Alternatively, the external power supply can be located inside the host 2.

[0028] Storage system 1 is a storage device configured to write data to or read data from non-volatile memory. In the following description, storage system 1 implemented as a solid-state drive (SSD) will be used as an example. For example, storage system 1 can be implemented as a memory card or a universal flash memory (UFS) device.

[0029] The storage system 1 includes a controller 4, a non-volatile memory 5, a volatile memory 6, a power control circuit 7, and an energy storage device 8.

[0030] Non-volatile memory 5 is a semiconductor memory device that stores data in a non-volatile manner. Non-volatile memory 5 is an example of a first memory. For example, non-volatile memory 5 is NAND flash memory. NAND flash memory includes multiple blocks. Each of the multiple blocks includes multiple memory cells. The block is a data erasure unit. The block includes multiple pages. A page is a data read / write unit. Hereinafter, non-volatile memory 5 will be referred to as NAND memory 5.

[0031] NAND memory 5 includes a NAND interface (NAND I / F) 51. NAND I / F 51 is an example of a fourth circuit. NAND I / F 51 communicates with controller 4 by exchanging data with NAND I / F 43 in controller 4, which will be described below.

[0032] Volatile memory 6 is a semiconductor memory device that stores data in a volatile manner. Volatile memory 6 is an example of a second memory. Dynamic RAM (DRAM) is used as volatile memory 6. Alternatively, static RAM (SRAM) can be used. Volatile memory 6 includes a write buffer for temporarily storing data to be written to NAND memory 5 and a read buffer for temporarily storing data read from NAND memory 5 as buffers. Volatile memory 6 also includes a cache of lookup tables (LUTs) and a storage area for system management information. The LUT stores the following mapping information: mapping the logical address specified by host 2 for accessing storage system 1 to the physical address of NAND memory 5. In the following text, volatile memory 6 is referred to as DRAM 6.

[0033] DRAM 6 includes DRAM I / F 61. DRAM I / F 61 communicates with controller 4 by exchanging data with DRAM I / F 44 in controller 4, which will be described below.

[0034] Controller 4 serves as the memory controller for storage system 1. Controller 4 is implemented using circuitry such as a system-on-a-chip (SoC). Controller 4 can perform command processing to handle various commands from host 2.

[0035] Controller 4 performs various processes via firmware (FW) stored in a non-volatile manner in NAND memory 5 or read-only memory (ROM) (not shown). It should be noted that dedicated hardware in controller 4 can perform some or all of these processes.

[0036] Controller 4 controls power control circuit 7. Controller 4 communicates with power control circuit 7 via, for example, an internal integrated circuit (I2C) bus.

[0037] Controller 4 performs power failure protection (PLP) processing. PLP processing is the process of using the charge of the energy storage device 8 to write the data to be stored into the NAND memory 5 and store the data in a non-volatile manner when the power supply to the storage system 1 is interrupted.

[0038] The controller 4 includes a central processing unit (CPU) 41, a host interface (host I / F) 42, a NAND interface (NAND I / F) 43, a DRAM interface (DRAM I / F) 44, and a buffer memory 45. The CPU 41, host I / F 42, NAND I / F 43, DRAM I / F 44, and buffer memory 45 can be interconnected via a bus.

[0039] CPU 41 performs various functions by executing functions stored in NAND memory 5, etc.

[0040] Host I / F 42 includes circuitry for performing communication control or receiving commands with host 2. Host I / F 42 is an example of the first circuitry. Storage system 1 is connected to host 2 via host I / F 42. Host I / F 42 receives various commands from host 2, such as I / O commands. I / O commands include write commands and read commands. Host I / F 42 conforms to interface standards such as PCI Express (PCIe)® or NVM Express (NVMe)®.

[0041] NAND I / F 43 includes circuitry for sending and receiving commands or data between controller 4 and NAND memory 5. NAND I / F 43 is an example of a second circuit. NAND I / F 43 electrically connects controller 4 to NAND memory 5. NAND I / F 43 conforms to interface standards such as Toggle DDR or Open NAND Flash Interface (ONFI).

[0042] DRAM I / F 44 includes circuitry for sending commands or data to DRAM 6 and receiving commands or data from DRAM 6. DRAM I / F 44 is an example of a third circuit. DRAM I / F 44 electrically connects controller 4 to DRAM 6.

[0043] Buffer memory 45 is a semiconductor memory device that stores data in a volatile manner. SRAM is used as buffer memory 45. Alternatively, DRAM can be used.

[0044] CPU 41 receives data from host 2 that is to be written to NAND memory 5 and temporarily stores it in the write buffer of DRAM 6. CPU 41 stores the data temporarily stored in the write buffer of DRAM 6 in buffer memory 45. CPU 41 writes the data stored in buffer memory 45 into NAND memory 5.

[0045] The write buffers of buffer memory 45 and DRAM 6 temporarily store data supplied from host 2 until that data is written to NAND memory 5. In other words, the write buffers of buffer memory 45 and DRAM 6 store data en route to NAND memory 5. Buffer memory 45 and DRAM 6 are volatile memories. Therefore, when power to storage system 1 is interrupted, data en route to be written will be lost.

[0046] The data stored from the write buffer of DRAM 6 to the buffer memory 45 is, for example, the amount corresponding to one page. Here, CPU 41 can write the data from the buffer memory 45 into the NAND memory 5 in batches.

[0047] The power control circuit 7 supplies power to various semiconductor components installed on the storage system 1, such as the controller 4, DRAM 6, and NAND memory 5, through multiple power supply circuits. The power control circuit 7 is, for example, a power management integrated circuit (PMIC). In response to specific events or instructions from the controller 4, the power control circuit 7 automatically executes control over the startup sequence of each power supply circuit, the on / off control of each power supply circuit, and so on. Details will be described below.

[0048] The energy storage device 8 includes one or more electronic components. The energy storage device 8 is, for example, a capacitor. A capacitor is an electronic component capable of being charged and discharged. Examples of capacitors include multilayer ceramic capacitors, aluminum electrolytic capacitors, functional polymer capacitors, and so on. The energy storage device can also be a battery.

[0049] The storage system 1 according to this embodiment disconnects the power supply to circuits unrelated to non-volatile data processing during PLP processing. Therefore, the storage system 1 according to this embodiment can reduce the power required for non-volatile processing.

[0050] Figure 2 This is a block diagram showing the power supply structure of the storage system 1 according to this embodiment. Power is supplied to the power control circuit 7 from an external power supply 10. The power control circuit 7 supplies power to the energy storage devices 8, the controller 4, the NAND memory 5, the DRAM 6, and other devices 9. Multiple energy storage devices 8 are connected to the power control circuit 7. The other devices 9 are, in addition to… Figure 1 Other components of the storage system 1 besides the components shown (e.g., clock oscillator and temperature sensor).

[0051] The power control circuit 7 includes a sequencer 71, multiple power supply circuits 720 to 729, a non-volatile memory 711, and voltage monitoring terminals (not shown). The non-volatile memory 711 is, for example, NOR flash memory. In the following text, the non-volatile memory 711 is referred to as ROM 711.

[0052] Power supply circuits 720 to 729 are transformers that convert the input voltage to other voltages. Power supply circuits 720 to 729 are, for example, DC / DC converters or low-dropout regulators (LDO regulators). It should be noted that power supply circuits 720 to 729 can also be located externally to the power control circuit 7. Here, the power control circuit 7 and power supply circuits 720 to 729 are connected via terminals.

[0053] The voltage monitoring terminal is used to monitor whether power is being supplied from the external power supply 10 to the power control circuit 7.

[0054] Controller 4 includes a host I / F 42, a NAND I / F 43, a DRAM I / F 44, a buffer memory 45, and other circuitry 46. The other circuitry 46 includes circuitry that communicates with the CPU 41 and the power control circuitry 7. The host I / F 42, NAND I / F 43, DRAM I / F 44, buffer memory 45, and other circuitry 46 are independently connected to the power control circuitry 7, allowing voltage to be applied or stopped individually by switching the power circuits 720 to 724 on and off.

[0055] Voltage is applied from power control circuit 7 to host I / F 42 via power circuit 720. Voltage is applied from power control circuit 7 to NAND I / F 43 via power circuit 721. Voltage is applied from power control circuit 7 to DRAM I / F 44 via power circuit 722. Voltage is applied from power control circuit 7 to cache memory 45 via power circuit 723. Voltage is applied from power control circuit 7 to other circuits 46 via power circuit 724.

[0056] NAND memory 5 includes NAND I / F 51 and core circuitry 52. ​​Core circuitry 52 includes memory cells and circuitry for controlling the voltage applied to the memory cells. NAND I / F 51 and core circuitry 52 are independently connected to power control circuitry 7, thereby allowing voltage to be applied or stopped individually by turning power circuits 725 and 726 on and off.

[0057] Voltage is applied to NAND I / F 51 from power control circuit 7 via power circuit 725. Voltage is applied to core circuit 52 from power control circuit 7 via power circuit 726.

[0058] DRAM 6 includes DRAM I / F 61 and core circuitry 62. Core circuitry 62 includes memory cells that serve as a buffer or storage area for system management information, and circuitry for controlling the voltage applied to the memory cells. DRAM I / F 61 and core circuitry 62 are independently connected to power control circuitry 7, thereby allowing voltage to be applied or stopped independently by turning power circuits 727 and 728 on and off.

[0059] Voltage is applied to DRAM I / F 61 from power control circuit 7 via power circuit 727. Voltage is applied to core circuit 62 from power control circuit 7 via power circuit 728.

[0060] Voltage is applied to other devices 9 from the power control circuit 7 via the power circuit 729.

[0061] The sequencer 71 of the power control circuit 7 controls the power sequence by executing a sequence code. This sequence code is stored in the ROM 711 before the storage system 1 is shipped from the factory. When the storage system 1 starts up, the sequencer 71 controls the startup sequence of each power circuit 720 to 729. The sequencer 71 detects the interruption of power supply from the external power source 10 by monitoring the voltage at the voltage monitoring terminal. The sequencer 71 performs power control such as controlling the on / off state of each power circuit 720 to 729. The sequencer 71 can independently control the on / off state of each power circuit 720 to 729.

[0062] The sequencer 71 also controls the charging and discharging of the energy storage device 8. When power is supplied to the power control circuit 7 from the external power source 10, the sequencer 71 uses the power supplied from the external power source 10 to charge the energy storage device 8.

[0063] The power control circuit 7 uses an external power supply 10 connected to the storage system 1 to apply voltage to each semiconductor element of the storage system 1. The voltage based on the power output from the external power supply 10 is applied to the power control circuit 7 via a connector (not shown). The voltage based on the power output from the external power supply 10 is, for example, 12V. When power is supplied from the external power supply 10, the sequencer 71 supplies power from the external power supply 10 to each of the power supply circuits 720 to 729.

[0064] On the other hand, when the power from the external power source 10 to the power control circuit 7 is cut off, the sequencer 71 uses the energy storage device 8 as a backup power source, supplying power from the energy storage device 8 to each of the power circuits 720 to 729. That is, the sequencer 71 can switch between the external power source 10 and the energy storage device 8 to supply power to each of the power circuits 720 to 729.

[0065] Power supply circuits 720 to 729 use the supplied power to generate multiple voltages required by the semiconductor elements of the storage system 1, and apply the generated multiple voltages to the semiconductor elements. The multiple voltages applied to the semiconductor elements are, for example, 0.8V or 3.3V.

[0066] The power supplied from the external power source 10 is an example of a first power source, and the voltage supplied to each semiconductor element based on the first power source is an example of a first voltage. The power supplied from the energy storage device 8 is an example of a second power source, and the voltage supplied to each semiconductor element based on the second power source is an example of a second voltage.

[0067] The sequencer 71 of the power control circuit 7 detects the interruption of power supply to the storage system 1 by monitoring the voltage at the voltage monitoring terminal. The sequencer 71 compares the voltage based on the power output from the external power source with a threshold voltage. When it detects that the voltage based on the power output from the external power source is equal to or less than the threshold voltage, the sequencer 71 determines that the power supplied to the storage system 1 has been interrupted. The sequencer 71 applies voltage to each semiconductor element of the storage system 1 using the charge from charging the energy storage device 8. This executes PLP processing.

[0068] Figure 3 This is a flowchart illustrating power control in the PLP processing of a storage system according to this embodiment.

[0069] like Figure 3 As shown, when the power control circuit 7 detects that the power supplied from the external power source 10 is cut off (S100), the power control circuit 7 shuts down the power circuit 720 and stops applying voltage to the host I / F 42 of the controller 4 (S101). Therefore, the host I / F 42, which controls communication with the host 2, stops operating.

[0070] Controller 4 evacuates data from DRAM 6 to buffer memory 45 (S102). This data includes data being written from host 2 to NAND memory 5. This data may include LUTs or system management information.

[0071] Controller 4 determines whether the data backup has been completed (S103).

[0072] When the data backup is not completed (No in S103), the processing of controller 4 returns to S103.

[0073] When the data backup is complete (Yes in S103), the controller 4 notifies the power control circuit 7 that the data backup is complete (S104).

[0074] Upon completion, the power control circuit 7 shuts down power circuits 727 and 728 and stops applying voltage to the DRAM I / F 61 and core circuit 62 of DRAM 6 (S105). Here, the power control circuit 7 also shuts down power circuit 722 and stops applying voltage to the DRAM I / F 44 of controller 4. Therefore, DRAM 6 and the DRAM I / F 44 controlling communication with DRAM 6 cease operation.

[0075] Subsequently, controller 4 sends a write command sequence to NAND memory 5 to write data from buffer memory 45 to NAND memory 5 (S106). The write command sequence includes a write command and the data to be written to NAND memory 5. The write command is sent from controller 4 to NAND memory 5. The data to be written is sent from buffer memory 45 to NAND memory 5. The write command sequence may include the address of the data to be written to NAND memory 5.

[0076] Controller 4 determines whether the sending of the write command sequence has been completed (S107).

[0077] If the writing command sequence is not completed (No in S107), the process returns to S107.

[0078] When the transmission of the write command sequence is complete (S107), the controller 4 notifies the power control circuit 7 that the transmission of the write command sequence has been completed (S108).

[0079] The power control circuit 7 shuts down the power circuits 721, 723 and 725, and stops applying voltage to each of the NAND I / F 43 and buffer memory 45 of the controller 4 and the NAND I / F 51 of the NAND memory 5 (S109).

[0080] The NAND memory 5 receives a write command sequence from the controller 4 and then writes data. The power supply circuit 725, which applies voltage to the NAND I / F 51 of the NAND memory 5, can stop earlier than the power supply circuit 726, which applies voltage to the circuitry performing the write (core circuitry 52), because the time required for the NAND memory 5 to receive the write command sequence is shorter than the time required to write data. Therefore, by stopping the application of voltage to the NAND I / F 51 before applying voltage to the core circuitry 52, power consumption can be further reduced.

[0081] Controller 4 determines whether the data writing to NAND memory 5 has been completed (S110).

[0082] When the data writing is not completed (No in S110), the processing of controller 4 returns to S110.

[0083] When the data writing is complete (Yes in S110), the controller 4 notifies the power control circuit 7 that the data writing is complete (S111).

[0084] The power control circuit 7 shuts down the remaining power circuits 724, 726 and 729 that are not turned off (S112), and the storage system 1 ends the PLP process.

[0085] Figure 4AThis is a table used to manage the sequence in which the power supply control circuit 7 stops applying voltage. The sequence in which the power supply control circuit 7 stops applying voltage can be used as... Figure 4A Table 7111 is stored in ROM 711. In response to a notification from controller 4 or a detected power interruption from external power supply 10, power control circuit 7 (specifically, sequencer 71) refers to table 7111 in ROM 711 to shut down power circuits 720 to 729.

[0086] like Figure 4B As shown, the power control circuit 7 includes terminals connected to power circuits 720 to 729. A terminal connects the sequencer 71 to one or more of the power circuits 720 to 729. For example, the power control circuit 7 includes a first terminal A, a second terminal B, a third terminal C, and a fourth terminal D. When the power circuits 720 to 729 are located inside the power control circuit 7, these terminals are internal terminals. When the power circuits 720 to 729 are located outside the power control circuit 7, these terminals are external terminals.

[0087] The first terminal A is connected to the power supply circuit 720, and the sequencer 71 turns the power supply circuit 720 on and off through the first terminal A.

[0088] The second terminal B is connected to power circuits 722, 727 and 728, and the sequencer 71 turns power circuits 722, 727 and 728 on and off via the second terminal B.

[0089] The third terminal C is connected to power supply circuits 721, 723 and 725, and the sequencer 71 turns power supply circuits 721, 723 and 725 on and off via the third terminal C.

[0090] The fourth terminal D is connected to power circuits 724, 726 and 729, and the sequencer 71 turns power circuits 724, 726 and 729 on and off via the fourth terminal D.

[0091] When the power control circuit 7 (specifically, the sequencer 71) detects a cutoff in the power supplied from the external power source 10, the power control circuit 7 refers to Table 7111. Without waiting for notification from the controller 4, the power control circuit 7 shuts off the power circuit 720 via the first terminal A to stop applying voltage to the host I / F 42.

[0092] When the controller 4 notifies the power control circuit 7 that the backup of data from DRAM 6 to buffer memory 45 is complete, the power control circuit 7 refers to Table 7111. The power control circuit 7 shuts down power circuits 722, 727 and 728 via the second terminal B, stopping the application of voltage to the controller 4's DRAM I / F 44, the DRAM 6's DRAM I / F 61 and the core circuit 62.

[0093] When the controller 4 notifies the power control circuit 7 that the transmission of the write command sequence from the controller 4 to the NAND memory 5 has been completed, the power control circuit 7 refers to Table 7111. The power control circuit 7 shuts down the power circuits 721, 723, and 725 via the third terminal C, stopping the application of voltage to the NAND I / F 43 and buffer memory 45 of the controller 4, and the NAND I / F 51 of the NAND memory 5.

[0094] When the controller 4 notifies the power control circuit 7 that the data writing to the NAND memory 5 has been completed, the power control circuit 7 refers to Table 7111. The power control circuit 7 shuts down the power circuits 724, 726 and 729 through the fourth terminal D, stopping the application of voltage to the other circuits 46 of the controller 4, the core circuit 52 of the NAND memory 5 and the other devices 9 of the storage system 1.

[0095] Figure 5 This is a timing diagram illustrating an example of power control in the PLP processing of a storage system according to this embodiment.

[0096] Figure 5 (a) indicates the voltage applied from the external power supply 10, (b-1) to (b-5) indicate the controller 4, (c) indicates the DRAM 6 (DRAM I / F 61 and core circuit 62), (d-1) and (d-2) indicate the NAND memory 5, and (e) indicates the on / off state of the power supplies of other devices 9.

[0097] Figure 5 (b-1) represents the host I / F 42 of controller 4, (b-2) represents the DRAM I / F 44 of controller 4, (b-3) represents the NAND I / F 43 of controller 4, (b-4) represents the buffer memory 45 of controller 4, and (b-5) represents the on / off state of each power supply of the other circuits 46 of controller 4. (d-1) represents the NAND I / F 51 of NAND memory 5, and (d-2) represents the on / off state of each power supply of the core circuit 52 of NAND memory 5.

[0098] As shown in (a), when the power supplied from the external power source 10 is cut off, the voltage applied to the voltage monitoring terminal drops from 12V to 0V. Therefore, the power control circuit 7 detects the cut-off of the power supplied from the external power source 10 (T1).

[0099] As shown in (b-1), the power control circuit 7 shuts down the power circuit 720 (T2) that applies voltage to the host I / F 42.

[0100] Subsequently, controller 4 backs up the data from DRAM 6 to buffer memory 45. When the data backup is complete, as shown in (b-2) and (c), power control circuit 7 shuts down power circuit 722 that applies voltage to DRAM I / F 44, and power circuits 727 and 728 (T3) that apply voltage to DRAM 6.

[0101] Subsequently, controller 4 sends a write command sequence through NAND memory 5 to write data from buffer memory 45 into NAND memory 5. When the write command sequence is completed, as shown in (b-3), (b-4), and (d-1), power control circuit 7 shuts off power circuits 721 and 723 that apply voltage to NAND I / F 43 of controller 4 and buffer memory 45, as well as the voltage (T4) applied to NAND I / F 51 of NAND memory 5.

[0102] Data is written to NAND memory 5. Once the data writing is complete, as shown in (b-5), (d-2), and (e), the power control circuit 7 shuts down the power circuits 724, 726, and 729 (T5) that apply voltage to the other circuits 46 of controller 4, the core circuit 52 of NAND memory 5, and each of the other devices 9 of storage system 1. In other words, all power circuits 720 to 729 are turned off after PLP processing is complete. Thus, the PLP processing of storage system 1 ends.

[0103] According to this embodiment, the storage system 1, during PLP processing, sequentially shuts down any of the power supply circuits 720 to 729 that apply voltage to circuits unrelated to the non-volatile processing of data. Therefore, the power consumption during PLP processing can be reduced. By reducing power consumption during PLP processing, the amount of energy storage devices 8 to be installed can also be reduced.

[0104] (Second Implementation) Next, a storage system 1a according to a second embodiment will be described. The storage system 1a according to the second embodiment includes a plurality of DRAMs. The plurality of DRAMs is an example of a plurality of volatile memories.

[0105] Figure 6 This diagram illustrates the power supply structure of the storage system 1a according to this embodiment. The components of the storage system 1a according to the second embodiment are given the same reference numerals as those in the storage system 1 according to the first embodiment. The controller 4, NAND memory 5, other devices 9, and power supply circuits 720 to 726 and 729 in the storage system 1a are the same as those in the storage system 1, and therefore will not be described further.

[0106] The difference between the storage system 1a according to the second embodiment and the storage system according to the first embodiment is that the storage system 1a includes multiple DRAMs 6a, 6b, 6c, and 6d, and in the PLP process, data stored in the multiple DRAMs 6a, 6b, 6c, and 6d is copied (concentrated) into a single DRAM 6a. The multiple DRAMs 6a, 6b, 6c, and 6d are in different packages. DRAMs 6a, 6b, 6c, and 6d respectively include DRAM I / Fs 61a, 61b, 61c, and 61d and core circuits 62a, 62b, 62c, and 62d.

[0107] The power control circuit 7a includes a sequencer 71, multiple power circuits 730 to 737, a non-volatile memory 711, and power monitoring terminals (not shown). The non-volatile memory 711 is, for example, ROM or NOR flash memory.

[0108] Power supply circuits 730 to 737 are transformers that convert the input voltage to other voltages. Power supply circuits 730 to 737 are, for example, DC / DC converters or LDO regulators. It should be noted that power supply circuits 730 to 737 can be installed externally to the power control circuit 7a. Here, the power control circuit 7a and power supply circuits 730 to 737 are connected via terminals.

[0109] Voltage is applied to DRAM I / F 61a from power control circuit 7a via power circuit 730. Voltage is applied to core circuit 62a from power control circuit 7a via power circuit 731. Voltage is applied to DRAM I / F 61b from power control circuit 7a via power circuit 732. Voltage is applied to core circuit 62b from power control circuit 7a via power circuit 733. Voltage is applied to DRAM I / F 61c from power control circuit 7a via power circuit 734. Voltage is applied to core circuit 62c from power control circuit 7a via power circuit 735. Voltage is applied to DRAM I / F 61d from power control circuit 7a via power circuit 736. Voltage is applied to core circuit 62d from power control circuit 7a via power circuit 737.

[0110] Controller 4 can access multiple DRAMs 6a, 6b, 6c and 6d in parallel.

[0111] Figure 7 This is a flowchart illustrating power control in the PLP processing of the storage system according to the second embodiment. Here, the differences from the first embodiment will be described, and the description of common processing will be omitted or simplified. Processes common to the first embodiment are indicated by the same reference numerals.

[0112] The power control circuit 7a detects the disconnection of power supplied from the external power supply 10 (S100), and shuts down the power circuit 720, stopping the application of voltage to the host I / F 42 (S101).

[0113] Subsequently, controller 4 determines whether the data is stored in a non-volatile manner in multiple DRAMs 6a, 6b, 6c, and 6d (S201). This data includes data during the write process from host 2 to NAND memory 5. This data may include LUTs or system management information.

[0114] When data is stored in multiple DRAMs 6a, 6b, 6c and 6d (as in S201), the controller 4 copies the data from the multiple DRAMs 6a, 6b, 6c and 6d to a single DRAM 6a (S202).

[0115] The controller 4 notifies the power control circuit 7a that the data copying has been completed (S203).

[0116] Conversely, when the data is not stored in multiple DRAMs 6b, 6c, and 6d, i.e., when the data is stored in only one DRAM 6a (No in S201), the controller 4 does not need to copy the data.

[0117] Subsequently, the power control circuit 7a shuts down the power circuits 732 to 737 and stops applying voltage to the DRAMs 6b, 6c and 6d that do not store data (S204).

[0118] The controller 4 backs up the data from DRAM 6a to buffer memory 45 (S102).

[0119] The subsequent processing (S103 to S112) is similar to that of the first embodiment. It should be noted that before the copying of data from the multiple DRAMs 6b, 6c and 6d to a single DRAM 6a is completed (S202), a sequence of write commands can be sent from the controller 4 to the NAND memory 5 (S106).

[0120] When power is stopped to DRAMs 6b, 6c, and 6d, the number of DRAMs that controller 4 can access in parallel decreases. Therefore, the transfer rate between controller 4 and all DRAMs 6, including DRAMs 6a, 6b, 6c, and 6d, decreases. Generally, the transfer rate between NAND memory 5 and DRAM 6 via controller 4 is approximately 1 / 100th of the transfer rate between DRAM 6 and controller 4. In other words, the transfer rate between NAND memory 5 and controller 4 is slower than the transfer rate between DRAM 6 and controller 4.

[0121] Therefore, in PLP processing, the time spent processing data in a non-volatile manner is limited to the transfer rate between NAND memory 5 and controller 4. Thus, this speed is permissible as long as the speed of non-volatile data processing is at least faster than the transfer rate between NAND memory 5 and controller 4, even if the transfer rate between DRAM 6 and controller 4 is reduced. For example, even if the transfer rate between DRAM 6 and controller 4 is reduced to 1 / 4, it is still fast enough compared to the transfer rate between NAND memory 5 and controller 4. Therefore, even if the power supplied to DRAM 6 is reduced and the transfer rate is decreased, the rate of non-volatile data processing will not slow down.

[0122] According to the above implementation method, the power consumed by the storage system 1a in PLP processing can be reduced. By reducing the power consumption in PLP processing, the number of energy storage devices 8 to be installed can also be reduced.

[0123] Although certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of this disclosure. In fact, the novel embodiments described herein can be embodied in many other forms; furthermore, various omissions, substitutions, and changes can be made to the forms of the embodiments described herein without departing from the spirit of this disclosure. The appended claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of this disclosure.

Claims

1. A power control circuit for a storage system including a controller communicating with a host, the power control circuit comprising: Sequencer; The first terminal is connected to the first power supply circuit; as well as The second terminal is connected to the second power supply circuit. The sequencer is configured as follows: Upon detecting the disconnection of external power supply, without waiting for a request from the controller, the first power circuit is disconnected from the sequencer via the first terminal, and in response to the request from the controller, the second power circuit is disconnected from the sequencer via the second terminal. The storage system includes a first semiconductor memory as a non-volatile memory, a second semiconductor memory as a volatile memory, and an energy storage device.

2. The power control circuit according to claim 1, wherein, During the period when the first power supply from the external power source is cut off The sequencer is controlled to apply a second voltage based on the second power supplied from the energy storage device to the first semiconductor memory and the second semiconductor memory. After reading data from the second semiconductor memory and before the writing of the data to the first semiconductor memory is completed, the application of the second voltage to the second semiconductor memory is stopped; as well as After the data has been written to the first semiconductor memory, the application of the second voltage to the first semiconductor memory is stopped.

3. The power control circuit according to claim 2, wherein, The controller includes a third semiconductor memory as volatile memory, and writes the data read from the second semiconductor memory into the third semiconductor memory. After the data is written to the third semiconductor memory, the controller reads the data from the third semiconductor memory and sends the data to the first semiconductor memory. After the data is written to the third semiconductor memory, the sequencer controls the process to stop applying the second voltage to the second semiconductor memory. as well as After the data is read from the third semiconductor memory and before the data is written to the first semiconductor memory, the sequencer controls the application of the second voltage to the third semiconductor memory to stop.

4. The power control circuit according to claim 2, wherein, After the data is written to the third semiconductor memory, the controller sends a first request to the sequencer, and after the data is written to the first semiconductor memory, it sends a second request to the sequencer. as well as The sequencer, in response to the first request, controls to stop applying the second voltage to the second semiconductor memory, and in response to the second request, controls to stop applying the second voltage to the first semiconductor memory.

5. The power control circuit according to claim 2, wherein, After the data is sent to the controller and before the data is written to the first semiconductor memory, the sequencer controls the process to stop applying the second voltage to the second semiconductor memory.

6. The power control circuit according to claim 5, wherein, The sequencer controls the switching on and off of the output of the first voltage or the second voltage from the power supply circuit.

7. The power control circuit according to claim 5, wherein, The storage system also includes at least one power supply circuit. The at least one power supply circuit includes one or more of a plurality of power supply circuits. The controller includes a first circuit that communicates with a host, a second circuit that communicates with the first semiconductor memory, and a third circuit that communicates with the second semiconductor memory. as well as The sequencer applies the first voltage and the second voltage to the first circuit, the second circuit, and the third circuit through at least one of the plurality of power supply circuits.

8. The power control circuit according to claim 7, wherein, During the period when the first power supplied from the external power source is cut off, After the data is copied from the second semiconductor memory to the controller, the sequencer stops applying the second voltage to the power supply circuit corresponding to the third circuit and the power supply circuit corresponding to the second semiconductor memory.

9. The power control circuit according to claim 7, wherein, The first semiconductor memory also includes a fourth circuit that communicates with the controller. During the period when the first power supplied from the external power source is cut off The controller issues a command to request that the data be written into the first semiconductor memory; as well as After the data is transmitted to the first semiconductor memory and before the data is written to the first semiconductor memory, the sequencer stops applying the second voltage to the power supply circuit corresponding to the second circuit and the fourth circuit.

10. The power control circuit according to claim 2, wherein, It also includes a fifth semiconductor memory as a non-volatile memory, the fifth semiconductor memory storing a table indicating the order in which power is stopped from the first power supply circuit and the second power supply circuit via the first terminal and the second terminal, respectively.

11. A power control circuit for a storage system including a controller communicating with a host, the power control circuit comprising: Sequencer; The first terminal is connected to the first power supply circuit; The second terminal is connected to the second power supply circuit; as well as The third terminal is connected to an external power source. The sequencer is configured as follows: The system detects the disconnection of the external power supply at the third terminal, disconnects the first power circuit from the sequencer via the first terminal without waiting for a request from the controller, and disconnects the second power circuit from the sequencer via the second terminal in response to the request from the controller. The storage system includes a first semiconductor memory as a non-volatile memory, a second semiconductor memory as a volatile memory, and an energy storage device.

12. The power control circuit according to claim 11, wherein, During the period when the first power supply from the external power source is cut off The sequencer is controlled to apply a second voltage based on the second power supplied from the energy storage device to the first semiconductor memory and the second semiconductor memory. After reading data from the second semiconductor memory and before the writing of the data to the first semiconductor memory is completed, the application of the second voltage to the second semiconductor memory is stopped; as well as After the data has been written to the first semiconductor memory, the application of the second voltage to the first semiconductor memory is stopped.

13. The power control circuit according to claim 12, wherein, The controller includes a third semiconductor memory as volatile memory, and writes the data read from the second semiconductor memory into the third semiconductor memory. After the data is written to the third semiconductor memory, the controller reads the data from the third semiconductor memory and sends the data to the first semiconductor memory. After the data is written to the third semiconductor memory, the sequencer controls the process to stop applying the second voltage to the second semiconductor memory. as well as After the data is read from the third semiconductor memory and before the data is written to the first semiconductor memory, the sequencer controls the application of the second voltage to the third semiconductor memory to stop.

14. The power control circuit according to claim 12, wherein, After the data is written to the third semiconductor memory, the controller sends a first request to the sequencer, and after the data is written to the first semiconductor memory, it sends a second request to the sequencer. as well as The sequencer, in response to the first request, controls to stop applying the second voltage to the second semiconductor memory, and in response to the second request, controls to stop applying the second voltage to the first semiconductor memory.

15. The power control circuit according to claim 12, wherein, After the data is sent to the controller and before the data is written to the first semiconductor memory, the sequencer controls the process to stop applying the second voltage to the second semiconductor memory.

16. The power control circuit according to claim 15, wherein, The sequencer controls the switching on and off of the output of the first voltage or the second voltage from the power supply circuit.

17. The power control circuit according to claim 15, wherein, The storage system also includes at least one power supply circuit. The at least one power supply circuit includes one or more of a plurality of power supply circuits. The controller includes a first circuit that communicates with a host, a second circuit that communicates with the first semiconductor memory, and a third circuit that communicates with the second semiconductor memory. as well as The sequencer applies the first voltage and the second voltage to the first circuit, the second circuit, and the third circuit through at least one of the plurality of power supply circuits.

18. The power control circuit according to claim 17, wherein, During the period when the first power supplied from the external power source is cut off, After the data is copied from the second semiconductor memory to the controller, the sequencer stops applying the second voltage to the power supply circuit corresponding to the third circuit and the power supply circuit corresponding to the second semiconductor memory.

19. The power control circuit according to claim 17, wherein, The first semiconductor memory also includes a fourth circuit that communicates with the controller. During the period when the first power supplied from the external power source is cut off The controller issues a command to request that the data be written into the first semiconductor memory; as well as After the data is transmitted to the first semiconductor memory and before the data is written to the first semiconductor memory, the sequencer stops applying the second voltage to the power supply circuit corresponding to the second circuit and the fourth circuit.

20. The power control circuit according to claim 12, wherein, It also includes a fifth semiconductor memory as a non-volatile memory, the fifth semiconductor memory storing a table indicating the order in which power is stopped from the first power supply circuit and the second power supply circuit via the first terminal and the second terminal, respectively.

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