storage device

Abstract

A memory device includes a first memory cell including a first variable resistance element and a first switching element connected to the first variable resistance element. A first wiring is connected to the first memory cell. The first switching element has a first terminal connected to the first wiring and a second terminal. A second wiring is connected to the second terminal. A first precharge circuit is connected to the second wiring. A first transistor has a third terminal connected to a first node that receives a first voltage, a fourth terminal, and a gate connected to the first wiring. A third wiring is connected to the fourth terminal of the first transistor. A sense amplifier circuit is connected to the third wiring.

Description

Technical Field

[0001] The implementation methods generally involve storage devices. Background Technology

[0002] Storage devices that utilize magnetoresistive elements are known. These storage devices are required to operate at high speeds. Summary of the Invention

[0003] Provides a storage device that operates at high speed.

[0004] One embodiment of the storage device includes a first storage cell, a first wiring, a first switch, a second wiring, a first precharge circuit, a first transistor, a third wiring, and a sense amplifier circuit. The first storage cell includes a first variable resistor element and a first switch element connected to the first variable resistor element. The first wiring is connected to the first storage cell. The first switch has a first terminal and a second terminal connected to the first wiring. The second wiring is connected to the second terminal. The first precharge circuit is connected to the second wiring. The first transistor has a third terminal and a fourth terminal connected to a first node receiving a first voltage, and a gate connected to the first wiring. The third wiring is connected to the fourth terminal of the first transistor. The sense amplifier circuit is connected to the third wiring. Attached Figure Description

[0005] Figure 1 This is a block diagram of the storage device according to the first embodiment.

[0006] Figure 2 This is a block diagram of the core circuit of the storage device according to the first embodiment.

[0007] Figure 3 The components and connections of the GWL selector and GBL selector of the storage device according to the first embodiment are shown.

[0008] Figure 4 The functional blocks of the sub-core circuit of the storage device of the first embodiment are shown.

[0009] Figure 5 The components of the WL selector and BL selector of the storage device according to the first embodiment and the connection of the components are shown.

[0010] Figure 6 This is a perspective view of a portion of the storage cell array of the storage device according to the first embodiment.

[0011] Figure 7 An example of a cross-section showing the structure of a storage cell in the storage device of the first embodiment.

[0012] Figure 8 An example illustrating the voltage and current characteristics of the storage cell of the storage device according to the first embodiment is shown.

[0013] Figure 9 The diagram shows the components of the conversion circuit and readout circuit of the storage device according to the first embodiment, the connections between the components, and the associated components.

[0014] Figure 10 The components and connections of the sensing amplifier circuit of the storage device in a modified example of the first embodiment are shown.

[0015] Figure 11 Examples of the components of the readout circuit of the storage device according to the first embodiment and the connections of the components are shown.

[0016] Figure 12 The process of reading data from the storage device of the first embodiment is shown.

[0017] Figure 13 Several signals and wiring potentials during data readout of the storage device of the first embodiment are shown along time.

[0018] Figure 14 The diagram shows a portion of the components of the storage device according to the first embodiment, the connections between the components, and the associated components.

[0019] Explanation of reference numerals in the attached figures

[0020] 1… Storage device,

[0021] 11…core circuit,

[0022] 12…Input / output circuit,

[0023] 13…control circuit,

[0024] 14…decoding circuit,

[0025] 15…page buffer,

[0026] 16…Voltage generation circuit,

[0027] MC… storage unit,

[0028] GWL…Global Word Line

[0029] GBL…Global Bitline

[0030] GWS…GWL selector,

[0031] GBS…GBL selector

[0032] CC…conversion circuit,

[0033] DYL…wiring,

[0034] DXL…wiring,

[0035] DXLR... wiring

[0036] 18…written into the circuit,

[0037] 19…Readout circuit,

[0038] GWSW… switch,

[0039] GBSW… switch,

[0040] MCA… storage cell array,

[0041] WL…word line,

[0042] BL…bitline,

[0043] GWL…Global Word Line

[0044] GBL…Global Bitline

[0045] MTJ…MTJ components,

[0046] SE…switching element. Detailed Implementation

[0047] Hereinafter, embodiments will be described with reference to the accompanying drawings. Sometimes, to distinguish between multiple components having substantially the same function and structure in a certain embodiment or different embodiments, numbers or words are added to the end of the reference numerals. In embodiments that follow a previously described embodiment, the differences from the previously described embodiment are mainly described. The description of a certain embodiment is applicable to the description of other embodiments unless explicitly stated or obviously excluded.

[0048] Each functional block can be implemented as hardware, computer software, or a combination of both. A portion of the functionality of each functional block can also be executed by other functional blocks, or by finely defined sub-functional blocks.

[0049] In this specification and claims, a first element being "connected" to another second element includes: the first element being directly, or always or selectively, connected to the second element via an element that is conductive.

[0050] The following describes the implementation using a three-dimensional orthogonal coordinate system. The direction of the x-axis is called the X-direction. The direction opposite to the X-direction is called the -X-direction. The direction of the y-axis is called the Y-direction. The direction opposite to the Y-direction is called the -Y-direction. The direction of the z-axis is called the Z-direction, and the direction opposite to the Z-direction is called the -Z-direction.

[0051] 1. First Implementation Method

[0052] 1.1. Composition (structure)

[0053] Figure 1 The functional blocks of the storage device according to the first embodiment are shown. The storage device 1 includes a core circuit 111, an input / output circuit 12, a control circuit 13, a decoding circuit 14, a page buffer 15, and a voltage generation circuit 16.

[0054] The core circuit 11 is a circuit that includes multiple memory cells MC and wiring and circuitry for accessing the memory cells MC.

[0055] Input / output circuit 12 is a circuit for inputting and outputting data and signals. Input / output circuit 12 receives control signals CNT, commands CMD, address information ADD, and data DAT from an external source of storage device 1, such as a storage controller. Input / output circuit 12 outputs data DAT.

[0056] Control circuit 13 receives commands CMD and control signals CNT from input / output circuit 12. Based on the commands CMD and CNT, control circuit 13 controls core circuit 11, controlling the reading of data from memory cell MC and the writing of data to memory cell MC. Control circuit 13 also controls voltage generation circuit 16 based on the commands CMD and CNT.

[0057] Decoding circuit 14 is a circuit that decodes address information ADD. Decoding circuit 14 receives address information ADD from input / output circuit 12. Decoding circuit 14 decodes address information ADD and, based on the decoding result, generates a signal for selecting the storage cell MC of the object to be read from or written to. The generated signal is sent to core circuit 11.

[0058] Page buffer 15 is a circuit that temporarily stores data of a certain size. Page buffer 15 receives data DAT to be written to memory cell MC from input / output circuit 12, temporarily stores the data, and transfers the data to core circuit 11. Page buffer 15 also receives data read from memory cell MC, temporarily stores the read data, and transfers the data DAT to input / output circuit 12.

[0059] During the writing of data to the storage cell MC, the voltage generation circuit 16 supplies the voltage for data writing to the core circuit 11. During the reading of data from the storage cell MC, the voltage generation circuit 16 supplies the voltage for data reading to the core circuit 11.

[0060] Figure 2 The functional blocks of the core circuitry of the storage device according to the first embodiment are shown. For example... Figure 2 As shown, the core circuit 11 includes multiple sub-core circuits SCC, multiple global word lines GWL, multiple global bit lines GBL, GWL selector GWS, GBL selector GBS, multiple conversion circuits CC, routing DYL, routing DXL, multiple routing DXLR, write circuit 18, and read circuit 19. In the following description, the terms "word line" and "bit line" are used only to distinguish the two types of routing and can be referred to by interchangeable names.

[0061] Each sub-chip circuit (SCC) is a group of multiple components, including multiple memory cells (MC), multiple selectors, and multiple wirings. Each SCC is connected to one global word line (GWL) and one global bit line (GBL).

[0062] Each global word line (GWL) is connected to multiple sub-chip circuits (SCC). Each global bit line (GBL) is connected to multiple sub-chip circuits (SCC).

[0063] The GWL selector (GWS) is a circuit that selects one global word line from a plurality of global word lines (GWLs). Each GWL selector (GWS) receives address information (ADD) or a signal based on address information (ADD), and connects the one global word line (GWL) determined by the received address information (ADD) or the signal based on address information to the wiring (DYL).

[0064] Wiring DYL is connected to the readout circuit 19 and the write circuit 18.

[0065] The GBL selector GBS is a circuit that selects one global bit line from a plurality of global bit lines (GBLs). Each GBL selector GBS receives address information ADD or a signal based on address information ADD, and connects the one global bit line GBL determined by the received address information ADD or the signal based on address information to the wiring DXL.

[0066] Each conversion circuit (CC) is a circuit that converts current into voltage. Each conversion circuit (CC) is connected between a global bit line (GBL) and a routing line (DXLR). The conversion circuit (CC) applies a voltage to the routing line (DXLR) based on the magnitude of the current flowing in the global bit line (GBL).

[0067] The wiring DXLR is connected to the readout circuit 19.

[0068] The write circuit 18 is a circuit that controls the writing of data to the storage cell MC. The write circuit 18 receives write data DAT from the input / output circuit 12 and receives the voltage for data writing from the voltage generation circuit 16. Based on the control of the control circuit 13 and the write data DAT, the write circuit 18 supplies the voltage and current for data writing to the wirings DXL and DYL.

[0069] The readout circuit 19 is a circuit that controls the reading of data from the storage cell MC. The readout circuit 19 receives a voltage from the voltage generation circuit 16 for data reading. Based on the control of the control circuit 13, the readout circuit 19 uses the voltage for data reading to determine the data stored in the storage cell MC. The determined data is supplied to the input / output circuit 12 as readout data DAT. The readout circuit 19 includes multiple sense amplifier circuits SAC. The sense amplifier circuit SAC is a circuit that outputs data determined to be stored in the storage cell MC based on the voltage of the data stored in the storage cell MC. Details of the sense amplifier circuit SAC will be described later.

[0070] Figure 3 The components and connections of the GWL selector and GBL selector of the storage device according to the first embodiment are shown. Figure 3 As shown, the GWL selector GWS includes the same number of switches GWSW as the number of sub-core circuits SCC connected to each global word line GBL. Each switch GWSW is connected at one end to the wiring DYL and at the other end to one global word line GWL. Each switch GWSW is a p-type or n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or, a p-type and n-type MOSFET connected in parallel and receiving complementary signals at their respective gates. The description of the switch GWSW also applies to the switches GWSW, WSW, BSW, SW1, SW2, SW3, SW4, SW5, SW6, SW7, SW11, and SW12 described later. Each switch GWSW is turned on (ON) or off (OFF) by a read circuit 19 or a write circuit 18 based on the address information ADD or the following signal: a signal based on the address information ADD.

[0071] The GBL selector GBS includes the same number of switches GBSW as the number of sub-core circuits SCC connected to each global word line GWL. Each switch GBSW is connected at one end to wiring DXL and at the other end to one global bit line GBL. Each switch GBSW is turned on or off by read circuit 19 or write circuit 18 based on address information ADD or the following signal, which is based on address information ADD.

[0072] Figure 4 The functional blocks of the sub-chip circuit of the storage device according to the first embodiment are shown. For example... Figure 4 As shown, each sub-core circuit SCC includes a memory cell array MCA, multiple word lines WL, multiple bit lines BL, WL selector WS, BL selector BS, global word line GWL, and global bit line GBL.

[0073] A memory cell array (MCA) is a collection of multiple memory cells (MCs) arranged in a row. Each memory cell (MC) stores data in a non-volatile manner. Word lines (WLs) and bit lines (BLs) are also located within the MCA. The following description is based on an example where the word line (WL) is associated with a row and the bit line (BL) is associated with a column. Each memory cell (MC) is connected to one word line (WL) and one bit line (BL). A memory cell (MC) is determined by selecting one row and one column.

[0074] Each word line (WL) is connected to multiple memory cells (MC). Each bit line (BL) is connected to multiple memory cells (MC).

[0075] Each memory cell (MC) uses dynamically variable resistance to store data, including variable resistance elements. A variable resistance element is a component that can switch between a low resistance state and a high resistance state. The following description is based on the example of the variable resistance element as described later in the MTJ element section. Other examples of variable resistance elements include phase-change elements.

[0076] Each memory cell (MC) includes one MTJ element and one switching element (SE). In each memory cell (MC), the MTJ element and the switching element (SE) are connected in series. The switching element (SE) of each memory cell (MC) is connected to one word line (WL). The MTJ element of each memory cell (MC) is connected to one bit line (BL). The MTJ element is a device exhibiting the tunneling magnetoresistive effect, in one example including a magnetic tunnel junction (MTJ). The MTJ element is also called a magnetoresistive effect element (MTJ). The MTJ element is a variable resistance element capable of switching between a low-resistance state and a high-resistance state. The MTJ element can store one bit of data using the difference between the two resistance states. In one example, the MTJ element stores "0" data in the low-resistance state and "1" data in the high-resistance state.

[0077] A switching element SE is a component with two terminals that electrically connects or disconnects the two terminals. When the voltage applied between the two terminals of the switching element SE in a first direction is less than a certain threshold voltage, it becomes a high-resistance state, for example, a non-conducting state (or, a cut-off state). When the voltage applied between the two terminals rises and becomes above the threshold voltage, the switching element SE becomes a low-resistance state, for example, a conducting state (or, a conducting state). When the voltage between the two terminals of the switching element SE in a low-resistance state drops and becomes less than the threshold voltage, the switching element SE becomes a high-resistance state. The switching element SE also has the same function in a second direction opposite to the first direction, switching between high-resistance and low-resistance states based on the magnitude of the voltage applied in the first direction. That is, the switching element SE is a bidirectional switching element. By turning the switching element SE on or off, the presence or absence of current supply to the MTJ element MTJ connected to the switching element SE can be controlled, that is, the selection or non-selection of the MTJ element MTJ can be controlled.

[0078] Each WL selector (WS) is a circuit that selects one word line from multiple word lines (WL). Each WL selector (WS) receives address information ADD or a signal based on address information ADD, and connects one word line (WL) determined by the received address information ADD or the signal based on address information ADD to a global word line (GWL).

[0079] Each BL selector BS is a circuit that selects one bit line from multiple bit lines BL. Each BL selector BS receives address information ADD or a signal based on address information ADD, and connects one bit line BL determined by the received address information ADD or the signal based on address information ADD to a global bit line GBL.

[0080] Figure 5 The components and connections of the WL selector and BL selector of the storage device according to the first embodiment are shown. Figure 5 As shown, the WL selector WS includes the same number of switches WSW as the number of memory cells MC connected to each bit line BL. Each switch WSW is connected at one end to the global word line GWL and at the other end to one word line WL. Each switch WSW is turned on or off by the control of the read circuit 19 or the write circuit 18 based on the address information ADD or the following signal, which is the signal based on the address information ADD.

[0081] The BL selector BS includes the same number of switches BSW as the number of memory cells MC connected to each word line WL. Each switch BSW is connected at one end to the global bit line GBL and at the other end to one bit line BL. Each switch BSW is turned on or off by the control of the read circuit 19 or the write circuit 18 based on the address information ADD or the following signal, which is the signal based on the address information ADD.

[0082] exist Figure 2 , Figure 3 , Figure 4 as well as Figure 5 In this example, the core circuit 11 has two levels. The lowest level, the first level, includes... Figure 4 The diagram shows a group of memory cells (MC), word lines (WL), bit lines (BL), WL selectors (WS), and BL selectors (BS). The second level includes... Figure 2 The configuration shown is a group of sub-core circuit SCC, global word line GWL, global bit line GBL, GWL selector GWS, and GBL selector GBS.

[0083] The core circuit 11 can also have more than three levels. By turning on the selector switches in each level, a word line WL is connected to the write circuit 18 and the read circuit 19. Similarly, by turning on the selector switches in each level, a bit line BL is connected to the write circuit 18 and the read circuit 19.

[0084] Figure 6 This is a perspective view of a portion of the storage cell array of the storage device according to the first embodiment. Figure 6 As shown, multiple conductors 21 and multiple conductors 22 are provided.

[0085] The conductors 21 have a straight line shape, extend in the X direction and are arranged in the Y direction. Each conductor 21 functions as at least part of a word line WL.

[0086] Conductor 22 is located further Z-direction than conductor 21. Conductor 22 has a straight shape, extends in the Y-direction and is arranged in the X-direction. Each conductor 22 functions as at least part of a bit line BL.

[0087] One memory cell MC is disposed at each intersection of conductor 21 and conductor 22. The memory cells MC are arranged in rows and columns along the xy plane formed by the X and Y directions. Each memory cell MC includes a structure that functions as a switching element SE and a structure that functions as an MTJ element MTJ. The structure that functions as a switching element SE and the structure that functions as an MTJ element MTJ each include one or more layers. In one example, the structure that functions as an MTJ element MTJ is located on the upper surface of the structure that functions as a switching element SE. The -Z direction side surface (lower surface) of the memory cell MC is in contact with the upper surface of one conductor 21. The Z direction side surface (upper surface) of the memory cell MC is in contact with the lower surface of one conductor 22.

[0088] Figure 7 An example of a cross-section showing the structure of a storage cell in the storage device of the first embodiment.

[0089] The switching element SE includes a variable resistive material 32. The variable resistive material 32 is a material exhibiting dynamically variable resistance, for example, having a layered shape. The variable resistive material 32 is a two-terminal switching element, where the first terminal is one of the upper and lower surfaces of the variable resistive material 32, and the second terminal is the other of the upper and lower surfaces. When the voltage applied between the two terminals is less than a certain threshold voltage, the variable resistive material 32 is in a "high resistance" state, for example, a non-conductive state. When the voltage applied between the two terminals rises and becomes above the threshold voltage, the variable resistive material 32 becomes in a "low resistance" state, for example, a conductive state. When the voltage applied between the two terminals of the variable resistive material 32 in the low resistance state drops and becomes less than the threshold voltage, the variable resistive material 32 becomes in a high resistance state.

[0090] In one example, the variable resistor material 32 comprises an insulator and a dopant introduced into the insulator via ion implantation. The insulator may comprise, for example, an oxide, SiO2, or a material substantially formed from SiO2. In one example, the dopant comprises arsenic (As) or germanium (Ge). The description of “substantially formed (or constituted)” and similar descriptions imply that “substantially formed” constituent elements are permitted to contain unwanted impurities.

[0091] The switching element SE may also include a lower electrode 31 and an upper electrode 33. Figure 7An example is shown. Variable resistivity material 32 is located on the upper surface of the lower electrode 31, and upper electrode 33 is located on the upper surface of variable resistivity material 32.

[0092] The MTJ element includes a strongly magnetic layer 35, an insulating layer 36, and a strongly magnetic layer 37. For example, ... Figure 7 As shown, the insulating layer 36 is located on the upper surface of the strongly magnetic layer 35, and the strongly magnetic layer 37 is located on the upper surface of the insulating layer 36.

[0093] The strong magnetic layer 35 is a layer of material exhibiting strong magnetism. The strong magnetic layer 35 has an easy magnetization axis along the direction that runs through the interface of the strong magnetic layer 35, the insulating layer 36, and the strong magnetic layer 37. In one example, it has an easy magnetization axis at an angle of 45° or more and 90° or less relative to the interface; in another example, it has an easy magnetization axis perpendicular to the interface. The direction of magnetization of the strong magnetic layer 35 remains unchanged even when data is read from and written to the memory cell MC. The strong magnetic layer 35 can function as a so-called reference layer (RL). The strong magnetic layer 35 may also comprise multiple layers. Hereinafter, the strong magnetic layer 35 is sometimes referred to as the reference layer RL.

[0094] Insulating layer 36 is a layer of insulator. Insulating layer 36 may contain, for example, magnesium oxide (MgO), or be substantially composed of MgO, and function as a so-called tunnel barrier (TB).

[0095] The strong magnetic layer 37 is a layer of material exhibiting strong magnetism. The strong magnetic layer 37 may contain, for example, cobalt iron boron (CoFeB) or iron boride (FeB), or be substantially composed of CoFeB or FeB. The strong magnetic layer 37 has an easy magnetization axis along the direction that penetrates the interface of the strong magnetic layer 35, the insulating layer 36, and the strong magnetic layer 37. In one example, it has an easy magnetization axis at an angle of 45° or more and 90° or less relative to the interface; in another example, it has an easy magnetization axis along a direction orthogonal to the interface. The direction of magnetization of the strong magnetic layer 37 can vary depending on the data written to the memory cell MC, and the strong magnetic layer 37 can function as a so-called memory layer (SL). Hereinafter, the strong magnetic layer 37 is sometimes referred to as the memory layer SL.

[0096] When the magnetization direction of the storage layer SL is parallel to the magnetization direction of the reference layer RL, the MTJ element has a low resistance. When the magnetization direction of the storage layer SL is antiparallel to the magnetization direction of the reference layer RL, the MTJ element has a higher resistance than when the magnetization direction of the storage layer SL is antiparallel to the magnetization direction of the reference layer RL.

[0097] When a current of magnitude Icp or greater flows from the storage layer SL toward the reference layer RL, the magnetization direction of the storage layer SL becomes parallel to the magnetization direction of the reference layer RL. When a current of magnitude Icap or greater flows from the reference layer RL toward the storage layer SL, the magnetization direction of the storage layer SL becomes antiparallel to the magnetization direction of the reference layer RL.

[0098] MTJ components can also contain more layers.

[0099] Figure 8 An example illustrating the voltage and current characteristics of the storage cell in the storage device of the first embodiment is shown. The horizontal axis of the graph shows the magnitude of the terminal voltage (i.e., the potential difference between the two ends) of the storage cell MC. The vertical axis of the graph shows the magnitude of the current flowing in the storage cell MC on a logarithmic scale. Figure 8 Dashed lines are used to indicate hypothetical properties that are not actually visible. Figure 8 This shows the case where the memory cell MC is in a low resistance state and the case where it is in a high resistance state.

[0100] As the voltage increases from 0, the current continues to increase until it reaches the threshold voltage Vth. Before the voltage reaches the threshold voltage Vth, the switching element SE of the memory cell MC is turned off, i.e., not conducting.

[0101] When the voltage increases further and reaches the threshold voltage Vth, i.e., point A, the voltage-current relationship exhibits a discontinuous change, displaying the characteristics shown at points B1 and B2. The current magnitudes at points B1 and B2 are significantly greater than the current magnitude at point A. This abrupt change in current is based on the fact that the switching element SE of the memory cell MC is turned on. The current magnitudes at points B1 and B2 depend on the resistance state of the MTJ element MTJ in the memory cell MC.

[0102] When the voltage is reduced from the state where the switching element SE is turned on, for example, the voltage and current exhibit the relationship shown at point B1 or point B2 and points with higher voltages than them, the current continues to decrease.

[0103] When the voltage decreases further and reaches a certain value, the voltage-current relationship exhibits discontinuous changes. The voltage at which this discontinuity begins depends on the terminal voltage of the MTJ element in the memory cell MC, i.e., whether the MTJ element is in a high-resistance or low-resistance state. When the MTJ element is in a low-resistance state, the voltage-current relationship exhibits discontinuities starting from point C1. When the MTJ element is in a high-resistance state, the voltage-current relationship exhibits discontinuities starting from point C2. The voltage-current relationship, when reaching points C1 and C2, exhibits the characteristics shown at points D1 and D2, respectively. The current magnitudes at points D1 and D2 are significantly smaller than the current magnitudes at points C1 and C2, respectively. This abrupt change in current is based on the fact that the switching element SE of the memory cell MC has been turned off.

[0104] The terminal voltage at point D1 of the memory cell MC of an MTJ element, including the low-resistance state, is called the low holding voltage VhdL. The terminal voltage at point D2 of the memory cell MC of an MTJ element, including the high-resistance state, is called the high holding voltage VhdH.

[0105] Figure 9 The diagram shows the components of the conversion circuit and readout circuit of the storage device according to the first embodiment, the connections between the components, and the associated components. Figure 9 An example of Q+1 global bit lines GBL_0~GBL_Q is shown.

[0106] Storage device 1 includes the same number of routing DXLRs as the number of global bit lines GBL, that is, it includes Q+1 routing DXLR_0~DXLR_Q.

[0107] Each conversion circuit CC includes an n-type MOSFET Tr1 and a switch SW1. Tr1 and SW1 are connected in series between a wiring DXLR and a node receiving ground voltage (or reference voltage) VSS. SW1 is turned on (ON) or off (OFF) based on signal S1. Tr1 is connected at its gate to a global bit line GBL.

[0108] The readout circuit 19 includes a readout control circuit RCC, a precharge circuit PCDXL, a precharge circuit PCDXLR, a sense amplifier circuit SAC, a number of switches SW2 equal to the number of global bit lines GBL, and a number of switches SW3 equal to the number of global bit lines GBL. That is, the readout circuit 19 includes Q+1 switches SW2 and Q+1 switches SW3.

[0109] Each switch SW2 is connected between a wiring DXLR and a sense amplifier circuit SAC. Each switch SW2 is turned on or off based on signal S2. Different switches SW2 receive different signals S2. Thus, each switch SW2 is turned on or off independently.

[0110] Each switch SW3 is connected between a wiring DXLR and a pre-charge circuit PCDXLR. Each switch SW3 is turned on or off based on a signal S3, described later. Different switches SW3 receive different signals S3. Thus, each switch SW3 is turned on or off independently.

[0111] The precharge circuit PCDXL is a circuit that applies a voltage to the wiring DXL. The precharge circuit PCDXL applies a precharge voltage VPRCH and a non-selection voltage VUSEL to the wiring DXL. The non-selection voltage VUSEL is higher than the ground voltage VSS. The precharge voltage VPRCH is higher than the non-selection voltage VUSEL. In one example, the precharge voltage VPRCH and the non-selection voltage VUSEL are supplied from the voltage generation circuit 16. In one example, the non-selection voltage VUSEL has half the height of the precharge voltage VPRCH.

[0112] The precharge circuit PCDXLR is a circuit that applies a precharge voltage VPC to the wiring DXLR. In one example, the precharge voltage VPC has the same or approximately the same magnitude as the non-selection voltage VUSEL. The following description is based on this example.

[0113] The RCC control circuit reads out the control data. The RCC control circuit controls the on / off state of switches SW1, SW2, and SW3, i.e., output signals S1, S2, and S3.

[0114] Figure 10 The diagram illustrates the components and connections of the sensing amplifier circuit of a storage device according to a variation of the first embodiment. Figure 10 As shown, the sensing amplifier circuit SAC includes switches SW11 and SW12, capacitors CP1 and CP2, and a p-type MOSFET TP1.

[0115] Switch SW11 is connected between one end of each switch SW2 and the node (or wiring) SAMP. Switch SW11 is turned on or off based on signal S11.

[0116] Switch SW12 is connected between one end of each switch SW2 and the node (or wiring) EVAL. Switch SW12 is turned on or off based on signal S12.

[0117] Capacitor CP1 is connected between node SAMP and the node receiving ground voltage VSS. Capacitor CP2 is connected between node EVAL and the node receiving ground voltage VSS.

[0118] Transistor TP1 is connected between the node receiving the power supply voltage VDD and one end of each switch SW2. Transistor TP1 is connected to node SAMP at its gate.

[0119] The operational amplifier circuit OP is connected to node SAMP at the inverting input terminal. The operational amplifier circuit OP is connected to node EVAL at the non-inverting input terminal.

[0120] Figure 11 This diagram illustrates the components of the read circuit of the storage device according to the first embodiment and an example of the connections between these components. As an example, Figure 11 Also shown is a selectable memory cell MCsel, a global bit line GBL, a conversion circuit CC connected to the global bit line GBL, a wiring DXLR connected to the conversion circuit CC, and associated components.

[0121] In one example, the precharge circuit PCDXL includes switches SW4 and SW5. Switch SW4 is connected between the node receiving the precharge voltage VPRCH and the wiring DXL. Switch SW4 is turned on or off based on signal S4.

[0122] Switch SW5 is connected between wiring DXL and the node that accepts the non-selective voltage VUSEL. Switch SW5 is turned on or off based on signal S5.

[0123] The readout circuit 19 also includes switches SW6 and SW7, and a node that receives the precharge voltage VPC.

[0124] Switch SW6 is connected between wiring DYL and the node that receives the non-selective voltage VUSEL. Switch SW6 is turned on or off based on signal S6.

[0125] Switch SW7 is connected between wiring DYL and the node receiving ground voltage VSS. Switch SW7 is turned on or off based on signal S7.

[0126] The node receiving the precharge voltage VPC is connected to a wiring DXLR via a switch SW3.

[0127] Read out the RCC output signals S1, S2, S3, S4, S5, S6 and S7 of the control circuit.

[0128] Switch SW1 is in the ON state when receiving a high-level or "H" level signal S1, maintaining the electrical connection between one end of switch SW1 and the other end. Switch SW1 is in the OFF state when receiving a low-level or "L" level signal S1, maintaining the electrical disconnection between one end of switch SW1 and the other end.

[0129] Let n be an integer greater than or equal to 2. The same applies to switches SWn and signals Sn. That is, for switch SWn, the description of switch SW1 is replaced with the description of switch SWn, and for signal Sn, the description of signal S1 is replaced with the description of signal Sn.

[0130] 1.2. Actions

[0131] Figure 12 The process of reading data from the storage device of the first embodiment is shown. Figure 12 The process begins when storage device 1 decides to read data from the selected storage unit MCsel. In one example, the decision to perform a data read is based on storage device 1 receiving a data read command.

[0132] like Figure 12 As shown, the first sensing (ST1) is performed. Sensing refers to obtaining data determined to be stored in the selected memory cell MCsel based on the resistance state of the MTJ element MTJ of the selected memory cell MCsel. During the first sensing, switch SW11 of the sensing amplifier circuit SAC is kept on, and switch SW12 is kept off. In this state, a voltage based on the resistance state of the MTJ element MTJ of the selected memory cell MCsel is applied to the wiring DXLR. As a result, the potential based on the resistance state of the MTJ element MTJ of the selected memory cell MCsel is displayed at node SAMP. After the potential is displayed at node SAMP, switch SW11 is turned off. As a result, the potential based on the resistance state of the MTJ element MTJ of the selected memory cell MCsel is stored at node SAMP. The potential of node SAMP controls the current flowing in transistor TP1 based on the resistance state of the MTJ element MTJ of the selected memory cell MCsel at the start time of data readout. Therefore, at the start of data readout, current flows into the wiring DXLR based on the resistance state of the MTJ element MTJ of the selected memory cell MCsel.

[0133] Write reference data (ST2) to the selected memory cell MCsel. Reference data is data with a predetermined, fixed value. Reference data can be either "0" or "1". The following description is based on an example with "0" data.

[0134] The second sensing (ST3) is performed. During the second sensing, switch SW12 of the sensing amplifier circuit SAC is kept on, and switch SW11 is kept off. In this state, a voltage based on the resistance state of the MTJ element MTJ of the selected memory cell MCsel (i.e., a voltage based on the low resistance state) is applied to the wiring DXLR. Furthermore, current based on the result of the first sensing flows into the wiring DXLR. Therefore, the potential of the resistance state of the MTJ element MTJ of the selected memory cell MCsel at the start time of data readout, based on the result of the first sensing, is displayed on the wiring DXLR.

[0135] By enabling the operational amplifier circuit OP, data OUT with values ​​based on the potentials of node SAMP and node EVAL is output. Data OUT has a value based on the data determined to be stored in memory cell MCsel at the start of data readout. If memory cell MCsel stores "0" data at the start of data readout, the data stored in memory cell MCsel at the start of data readout is the same as the written reference data. Data OUT with a value reflecting this situation is output.

[0136] On the other hand, if the selected storage unit MCsel stores "1" data at the start time of data readout, the data stored in the selected storage unit MCsel at the start time of data readout may differ from the reference data that was written. Data OUT, reflecting this situation, is output.

[0137] After the data OUT is output, the data that was stored in the selected storage unit MCsel at the start time of data reading will be written to the selected storage unit MCsel.

[0138] Figure 13 Several signals and wiring potentials during data readout of the storage device of the first embodiment are shown along time. Figure 13 This indicates that one selectable memory cell MCsel has been selected. That is, the switches BSW, WSW, and GWSW connected to the selectable memory cell MCsel are in [selected state]. Figure 13 Conduction is enabled during the period shown. Figure 13 The actions during the period shown begin when data reading starts, provided that the selected storage unit MCsel of the data reading object is selected.

[0139] Hereinafter, the word line WL connected to the select memory cell MCsel is sometimes referred to as the select word line WL. The bit line BL connected to the select memory cell MCsel is sometimes referred to as the select bit line BL. The transistor Tr1 connected to the select global bit line GBL is sometimes referred to as the select transistor Tr1. The global word line GWL connected to the select word line WLsel is sometimes referred to as the select global word line GWL. Figure 13 The diagram shows the select word line WL, select bit line BL, select global bit line GBL, select transistor Tr1, the wiring DXLR connected to select transistor Tr1, and select global word line GWL. Figure 13 The signal SGB is shown to be supplied to the switch GBSW, which is connected to the global bit line GBL. Figure 13 The signal S1 is shown to be connected to a switch SW1 with a gate connected to a select global bit line GBL.

[0140] Pervasive Figure 13 During the period shown, switch SW1, which is connected to transistor Tr1 other than selection transistor Tr1, is kept off. (This applies throughout...) Figure 13 During the period shown, the switch GBSW, except for the switch connected to the global bit line GBL, is kept off.

[0141] At time t0, the signals and wiring have the following potentials or levels. Signals S4 and S7 are low, and signals S5 and S6 are high. Therefore, switches SW4 and SW7 are off, and switches SW5 and SW6 are on. Signal SGB is high, thus the global bit line GBL is connected to wiring DXL. Signal S1 is low, thus the select transistor Tr1 is cut off from the node receiving ground voltage VSS. Signal S3 is high, thus switch SW3 is on.

[0142] Given that switch SW4 is off and switch SW5 is on, the potential VDXL of wiring DXL has a non-selection potential VUSEL. The non-selection potential VUSEL is the potential that the wiring has by receiving the non-selection voltage VUSEL; in one example, it has essentially the same magnitude as the non-selection voltage VUSEL. Furthermore, since signal SGB is high, the potential of select bit line BL (selection bit line potential) VBL has the same potential as potential VDXL, namely the non-selection potential VUSEL.

[0143] Given that switch SW7 is off and switch SW6 is on, wiring DYL receives the non-selection voltage VUSEL. Therefore, the potential of select word line WL (select word line potential) VWL has the non-selection potential VUSEL.

[0144] With switch SW3 turned on, wiring DXLR receives a pre-charge voltage VPC, which is the non-selection voltage VUSEL. Therefore, the potential VDXLR of wiring has a pre-charge potential VPC, i.e., the non-selection potential VUSEL. The pre-charge potential VPC is the potential that the wiring has by receiving the pre-charge voltage VPC; in one example, it has a potential substantially the same as the pre-charge voltage VPC.

[0145] The period from time t1 to time t8 is the period of the first sensing (step ST1).

[0146] At time t1, signal S4 is set to high and signal S5 is set to low. Therefore, switch SW4 is turned on and switch SW5 is turned off. Consequently, from time t1, potential VDXL and the select bit line potential VBL rise and become the precharge potential VPRCH. The precharge potential VPRCH is the potential that the wiring has by receiving the precharge voltage VPRCH, and in one example, it has substantially the same magnitude as the precharge voltage VPRCH.

[0147] At time t2, signal S4 is set to low. Consequently, switch SW4 is turned off, and wiring DXL, global select bit line GBL, and select bit line BL are electrically floating. After time t2, the potentials VDXL and VBL remain at the precharge potential VPRCH.

[0148] At time t2, signal SGB is set to low. As a result, switch GBSW is turned off, and global select bit line GBL and select bit line BL are disconnected from wiring DXL and become electrically floating.

[0149] At time t2, signal S3 is set to low. Therefore, SW3 is turned off, and pre-charging of the wiring DXLR stops.

[0150] At time t3, signal S6 is set to low and signal S7 is set to high. Consequently, switch SW6 is turned off and switch SW7 is turned on. Therefore, the select word line potential VWL drops towards the ground potential VSS. The ground potential VSS is the potential that the wiring has by receiving the ground voltage VSS, and in one example, it has essentially the same magnitude as the ground voltage VSS.

[0151] At time t4, the difference between the select word line potential VWL and the select bit line potential VBL reaches the threshold voltage Vth. Consequently, the switching element SE of the select memory cell MCsel turns on. Therefore, the select word line WL is connected to the select bit line BL via the turned-on switching element SE in the select memory cell MCsel. As a result, cell current flows from the select bit line BL towards the select word line WL.

[0152] Because the selection bit line BL is electrically floating, its potential VBL decreases due to the flowing cell current. At this time, the decrease in the selection bit line potential VBL is based on the resistance state of the MTJ element MTJ of the selection memory cell MCsel, and the rate of decrease varies. The selection bit line potential VBL decreases more slowly when the MTJ element MTJ of the selection memory cell MCsel is in a high-resistance state than when the MTJ element MTJ of the selection memory cell MCsel is in a low-resistance state.

[0153] At time t5, the select bit line potential VBL becomes the magnitude of the resistance state of the MTJ element MTJ based on the select memory cell MCsel. That is, as the select bit line potential VBL decreases, the difference between the select bit line potential VBL and the select word line potential VWL decreases. Therefore, when the terminal voltage of the select memory cell MCsel reaches a certain magnitude, the switching element SE of the select memory cell MCsel is turned off. As a result, the decrease in the select bit line potential VBL stops, leaving the select bit line potential VBL with a certain magnitude.

[0154] Through actions from time t3 to time t5, the selected bit line potential VBL, and subsequently the global bit line GBL, is made to have a potential based on the state of the selected memory cell MCsel.

[0155] At time t6, signal S1 is set to high. This turns on switch SW1, creating a current path between transistor Tr1 and the node receiving ground voltage VSS. At time t6, the global bit line GBL has a potential corresponding to the state of the selected memory cell MCsel, thus applying a voltage based on the state of the selected memory cell MCsel to the gate of transistor Tr1. Therefore, potential VDXLR becomes a potential based on the state of the selected memory cell MCsel. In this way, the cell current based on the magnitude of the state of the selected memory cell MCsel is converted into a potential (voltage).

[0156] At time t7, signal S1 is set to low. Consequently, switch SW1 is turned off, and transistor Tr1 is disconnected from the node receiving voltage VSS. At least from time t6 to time t7, switch SW11 of the sense amplifier circuit SAC is kept on and switch SW12 is kept off. Thus, potential VDXLR is stored at node SAMP.

[0157] At time t7, signal SGB is set to high. This turns on switch GBSW, selecting the global bit line GBL to connect with routing DXL.

[0158] The period from time t8 to time t10 is the period for writing the baseline data (step ST2).

[0159] At time t10, signals S4 and S7 are at a low level, while signals S3, S5, S6, and SGB are at a high level. Therefore, switches SW4 and SW7 are off, while switches SW3, SW5, SW6, and GBSW are on.

[0160] With switch SW4 off and switch SW5 on, potential VDXL has a non-selection potential VUSEL. Conversely, with switch GBSW on, the selection bit line potential VBL has the same potential as potential VDXL, i.e., the non-selection potential VUSEL.

[0161] Given that switch SW7 is off and switch SW6 is on, the select word line potential VWL has a non-select potential VUSEL.

[0162] Given that switch SW3 is turned on, potential VDXLR has a pre-charge potential VPC, which is the non-selection potential VUSEL.

[0163] The period from time t11 to time t17 is the period of the second sensing (step ST3). The changes in signal level and wiring potential at times t11, t12, t13, t14, t15, t16, and t17 are the same as the changes in signal level and wiring potential at times t1, t2, t3, t4, t5, t6, and t7, respectively.

[0164] At time t16, the global bit line GBL has a potential corresponding to the state of the selected memory cell MCsel. Therefore, a voltage based on the low resistance state of the MTJ element MTJ of the selected memory cell MCsel is applied to the gate of transistor Tr1. Consequently, a current based on the low resistance state of the MTJ element MTJ of the selected memory cell MCsel flows between transistor Tr1 and the node receiving the ground voltage VSS. In addition, the wiring DXLR receives a current based on the result of the first sensing via transistor TP1 of the sense amplifier circuit SAC. Therefore, from time t16, the potential VDXLR begins to change towards a magnitude determined by the result of the first sensing. When the result of the first sensing indicates that the MTJ element MTJ of the selected memory cell MCsel is in a high resistance state, the potential VDXLR rises to become potential VH. When the result of the first sensing indicates that the MTJ element MTJ of the selected memory cell MCsel is in a low resistance state, the potential VDXLR falls to become potential VL.

[0165] From at least time t16 to time t17, switch SW11 of the sense amplifier circuit SAC is kept off and switch SW12 is kept on. As a result, the potential VDXLR is stored at node EVAL.

[0166] Next, the sense amplifier circuit SAC outputs data OUT, which is determined by the potential of node SAMP and node EVAL, and is used to select the storage unit MCsel for storage.

[0167] 1.3. Advantages (Effects)

[0168] According to the first embodiment, as described below, a storage device that operates at high speed is provided.

[0169] As a reference storage device for comparison, consider a circuit where transistor Tr1 is connected to wiring DXL without wiring DXLR. In this case, parasitic capacitance generated by many switching circuits CC will be added to wiring DXL. Therefore, the charging and discharging of wiring DXL requires time.

[0170] Additionally, in the reference storage device, the potential is based on the state of the selected storage cell MCsel from... Figure 13 The reflection begins at time t3 and at a time equivalent to t3. The initial potential VDXL at the start of the reflection has the same potential as the selection bit line potential VBL, i.e., the precharge potential VPRCH. Therefore, in the second sensing, the potential VDXL drops from the precharge potential VPRCH to potential VH or potential VL based on the state of the selection memory cell MCsel. Because potential VL has a large difference from the precharge potential VPRCH, it takes time for potential VDXL to reach potential VL.

[0171] Thus, the charging and discharging of the wiring DXL and the time required until the potential VDXL settles are all taken, so data reading takes time.

[0172] According to the first embodiment, a conversion circuit CC and a wiring DXLR are provided for each global bit line GBL, and each transistor Tr1 is connected to the wiring DXLR instead of being connected to the wiring DXL. Therefore, the wiring DXL is not subject to the parasitic capacitance of the additional conversion circuit CC. Furthermore, according to the first embodiment, since the transistor Tr1 is connected to the wiring DXLR, the potential of the wiring DXLR does not need to be set to the precharge potential VPRCH as in the reference storage device, and can be set to any precharge potential VPC. Therefore, the potential VDXLR at which the potential based on the state of the selected storage cell MCsel begins to reflect to the potential VDXLR can be set to a potential close to the potential VH and / or the potential VL. This helps to shorten the time from the potential based on the state of the selected storage cell MCsel reflecting to the potential VDXLR until it is fully reflected to the potential VDXLR. Thus, the storage device 1 enables high-speed data readout.

[0173] Furthermore, according to the first embodiment, transistor Tr1 is not connected to wiring DXL. Therefore, the high voltage applied to wiring DXL during data writing is not applied to transistor Tr1. As a result, transistor Tr1 does not need to be a high-voltage transistor, current consumption is suppressed, and circuit design is simplified.

[0174] 2. Second Implementation Method

[0175] The second embodiment differs from the first embodiment in the number of groups of the conversion circuit CC, the precharge circuit PCDXLR, and the sense amplifier circuit SAC.

[0176] Figure 14 The diagram shows a portion of the components of the storage device according to the second embodiment and the connections between those components. Figure 14 Several global bit lines (GBLs) and their surrounding areas are shown.

[0177] like Figure 14 As shown, the storage device 1b of the second embodiment includes T switches SW21 (T is an integer of 2 or more). K is an integer of 1 or more and less than T. Each of the T global bit lines GBL is connected to the gate of a transistor Tr1 via one switch SW21. That is, the T global bit lines GBL are connected to a conversion circuit CC via the switch SW21. Thus, one conversion circuit CC and one wiring DXLR are shared by the T global bit lines GBL. Figure 14 One wiring DXLR_0 is shown as a representative.

[0178] Each switch SW21 is turned on or off based on signal S21. Different switches SW21 receive different signals S21. Therefore, each switch SW21 is turned on or off independently.

[0179] According to the second embodiment, the same advantages as the first embodiment can be obtained. Furthermore, according to the second embodiment, the conversion circuit CC and the wiring DXLR are shared by multiple global bit lines GBL. Therefore, it is unnecessary to provide the same number of conversion circuits CC and the same number of wiring DXLR as the global bit lines GBL. Thus, the same advantages as the first embodiment can be obtained with a simplified circuit.

[0180] Furthermore, according to the second embodiment, the number of switching circuits CC, and consequently the number of transistors Tr1, is less than that in the first embodiment. Therefore, the unavoidable deviation in the characteristics of transistors Tr1 is smaller than in the first embodiment. Consequently, it is easier to address deviations in the characteristics of transistors Tr1. That is, generally, to address deviations, a margin is needed to ensure operation matching the worst-performing transistor Tr1; in contrast, this margin can be reduced accordingly to accommodate smaller deviations.

[0181] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in a variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A storage device comprising: The first storage unit includes a first variable resistor element and a first switching element connected to the first variable resistor element; The first wiring is connected to the first storage unit; The first switch has a first terminal and a second terminal connected to the first wiring; The second wiring is connected to the second end; The first pre-charging circuit is connected to the second wiring; The first transistor has a third terminal and a fourth terminal connected to a first node receiving a first voltage, and a gate connected to the first wiring. The third wiring is connected to the fourth terminal of the first transistor; as well as The sensing amplifier circuit is connected to the third wiring.

2. The storage device according to claim 1, The fourth terminal of the first transistor is not connected to the second wiring.

3. The storage device according to claim 1, The storage device also includes: The second storage unit includes a second variable resistor element and a second switching element connected to the second variable resistor element; The fourth wiring is connected to the second storage unit; The second switch has a fifth terminal and a sixth terminal connected to the fourth wiring; The second transistor has a 7th terminal and an 8th terminal connected to the first node, and a gate connected to the 4th wiring. as well as The fifth wiring between the eighth terminal of the second transistor and the sense amplifier circuit.

4. The storage device according to claim 3, The fourth terminal of the first transistor is not connected to the second wiring. The eighth terminal of the second transistor is not connected to the second wiring.

5. The storage device according to claim 1, The storage device also includes a write circuit, which is connected to the second wiring.

6. The storage device according to claim 1, The second wiring is pre-charged by the first pre-charging circuit. Based on the potential of the third wiring, a signal based on the data stored in the first storage cell is output from the sensing amplifier circuit.

7. The storage device according to claim 1, The storage device also includes a second pre-charge circuit, which is connected to the third wiring.

8. The storage device according to claim 7, The storage device further includes a sixth wiring, which is connected to the end of the first storage cell opposite to the end connected to the first wiring. The third wiring is pre-charged by the second pre-charging circuit. During the first period, the first switch remains on. During the first period, the second wiring receives the second voltage through the first pre-charge circuit. After the second wiring receives the second voltage, during the second period, the first memory cell is disconnected from the second wiring. During the second period, the sixth wiring receives a third voltage that is lower than the second voltage.

9. The storage device according to claim 8, Following the second period, the third wiring is pre-charged via the second pre-charge circuit. After the third wiring was pre-charged following the second period, During the third period, the first switch remains on. During the third period, the second wiring receives the second voltage through the first pre-charge circuit. After the second wiring receives the second voltage, during the fourth period, the first memory cell is disconnected from the second wiring. During the fourth period, the sixth wiring receives the third voltage. Data based on the potential of the third wiring in the second period and the potential of the third wiring in the fourth period are output from the sensing amplifier circuit.

10. The storage device according to claim 9, The sensing amplifier circuit includes: The seventh wiring is connected to the third wiring via the third switch and has capacitance; The eighth wiring, connected to the third wiring via the fourth switch, and having a capacitor; and An operational amplifier having an inverting input terminal connected to the 7th wiring and a non-inverting input terminal connected to the 8th wiring.

11. The storage device according to claim 10, The potential of the third wiring during the second period is preserved in the seventh wiring. The potential of the third wiring in the fourth period is preserved in the eighth wiring.

12. The storage device according to claim 11, The storage device also includes a third transistor connected between a node receiving a fourth voltage higher than the third voltage and the third wiring, and having a gate connected to the seventh wiring.

13. The storage device according to claim 1, The storage device also includes: The fifth switch between the first wiring and the gate of the first transistor; The 9th wiring; and The sixth switch between the ninth wiring and the gate of the first transistor.

14. The storage device according to claim 13, The storage device also includes: The third storage cell includes a second variable resistor element and a second switching element connected to the second variable resistor element, and is connected to the ninth wiring; and The 7th switch is located between the 5th terminal connected to the 9th wiring and the 2nd wiring.

15. The storage device according to claim 13, The fourth terminal of the first transistor is not connected to the second wiring.

16. The storage device according to claim 13, The storage device also includes a second pre-charge circuit, which is connected to the third wiring.

17. The storage device according to claim 1, The first variable resistor element includes a magnetoresistive element.

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