Dual-mode multiplex self-termination memory access circuit and working method thereof

Abstract

This invention discloses a dual-mode multiplexed self-terminating memory access circuit and its operating method, belonging to the field of integrated circuits. The circuit includes a sensing circuit module, a trigger and lock logic circuit module, and a write driver circuit module. In write memory mode, the sensing circuit module uses a self-biased stacked inverter and coupling capacitor to capture the bit line voltage jump caused by the resistance state reversal of the magnetic tunnel junction; the trigger and lock logic circuit module shapes and locks the jump signal, dynamically outputting a write termination signal; the write driver circuit module responds to this signal by immediately cutting off the high-voltage power supply to the bit line and simultaneously starting pull-down discharge, achieving sub-nanosecond self-termination and effectively avoiding magnetic moment precession flip-back errors. In read mode, the circuit is multiplexed as a high-precision sensitive amplifier. This invention reduces the area overhead and power consumption of the external circuitry through dual-mode hardware multiplexing.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a dual-mode multiplexed self-terminating memory access circuit and its operating method. Background Technology

[0002] With the continuous evolution of integrated circuit manufacturing processes and the rapid development of information technology, higher demands are being placed on storage systems in application scenarios such as cloud computing, big data processing, and artificial intelligence, in terms of speed, power consumption, reliability, and non-volatility. Under one possible application scenario, traditional storage technologies, represented by Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM), are gradually revealing their respective technical bottlenecks. For example, in some implementations, while SRAM has the advantages of fast read / write speeds and low latency, its large cell area and high leakage power consumption are not conducive to high-density integration; DRAM requires periodic refreshing, cannot retain data under power-off conditions, and has high system power consumption.

[0003] Against this backdrop, Magnetic Random Access Memory (MRAM), as a novel non-volatile memory technology, has attracted widespread attention in one possible design due to its advantages of high speed, low power consumption, non-volatility, and good CMOS process compatibility. The basic storage unit of MRAM is a magnetic tunnel junction, which typically includes a free magnetic layer, a fixed magnetic layer, and a tunneling insulating layer between them. By changing the relative magnetization directions of the free and fixed magnetic layers, the magnetic tunnel junction can exhibit different resistance states, thereby enabling the storage of binary information. In one feasible implementation, high-resistance and low-resistance states are used to represent different logic states. Since the magnetization state of the magnetic tunnel junction can be maintained after power is turned off, MRAM inherently possesses non-volatility characteristics and shows promising application prospects in embedded storage and high-performance cache applications.

[0004] In the existing MRAM technology system, Spin-Transfer Torque MRAM (STT-MRAM) is a relatively mature implementation. However, under a possible process evolution path, as the process node continues to shrink, STT-MRAM gradually reveals problems during the storage process, such as high write current requirements, high power consumption, and sensitivity of write reliability to process and temperature fluctuations. To overcome these shortcomings, in some embodiments, researchers have proposed an MRAM write mechanism based on voltage-controlled magnetic anisotropy effects: by applying a voltage across the magnetic tunnel junction to change the magnetic anisotropy energy barrier at the free magnetic layer interface, the critical current required for magnetization reversal is reduced to a certain extent.

[0005] Under one possible physical mechanism, VCMA writing primarily relies on the precession and flipping of the magnetic moment under the influence of an effective magnetic field, and its flipping behavior exhibits a distinct periodic characteristic. When the duration of the applied voltage pulse matches the half-cycle of the magnetic moment precession, the magnetization direction can achieve the desired flip; however, when the pulse duration deviates from this window, the magnetic moment may continue to precess and return to its initial state, resulting in a flip-back error. Therefore, under feasible design requirements, it is necessary to introduce a self-terminating memory access circuit that can dynamically terminate the memory access process based on changes in the state of the magnetic tunnel junction.

[0006] To address this, researchers have proposed a feedback-based self-termination technique for memory access in some embodiments. The core idea is to monitor the state changes of the magnetic tunnel junction in real time during the write process and terminate the write stimulus promptly upon detecting a flip-over, thereby avoiding redundant energy consumption and precession-to-flip errors. However, existing self-termination schemes are mostly designed for bidirectional high-current memory access modes in STT (Short-Terminal Memory) scenarios, and their driving and sensing structures typically rely on bipolar signal interaction. In VCMA (Voltage-Cooled Memory) scenarios, data writing exhibits unipolar voltage triggering characteristics based on the electric field effect. Traditional driving circuits struggle to meet the speed requirements of basic write logic, high-sensitivity state capture, and sub-nanosecond voltage instantaneous cutoff.

[0007] Existing circuit implementations face several technical bottlenecks. First, traditional sensing structures suffer from insufficient gain and extremely slow response to low-level disturbances, failing to meet the sub-nanosecond feedback loop requirements of VCMA. Second, in 28nm and more advanced processes, the offset voltage generated by transistor threshold voltage mismatch often completely masks the true sensing signal, leading to false triggering of the self-termination circuit. Third, thermal noise interference during VCMA switching easily causes logic jitter in the sensing output; if the feedback link lacks effective logic locking and shaping, write failures will occur. Finally, introducing additional memory access termination circuits into the memory peripheral circuitry increases the number of transistors, resulting in redundant peripheral circuit area.

[0008] Against this technical backdrop, a possible design proposes a dual-mode multiplexed self-terminating memory access circuit that hardware-multiplexes the memory access self-termination function and the read sensitivity amplification function. In write mode, this circuit monitors voltage changes caused by magnetic tunnel junction flipping and dynamically terminates the write process. In read mode, it acts as a sensitive amplifier to amplify the voltage difference between the bit line and the source line, thereby improving the overall system efficiency and reliability without significantly increasing the peripheral circuit area. Summary of the Invention

[0009] Technical Problem: The purpose of this invention is to provide a dual-mode multiplexed self-terminating memory access circuit to solve existing problems including at least the following: precession flip-back error caused by magnetic moment precession during VCMA-MRAM writing, the traditional read-before-write operation process not conforming to VCMA characteristics, the impact of transistor offset on sensing accuracy under advanced process conditions, and the problem of large peripheral circuit area overhead.

[0010] Technical solution: In one specific embodiment, the present invention provides a dual-mode multiplexed self-terminating memory access circuit, comprising: a sensing circuit module for sensitively amplifying weak voltage jumps on bit lines or source lines; a trigger and lock logic circuit module for shaping, saving and outputting voltage difference changes after detection; and a write drive circuit module for instantaneously cutting off the write drive voltage after receiving a write termination signal.

[0011] The sensing circuit module includes a coupling capacitor and a stacked sensing core based on an inverter; one end of the coupling capacitor is coupled to the bit line of the memory array, and the circuit is configured to first connect the one end of the coupling capacitor to a reference voltage and then switch to connect it to the bit line to be read in read mode, and the other end is connected to the input terminal IN1 of the stacked sensing core; the stacked sensing core is used to amplify the signal at the input terminal IN1 into a full-amplitude voltage swing signal at the output terminal OUT1.

[0012] The trigger and lock logic circuit module includes a Schmitt trigger and an SR latch; the input of the Schmitt trigger is connected to the output OUT1, and its output generates a trigger signal OUT2; the set terminal of the SR latch receives the trigger signal OUT2, the reset terminal receives the write start signal WS, and the output terminal is used to output the write stop signal WD and the read data Qread.

[0013] The write driver circuit module has a control terminal that receives the write termination signal WD and an output terminal that is connected to the bit line. The write driver circuit module includes a combinational logic unit and a level conversion unit, and is configured to perform a dual shutdown after receiving the write termination signal: on the one hand, it cuts off the high-voltage path for writing to the bit line, and on the other hand, it simultaneously turns on the bit line pull-down discharge switch.

[0014] The circuit has dual-mode operation characteristics:

[0015] In write memory mode, the write drive circuit module applies a write voltage to the bit line; the sensing circuit module captures the bit line voltage jump caused by the magnetic tunnel junction resistance state flip through the coupling capacitor, and after being amplified by the stacked sensing core, the trigger and lock logic circuit module generates a write termination signal WD; the write drive circuit module responds to WD by performing a double shutdown, causing the bit line to discharge rapidly to ground potential, thereby avoiding magnetic moment precession flip-back error.

[0016] In read mode, the write drive circuit module remains inactive; first, one end of the coupling capacitor is connected to a reference voltage to establish a reference level, and then the connection to the bit line to be read is switched to form a differential signal; after being amplified by the coupling capacitor, the stacked sensing core and the Schmitt trigger, the differential signal is locked by the SR latch and output as the read data Qread.

[0017] In one possible design, the sensing circuit module further includes: an offset cancellation switch SW1, with its two ends connected between the input terminal IN1 and the output terminal OUT1, for closing during the offset cancellation phase to compensate for the offset voltage; a switch SW2, connected between the output terminal OUT1 and the input terminal of the Schmitt trigger, for closing during the write monitoring phase and the read sensing phase; a switch SW3, connected between the output terminal of the Schmitt trigger and the set terminal of the SR latch, for closing during the write monitoring phase and the read sensing phase; and a switch SW4, with one end connected to an internal node of the Schmitt trigger and the other end connected to a preset level, for closing during the offset cancellation phase to preset the Schmitt trigger to a critical state.

[0018] In one possible design, the inverter-based stacked sensing core consists of four MOS transistors, including PMOS transistors P1 and P2 and NMOS transistors N1 and N2, connected as follows: P1's gate is connected to IN1, its source is connected to the drain of P2, and its drain is connected to OUT1; P2's gate is connected to the inverting sensing enable signal BSEN, and its source is connected to VDD; N1's gate is connected to IN1, its source is connected to the drain of N2, and its drain is connected to OUT1; N2's gate is connected to the non-inverting sensing enable signal SEN, and its source is grounded.

[0019] In one possible design, the Schmitt trigger introduces hysteresis characteristics through positive feedback; the reset terminal of the SR latch receives a write start signal WS, and the set terminal receives a trigger signal OUT2 through the switch SW3.

[0020] In one possible design, the combinational logic unit of the write drive circuit module includes a first NAND gate, an XNOR gate, a NOR gate, and a second NAND gate; the input of the first NAND gate is connected to a write enable signal and a bit select enable signal; the input of the XNOR gate is connected to a write data signal and a read-out data signal; the output of the first NAND gate and the output of the XNOR gate are respectively connected to the two inputs of the NOR gate; the output of the NOR gate and the inverted signal of the write termination signal are connected to the two inputs of the second NAND gate; the level conversion unit includes a level converter, the input of which is connected to the output of the second NAND gate, for converting the logic voltage into a high-voltage drive signal to drive the bit line pull-down path; the bit line pull-down path is provided with a pull-down discharge tube controlled by the write termination signal.

[0021] Based on the above circuit, the present invention also provides a method for operating a dual-mode multiplexed self-terminating memory access circuit, including a write operation method and a read operation method.

[0022] Write operation methods include:

[0023] Offset cancellation phase: Close SW1 and SW4, open SW2 and SW3, so that the stacked sensing core is biased to the logic threshold and the Schmitt trigger is preset.

[0024] Write monitoring phase: Disconnect SW1 and SW4, close SW2 and SW3, the write start signal WS becomes valid, enabling the write drive circuit to apply the write voltage to the bit line; when the magnetic tunnel junction flips and causes the bit line voltage to jump, the jump is amplified by the coupling capacitor and the stacked sensing core, and then OUT2 is generated by the Schmitt trigger through SW2. OUT2 is then sent to the SR latch through SW3, so that the SR latch outputs a valid write stop signal WD.

[0025] Instantaneous termination phase: In response to WD, the write drive circuit cuts off the high voltage of the bit line and simultaneously turns on the pull-down discharge tube.

[0026] Read operation methods include:

[0027] Read offset cancellation phase: Close SW1 and SW4, open SW2 and SW3, and the write drive circuit remains invalid;

[0028] Reading sensing stage: Disconnect SW1 and SW4, and close SW2 and SW3; first connect one end of the coupling capacitor to the reference voltage, and then switch to connect the bit line to be read to form a differential signal; the differential signal is sent to the SR latch through the coupling capacitor, the stacked sensing core, SW2, the Schmitt trigger, and SW3; the SR latch locks and outputs the read data Qread.

[0029] Beneficial effects: The present invention, by adopting the above technical solution, has the following beneficial effects:

[0030] (1) This invention is a write self-termination and sensing dual-mode circuit for VCMA-MRAM. By utilizing a stacked sensing core based on inverters, an offset cancellation switch, a coupling capacitor, a Schmitt trigger, and an SR latch with reset priority logic, the precession-back error of the VCMA magnetic moment during the write process can be effectively solved. Through a sub-nanosecond asynchronous feedback loop, the circuit can accurately shut off the write pulse at the instant the magnetic moment flip is completed, significantly widening the write window and greatly improving the reliability of the write operation.

[0031] (2) In response to the physical challenges of write operations being almost entirely independent of charge transport and resistance state transitions being difficult to detect in VCMA unipolar voltage write mode, this invention innovatively designs a high-gain dynamic sensing link for a unipolar write architecture. During the write monitoring phase, this structure can convert the weak resistance change of the magnetic tunnel junction into a significant bit line voltage transition ΔV under unipolar voltage bias. Combined with self-reference offset cancellation technology, this invention can effectively eliminate the offset effect caused by transistor threshold voltage mismatch in 28nm and more advanced processes, ensuring sensing accuracy and speed.

[0032] (3) The present invention adopts a dual-mode hardware multiplexing design, which deeply integrates the sensitive amplifier function required for the read operation and the self-termination function required for the write operation on the same sensing link. Through the coordinated control of SW1, SW2, SW3 and SW4, the circuit can share the sensing core and offset cancellation network in different modes. Compared with the traditional scheme of designing the sensitive amplifier (SA) and write termination (WT) separately, the present invention can significantly reduce the number of transistors in the peripheral circuit of the memory, effectively reduce chip area overhead and reduce static leakage power consumption. Attached Figure Description

[0033] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be simplified. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 The background section provides a structural block diagram of VCMA-MRAM in the prior art;

[0035] Figure 2 This is a schematic diagram of the magnetic tunnel junction and storage bits in the dual-mode multiplexed self-terminating memory access circuit proposed in an embodiment of the present invention;

[0036] Figure 3 This is a schematic diagram of the VCMA effect of the dual-mode multiplexed self-terminating memory access circuit proposed in the embodiments of the present invention;

[0037] Figure 4 This is a schematic diagram showing the change of the switching delay of the magnetic tunnel junction with the pulse width when the VCMA effect occurs in the dual-mode multiplexed self-terminating memory access circuit proposed in this embodiment of the invention.

[0038] Figure 5 This is a timing diagram of the magnetization vector reversal in the dual-mode multiplexed self-terminating memory access circuit proposed in this embodiment of the invention.

[0039] Figure 6 This is a schematic diagram of the dual-mode multiplexing self-terminating memory access circuit proposed in an embodiment of the present invention;

[0040] Figure 7 This is a timing diagram of the write memory cycle when writing "1", reading "1" and writing "0" in the dual-mode multiplexed self-terminating memory access circuit proposed in this embodiment of the invention. Detailed Implementation

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0042] Figure 1 This is a system architecture block diagram of a voltage-controlled magnetic anisotropic magnetic random access memory (VCMA-MRAM) in the prior art, including a memory array, decoding and word line driver, global reference module, column selector, dual-mode write self-termination / sensitive amplifier, write driver, and input / output module. In the prior art, the write pulse width is fixed, which is difficult to adapt to the changes in flip-flop time caused by process, voltage, and temperature fluctuations, and the independent design of read and write circuits results in a large area overhead.

[0043] VCMA-MRAM, as an ultra-low-power memory technology, alters the magnetic anisotropy of the magnetic tunnel junction using an electric field (voltage) rather than current. Compared to traditional STT, VCMA offers higher energy efficiency. However, VCMA exhibits precession during switching, meaning the width of the write pulse must precisely match half a precession cycle of the magnetic tunnel junction. A pulse that is too short will cause switching failure, while a pulse that is too long may cause the magnetic tunnel junction to flip back to its initial state. To address these issues, this invention designs a self-termination circuit that generates a self-termination signal by real-time monitoring of the bit line voltage transition caused by the magnetic tunnel junction resistance switching, immediately cutting off the write drive. This provides physical-level precision timing protection for VCMA and also incorporates sensitive amplification functionality in read mode.

[0044] Figure 2This is a schematic diagram of the magnetic tunnel junction and storage bit structure in the dual-mode multiplexed self-terminating memory access circuit proposed in an embodiment of the present invention. In a feasible implementation method, the storage bit is a 1T1MTJ structure, which is mainly composed of a magnetic tunnel junction and a gate transistor connected in series. The magnetic tunnel junction includes, from top to bottom, a free layer, an insulating tunneling layer (located between the free layer and the pinning layer), and a pinning layer. By changing the relative orientation of the magnetic moment of the free layer with respect to the magnetic moment of the pinning layer, the magnetic tunnel junction switches between an anti-parallel state (AP state) and a parallel state (P state), corresponding to a high-resistance state and a low-resistance state, respectively, to achieve non-volatile binary data storage.

[0045] In one feasible implementation, one end electrode of the magnetic tunnel junction is connected to the bit line, and the other end electrode is connected to the drain of the selector. The gate of the selector is controlled by the word line (WL) signal, and its source is connected to the source line. Thus, in the word line selected state, a voltage excitation is applied to the magnetic tunnel junction through the potential difference between the bit line and the source line, thereby using VCMA to change the energy barrier of the free layer and drive the magnetization vector to precess and flip.

[0046] Figure 3 The physical flipping mechanism of the magnetic tunnel junction proposed in this embodiment of the invention is mainly manifested as: dynamic control of the magnetic anisotropy of the interface based on the electric field.

[0047] It should be noted that, in the initial state without bias voltage, the magnetic tunnel junction has a high vertical magnetic anisotropy energy barrier, represented by solid lines, which stably locks the magnetic moment vector mz in an antiparallel state (0° phase) or a parallel state (180° phase) along the vertical axis (z-axis). As the bias voltage V is applied and gradually increases to the critical value Vb or above, the interface electric field effect causes the PMA energy barrier to decrease significantly, flatten, or even reverse, causing the magnetic moment vector to lose its vertical axis constraint and leave the equilibrium position. Subsequently, the magnetic moment vector enters the coherent precession stage, rotating around the easy-or-difficult axis under the drive of the effective field. Its evolution trajectory passes through the critical position of 90° in the plane, and the tunneling resistance changes with the deflection angle of the magnetic moment vector. When it flips to the target phase and the external electric field is removed, the PMA energy barrier recovers rapidly, relocking the magnetic moment vector in a new stable polarity state. Figure 4This is a schematic diagram illustrating the variation of the switching delay of the magnetic tunnel junction with pulse width under the VCMA effect in the dual-mode multiplexed self-terminating memory access circuit proposed in this invention embodiment. The main characteristics are: the switching behavior of the magnetic moment component exhibits high voltage sensitivity and a specific pulse width window characteristic. The switching delay of the magnetic tunnel junction shows a non-linear relationship with the write pulse width: there exists a pulse width range (approximately 0.2 ns to 0.75 ns), within which the switching time first decreases and then increases with increasing pulse width, reaching an extreme point in switching speed at approximately 0.5 ns; when the pulse width is too narrow (<0.2 ns) or too wide (>0.75 ns), the magnetic moment is in a region where it cannot switch due to insufficient or excessive precession phase.

[0048] Figure 5 This is a timing diagram of the magnetization vector reversal in the dual-mode multiplexed self-terminating memory access circuit proposed in this embodiment of the invention. The main features are as follows: In the initial state without bias voltage, the magnetic moment vector of the magnetic tunnel junction is stable at -1; when a positive bias voltage of 1.2V and a width of 0.6ns is applied across the magnetic tunnel junction, the magnetic moment vector precesses. By controlling the pulse width of the bias voltage, the magnetic moment vector is controlled so that it eventually stops at +1, completing the change in the state of the magnetic tunnel junction; the same positive bias voltage is applied again across the magnetic tunnel junction, causing it to eventually stop at -1.

[0049] Figure 6 The specific circuit connection of the dual-mode multiplexing self-terminating memory access circuit described in this invention is shown in one embodiment of the self-terminating memory access circuit in this application, which includes: a sensing circuit module, a trigger logic circuit, a locking logic circuit, and a write driver circuit.

[0050] Specifically: the sensing circuit module includes a coupling capacitor and a stacked sensing core based on an inverter; one end of the coupling capacitor is coupled to the bit line of the memory array, and the circuit is configured to first connect the one end of the coupling capacitor to a reference voltage and then switch to connect it to the bit line to be read in read mode, and the other end is connected to the input terminal IN1 of the stacked sensing core; the stacked sensing core is used to amplify the signal at the input terminal IN1 into a full-amplitude voltage swing signal at the output terminal OUT1.

[0051] The trigger and lock logic circuit module includes a Schmitt trigger and an SR latch; the input of the Schmitt trigger is connected to the output OUT1, and its output generates a trigger signal OUT2; the set terminal of the SR latch receives the trigger signal OUT2, the reset terminal receives the write start signal WS, and the output terminal is used to output the write stop signal WD and the read data Qread.

[0052] The write driver circuit module has a control terminal that receives the write termination signal WD and an output terminal that is connected to the bit line. The write driver circuit module includes a combinational logic unit and a level conversion unit, and is configured to perform a dual shutdown after receiving the write termination signal: on the one hand, it cuts off the high-voltage path for writing to the bit line, and on the other hand, it simultaneously turns on the bit line pull-down discharge switch.

[0053] The circuit has dual-mode operation characteristics:

[0054] In write memory mode, the write drive circuit module applies a write voltage to the bit line; the sensing circuit module captures the bit line voltage jump caused by the magnetic tunnel junction resistance state flip through the coupling capacitor, and after being amplified by the stacked sensing core, the trigger and lock logic circuit module generates a write termination signal WD; the write drive circuit module responds to WD by performing a double shutdown, causing the bit line to discharge rapidly to ground potential, thereby avoiding magnetic moment precession flip-back error.

[0055] In read mode, the write drive circuit module remains inactive; first, one end of the coupling capacitor is connected to a reference voltage to establish a reference level, and then the connection to the bit line to be read is switched to form a differential signal; after being amplified by the coupling capacitor, the stacked sensing core and the Schmitt trigger, the differential signal is locked by the SR latch and output as the read data Qread.

[0056] In one feasible implementation, the sensing circuit module further includes: an offset cancellation switch SW1, with its two ends connected between the input terminal IN1 and the output terminal OUT1, for closing during the offset cancellation phase to compensate for the offset voltage; a switch SW2, connected between the output terminal OUT1 and the input terminal of the Schmitt trigger, for closing during the write monitoring phase and the read sensing phase; a switch SW3, connected between the output terminal of the Schmitt trigger and the set terminal of the SR latch, for closing during the write monitoring phase and the read sensing phase; and a switch SW4, with one end connected to the internal node of the Schmitt trigger and the other end connected to a preset level, for closing during the offset cancellation phase to preset the Schmitt trigger to a critical state.

[0057] In one feasible implementation, the inverter-based stacked sensing core consists of four MOS transistors, including PMOS transistors P1 and P2 and NMOS transistors N1 and N2, connected as follows: P1's gate is connected to IN1, its source is connected to the drain of P2, and its drain is connected to OUT1; P2's gate is connected to the inverting sensing enable signal BSEN, and its source is connected to VDD; N1's gate is connected to IN1, its source is connected to the drain of N2, and its drain is connected to OUT1; N2's gate is connected to the non-inverting sensing enable signal SEN, and its source is grounded.

[0058] In one feasible implementation, the Schmitt trigger introduces hysteresis characteristics through positive feedback; the reset terminal of the SR latch receives a write start signal WS, and the set terminal receives a trigger signal OUT2 through the switch SW3.

[0059] In one feasible implementation, the combinational logic unit of the write drive circuit module includes a first NAND gate, an XNOR gate, a NOR gate, and a second NAND gate; the input of the first NAND gate is connected to a write enable signal and a bit select enable signal; the input of the XNOR gate is connected to a write data signal and a read-out data signal; the output of the first NAND gate and the output of the XNOR gate are respectively connected to the two inputs of the NOR gate; the output of the NOR gate and the inverted signal of the write termination signal are connected to the two inputs of the second NAND gate; the level conversion unit includes a level converter, the input of which is connected to the output of the second NAND gate, for converting the logic voltage into a high-voltage drive signal to drive the bit line pull-down path; the bit line pull-down path is provided with a pull-down discharge tube controlled by the write termination signal.

[0060] Based on the above circuit, the present invention also provides a method for operating a dual-mode multiplexed self-terminating memory access circuit, including a write operation method and a read operation method.

[0061] The circuit's workflow during writing consists of three parts: offset cancellation phase, write monitoring phase, and instantaneous termination phase.

[0062] The write operation methods specifically include:

[0063] Offset cancellation stage: SW1 and SW4 are closed, and SW2 and SW3 are opened, causing the stacked sensing core to self-bias to the logic threshold and the Schmitt trigger to be preset. In this implementation, the write start signal WS is in a disabled state, the offset cancellation switch SW1 is closed, shorting the output terminal OUT1 of the stacked inverter to the sensing input terminal IN1, allowing the circuit to automatically stabilize at its logic threshold level. At this time, the sensing circuit operates in the linear amplification region with the maximum transconductance. One end of the coupling capacitor latches the threshold voltage at this time, compensating for the threshold drift caused by process corner deviation. Simultaneously, the internal switch SW4 is closed, pulling the internal node of the Schmitt trigger to the preset level, putting it in a "ready to fire" state.

[0064] Write monitoring phase: SW1 and SW4 are disconnected, SW2 and SW3 are closed, the write start signal WS becomes valid, resetting the SR latch. The write drive circuit is enabled to apply a write voltage to the bit line. In this implementation, switch SW1 is open, and SW2 and SW3 are closed, establishing a complete path between the sensing circuit and the trigger circuit. Simultaneously, the write drive circuit is turned on, applying a unipolar write voltage to the bit line through the high-voltage path to establish a strong electric field across the magnetic tunnel junction and drive the free layer magnetization precession. Under this unipolar high-voltage bias, the on-resistance of the write drive transistor and the extremely high barrier resistance of the magnetic tunnel junction naturally form a dynamic impedance network; when the magnetic tunnel junction crosses the critical point and undergoes a magnetization reversal (e.g., from a high-resistance state to a low-resistance state), the sudden change in its resistance is directly reflected as a weak but instantaneous voltage jump on the bit line. This voltage jump is conducted to the IN1 node in real time through the coupling capacitor and amplified by the stacked inverter into a sharp voltage jump at the OUT1 node. Subsequently, the OUT1 signal is input to the Schmitt trigger with hysteresis characteristics via SW2. When the amplified signal strength exceeds the Schmitt trigger's turn-on threshold, the trigger's output signal OUT2 quickly flips to a high level, serving as a "flip complete" signal that is connected to the SR latch via SW3. Upon receiving the OUT2 signal, the SR latch immediately changes its output state, generating a valid (e.g., high level) write termination signal WD, thereby triggering the external write drive circuit to enter the instantaneous termination phase of rapid discharge.

[0065] Instantaneous Termination Phase: In response to WD, the write drive circuit cuts off the high voltage on the bit line and simultaneously turns on the pull-down discharge transistor. At the instant the write termination signal goes high, the drive circuit immediately cuts off the electric field acting on the magnetic tunnel junction and simultaneously turns on the bit line pull-down discharge switch for rapid discharge.

[0066] The read workflow includes: read offset cancellation stage and read sensing stage.

[0067] The specific read operation methods include:

[0068] Read offset cancellation stage: SW1 and SW4 are closed, SW2 and SW3 are opened, and the write drive circuit remains invalid. In this implementation, the circuit operation is basically the same as the offset cancellation stage before writing. When switch SW1 is closed, the stacked inverter is in a self-biased state, and the sensing node IN1 is pre-charged to the logic threshold. At this time, the Schmitt trigger completes the internal node pre-setting through SW4, ensuring that the circuit is at the critical point most sensitive to input disturbances.

[0069] Read sensing phase: Disconnect SW1 and SW4, and close SW2 and SW3; first connect one end of the coupling capacitor to the reference voltage (provided by the global reference cell), then switch to the bit line to be read, forming a differential signal. In this implementation, the write enable signal is kept at an invalid level to cut off the high-voltage write path and avoid voltage-type read interference to the magnetic tunnel junction. During signal extraction, the input side of the coupling capacitor is first connected to the global reference cell to establish a reference voltage; then, it is switched to the bit line to be read, so that a differential signal is formed between the bit line sensing voltage and the reference voltage. The polarity of this differential signal represents the current resistance state of the magnetic tunnel junction. The differential signal is AC coupled to the input node IN1 via the coupling capacitor. Since the input node has been pre-charged to the logic threshold voltage, the weak differential signal is amplified by the stacked inverter structure at high gain, forming a full-amplitude voltage swing at the output node OUT1. Subsequently, the full-amplitude signal is sent to the SR latch via SW2, Schmitt trigger, and SW3. Since the write termination feedback is not activated in read mode, the SR latch is configured as a data holding unit to lock and output the read data Qread.

[0070] Appendix Figure 7 This paper presents the write memory timing cycle diagrams of the dual-mode multiplexed self-terminating memory access circuit proposed in this embodiment of the invention during writing "1", reading "1", and writing "0" under simulation based on the TSMC-28nm process node. The simulation results show that the dual-mode multiplexed self-terminating memory access circuit proposed in this embodiment of the invention can precisely cut off the power supply at the instant the magnetic tunnel junction flips. By setting a 2.0ns offset cancellation (OC) stage, this invention achieves a write termination time of 0.42ns within a write access cycle of VDD = 1.2V and T = 20ns. Compared to the traditional fixed write pulse width (0.6ns), this technology can save approximately 30% of power consumption during the write process, which fully verifies the technical advantages of this circuit in sub-nanosecond feedback control and system-level energy efficiency optimization.

[0071] In the embodiments of the present invention, by coordinating the timing of the levels of multiple control signals, the memory access self-termination after the state flip of the memory cell is realized; this architecture not only significantly reduces the power consumption waste caused by invalid bias, but also effectively avoids the additional hardware cost caused by traditional complex self-termination structures, and significantly optimizes the area efficiency of the circuit.

[0072] The parts of this invention not disclosed in detail are well-known technologies in the field.

[0073] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A dual-mode multiplexed self-terminating memory access circuit, comprising: The circuit includes: a sensing circuit module, a trigger and lock logic circuit module, and a write drive circuit module; The sensing circuit module includes a coupling capacitor and a stacked sensing core based on an inverter; one end of the coupling capacitor is coupled to the bit line of the memory array, and the circuit is configured to first connect the one end of the coupling capacitor to a reference voltage and then switch to connect it to the bit line to be read in read mode, and the other end is connected to the input terminal IN1 of the stacked sensing core; the stacked sensing core is used to amplify the signal at the input terminal IN1 into a full-amplitude voltage swing signal at the output terminal OUT1; The trigger and lock logic circuit module includes a Schmitt trigger and an SR latch; the input of the Schmitt trigger is connected to the output OUT1, and its output generates a trigger signal OUT2; the set terminal of the SR latch receives the trigger signal OUT2, the reset terminal receives the write start signal WS, and the output terminal is used to output the write stop signal WD and the read data Qread. The write driver circuit module has a control terminal that receives the write termination signal WD and an output terminal that is connected to the bit line. The write driver circuit module includes a combinational logic unit and a level conversion unit, and is configured to perform a dual shutdown after receiving the write termination signal: on the one hand, it cuts off the write high voltage path provided to the bit line, and on the other hand, it simultaneously turns on the bit line pull-down discharge switch. The circuit has dual-mode operation characteristics: in write storage mode, the sensing circuit module captures the bit line voltage jump and generates a write termination signal WD. The write drive circuit module responds to WD, cuts off the high voltage, and simultaneously starts pull-down discharge. In read mode, the write drive circuit module remains inactive. One end of the coupling capacitor is first connected to the reference voltage and then switched to the bit line to be read to form a differential signal. After amplification, the SR latch outputs the read data Qread.

2. The circuit according to claim 1, characterized in that, The sensing circuit module further includes: Offset cancellation switch SW1 is connected at both ends between the input terminal IN1 and the output terminal OUT1, and is used to close during the offset cancellation phase to compensate for the offset voltage. Switch SW2 is connected between the output terminal OUT1 and the input terminal of the Schmitt trigger, and is used to close during the write monitoring phase and the read sensing phase. Switch SW3 is connected between the output of the Schmitt trigger and the set terminal of the SR latch, and is used to close during the write monitoring phase and the read sensing phase. Switch SW4 is connected at one end to the internal node of the Schmitt trigger and at the other end to a preset level. It is used to close during the offset cancellation phase to preset the Schmitt trigger to a critical state.

3. The circuit according to claim 1, characterized in that, The inverter-based stacked sensing core consists of four MOS transistors, including PMOS transistors P1 and P2 and NMOS transistors N1 and N2, connected as follows: P1 gate is connected to IN1, source is connected to P2 drain, drain is connected to OUT1; P2 gate is connected to the inverting sensing enable signal BSEN, source is connected to VDD. N1's gate is connected to IN1, its source is connected to N2's drain, and its drain is connected to OUT1; N2's gate is connected to the positive inverting sensing enable signal SEN, and its source is grounded.

4. The circuit according to claim 2, characterized in that, In the trigger and lock logic circuit module: the Schmitt trigger introduces hysteresis characteristics through positive feedback; the reset terminal of the SR latch receives the write start signal WS, the set terminal receives the trigger signal OUT2 through the switch SW3, and the output terminal outputs the write stop signal WD and the read data Qread.

5. The circuit according to claim 1, characterized in that, The write driver circuit module includes a combinational logic unit and a level conversion unit; The combinational logic unit includes a first NAND gate, an XNOR gate, a NOR gate, and a second NAND gate; the input of the first NAND gate is connected to a write enable signal and a bit select enable signal; the input of the XNOR gate is connected to a write data signal and a read-out data signal; the output of the first NAND gate and the output of the XNOR gate are respectively connected to the two inputs of the NOR gate; the output of the NOR gate and the inverted signal of the write termination signal are connected to the two inputs of the second NAND gate. The level conversion unit includes a level converter, whose input is connected to the output of the second NAND gate, and is used to convert the logic voltage into a high-voltage drive signal to drive the bit line pull-up path; The bit-line pull-down path is equipped with a pull-down discharge tube controlled by the write termination signal.

6. A method of operating the circuit according to any one of claims 2 to 5, characterized in that, Write operations include: Offset cancellation phase: Close SW1 and SW4, open SW2 and SW3, so that the stacked sensing core is biased to the logic threshold and the Schmitt trigger is preset. Write monitoring phase: Disconnect SW1 and SW4, close SW2 and SW3, the write start signal WS becomes valid, enabling the write drive circuit to apply the write voltage to the bit line; when the magnetic tunnel junction flips and causes the bit line voltage to jump, the jump is amplified by the coupling capacitor and the stacked sensing core, and then OUT2 is generated by the Schmitt trigger through SW2. OUT2 is then sent to the SR latch through SW3, so that the SR latch outputs a valid write stop signal WD. Instantaneous termination phase: In response to WD, the write drive circuit cuts off the high voltage of the bit line and simultaneously turns on the pull-down discharge tube.

7. A method of operating the circuit according to any one of claims 2 to 5, characterized in that, The read operation includes: Read offset cancellation phase: Close SW1 and SW4, open SW2 and SW3, and the write drive circuit remains invalid; Reading sensing stage: Disconnect SW1 and SW4, and close SW2 and SW3; first connect one end of the coupling capacitor to the reference voltage, and then switch to connect the bit line to be read to form a differential signal; the differential signal is sent to the SR latch through the coupling capacitor, the stacked sensing core, SW2, the Schmitt trigger, and SW3; the SR latch locks and outputs the read data Qread.

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