Memory device, operating method thereof, and memory system

Abstract

This disclosure provides a memory device, its operation method, and a memory system. The memory device includes: a memory cell array including a plurality of memory strings, each memory string including a select transistor and memory cells connected in series; a plurality of word lines coupled to the plurality of memory cells; a select gate line coupled to the select transistor; and peripheral circuitry coupled to the memory cell array, word lines, and select gate line, configured to: apply a first programming voltage to the selected word line to perform a first programming operation on the plurality of selected memory cells coupled to the selected word line; and apply an on-state voltage to the select gate line during the execution of the first programming operation; wherein the select transistor coupled to the same select gate line includes at least two select transistor groups, each select transistor group including at least one select transistor, and the select transistors in different select transistor groups have different threshold voltages.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, including but not limited to a memory device, its operating method, and a memory system. Background Technology

[0002] In three-dimensional NAND flash memory devices, memory cells can be programmed using charge trapping technology to store data. The amount of data stored in a memory cell depends on the amount of charge trapped in the memory layer. However, miniaturization of three-dimensional NAND flash memory devices becomes increasingly difficult as the number of stacked layers increases.

[0003] Based on industry research, incorporating ferroelectric materials into 3D NAND flash memory devices can improve their reliability and enable further miniaturization. The ferroelectric layer can be positioned between the gate electrode layer and the channel layer to form ferroelectric transistors, thus creating a ferroelectric memory device (FeNAND). The application of ferroelectric memory devices can reduce operating voltage, increase storage density, and significantly reduce manufacturing costs. Currently, there is an urgent need to improve the operating methods of ferroelectric memory devices. Summary of the Invention

[0004] In view of the above, embodiments of the present disclosure provide a memory device, a method of operating the same, and a memory system.

[0005] In a first aspect, embodiments of this disclosure provide a memory device, the memory device comprising: a memory cell array including a plurality of memory strings, the memory strings including select transistors and memory cells connected in series; a plurality of word lines coupled to the plurality of memory cells; a select gate line coupled to the select transistors; and peripheral circuitry coupled to the memory cell array, the word lines, and the select gate line, configured to: apply a first programming voltage to the selected word line to perform a first programming operation on the plurality of selected memory cells coupled to the selected word line; and apply an on-state voltage to the select gate line during the execution of the first programming operation; wherein the select transistors coupled to the same select gate line include at least two select transistor groups, the select transistor groups including at least one select transistor, and the select transistors in different select transistor groups have different threshold voltages.

[0006] In some embodiments, the peripheral circuitry further includes a word line driving circuit coupled to a coupling node of the word line, configured to provide the first programming voltage to the selected word line through a selected coupling node of the selected word line.

[0007] In some embodiments, among a plurality of select transistor groups coupled to the same select gate line, the smaller the distance between the selected memory cell and the selected coupling node, the larger the threshold voltage of the select transistor in the selected transistor group coupled to it, and the later the select transistor in the selected transistor group is turned on during the execution of the first programming operation.

[0008] In some embodiments, the smaller the distance between the selected storage unit and the selected coupling node among the plurality of selected storage units, the later the selected storage unit is programmed during the execution of the first programming operation.

[0009] In some embodiments, the plurality of selection transistor groups coupled to the same selection gate line include: a first selection transistor group and a second selection transistor group, wherein the distance between the selected memory cell and the selected coupling node coupled to the first selection transistor group is a first distance, and the distance between the selected memory cell and the selected coupling node coupled to the second selection transistor group is a second distance; wherein the first distance is less than the second distance, and the threshold voltage of the selection transistor in the first selection transistor group is greater than the threshold voltage of the selection transistor in the second selection transistor group.

[0010] In some embodiments, the plurality of select transistor groups coupled to the same select gate line further includes a third select transistor group disposed between the first select transistor group and the second select transistor group, wherein the threshold voltage of the select transistor in the first select transistor group is greater than the threshold voltage of the select transistor in the third select transistor group, and the threshold voltage of the select transistor in the third select transistor group is greater than the threshold voltage of the select transistor in the second select transistor group.

[0011] In some embodiments, the memory device further includes: a plurality of bit lines coupled to the memory cell array, the selection transistor being disposed between the bit lines and the memory cell; the peripheral circuitry is further configured to: apply a ground voltage to all of the plurality of bit lines coupled to the selected memory cell during the execution of the first programming operation.

[0012] In some embodiments, the different threshold voltages of the select transistors in different select transistor groups are achieved by performing a second programming operation or a third programming operation.

[0013] In some embodiments, prior to performing the first programming operation, the peripheral circuitry is further configured to: apply a second programming voltage to the select gate line to perform the second programming operation on a plurality of select transistor groups coupled to the select gate line; the duration of performing the second programming operation is less than the duration of performing the first programming operation; and during the performance of the second programming operation, apply a ground voltage to a plurality of bit lines coupled to the plurality of select transistor groups.

[0014] In some embodiments, prior to performing the first programming operation, the peripheral circuitry is further configured to: apply a third programming voltage to the select gate line to perform the third programming operation on a plurality of select transistor groups coupled to the select gate line; the duration of performing the third programming operation is longer than the duration of performing the second programming operation; during the performance of the third programming operation, apply different bit line voltages to a plurality of bit lines coupled to the plurality of select transistor groups; wherein, among the plurality of bit lines coupled to the plurality of select transistor groups, the smaller the distance between the selected memory cell and the selected coupling node corresponding to the select transistor group coupled to the bit line, the smaller the bit line voltage applied to the bit line.

[0015] In some embodiments, the different threshold voltages of the select transistors in different select transistor groups are achieved through an ion implantation process.

[0016] In some embodiments, the memory device includes a ferroelectric memory device, wherein the memory cell includes a channel layer, a gate electrode layer, and a ferroelectric layer disposed between the channel layer and the gate electrode layer.

[0017] Secondly, embodiments of this disclosure provide a memory system, the memory system comprising: a memory device as described in the above technical solutions; and a controller coupled to the memory device and configured to control the memory device.

[0018] Thirdly, embodiments of this disclosure provide an operating method for a memory device, the memory device comprising: a memory cell array including a plurality of memory strings, the memory strings including select transistors and memory cells connected in series; a word line coupled to the plurality of memory cells; a select gate line coupled to the select transistors; and peripheral circuitry coupled to the memory cell array, the word line, and the select gate line; the method comprising: applying a first programming voltage to the selected word line to perform a first programming operation on a plurality of selected memory cells coupled to the selected word line; and applying an on-state voltage to the select gate line during the execution of the first programming operation; wherein the select transistors coupled to the same select gate line include at least two select transistor groups, the select transistor groups including at least one select transistor, and the threshold voltages of the select transistors in different select transistor groups are different.

[0019] In some embodiments, the peripheral circuitry includes: a word line driving circuit coupled to a coupling node of the word line; applying a first programming voltage to the selected word line includes: the word line driving circuit providing the first programming voltage to the selected word line through the selected coupling node of the selected word line.

[0020] In some embodiments, among a plurality of select transistor groups coupled to the same select gate line, the smaller the distance between the selected memory cell and the selected coupling node, the larger the threshold voltage of the select transistor in the selected transistor group coupled to it, and the later the select transistor in the selected transistor group is turned on during the execution of the first programming operation.

[0021] In some embodiments, the smaller the distance between the selected storage unit and the selected coupling node among the plurality of selected storage units, the later the selected storage unit is programmed during the execution of the first programming operation.

[0022] In some embodiments, the plurality of selection transistor groups coupled to the same selection gate line include: a first selection transistor group and a second selection transistor group, wherein the distance between the selected memory cell and the selected coupling node coupled to the first selection transistor group is a first distance, and the distance between the selected memory cell and the selected coupling node coupled to the second selection transistor group is a second distance; wherein the first distance is less than the second distance, and the threshold voltage of the selection transistor in the first selection transistor group is greater than the threshold voltage of the selection transistor in the second selection transistor group.

[0023] In some embodiments, the plurality of select transistor groups coupled to the same select gate line further includes a third select transistor group disposed between the first select transistor group and the second select transistor group, wherein the threshold voltage of the select transistor in the first select transistor group is greater than the threshold voltage of the select transistor in the third select transistor group, and the threshold voltage of the select transistor in the third select transistor group is greater than the threshold voltage of the select transistor in the second select transistor group.

[0024] In some embodiments, the memory device further includes: a plurality of bit lines coupled to the memory cell array, the selection transistor being disposed between the bit lines and the memory cell; the method further includes: applying a ground voltage to all of the plurality of bit lines coupled to the selected memory cell during the execution of the first programming operation.

[0025] In some embodiments, the different threshold voltages of the select transistors in different select transistor groups are achieved by performing a second programming operation or a third programming operation.

[0026] In some embodiments, before performing the first programming operation, the method further includes: applying a second programming voltage to the select gate line to perform the second programming operation on a plurality of select transistor groups coupled to the select gate line; the duration of performing the second programming operation is less than the duration of performing the first programming operation; and during the performance of the second programming operation, applying a ground voltage to a plurality of bit lines coupled to the plurality of select transistor groups.

[0027] In some embodiments, before performing the first programming operation, the method further includes: applying a third programming voltage to the select gate line to perform the third programming operation on a plurality of select transistor groups coupled to the select gate line; the duration of performing the third programming operation is longer than the duration of performing the second programming operation; during the performance of the third programming operation, applying different bit line voltages to a plurality of bit lines coupled to the plurality of select transistor groups; wherein, among the plurality of bit lines coupled to the plurality of select transistor groups, the smaller the distance between the selected memory cell and the selected coupling node corresponding to the select transistor group coupled to the bit line, the smaller the bit line voltage applied to the bit line.

[0028] In some embodiments, the different threshold voltages of the select transistors in different select transistor groups are achieved through an ion implantation process.

[0029] In some embodiments, the memory device includes a ferroelectric memory device, wherein the memory cell includes a channel layer, a gate electrode layer, and a ferroelectric layer disposed between the channel layer and the gate electrode layer.

[0030] This disclosure provides a memory device, its operation method, and a memory system. The memory device includes: a memory cell array including multiple memory strings, each memory string including select transistors and memory cells connected in series; multiple word lines coupled to the multiple memory cells; select gate lines coupled to the select transistors; and peripheral circuitry coupled to the memory cell array, word lines, and select gate lines, configured to: apply a first programming voltage to the selected word lines to perform a first programming operation on the multiple selected memory cells coupled to the selected word lines; and apply an on-state voltage to the select gate lines during the execution of the first programming operation; wherein the select transistors coupled to the same select gate line include at least two select transistor groups, each select transistor group including at least one select transistor, and the threshold voltages of the select transistors in different select transistor groups are different. In this disclosure, the threshold voltages of the select transistors in different select transistor groups are different, the times at which the select transistors in different select transistor groups are turned on are different, and correspondingly, the times at which the selected memory cells coupled to the different select transistor groups are programmed are different. In other words, the actual programming time of the selected memory cell coupled to different selection transistor groups is different, which can compensate for word line delay, thereby achieving a narrower threshold voltage distribution width and an increased read window. Attached Figure Description

[0031] Figure 1 Figure (a) shows a schematic diagram of a ferroelectric transistor during an erase operation. Figure 1 Figure (b) shows the relationship between drain current and gate voltage during the erase operation. Figure 1 Figure (c) is a schematic diagram of a ferroelectric transistor during programming operations. Figure 1 Figure (d) shows the relationship between drain current and gate voltage during programming operations;

[0032] Figure 2 Figure (a) is a schematic diagram of the memory string formed by ferroelectric transistors. Figure 2 Figure (b) is an enlarged schematic diagram of a ferroelectric transistor;

[0033] Figure 3 Figure (a) shows the voltage variation over time at the near and far ends of the word line. Figure 3 Figure (b) shows the relationship between drain current and gate voltage;

[0034] Figure 4 A schematic diagram of a memory device including a memory cell array provided for embodiments of this disclosure;

[0035] Figure 5 A cross-sectional schematic diagram of a storage cell array provided in an embodiment of this disclosure;

[0036] Figure 6 Voltage timing diagrams provided for embodiments of this disclosure;

[0037] Figure 7 A block diagram of a memory device including peripheral circuitry provided for embodiments of this disclosure;

[0038] Figure 8 A block diagram of an electronic device provided in an embodiment of this disclosure;

[0039] Figure 9 This is a flowchart illustrating the operation method of a memory device provided in an embodiment of this disclosure. Detailed Implementation

[0040] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0041] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0042] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0043] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0044] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0045] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0046] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0047] The following is a brief explanation of the changes in the ferroelectric layer during the application and removal of an external electric field. When an external electric field is applied to the ferroelectric layer, the polarization P follows a hysteresis loop as the applied external electric field strength E changes. More specifically, when a positive external electric field is applied to the ferroelectric layer and the external electric field strength E is gradually increased, the polarization P of the ferroelectric layer also gradually increases until it reaches a saturation state Ps. Afterward, if the external electric field strength E is decreased, when the external electric field strength E is 0, the ferroelectric layer still has remanent polarization Pr. In other words, after removing the positive external electric field, the polarization in the ferroelectric layer does not disappear; the ferroelectric layer still has remanent polarization Pr. If it is necessary to completely depolarize the ferroelectric layer, a negative external electric field needs to be applied until the external electric field strength E reaches the negative coercivity field -Ec. Continuing to increase the external electric field strength E, the polarization P of the ferroelectric layer also gradually increases until it reaches a saturation state -Ps. Subsequently, if the external electric field strength E is reduced, the ferroelectric layer still exhibits negative remanent polarization -Pr when the external electric field strength E is 0. In other words, removing the negative external electric field does not eliminate the polarization in the ferroelectric layer; the ferroelectric layer still possesses remanent polarization -Pr. If it is necessary to completely depolarize the ferroelectric layer, a positive external electric field needs to be applied until the external electric field strength E reaches the positive coercive field Ec. In this way, the hysteresis loop can be repeated multiple times to change the polarization direction in the ferroelectric layer. Depending on the direction of spontaneous polarization in the ferroelectric layer, either "0" or "1" can be stored.

[0048] refer to Figure 1 Figures (a) and (b) Figure 1 Figure (a) shows a schematic diagram of a ferroelectric transistor during an erase operation. Figure 1 Figure (b) shows the relationship between drain current (Idrain) and gate voltage (Vgate) during the erase operation. Figure 1 As shown in Figure (a), a ferroelectric transistor may include: a source and a drain disposed in a semiconductor layer; a ferroelectric layer disposed above the semiconductor layer, between the source and the drain; and a gate electrode layer disposed above the ferroelectric layer. The semiconductor layer may include a p-type substrate, and the semiconductor layer is doped to form the source and drain, which may be n-type doped regions. The gate electrode layer may include, for example, a metal gate electrode layer. During an erase operation, a positive voltage is applied to the channel of the ferroelectric transistor. When the polarization is upward, the ferroelectric layer induces a positive charge in the channel, resulting in a higher threshold voltage. Figure 1 As shown by the arrow in Figure (b), the threshold voltage of the ferroelectric transistor increases after the erase operation is performed.

[0049] refer to Figure 1 Figures (c) and (d) Figure 1 Figure (c) is a schematic diagram of a ferroelectric transistor during programming operations. Figure 1 Figure (d) shows the relationship between drain current (Idrain) and gate voltage (Vgate) during programming operations. Figure 1 As shown in Figure (c), the structure of a ferroelectric transistor can be referenced. Figure 1 The relevant descriptions in Figure (a) will not be repeated here. During programming, a positive voltage is applied to the gate electrode layer of the ferroelectric transistor. When the polarization is downward, the ferroelectric layer induces negative charges in the channel, resulting in a lower threshold voltage. For example... Figure 1 As shown by the arrow in Figure (d), the threshold voltage of the ferroelectric transistor decreases after the programming operation is performed.

[0050] refer to Figure 2 Figure (a) Figure 2 Figure (a) is a schematic diagram of a memory string formed by a ferroelectric transistor. Figure 2 As shown in Figure (a), the memory string includes bottom selective gates (BSGs), multiple memory cells, and top selective gates (TSGs) connected in series vertically. The memory cells can be, for example, ferroelectric transistors. Multiple bottom selective gates arranged horizontally can be coupled to the same drain selective line (DSL), multiple top selective gates arranged horizontally can be coupled to the same source selective line (SSL), and multiple memory cells arranged horizontally can be coupled to the same word line (WL). Figure 2 Figure (a) illustrates WL1, WL2, ..., WL arranged vertically. 16 Of course, this disclosure does not have any special limit on the number of character lines; it is only used as an example for illustration.

[0051] refer to Figure 2 Figure (b) Figure 2 Figure (b) is an enlarged schematic diagram of a ferroelectric transistor. (As shown in the image...) Figure 2 As shown in Figure (b), the memory stack layer includes alternating gate electrode layers and gate dielectric layers; a ferroelectric layer disposed between the gate electrode layers and the gate dielectric layers; and a channel structure extending through the memory stack layer, the channel structure including a channel layer and a fill layer radially inward; wherein the channel layer, the gate electrode layer, and the ferroelectric layer disposed between the channel layer and the gate electrode layer together form a ferroelectric transistor, that is, form a memory cell.

[0052] The following explanations, in conjunction with the accompanying diagrams, clarify the meanings of "voltage settling time," "near end of word line," "far end of word line," and "word line delay" in this document. Voltage settling time refers to the duration between the moment the target voltage is applied to the word line and the moment the word line reaches the target voltage. For example, applying a first programming voltage Vpgm1 to the selected word line at a certain moment does not mean that the voltage of the selected word line reaches the first programming voltage Vpgm1 at that moment. In other words, applying the first programming voltage Vpgm1 to the selected word line at a certain moment indicates that, starting from that moment, the voltage of the selected word line begins to rise in a ramp-up manner, and after the voltage settling time, the voltage of the selected word line reaches the first programming voltage Vpgm1. The voltage settling time may be the same or different for different word lines. Similarly, applying a turn-on voltage Vpass to the select gate line at a certain moment does not mean that the voltage of the select gate line reaches the turn-on voltage Vpass at that moment. In other words, at a certain moment, when a turn-on voltage Vpass is applied to the select gate line, it means that the voltage of the select gate line begins to rise in a ramp-up manner, and after a voltage build-up period, the voltage of the select gate line reaches the turn-on voltage Vpass.

[0053] The distance between the near end of the word line and the location where the word line receives the target voltage is less than the distance between the far end of the word line and the location where the word line receives the target voltage. For example, at a certain moment, when a first programming voltage Vpgm1 is applied to the selected word line, due to the presence of the word line resistance, the near end of the selected word line responds to the target voltage faster than the far end of the selected word line. That is, the time required for the near end of the selected word line to boost to the first programming voltage Vpgm1 from that moment is less than the time required for the far end of the selected word line to boost to the first programming voltage Vpgm1 from that moment.

[0054] refer to Figure 3 Figure (a) Figure 3 Figure (a) shows the voltage change over time at the near and far ends of the word line. Figure 3 As shown in Figure (a), the solid line illustrates the voltage change over time at the near end of the word line, while the dashed line illustrates the voltage change over time at the far end. When a target voltage is applied to the word line, the time it takes for the near end to reach the target voltage is shorter than the time it takes for the far end to reach the target voltage. Thus, during the process of the word line boosting to reach the target voltage, the voltage difference between the near and far ends of the word line can be measured at the same time. This voltage difference between the near and far ends of the word line is called the word line delay.

[0055] refer to Figure 3 Figure (b) Figure 3 Figure (b) shows the relationship between drain current and gate voltage. Figure 3As shown in Figure (b), when an erase operation is performed on the ferroelectric transistor, the ferroelectric transistor is in the erase state, and its threshold voltage is Vt. initial When programming a ferroelectric transistor, the transistor is in a programmed state. Because the near and far ends of the word line respond differently to the target voltage, the threshold voltage of the ferroelectric transistor differs after programming. The threshold voltage (i.e., Vt) of the memory cell coupled to the near end of the word line also differs. 近端 The threshold voltage (Vt) of the memory cell coupled to the far end of the word line is less than the threshold voltage of the memory cell (i.e., Vt). 远端 In other words, word line delay results in a wider threshold voltage distribution.

[0056] Ferroelectric memory devices based on ferroelectric transistors achieve programming and erasing operations by controlling the flipping of ferroelectric domains. The flipping speed of ferroelectric domains is very fast, typically around 1 microsecond or less. However, word line delay is usually between 1 and 10 microseconds, significantly longer than the time required for ferroelectric domain flipping. During programming, due to word line delay, the gate voltage of the memory cell coupled to the near end of the word line reaches the target voltage more quickly, resulting in a large number of ferroelectric domain flips. Conversely, the gate voltage of the memory cell coupled to the far end of the word line reaches the target voltage more slowly, with relatively fewer ferroelectric domain flips. This results in a larger threshold voltage difference between the near and far ends of the word line, leading to a wider threshold voltage distribution. Therefore, compared to NAND flash memory devices, word line delay has a greater impact on ferroelectric memory devices; in other words, ferroelectric memory devices are more sensitive to word line delay.

[0057] In view of the above, embodiments of the present disclosure provide a memory device, a method of operating the same, and a memory system.

[0058] refer to Figure 4 , Figure 4 This is a schematic diagram of a memory device including a memory cell array, provided for embodiments of this disclosure. Figure 4As shown, this disclosure provides a memory device 100, comprising: a memory cell array 102 including a plurality of memory strings 118, each memory string 118 including a selection transistor and a plurality of memory cells 104 connected in series; a plurality of word lines 106 coupled to the plurality of memory cells 104, wherein the word lines 106 can select which row is affected by read and program operations; a selection gate line coupled to the selection transistor; and peripheral circuitry 110 coupled to the memory cell array 102, the word lines 106, and the selection gate line, configured to: apply a first programming voltage Vpgm1 to the selected word line to perform a first programming operation on the plurality of selected memory cells coupled to the selected word line; and apply an on-state voltage Vpass to the selection gate line during the execution of the first programming operation; wherein the selection transistor coupled to the same selection gate line includes at least two selection transistor groups, each selection transistor group including at least one selection transistor, and the threshold voltages of the selection transistors in different selection transistor groups are different.

[0059] Here, the selection transistor may include a drain selective transistor 124 (DST), also known as a top select transistor. Multiple drain selective transistors 124 arranged horizontally may be coupled to the same drain select gate line 126.

[0060] Here, a first programming voltage Vpgm1 is applied to the selected word line to perform a programming operation on at least a portion of the memory cells coupled to the selected word line. This portion of the memory cells that need to be programmed is the selected memory cell.

[0061] Here, the select transistors coupled to the same select gate line include at least two select transistor groups, each select transistor group including at least one select transistor. In some embodiments, the number of select transistors included in each select transistor group may be the same or different.

[0062] For example, the number of select transistors coupled to the same select gate line can be, for example, 100. If the number of select transistor groups is 2, then the number of select transistors included in each select transistor group can be 50; if the number of select transistor groups is 4, then the number of select transistors included in each select transistor group can be 25; if the number of select transistor groups is 100, then the number of select transistors included in each select transistor group can be 1.

[0063] For example, the number of select transistors coupled to the same select gate line can be, for instance, 100. If there are two select transistor groups, the number of select transistors included in each select transistor group can be 10 or 90, respectively; if there are four select transistor groups, the number of select transistors included in each select transistor group can be 10, 20, 30, or 40, respectively. The above-mentioned number of select transistors and the number of select transistor groups are for illustrative purposes only and do not constitute a limitation on the scope of protection of this disclosure.

[0064] Here, the threshold voltages of the select transistors in different select transistor groups are different, while the threshold voltages of the select transistors in the same select transistor group can be basically the same.

[0065] For example, the number of select transistor groups coupled to the same select gate line can be, for instance, two, and the threshold voltages of the select transistor groups can be 1 ± 0.1 V and 2 ± 0.1 V, respectively. The threshold voltages of the select transistor groups described above are for illustrative purposes only and do not constitute a limitation on the scope of this disclosure.

[0066] like Figure 4 As shown, in some embodiments, the peripheral circuit 110 may further include a word line driving circuit 112 coupled to a coupling node 114 of the word line 106, configured to provide a first programming voltage Vpgm1 to the selected word line through the selected coupling node of the selected word line.

[0067] Here, coupling node 114 refers to the location where word line 106 receives the target voltage. That is, when the target voltage is applied to word line 106, the transmission of the electrical signal will sequentially pass through coupling node 114, the near end of word line 106, and the far end of word line 106. Coupling node 114 is located between word line 106 and word line drive circuit 112. Coupling node 114 may refer to a part of word line 106, or it may refer to a part of the lead-out structure of word line 106.

[0068] In some embodiments, the memory cell array 102 and peripheral circuitry 110 can be fabricated on the same wafer, with the peripheral circuitry 110 located next to the memory cell array 102 (Peripheral Near Core, PNC). In other embodiments, the memory cell array 102 and peripheral circuitry 110 can be fabricated on different wafers, and the two wafers can be bonded together to form a memory device 100, with the memory cell array 102 and peripheral circuitry 110 stacked. For example, the peripheral circuitry 110 can be located above the memory cell array 102 (Peripheral Above Core, PAC) or below the memory cell array 102 (Peripheral Under Core, PUC). Regardless of the relative positions of the memory cell array 102 and peripheral circuitry 110, the distance between the selected memory cell and the selected coupling node refers to the distance of electrical signal transmission. A first programming voltage Vpgm1 is applied to the selected word line through the word line driving circuit 112, and the electrical signal transmission sequentially passes through the selected coupling node, the near end of the selected word line, and the far end of the selected word line.

[0069] In some embodiments, storage unit 104 stores string 118 (e.g. Figure 4 The array (shown in the dashed box) is provided, with each memory string 118 extending vertically above the substrate. That is, one memory string 118 corresponds to one channel structure, which will be discussed later in conjunction with... Figure 5 A detailed description is provided. Each memory string 118 includes a plurality of memory cells 104 that are series-coupled and vertically stacked. Each memory string 118 may include a source-selective transistor 120 (SST), also referred to as a bottom-select transistor, at its source end, and a drain-selective transistor 124 (DST), also referred to as a top-select transistor, at its drain end. The source-selective transistor 120 and the drain-selective transistor 124 may be configured to activate a selected memory string 118 (column of the array) during read and program operations. In other embodiments, multiple channel structures coupled to the same drain-select gate line collectively form a single memory string.

[0070] In some embodiments, the memory device 100 may further include: a source select gate line 122 coupled to a source select transistor 120; a drain select gate line 126 coupled to a drain select transistor 124; and the drain of each memory string 118 of the drain select transistor 124 coupled to a corresponding bit line 108. Each memory string 118 is configured to be selected or deselected by applying a selection voltage (e.g., higher than a threshold voltage of the drain select transistor 124) or a deselection voltage (e.g., 0V) to the corresponding drain select transistor 124 via one or more drain select gate lines 126; and / or by applying a selection voltage (e.g., higher than a threshold voltage of the source select transistor 120) or a deselection voltage (e.g., 0V) to the corresponding source select transistor 120 via one or more source select gate lines 122.

[0071] In some embodiments, the storage strings 118 may be organized into multiple storage blocks 116, each of which may have a source line 128 (SL) (e.g., a common SL). The sources of the storage strings 118 in the same storage block 116 are coupled through the same source line 128. In other words, in some embodiments, all storage strings 118 in the same storage block 116 have an array common source (ACS).

[0072] refer to Figure 5 , Figure 5 This is a cross-sectional schematic diagram of a storage cell array provided in an embodiment of this disclosure. Figure 5 As shown, the memory string 118 can extend vertically through the memory stack layer 204 above the substrate 202. The substrate 202 can include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0073] Here, the memory stack layer 204 may include alternating gate electrode layers 208 and gate dielectric layers 206. The number of pairs of gate electrode layers 208 and gate dielectric layers 206 in the memory stack layer 204 determines the number of memory cells 104 in the memory cell array 102. The gate electrode layer 208 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate electrode layer 208 includes a metal layer, such as a tungsten layer. In some embodiments, each gate electrode layer 208 includes a doped polysilicon layer. Each gate electrode layer 208 may include a control gate surrounding the memory cell 104 and may extend laterally at the top of the memory stack layer 204 as a drain select gate line 126, at the bottom of the memory stack layer 204 as a source select gate line 122, or between the drain select gate line 126 and the source select gate line 122 as a word line 106.

[0074] like Figure 5 As shown, the memory string 118 includes a channel structure 210 extending vertically through the memory stack layer 204. In some embodiments, the channel structure 210 may have a cylindrical shape (e.g., a pillar shape), and the channel structure 210 includes, radially inwardly, a ferroelectric layer 212, a channel layer 214, and a fill layer 216. Here, the ferroelectric layer 212 may include a ferroelectric material, such as a transition metal oxide of hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), titanium oxide (TiO2), niobium oxide (Nb2O5), tantalum oxide (Ta2O5), tungsten oxide (WO3), molybdenum oxide (MO3), vanadium oxide (V2O3), lanthanum oxide (La2O3), and / or any combination thereof; the channel layer 214 may include a semiconductor material, such as polycrystalline silicon; and the fill layer 216 may include a dielectric material, such as silicon oxide.

[0075] In some embodiments, the memory device 100 includes a ferroelectric memory device, and the memory cell 104 includes a channel layer 214, a gate electrode layer 208, and a ferroelectric layer 212 disposed between the channel layer 214 and the gate electrode layer 208. Here, the memory cell 104 includes a ferroelectric transistor, and the ferroelectric layer 212 can serve as a storage layer, utilizing the polarization state of the ferroelectric layer 212 to store data.

[0076] In some embodiments, the memory cell 104 may further include an interface layer disposed between the ferroelectric layer 212 and the channel layer 214. The interface layer may be used to reduce the possibility of material mixing between the ferroelectric layer 212 and the channel layer 214. The material of the interface layer may be, for example, silicon oxide, silicon nitride, silicon oxynitride, or other dielectric materials.

[0077] In some embodiments, the memory cell 104 may further include a barrier layer disposed between the ferroelectric layer 212 and the gate electrode layer 208, the barrier layer being used to reduce the interaction between the ferroelectric layer 212 and the gate electrode layer 208. The material of the barrier layer may be, for example, silicon oxide, silicon nitride, silicon oxynitride, or other dielectric materials.

[0078] In some embodiments, wells (e.g., P-wells and / or N-wells) may be formed in substrate 202, and the source end of memory string 118 contacts the well. In some embodiments, memory string 118 further includes a channel plug at the drain end of memory string 118. It should be understood that, although in Figure 5 Additional components, not shown in the diagram, can form the memory cell array 102. These additional components include, but are not limited to, gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0079] Return to reference Figure 4 The peripheral circuitry 110 can be coupled to the memory cell array 102 via bit line 108, word line 106, source line 128, source-select-gate line 122, and drain-select-gate line 126. The peripheral circuitry 110 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 102 by applying voltage and / or current signals to each target memory cell 104 and sensing voltage and / or current signals from each target memory cell 104 via bit line 108, word line 106, source line 128, source-select-gate line 122, and drain-select-gate line 126. The peripheral circuitry 110 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0080] In this embodiment, a first programming voltage Vpgm1 is applied to the selected word line to perform a first programming operation on the plurality of selected memory cells coupled to the selected word line; during the execution of the first programming operation, a conduction voltage Vpass is applied to the selected gate line. Since the threshold voltages of the selected transistors in different selection transistor groups are different, the times at which the selected transistors in different selection transistor groups are turned on are different. Correspondingly, the times at which the selected memory cells coupled to the different selection transistor groups are programmed are different. That is, the actual programming time of the selected memory cells coupled to the different selection transistor groups is different, thereby achieving compensation for word line delay, and further achieving a narrower threshold voltage distribution width and an increased read window.

[0081] In some embodiments, among multiple select transistor groups coupled to the same select gate line (e.g., drain select gate line 126), the smaller the distance between the selected memory cell and the selected coupling node, i.e., the closer the selected memory cell is to the near end of the select word line, the faster the selected memory cell coupled to the near end of the select word line responds to the first programming voltage Vpgm1; the larger the threshold voltage of the select transistor in the selected transistor group coupled to it, the later the select transistor in the selected transistor group is turned on during the execution of the first programming operation, i.e., the shorter the actual programming time of the selected memory cell coupled to the near end of the select word line. Here, the distance between the selected memory cell and the selected coupling node refers to the distance of electrical signal transmission, i.e., the distance the electrical signal travels through the selected coupling node and the selected memory cell.

[0082] Here, the greater the distance between the selected memory cell and the selected coupling node, that is, the more the selected memory cell coupled to the far end of the selected word line responds to the first programming voltage Vpgm1 more slowly; the smaller the threshold voltage of the selection transistor in the selected transistor group coupled to it, the earlier the selection transistor in the selected transistor group is turned on during the execution of the first programming operation, that is, the longer the actual programming time of the selected memory cell coupled to the far end of the selected word line.

[0083] In some embodiments, among a plurality of selected memory cells, the smaller the distance between the selected memory cell and the selected coupling node, that is, the more the selected memory cell is coupled to the near end of the selected word line, the faster the selected memory cell coupled to the near end of the selected word line responds to the first programming voltage Vpgm1; during the execution of the first programming operation, the later the selected memory cell is programmed, that is, the shorter the actual programming time of the selected memory cell coupled to the near end of the selected word line.

[0084] Here, the greater the distance between the selected memory cell and the selected coupling node, that is, the more the selected memory cell is coupled to the far end of the selected word line, the slower the selected memory cell coupled to the far end of the selected word line responds to the first programming voltage Vpgm1; during the execution of the first programming operation, the earlier the selected memory cell is programmed, that is, the longer the actual programming time of the selected memory cell coupled to the far end of the selected word line.

[0085] Return to reference Figure 4This document explains the meanings of "near-end top select transistor (Sel TSG_near-end)" and "far-end top select transistor (Sel TSG_far-end)" in this paper. The distance between the memory cell coupled to the near-end top select transistor and the coupling node is less than the distance between the memory cell coupled to the far-end top select transistor and the coupling node. The memory cell coupled to the near-end top select transistor is coupled to the near end of the word line, and the memory cell coupled to the far-end top select transistor is coupled to the far end of the word line.

[0086] In this embodiment, the response speed of the near end of the selected word line to the first programming voltage Vpgm1 is faster than that of the far end of the selected word line. The actual programming time of the selected memory cell coupled to the top selection transistor at the near end is less than that of the selected memory cell coupled to the top selection transistor at the far end, thereby achieving compensation for word line delay, and thus achieving a narrower threshold voltage distribution width and an increased read window.

[0087] In some embodiments, a plurality of select transistor groups coupled to the same select gate line includes at least two select transistor groups, each select transistor group including at least one select transistor. The plurality of select transistor groups coupled to the same select gate line include: a first select transistor group and a second select transistor group. The distance between the selected memory cell coupled to the first select transistor group and the selected coupling node is a first distance, and the distance between the selected memory cell coupled to the second select transistor group and the selected coupling node is a second distance; wherein the first distance is less than the second distance. That is, the select transistor included in the first select transistor group is a near-end top select transistor, and the select transistor included in the second select transistor group is a far-end top select transistor. The threshold voltage of the select transistor in the first select transistor group is the first threshold voltage, and the threshold voltage of the select transistor in the second select transistor group is the second threshold voltage. The first threshold voltage is greater than the second threshold voltage, and the actual programming time of the selected memory cell coupled to the select transistor in the first select transistor group is less than the actual programming time of the selected memory cell coupled to the select transistor in the second select transistor group.

[0088] refer to Figure 6 , Figure 6 A voltage timing diagram provided for embodiments of this disclosure. For example... Figure 6 As shown, at the first moment T1, a first programming voltage Vpgm1 is applied to the selected word line, and a turn-on voltage Vpass is applied to the drain select gate line.

[0089] Taking the selected word line as an example, a first programming voltage Vpgm1 is applied to the selected word line. After a voltage build-up period, the voltage ramp of the selected word line rises to the first programming voltage Vpgm1. Similarly, the drain-select-gate line also needs to undergo a voltage build-up period, and its voltage ramp rises to the turn-on voltage Vpass. The voltage build-up periods experienced by the selected word line and the drain-select-gate line during the voltage ramp rise process can be the same or different.

[0090] In some embodiments, the memory device 100 may further include: a plurality of bit lines 108 coupled to the memory cell array 102, a selection transistor (e.g., a drain selection transistor 124) disposed between the bit lines 108 and the memory cell 104; and peripheral circuitry 110 is further configured to apply a ground voltage Vss to the plurality of bit lines 108 coupled to the selected memory cell during the execution of a first programming operation.

[0091] At the second time T2, during the application of the turn-on voltage Vpass to the drain-select gate line, the voltage of the drain-select gate line rises to a first voltage V1, which is less than the turn-on voltage Vpass. Since the threshold voltage of the far-end top-select transistor is small, the voltage difference between the first voltage V1 and the bit line voltage is sufficient to turn on the far-end top-select transistor.

[0092] At time T3, during the application of the turn-on voltage Vpass to the drain-select gate line, the voltage of the drain-select gate line continues to rise to the second voltage V2, which is less than the turn-on voltage Vpass. Since the threshold voltage of the near-end top-select transistor is relatively large, the voltage difference between the second voltage V2 and the bit line voltage is sufficient to turn on the far-end top-select transistor.

[0093] At the fourth moment T4, the selected word line and the drain selected gate line begin to discharge.

[0094] In summary, for the far-end top-select transistor, its inactive period is from time 1 to time 2, during which the selected memory cell coupled to the far-end top-select transistor is not programmed. The far-end top-select transistor is turned on from time 2 to time 4, during which time the selected memory cell coupled to the far-end top-select transistor is programmed. In other words, the actual programming time for the selected memory cell coupled to the far-end top-select transistor is from time 2 to time 4.

[0095] For the near-end top-select transistor, its off-time is from the first time point T1 to the third time point T3. During this period, the selected memory cell coupled to the near-end top-select transistor is not programmed. The near-end top-select transistor is turned on from the third time point T3 to the fourth time point T4. During this period, the selected memory cell coupled to the near-end top-select transistor is programmed. In other words, the actual programming time for the selected memory cell coupled to the near-end top-select transistor is from the third time point T3 to the fourth time point T4.

[0096] In this embodiment, from the first time T1 to the second time T2, all top select transistors are not turned on. During this time, all selected memory cells coupled to the selected word line are not programmed. The voltage of the drain select gate line rises to a first voltage V1. At this time, the far-end top select transistor is turned on first, and the selected memory cells coupled to the far-end top select transistor are programmed first. The voltage of the drain select gate line continues to rise to a second voltage V2. At this time, the near-end top select transistor is turned on next, and the selected memory cells coupled to the near-end top select transistor are programmed next. The word line delay is compensated by the difference in the effective programming pulse width (i.e., the actual programming duration) of the selected memory cells coupled to the far-end and near-end top select transistors, thereby achieving a narrower threshold voltage distribution width and an increased read window.

[0097] In some embodiments, the plurality of select transistor groups coupled to the same select gate line further includes a third select transistor group disposed between the first select transistor group and the second select transistor group, wherein the distance between the selected memory cell coupled to the third select transistor group and the selected coupling node is a third distance; wherein, the first distance < the third distance < the second distance. The threshold voltage of the select transistor in the third select transistor group is a third threshold voltage, wherein the first threshold voltage > the third threshold voltage > the second threshold voltage. That is, the actual programming time of the selected memory cell coupled to the select transistor in the first select transistor group is less than the actual programming time of the selected memory cell coupled to the select transistor in the third select transistor group, and the actual programming time of the selected memory cell coupled to the select transistor in the third select transistor group is less than the actual programming time of the selected memory cell coupled to the select transistor in the second select transistor group.

[0098] It should be noted that, in this embodiment of the disclosure, the example is provided using multiple selection transistors including a first selection transistor group, a second selection transistor group, and a third selection transistor group. In practice, the multiple selection transistors can be grouped into more groups, allowing for more precise control of the on-state voltage Vpass applied to the selection gate line. Each selection transistor can even be treated as a separate group (i.e., each selection transistor group can include one selection transistor), with each selection transistor having a different threshold voltage and controlling the on-state timing of each selection transistor to achieve more accurate compensation for word line delay.

[0099] As mentioned earlier, the threshold voltages of the select transistors in different select transistor groups are different. Two methods are provided below to enable different threshold voltages for the select transistors in different select transistor groups.

[0100] In some embodiments, the different threshold voltages of the select transistors in different select transistor groups are achieved through an ion implantation process. Here, during the fabrication of the memory device 100, ion implantation can be performed on the channels of the select transistors. For example, the ion implantation concentrations in the channels of different select transistors in different select transistor groups are different, resulting in different threshold voltages of the select transistors in different select transistor groups.

[0101] In some embodiments, the different threshold voltages of the select transistors in different select transistor groups are achieved by performing a second programming operation or a third programming operation. Here, in the operation method of the memory device 100, different select transistors in different select transistor groups can be programmed to make the threshold voltages of the different select transistors in different select transistor groups different.

[0102] In some embodiments, prior to performing the first programming operation, the peripheral circuit 110 is further configured to: apply a second programming voltage Vpgm2 to a select gate line (e.g., drain select gate line 126) to perform a second programming operation on a plurality of select transistor groups coupled to the select gate line; the duration of performing the second programming operation is shorter than the duration of performing the first programming operation; and during the performance of the second programming operation, a ground voltage Vss is applied to a plurality of bit lines 108 coupled to the plurality of select transistor groups.

[0103] Here, a second programming voltage Vpgm2 is applied to the drain select gate line 126, that is, the second programming voltage Vpgm2 is applied to the gates of the plurality of drain select transistors 124 coupled to the drain select gate line 126; and a ground voltage Vss is applied to the plurality of bit lines 108 coupled to the plurality of drain select transistors 124. Because the duration of the second programming operation is shorter than the duration of the first programming operation, the near end of the drain-select-gate line 126 responds faster to the second programming voltage Vpgm2 than the far end of the drain-select-gate line 126. Consequently, the voltage difference between the near end of the drain-select-gate line 126 and the bit line 108 is greater than the voltage difference between the far end of the drain-select-gate line 126 and the bit line 108. After the second programming operation, the threshold voltage of the drain-select transistor 124 coupled to the near end of the drain-select-gate line 126 is greater than the threshold voltage of the drain-select transistor 124 coupled to the far end of the drain-select-gate line 126. In other words, when the duration of the second programming operation is short, the delay of the drain-select-gate line 126 can be used to make the threshold voltages of multiple drain-select transistors 124 coupled to the same drain-select-gate line 126 different.

[0104] In some embodiments, prior to performing the first programming operation, the peripheral circuit 110 is further configured to: apply a third programming voltage Vpgm3 to a select gate line (e.g., drain select gate line 126) to perform a third programming operation on a plurality of select transistor groups coupled to the select gate line; the duration of performing the third programming operation is longer than the duration of performing the second programming operation; during the performance of the third programming operation, different bit line voltages are applied to a plurality of bit lines 108 coupled to the plurality of select transistor groups; wherein, among the plurality of bit lines 108 coupled to the plurality of select transistor groups, the smaller the distance between the selected memory cell and the selected coupling node corresponding to the select transistor group coupled to the bit line 108, the smaller the bit line voltage applied to the bit line.

[0105] Here, a third programming voltage Vpgm3 is applied to the drain select gate line 126, that is, the third programming voltage Vpgm3 is applied to the gates of the multiple drain select transistors 124 coupled to the drain select gate line 126; different bit line voltages are applied to the multiple bit lines 108 coupled to the multiple drain select transistors 124. Since the duration of the third programming operation is longer than the duration of the second programming operation, the smaller the distance between the selected memory cell and the selected coupling node corresponding to the select transistor group coupled to the bit line 108, the smaller the bit line voltage applied to the bit line. The voltage difference between the near end of the drain select gate line 126 and the bit line 108 is greater than the voltage difference between the far end of the drain select gate line 126 and the bit line 108. After the third programming operation, the threshold voltage of the drain select transistor 124 coupled to the near end of the drain select gate line 126 is greater than the threshold voltage of the drain select transistor 124 coupled to the far end of the drain select gate line 126. In other words, when performing the third programming operation, different bit line voltages can be used to make the threshold voltages of multiple drain select transistors 124 coupled to the same drain select gate line 126 different.

[0106] refer to Figure 7 , Figure 7 This is a block diagram illustrating a memory device including peripheral circuitry, as shown in an embodiment of this disclosure. Figure 7 As shown, the peripheral circuitry 110 includes a page buffer / sensor amplifier 302, a column driver / bit line driver circuit 304, a row driver / word line driver circuit 306, a voltage generator 308, a control logic unit 310, a register 312, an interface 314 (I / F), and a data bus 316. It should be understood that in some embodiments, it may also include... Figure 7 Additional peripheral circuits not shown in the diagram.

[0107] Page buffer / sensor amplifier 302 can be configured to read data from memory cell array 102 and program (also known as write) data to memory cell array 102 according to control signals from control logic unit 310. In other embodiments, page buffer / sensor amplifier 302 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 104 coupled to selected word line 106. In still other embodiments, page buffer / sensor amplifier 302 can also sense a low-power signal from bit line 108 representing a data bit stored in memory cell 104 and amplify a small voltage swing to a recognizable logic level during read operations. Column driver / bit line driver circuit 304 can be configured to be controlled by control logic unit 310 and select one or more memory strings 118 by applying a bit line voltage generated from voltage generator 308.

[0108] The row driver / word line driver circuit 306 can be configured to be controlled by the control logic unit 310 and to select / deselect memory blocks 116 of the memory cell array 102 and to select / deselect word lines 106 of the memory blocks 116. The row driver / word line driver circuit 306 can also be configured to drive word lines 106 using word line voltages generated from the voltage generator 308. In some embodiments, the row driver / word line driver circuit 306 can also select / deselect and drive source select gate line 122 and drain select gate line 126. As described in detail below, the row driver / word line driver circuit 306 is configured to perform an erase operation on memory cells 104 coupled to (one or more) the selected word lines 106. The voltage generator 308 can be configured to be controlled by the control logic unit 310 and to generate word line voltages (e.g., read voltage, programming voltage, on-state voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 102.

[0109] Control logic unit 310 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 312 can be coupled to control logic unit 310 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 314 can be coupled to control logic unit 310 and acts as a control buffer to buffer slave devices (…). Figure 7 (Not shown in the diagram) It receives control commands and relays them to control logic unit 310, and buffers status information received from control logic unit 310 and relays it to the host. Interface 314 can also be coupled to column driver / bit line driver circuit 304 via data bus 316, and acts as a data input / output (I / O) interface and data buffer to buffer data and relay it to or from memory cell array 102.

[0110] refer to Figure 8 , Figure 8 A block diagram of an electronic device provided in an embodiment of this disclosure. (As shown) Figure 8 As shown, this disclosure provides a memory system 404 (as shown in the figure). Figure 8 (shown in the dashed box) includes: a memory device 100 as described in the above technical solution; and a controller 406 coupled to the memory device 100 and configured to control the memory device 100.

[0111] In some embodiments, the controller 406 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0112] In some embodiments, the controller 406 is designed to operate in a high duty cycle environment solid-state drive (SSD) or embedded multi-media card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0113] Controller 406 can be configured to control the operation of memory device 100, such as read, erase, and program operations. Controller 406 can also be configured to manage various functions relating to data stored or to be stored in memory device 100, including but not limited to bad block management, garbage collection, logical address to physical address translation, wear leveling, etc. In some embodiments, controller 406 is also configured to process error correcting codes (ECCs) relating to data read from or written to memory device 100.

[0114] Controller 406 may also perform any other suitable function, such as formatting memory device 100. Controller 406 may communicate with external devices (e.g., host 402) according to a specific communication protocol. For example, controller 406 may communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Drive Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0115] The controller 406 and one or more memory devices 100 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 404 can be implemented and packaged into different types of end electronic products.

[0116] This disclosure also provides an electronic device 400, which may include a host 402 and a memory system 404.

[0117] In some embodiments, controller 406 is coupled to memory device 100 and host 402 and is configured to control memory device 100. Controller 406 can manage data stored in memory device 100 and communicate with host 402.

[0118] Here, electronic device 400 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a memory device therein.

[0119] Here, host 402 can be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). Host 402 can be configured to send data to memory device 100 or receive data from memory device 100.

[0120] refer to Figure 9 , Figure 9 This is a flowchart illustrating an operation method of a memory device provided in an embodiment of this disclosure. (In conjunction with...) Figure 4 and Figure 9 As shown, this disclosure provides an operation method for a memory device. The memory device 100 includes: a memory cell array 102, including a plurality of memory strings 118, each memory string 118 including a selection transistor (e.g., a drain selection transistor 124) and a plurality of memory cells 104 connected in series; a word line 106 coupled to the plurality of memory cells 104; a selection gate line coupled to the selection transistor; and peripheral circuitry 110 coupled to the memory cell array 102, the word line 106, and the selection gate line. The method includes:

[0121] Step S510: Apply a first programming voltage to the selected word line to perform a first programming operation on the plurality of selected memory cells coupled to the selected word line;

[0122] Step S520: During the execution of the first programming operation, an on-state voltage is applied to the select gate line; wherein the select transistor coupled to the same select gate line includes at least two select transistor groups, each select transistor group including at least one select transistor, and the threshold voltages of the select transistors in different select transistor groups are different.

[0123] In some embodiments, the peripheral circuit 110 includes a word line driving circuit 112 coupled to a coupling node of the word line; step S510 includes: the word line driving circuit 112 providing a first programming voltage Vpgm1 to the selected word line through the selected coupling node of the selected word line.

[0124] In some embodiments, among a plurality of select transistor groups coupled to the same select gate line, the smaller the distance between the selected memory cell and the selected coupling node, the larger the threshold voltage of the select transistor in the selected transistor group coupled to it, and the later the select transistor in the selected transistor group is turned on during the execution of the first programming operation.

[0125] In some embodiments, among a plurality of selected memory cells, the smaller the distance between the selected memory cell and the selected coupled node, the later the selected memory cell is programmed during the execution of the first programming operation.

[0126] In some embodiments, a plurality of select transistor groups coupled to the same select gate line include: a first select transistor group and a second select transistor group, wherein the distance between the selected memory cell coupled to the first select transistor group and the selected coupling node is a first distance, and the distance between the selected memory cell coupled to the second select transistor group and the selected coupling node is a second distance; wherein the first distance is less than the second distance, and the threshold voltage of the select transistor in the first select transistor group is greater than the threshold voltage of the select transistor in the second select transistor group.

[0127] In some embodiments, the plurality of select transistor groups coupled to the same select gate line further includes a third select transistor group disposed between the first select transistor group and the second select transistor group, wherein the threshold voltage of the select transistor in the first select transistor group is greater than the threshold voltage of the select transistor in the third select transistor group, and the threshold voltage of the select transistor in the third select transistor group is greater than the threshold voltage of the select transistor in the second select transistor group.

[0128] In some embodiments, the memory device 100 further includes: a plurality of bit lines 108 coupled to the memory cell array 102, and a selection transistor disposed between the bit lines 108 and the memory cell 104; the method further includes: during the execution of a first programming operation, applying a ground voltage Vss to all of the plurality of bit lines 108 coupled to the selected memory cell.

[0129] In some embodiments, the different threshold voltages of the select transistors in different select transistor groups are achieved by performing a second programming operation or a third programming operation.

[0130] In some embodiments, prior to performing the first programming operation, the method further includes: applying a second programming voltage Vpgm2 to a select gate line to perform a second programming operation on a plurality of select transistor groups coupled to the select gate line; the duration of performing the second programming operation is less than the duration of performing the first programming operation; and during the performance of the second programming operation, applying a ground voltage Vss to a plurality of bit lines coupled to the plurality of select transistor groups.

[0131] In some embodiments, before performing the first programming operation, the method further includes: applying a third programming voltage Vpgm3 to a select gate line to perform a third programming operation on a plurality of select transistor groups coupled to the select gate line; the duration of performing the third programming operation is longer than the duration of performing the second programming operation; during the performance of the third programming operation, applying different bit line voltages to a plurality of bit lines 108 coupled to the plurality of select transistor groups; wherein, among the plurality of bit lines coupled to the plurality of select transistor groups, the smaller the distance between the selected memory cell corresponding to the selected transistor group coupled to the bit line and the selected coupling node, the smaller the bit line voltage applied to the bit line 108.

[0132] In some embodiments, the different threshold voltages of the select transistors in different select transistor groups are achieved through an ion implantation process.

[0133] In some embodiments, the memory device 100 includes a ferroelectric memory device, and the memory cell 104 includes a channel layer 214, a gate electrode layer 208, and a ferroelectric layer 212 disposed between the channel layer 214 and the gate electrode layer 208.

[0134] This disclosure provides a memory device, its operation method, and a memory system. The memory device includes: a memory cell array including multiple memory strings, each memory string including select transistors and memory cells connected in series; multiple word lines coupled to the multiple memory cells; select gate lines coupled to the select transistors; and peripheral circuitry coupled to the memory cell array, word lines, and select gate lines, configured to: apply a first programming voltage to the selected word lines to perform a first programming operation on the multiple selected memory cells coupled to the selected word lines; and apply an on-state voltage to the select gate lines during the execution of the first programming operation; wherein the select transistors coupled to the same select gate line include at least two select transistor groups, each select transistor group including at least one select transistor, and the threshold voltages of the select transistors in different select transistor groups are different. In this disclosure, the threshold voltages of the select transistors in different select transistor groups are different, the times at which the select transistors in different select transistor groups are turned on are different, and correspondingly, the times at which the selected memory cells coupled to the different select transistor groups are programmed are different. In other words, the actual programming time of the selected memory cell coupled to different selection transistor groups is different, which can compensate for word line delay, thereby achieving a narrower threshold voltage distribution width and an increased read window.

[0135] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0136] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A memory device, comprising: The memory device includes: A memory cell array comprising multiple memory strings, each memory string including select transistors and memory cells connected in series; Multiple word lines coupled to multiple of the aforementioned memory cells; Coupled to the select gate line of the select transistor; The peripheral circuitry coupled to the memory cell array, the word lines, and the select gate lines is configured as follows: A first programming voltage is applied to the selected word line to perform a first programming operation on a plurality of selected memory cells coupled to the selected word line; During the execution of the first programming operation, an on-state voltage is applied to the select gate line; wherein the select transistor coupled to the same select gate line comprises at least two select transistor groups, each select transistor group comprising at least one select transistor, and the select transistors in different select transistor groups have different threshold voltages.

2. The memory device of claim 1, wherein, The peripheral circuit also includes: A word line drive circuit coupled to a coupling node of the word line is configured to provide the first programming voltage to the selected word line through the selected coupling node of the selected word line.

3. The memory device of claim 2, wherein, In a plurality of select transistor groups coupled to the same select gate line, the smaller the distance between the selected memory cell and the selected coupling node, the larger the threshold voltage of the select transistor in the selected transistor group coupled to it, and the later the select transistor in the selected transistor group is turned on during the execution of the first programming operation.

4. The memory device of claim 3, wherein, Among the plurality of selected storage units, the smaller the distance between the selected storage unit and the selected coupling node, the later the selected storage unit is programmed during the execution of the first programming operation.

5. The memory device of claim 2, wherein, The plurality of selection transistor groups coupled to the same selection gate line include: a first selection transistor group and a second selection transistor group, wherein the distance between the selected memory cell coupled to the first selection transistor group and the selected coupling node is a first distance, and the distance between the selected memory cell coupled to the second selection transistor group and the selected coupling node is a second distance; wherein the first distance is less than the second distance, and the threshold voltage of the selection transistor in the first selection transistor group is greater than the threshold voltage of the selection transistor in the second selection transistor group.

6. The memory device of claim 5, wherein, The plurality of select transistor groups coupled to the same select gate line further includes a third select transistor group disposed between the first select transistor group and the second select transistor group, wherein the threshold voltage of the select transistor in the first select transistor group is greater than the threshold voltage of the select transistor in the third select transistor group, and the threshold voltage of the select transistor in the third select transistor group is greater than the threshold voltage of the select transistor in the second select transistor group.

7. The memory device of claim 2, wherein, The memory device further includes: a plurality of bit lines coupled to the memory cell array, wherein the selection transistor is disposed between the bit lines and the memory cells; The peripheral circuitry is also configured to apply a ground voltage to all of the bit lines coupled to the selected memory cell during the execution of the first programming operation.

8. The memory device of claim 7, wherein, The different threshold voltages of the select transistors in different select transistor groups are achieved by performing a second programming operation or a third programming operation.

9. The memory device of claim 8, wherein, Before performing the first programming operation, the peripheral circuit is also configured as follows: A second programming voltage is applied to the select gate line to perform the second programming operation on the plurality of select transistor groups coupled to the select gate line; The duration of executing the second programming operation is less than the duration of executing the first programming operation; During the execution of the second programming operation, a ground voltage is applied to each of the bit lines coupled to the plurality of select transistor groups.

10. The memory device of claim 8, wherein, Before performing the first programming operation, the peripheral circuit is also configured as follows: A third programming voltage is applied to the select gate line to perform the third programming operation on a plurality of select transistor groups coupled to the select gate line; the duration of the third programming operation is longer than the duration of the second programming operation. During the execution of the third programming operation, different bit line voltages are applied to multiple bit lines coupled to the plurality of select transistor groups; wherein, among the multiple bit lines coupled to the plurality of select transistor groups, the smaller the distance between the selected memory cell and the selected coupling node corresponding to the select transistor group coupled to the bit line, the smaller the bit line voltage applied to the bit line.

11. The memory device of claim 1, wherein, The different threshold voltages of the select transistors in different select transistor groups are achieved through an ion implantation process.

12. The memory device of claim 1, wherein, The memory device includes a ferroelectric memory device, and the memory cell includes a channel layer, a gate electrode layer, and a ferroelectric layer disposed between the channel layer and the gate electrode layer.

13. A memory system, characterized by comprising: The memory system includes: The memory device as claimed in any one of claims 1 to 12; and A controller coupled to the memory device and configured to control the memory device.

14. A method of operating a memory device, comprising: The memory device includes: a memory cell array including a plurality of memory strings, each memory string including a select transistor and memory cells connected in series; word lines coupled to the plurality of memory cells; select gate lines coupled to the select transistors; and peripheral circuitry coupled to the memory cell array, the word lines, and the select gate lines; the method includes: A first programming voltage is applied to the selected word line to perform a first programming operation on a plurality of selected memory cells coupled to the selected word line; During the execution of the first programming operation, an on-state voltage is applied to the select gate line; wherein the select transistor coupled to the same select gate line comprises at least two select transistor groups, each select transistor group comprising at least one select transistor, and the select transistors in different select transistor groups have different threshold voltages.

15. The method of operation of claim 14, wherein, The peripheral circuitry includes: a word line driving circuit coupled to the coupling node of the word line; applying a first programming voltage to the selected word line includes: The word line driving circuit provides the first programming voltage to the selected word line through the selected coupling node of the selected word line.

16. The method of operation of claim 15, wherein, In a plurality of select transistor groups coupled to the same select gate line, the smaller the distance between the selected memory cell and the selected coupling node, the larger the threshold voltage of the select transistor in the selected transistor group coupled to it, and the later the select transistor in the selected transistor group is turned on during the execution of the first programming operation.

17. The method of operation of claim 16, wherein, Among the plurality of selected storage units, the smaller the distance between the selected storage unit and the selected coupling node, the later the selected storage unit is programmed during the execution of the first programming operation.

18. The operating method according to claim 15, characterized in that, The plurality of selection transistor groups coupled to the same selection gate line include: a first selection transistor group and a second selection transistor group, wherein the distance between the selected memory cell coupled to the first selection transistor group and the selected coupling node is a first distance, and the distance between the selected memory cell coupled to the second selection transistor group and the selected coupling node is a second distance; wherein the first distance is less than the second distance, and the threshold voltage of the selection transistor in the first selection transistor group is greater than the threshold voltage of the selection transistor in the second selection transistor group.

19. The method of operation of claim 18, wherein, The plurality of select transistor groups coupled to the same select gate line further includes a third select transistor group disposed between the first select transistor group and the second select transistor group, wherein the threshold voltage of the select transistor in the first select transistor group is greater than the threshold voltage of the select transistor in the third select transistor group, and the threshold voltage of the select transistor in the third select transistor group is greater than the threshold voltage of the select transistor in the second select transistor group.

20. The operating method according to claim 15, characterized in that, The memory device further includes: a plurality of bit lines coupled to the memory cell array, wherein the selection transistor is disposed between the bit lines and the memory cells; the method further includes: During the execution of the first programming operation, a ground voltage is applied to all of the bit lines coupled to the selected memory cell.

21. The method of operation of claim 20, wherein, The different threshold voltages of the select transistors in different select transistor groups are achieved by performing a second programming operation or a third programming operation.

22. The method of claim 21, wherein, Before performing the first programming operation, the method further includes: A second programming voltage is applied to the select gate line to perform a second programming operation on a plurality of select transistor groups coupled to the select gate line; the duration of performing the second programming operation is less than the duration of performing the first programming operation. During the execution of the second programming operation, a ground voltage is applied to each of the bit lines coupled to the plurality of select transistor groups.

23. The method of claim 21, wherein, Before performing the first programming operation, the method further includes: A third programming voltage is applied to the select gate line to perform the third programming operation on a plurality of select transistor groups coupled to the select gate line; the duration of the third programming operation is longer than the duration of the second programming operation. During the execution of the third programming operation, different bit line voltages are applied to multiple bit lines coupled to the plurality of select transistor groups; wherein, among the multiple bit lines coupled to the plurality of select transistor groups, the smaller the distance between the selected memory cell and the selected coupling node corresponding to the select transistor group coupled to the bit line, the smaller the bit line voltage applied to the bit line.

24. The method of claim 14, wherein, The different threshold voltages of the select transistors in different select transistor groups are achieved through an ion implantation process.

25. The method of claim 14, wherein, The memory device includes a ferroelectric memory device, and the memory cell includes a channel layer, a gate electrode layer, and a ferroelectric layer disposed between the channel layer and the gate electrode layer.

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