Memory device and method of operation thereof

Abstract

The memory device includes multiple memory cells, each of which includes an access transistor, a control gate transistor, a resistive element, a read select transistor, and a write select transistor; a word line; a control gate line; a bit line; a read select line; and a write select line. For each of the multiple memory cells, the access transistor, the control gate transistor, and the resistive element are connected in series with each other. The gate terminal of the access transistor and the gate terminal of the control gate transistor are respectively connected to the first source / drain terminal and the second source / drain terminal of the read select transistor, and the gate terminal of the control gate transistor and a corresponding control gate line are respectively connected to the first source / drain terminal and the second source / drain terminal of the write select transistor. Embodiments of this application also provide a method of operating the memory device.

Description

Technical Field

[0001] Embodiments of this application relate to memory devices and methods of operating the same. Background Technology

[0002] eFuse bit cells are non-volatile memory elements used for one-time programmable (OTP) memory in integrated circuits. The resistance of the fuse-like structure can be permanently changed during operation, allowing selective programming of the stored data. eFuse bit cells can be used for device configuration, secure key storage, or chip identification. eFuse technology enables on-chip programming without the need for external memory components, facilitating secure and efficient customization of semiconductor devices. Summary of the Invention

[0003] According to one aspect of the embodiments of this application, a memory device is provided, comprising: a plurality of memory cells, each of the plurality of memory cells including an access transistor, a control gate transistor, a resistive element, a read select transistor, and a write select transistor; a plurality of word lines; a plurality of control gate lines; a plurality of bit lines; a plurality of read select lines; and a plurality of write select lines, wherein, for each of the plurality of memory cells, the access transistor, the control gate transistor, and the resistive element are connected in series with each other, the gate terminal of the access transistor and the gate terminal of the control gate transistor are respectively connected to the first source / drain terminal and the second source / drain terminal of the read select transistor, and the gate terminal of the control gate transistor and a corresponding control gate line are respectively connected to the first source / drain terminal and the second source / drain terminal of the write select transistor.

[0004] According to another aspect of the embodiments of this application, a memory device is provided, comprising: a plurality of memory cells, each memory cell including an access transistor, a control gate transistor, a resistive element, a read select transistor, and a write select transistor, wherein the plurality of memory cells are respectively coupled to a plurality of word lines and are jointly coupled to a bit line, a read select line, a write select line, and a control gate line.

[0005] According to another aspect of the embodiments of this application, a method of operating a memory device is provided, comprising: selecting a memory cell from a plurality of memory cells, the memory cell including an access transistor, a control gate transistor, a resistive element, a read select transistor and a write select transistor electrically coupled to each other; during a read mode: asserting the read select transistor via a read select line; and deasserting the write select transistor via a write select line; and during a write mode: deasserting the read select transistor via a read select line; and asserting the write select transistor via a write select line. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 An example block diagram of a memory circuit including a memory array is shown according to some embodiments.

[0008] Figure 2 Illustrations are shown according to some embodiments Figure 1 An example schematic diagram of an eFuse cell in a memory array.

[0009] Figures 3A-3B Illustrations are shown according to some embodiments Figure 2 An example diagram of the eFuse unit during operation.

[0010] Figure 4 Illustrations are shown according to some embodiments Figure 1 An example schematic diagram of two eFuse cells in a memory array.

[0011] Figures 5A-5B The diagram illustrates, according to some embodiments, that during operation, includes at least Figure 2 An example schematic diagram of a memory array of eFuse cells.

[0012] Figure 6 Illustrations are shown according to some embodiments Figure 1 An example schematic diagram of an eFuse cell with p-channel metal-oxide-semiconductor (PMOS) switches in a memory array.

[0013] Figure 7 Illustrations are shown according to some embodiments Figure 1 An example schematic diagram of an eFuse cell with hybrid switches in a memory array.

[0014] Figure 8 The diagram illustrates the relationship between [various embodiments] and [other embodiments]. Figure 1 An example schematic diagram of a switch-coupled eFuse cell in a memory array.

[0015] Figure 9 Illustrations are shown according to some embodiments Figure 1 An example schematic diagram of an eFuse cell with three transistors in a memory array.

[0016] Figure 10 Illustrations are shown according to some embodiments Figure 1 An example schematic diagram of an eFuse cell that includes multiple access transistors and switches in a memory array.

[0017] Figure 11 The illustration shows a method for forming, according to some embodiments, including Figures 1-10 A flowchart of an example method for enhancing leakage tolerance in memory devices using eFuse bit cells in a stacked structure.

[0018] Figure 12 The following are illustrated, according to some embodiments, for operation including Figures 1-10 A flowchart of an example method for enhancing leakage tolerance in memory devices using eFuse bit cells in a stacked structure. Detailed Implementation

[0019] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0020] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0021] In the field of semiconductor memory technology, eFuse and / or one-time programmable (OTP) memory programming can be used in a variety of applications, such as advanced node core high-voltage (HV) memory circuits. eFuse or OTP can be included, correspond to, or implemented in one or more memory arrays. Memory arrays, such as eFuse or OTP, can be used to store data. Data stored in these memory arrays can be maintained or remain unchanged once written. Data stored in the memory array can be read after the memory array has been written (or programmed). In some systems, access transistors can be stacked to potentially prevent overvoltage stress, thereby improving the reliability and lifetime of the memory cells. Furthermore, a second word line for these stacked access transistors (e.g., sometimes called a control gate transistor) can be asserted in the same manner as a bit line (BL) to access a specific cell. However, this approach may involve enabling or asserting the control gate transistor to protect the stacked access transistor in unselected cells, resulting in higher leakage current, for example, during read operations. Enabling all control gate transistors in each read cycle is unnecessary and increases leakage (e.g., current or electrical leakage), which can adversely affect or degrade the read margin or overall performance of the memory array.

[0022] In some cases, in advanced node memory circuits with relatively high bit-line capacitive loads, the potential leakage of the control gate transistor during read cycles can be exacerbated. For example, leakage from unselected locations (or cells) can affect read margin. In some cases, structures that combine control gate enable with bit-line address decoding can result in relatively high total bit-line capacitive loads during read operations, potentially exacerbating leakage. Therefore, it may be necessary to form or fabricate eFuse bit cells in the stacked structure to enhance leakage tolerance, thereby reducing leakage and improving the reliability and performance of the memory array.

[0023] This disclosure provides various embodiments of a circuit including at least two additional metal-oxide-semiconductor (MOS) transistors to separate programming and read modes on a control gate controller. This disclosure may relate to modifying a dual-transistor (2T) structure to differentiate programming and read modes by adding at least one switch to the bit cell (e.g., utilizing additional transistors as switches). The two additional transistors can be independently controlled to separate read / write (or programming) operations on a single bit cell. For example, the two additional transistors may include a write select transistor and a read select transistor. Depending on the mode, the write select transistor and read select transistor can be enabled / asserted / on or disabled / deasserted / off, respectively. Asserting or deasserting the write select transistor can respectively connect or disconnect the control gate line (CG) to or from the gate terminal of the control gate transistor in the 2T structure. Asserting or deasserting the read select transistor can respectively connect or disconnect the WL to or from the gate terminal of the control gate transistor.

[0024] For example, in programming mode, the write select transistor can be enabled and the read select transistor can be disabled. In read mode, the write select transistor can be disabled and the read select transistor can be enabled. Depending on the mode, the word line (WL), bit line (BL), and CG can be set to corresponding predefined voltages for at least the selected cell. By implementing additional transistors (e.g., switches), programming and read modes can be separated to ensure that the control gate transistor for unselected cells is not unnecessarily enabled during read operations, thereby minimizing or avoiding leakage through unselected cells and improving read margin without introducing stress (or variation) to the memory cell during programming mode. The features or functions of this disclosure can be implemented in memory arrays of any size, not limited to those discussed herein. As a non-limiting example herein, the systems and methods may include memory circuitry comprising a 64x64 memory array, where off-state leakage current for unselected cells can be significantly reduced.

[0025] Figure 1 A block diagram of an example circuit 100 according to various embodiments is shown. This example circuit 100 includes voltage control circuitry that can be configured to provide different voltages for operating a memory array. For example, the memory circuitry 100 may include a memory array 102, row control circuitry (e.g., drivers, decoders, and / or level shifters) 104, column control circuitry (e.g., drivers, decoders, and / or electrically shifters) 106, input / output (I / O) circuitry 108, and voltage control circuitry 110. Although... Figure 1 Although not explicitly shown, all components of the memory circuitry 100 are operatively coupled to each other. Despite this, Figure 1In the embodiments shown, each component is shown as a separate block for clarity, but in some other embodiments, this may be the case. Figure 1 Some or all of the components shown can be integrated together.

[0026] Memory array 102 is a hardware component for storing data. In various embodiments, memory array 102 is implemented as a semiconductor memory device. Memory array 102 includes a plurality of memory cells (or other memory cells) 103. Memory array 102 includes a plurality of rows R1, R2, R3…R M Each row extends in the first direction (e.g., the X direction), and there are multiple columns C1, C2, C3…C N Each column extends in a second direction (e.g., the Y direction). Each row and each column may include one or more conductive (e.g., metallic) structures that serve as access lines (e.g., bit lines (BL), word lines (WL), and source / select lines (SL)). Each memory cell 103 is arranged at the intersection of a corresponding row and a corresponding column and can be operated according to the voltage or current through the corresponding conductive structures of the column and row. For example, each row may include one or more corresponding WLs, and each column may include one or more corresponding BLs and one or more corresponding SLs. In this example, the row control circuitry 104 may include at least a WL decoder and a WL level shifter, and the column control circuitry 106 may include at least a BL decoder and a BL level shifter.

[0027] The decoder can be configured to select one or more corresponding lines (e.g., WL or BL) based on an input address (e.g., an n-bit address). For example, the WL decoder of row control circuit 104 can be configured to receive and decode a first portion of the address signal, and the BL decoder of column control circuit 106 can be configured to receive and decode a second portion of the address signal. The WL decoder can select one or more WL lines based on the first portion of the address signal, and the BL decoder can select one or more BL lines based on the second portion of the address signal. The level shifter can be configured to adjust / shift or otherwise change a corresponding voltage in at least one line (e.g., WL voltage, BL voltage, CG voltage, read select line voltage, or write select line voltage) to a predetermined voltage level for operating the individual memory cells 103 in memory array 102.

[0028] In some embodiments, each memory cell 103 is implemented as a resistive random access memory (RRAM) cell. However, it should be understood that the memory cell 103 can be implemented as any of a variety of other non-volatile memory cells while still within the scope of this disclosure. For example, the memory cell 103 may include a magnetoresistive random access memory (MRAM) cell, a phase-change random access memory (PCRAM) cell, an efuse memory cell, an antifuse memory cell, etc. In another example, the memory cell 103 may be an OTP memory cell configured to maintain a state (e.g., bit value) after programming or writing.

[0029] In an example implemented as an RRAM cell, memory cell 103 may include resistors and transistors coupled in series with each other. Memory cell 103 may be operatively coupled to a corresponding set of BL, WL, and SL. Resistors may be formed as a multilayer stack including a top electrode (TE), a capping layer, a variable resistance dielectric (VRD) layer, and a bottom electrode. In some embodiments, the VRD layer may be formed of at least one transition metal oxide material, such as TiOx, NiOx, HfOx, NbOx, CoOx, FeOx, CuOx, VOx, TaOx, WOx, CrOx, and combinations thereof. In some embodiments, the VRD layer may include a high-k dielectric layer. The VRD layer may switch between a high resistance state (HRS) and a low resistance state (LRS), which may correspond to logic 0 and logic 1 of data bits stored in memory cell 103.

[0030] Generally, the resistor TE can be coupled to the corresponding BL, the resistor BE can be coupled to the first source / drain terminal of the transistor, the gate terminal of the transistor is coupled to the corresponding WL, and the second source / drain terminal of the transistor is coupled to the corresponding SL. To operate the memory cell 103 (implemented as an RRAM cell), the transistor is enabled (i.e., turned on) by an assertion signal of WL, and then a polarized voltage is applied across the memory cell 103 (e.g., BL is provided with a positive voltage, and SL is grounded). Therefore, the higher voltage at BL (and TE) pulls negatively charged oxygen ions from the VRD layer to the capping layer, thereby leaving oxygen vacancies in the VRD layer. This allows electrons present in BE to travel (jump) from BE through the VRD and capping layer, eventually reaching TE. Thus, a conductive path through the VRD layer is "formed". Before this conductive path is formed, the resistor can be held at HRS. In some embodiments, after the conductive path is formed, the resistor changes from HRS to LRS, and a relatively large current flows between BL and SL.

[0031] Row control circuit 104 is a hardware component that receives the row address of memory array 102 and asserts one or more conductive structures (e.g., WL) at that row address. Column control circuit 106 is a hardware component that receives the column address of memory array 102 and asserts one or more conductive structures (e.g., BL, SL, and / or CG) at that column address. I / O circuit 108 is a hardware component that can access (e.g., read, program) each memory cell 103 asserted by row control circuit 104 (or row decoder) and column control circuit 106 (or column decoder).

[0032] In various embodiments of this disclosure, voltage control circuitry 110 is a hardware component that can provide multiple suitable voltages to access or otherwise operate the memory array via row control circuitry 104, column control circuitry 106, and I / O circuitry 108, respectively. Voltage control circuitry 110 can operate in conjunction with row control circuitry 104 and column control circuitry 106 to access memory cells 103 of memory array 102 for desired read and / or write operations. Voltage control circuitry 110 can be configured to manage and regulate voltage levels supplied to various portions of circuitry 100. Voltage control circuitry 110 may include components such as voltage regulators, switches, and control logic that ensure stable and appropriate voltage levels are maintained across different operating modes. For example, voltage control circuitry 110 may interact with WL, BL, and CG (e.g., control gate lines) to manage the voltage supplied to selected and / or unselected memory cells 103. In some cases, level shifters (e.g., WL, BL, or CG level shifters) may be part of voltage control circuitry 110 to manage voltage levels on one or more access lines.

[0033] Figure 2 Illustrations are shown according to some embodiments Figure 1 An example schematic diagram of a memory cell 200 (e.g., an eFuse cell) in a memory array. As a non-limiting example, the memory cell 200 or components of the memory cell 200 (e.g., transistors 202A-D and resistor element 204) may be part of the memory array 102, although the memory cell 200 may be implemented as part of other memory devices or circuitry, not limited to memory circuitry 100. The memory cell 200 may be composed of hardware components. The memory cell 200 may be one of the memory cells 103, for example, at least in conjunction with… Figure 1 As described. Memory cell 200 may include more or fewer non-limiting components, elements, or features.

[0034] Memory cell 200 may include at least transistors 202A-D (e.g., sometimes referred to as transistor 202), at least one resistive element 204, at least one word line WL, at least one word line BL, at least one control gate line CG, at least one read select line, at least one write select line, etc. Transistor 202 may include access transistor 202A, control gate transistor 202B, read select transistor 202C, and write select transistor 202D. Example names or designations for transistor 202 may be provided for illustrative purposes and are not intended to be limiting herein. Each transistor 202 may include its own source / drain (S / D) terminal and gate terminal. The S / D terminal may be referred to as the emitter and collector of transistor 202. Transistor 202 may be a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0035] Transistor 202 can be an n-type (e.g., NMOS) transistor (e.g., asserted when a predefined voltage is applied and deasserted when no predefined voltage is applied). Transistor 202 can also be a p-type (e.g., PMOS) or other types of transistors, not limited to n-type transistors. In this case, transistors 202 can have the same conductivity type. In some other cases, one or more transistors 202 may include conductivity types different from other transistors 202.

[0036] Transistor 202 may be formed along the main surface of a semiconductor substrate (not shown) in one or more corresponding portions (e.g., a first portion) of memory cell 200 or other memory cell 103. For example, memory cell 200 may be fabricated at least in part by forming access transistor 202A, control gate transistor 202B, read select transistor 202C, and write select transistor 202D on the main surface of the semiconductor substrate. Transistor 202 may be formed thereon or disposed thereon. The main surface may refer to the top layer of the substrate. The main surface may include at least the fabricated transistor 202 or other microelectronic circuitry of memory cell 200. The semiconductor substrate may be composed of silicon, gallium arsenide (GaAs), silicon carbide (SiC), sapphire, or other suitable materials.

[0037] Resistive element 204 may be part of each memory cell 200. Resistive element 204 may be a hardware component, such as a non-volatile programmable component, configured to undergo a permanent electrical change when subjected to programming operations. Resistive element 204 may be formed in one or more corresponding portions (e.g., second portions) of memory cell 103 in one or more of a plurality of metallization layers (not shown) disposed on a main surface. The second portion of each memory cell 103 may include a corresponding resistive element 204. A metallization layer may refer to a conductive layer in circuit 100 that forms interconnections between transistor 202, memory cell 103, and other components. The metallization layer can be used to route electrical signals and power supplies on circuit 100. For example, the metallization layer may include metal traces separated by an insulating dielectric layer (e.g., silicon dioxide or a low-k material). The metallization layer may be composed of any suitable material, such as aluminum, copper, tungsten, etc.

[0038] Resistive element 204 can store data that cannot be changed after programming. Resistive element 204 can take different forms, such as an antifuse, which starts with a high-resistivity material and transitions to a low-resistivity state when a relatively high voltage is applied. In some embodiments, resistive element 204 can be a fuse-based element that starts with a conductive link (e.g., metal or polysilicon) and is broken by, for example, a relatively high current or laser operation. Resistive element 204 can be composed of any suitable material, such as silicon oxide or silicon nitride. Different types of resistive elements can be used depending on the configuration of memory cell 200.

[0039] Each corresponding type of line (e.g., WL, BL, CG, read select line, or write select line) can be one of multiple lines in the memory array 102 of circuit 100. For example, circuit 100 may include multiple memory cells 103, 200, multiple WL, multiple CG; multiple BL, multiple read select lines, and / or multiple write select lines, etc., in memory array 102. Each memory cell 103, 200 may be electrically connected / coupled to one or more corresponding lines for selecting (or deselecting) memory cells 103 and 200 for reading or writing / programming. Lines (e.g., WL, BL, CG, read select lines, and / or write select lines) may be formed in one or more metallization layers disposed on a main surface.

[0040] Different lines may extend from, be connected to, or be part of at least one component of circuit 100, such as row control circuit 104, column control circuit 106, I / O circuit 108, or voltage control circuit 110. For example, WL may extend from or be electrically connected to row control circuit 104, which is configured to select and enable specific rows (e.g., transistors in specific rows) of memory cells 103 within memory array 102. BL may extend from column control circuit 106, which may be configured to read or write data by transferring charge to or from selected memory cells in the enabled row. CG may be connected to column control circuit 106, voltage control circuit 110, or other components of circuit 100, for example, to manage and regulate the voltage level supplied to the control gate (e.g., the gate terminal of control gate transistor 202B) of memory cell 103 during write / programming mode or operation. Different lines may be controlled by other components within circuit 100. Read select lines and / or write select lines can be connected to I / O circuitry 108 to manage the mode of memory cell 200, for example, by switching between read and write modes by applying or stopping voltage to read select or write select transistors 202C-D. In some arrangements, different lines may be connected to or controlled by other circuitry or devices. In some embodiments, voltage control circuitry 110 or other components of circuitry 100 may supply the required current or voltage to memory cell 103 via different lines.

[0041] In some arrangements, the WL of circuit 100 may extend in a first direction, while the CG, BL, read select line, and write select line extend in a second direction perpendicular to the first direction. For example, in memory array 102, the first direction may be horizontal, and the second direction may be vertical. By extending in the respective directions, a corresponding one of the BL, write select line, and read select line may be shared in a column memory cell 103, and a corresponding one of the WL may be shared in a row memory cell 103, for example, at least in combination. Figures 5A-5B These lines can be arranged in other non-limiting directions based on the configuration of the memory array 102.

[0042] The interconnection or arrangement of components of memory cell 200 can at least be Figure 2As shown, for example, access transistor 202A may include a first S / D terminal (electrically) connected to ground (e.g., ground voltage), a second S / D terminal connected to the first S / D terminal of control gate transistor 202B, and a gate terminal connected to the corresponding WL and the first S / D terminal of read select transistor 202C. Control gate transistor 202B may include a second S / D terminal connected to resistor element 204, and a gate terminal connected to the second S / D terminal of read select transistor 202C and the first S / D terminal of write select transistor 202D. Access transistor 202A, control gate transistor 202B, and resistor element 204 may be connected in series between ground and the corresponding BL. Control gate transistor 202B may be electrically connected to BL via resistor element 204.

[0043] The read select transistor 202C may include a first S / D terminal connected to the gate terminal of the access transistor 202A and the WL transistor 202B, a second S / D terminal connected to the gate terminal of the control gate transistor 202B and the first S / D terminal of the write select transistor 202D, and a gate terminal connected to the read select line. The write select transistor 202D may include a first S / D terminal connected to the gate terminal of the control gate transistor 202B and the second S / D terminal of the read select transistor 202C, a second S / D terminal connected to the corresponding CG transistor, and a gate terminal connected to the write select line. An example of transistor 202 operating the memory cell 200 may at least combine... Figures 3A-3B To describe.

[0044] Figures 3A-3B Illustrations are shown according to some embodiments Figure 2 An example schematic diagram of a memory cell 200 (e.g., an eFuse cell) during operation. Figure 3A The memory cell 200 can be shown during an example write / programming operation. Figure 3B The memory cell 200 can be shown during an example read operation. Figures 3A-3B It may include memory cell 200 and at least combined with Figure 2 The components of the memory unit 200 described.

[0045] For example, memory cell 200 may be selected memory cells for read and / or write operations. For selected memory cells, WL, BL, and CG may carry their respective predefined currents or be set to corresponding predefined voltages. The corresponding voltages may be applied to one or more transistors 202 via WL, BL, and CG. As a non-limiting example, for selected memory cells, WL may be set to a first voltage level, BL may be set to a second voltage level, and CG may be set to a third voltage level. For example, a first voltage may be applied to access transistor 202A, thereby allowing current to flow through access transistor 202A of the selected cell. The voltage levels may be predetermined according to the configuration of the components of circuit 100. The applied voltage levels may be associated with the current levels from the corresponding lines. It should be noted that setting a corresponding line to a predetermined voltage may be referred to as asserting the line, and setting a corresponding line to a relatively low voltage or no voltage may be referred to as deasserting the line.

[0046] During write mode or operation, the read select transistor 202C can be deasserted via the read select line (e.g., by not applying voltage to the gate terminal of the read select transistor 202A or by reducing the voltage below a predefined threshold). Deasserting the read select transistor 202C disconnects WL from the gate terminal of the control gate transistor 202B. Deasserting transistor 202 can turn off or disable the transistor, thereby preventing current from flowing between the S / D terminals. The write select transistor 202D can be asserted by applying a predetermined voltage to its gate terminal via the write select line. Assertion transistor 202 can turn on or enable the transistor, thereby allowing current to flow between the S / D terminals.

[0047] Declaring an assertion to read select transistor 202C and an assertion to write select transistor 202D can make the voltage at CG (e.g., the control gate line) substantially equal to the gate voltage (VG) at the gate terminal of control gate transistor 202B. Applying a gate voltage equal to CG allows current to flow from BL through resistive element 204 (e.g., a fuse), control gate transistor 202B, and access transistor 202A to ground. For example, the voltage of BL can be set to a relatively high voltage level (e.g., an assertion) to program memory cell 200 by passing through fused resistive element 204, thereby producing a (permanent) resistance change representing the stored data.

[0048] During read mode or operation, read select transistor 202C can be asserted, and write select transistor 202D can be deasserted. Deasserting write select transistor 202D disconnects CG from the gate terminal of control gate transistor 202B. Subsequently, the voltage (e.g., VG) present at the gate terminal of control gate transistor 202B and the voltage on WL can be substantially equal to each other. In this case, access transistor 202A and control gate transistor 202B can be asserted to allow current to flow from BL to ground, and vice versa. The voltage drop across resistor element 204 can be sensed to determine the stored data used for the read operation. If resistor element 204 has blown, the resistance may be relatively high, resulting in relatively low current flow and a relatively high voltage drop, indicating a programmed state (e.g., logic "1"). If the fuse has not blown, the resistance may be relatively low, resulting in relatively high current flow and a relatively low voltage drop, indicating an unprogrammed state (e.g., logic "0").

[0049] For an unselected memory cell, at least one of WL and / or BL can be left unset to its corresponding predefined voltage (e.g., de-assertion). By implementing switches (e.g., read select transistor 202C and write select transistor 202D) in a 2T configuration, leakage to the unselected memory cell can be prevented or minimized. For example, in some circuits with a 2T configuration (without switches), the gate terminal of the control gate transistor can be directly connected to the corresponding CG. By sharing the corresponding CG and corresponding BL across a column of memory cells, if one memory cell in the 2T configuration is selected, the control gate transistors of other memory cells in that column can be asserted, resulting in a half-selected state where a leakage path from the corresponding BL through the unselected (or half-selected) memory cell to ground may exist. Therefore, by implementing switches (e.g., read select transistor 202C and write select transistor 202D), for example, during read mode, the assertion of the control gate transistors of the unselected memory cell can be de-asserted. This can be combined, but is not limited to... Figures 4-5B At least one of them is used to describe the use of read select transistor 202C and write select transistor 202D to minimize or prevent leakage.

[0050] Figure 4 Illustrations are shown according to some embodiments Figure 1 An example schematic diagram of two eFuse cells (e.g., memory cells 200, 400) in memory array 102. Figures 5A-5B The diagram illustrates, according to some embodiments, that during operation, includes at least Figure 2 Example schematic diagrams 500A-B of a memory array of eFuse cells (e.g., memory cell 200). Figure 4Memory cell 400 may be included, which includes components or configurations similar to those of memory cell 200. For example, memory cell 400 may include transistors 402A-D (e.g., sometimes referred to as transistor 402) and resistor element 404, similar to transistor 202 and resistor element 204 of memory cell 200. Memory cells 200 and 400 may be in the same column within memory array 102.

[0051] like Figure 4 As shown, memory cells 200 and 400 within a column of memory cell 103 can share corresponding CG, BL, read select line, and write select line. Each row of memory cells 103 can share a corresponding WL. When one of memory cells 200 and 400 is selected, BL and CG can be asserted. The WL associated with the selected memory cell can be asserted, and other WLs associated with unselected memory cells can be left unset to a predefined voltage (or the assertion can be canceled).

[0052] During a write operation, write select transistors 202D and 402D can be asserted, and read select transistors 202C and 402C can be deasserted, allowing programming of selected memory cells (if not already programmed). The write level (WL) of unselected memory cells can be left unset to a predefined voltage (e.g., 0V), thus deasserting the corresponding access transistor 202A or 402A. During a read operation, write select transistors 202D and 402D can be deasserted, and read select transistors 202C and 402C can be asserted, thus disconnecting the gate terminal of the control gate transistors 202B and 402B. The write level (WL) associated with an unselected memory cell can be left unset to a predefined voltage. By disconnecting the gate terminal of the control gate transistor 202B or 402B associated with the unselected memory cell, leakage can be minimized or avoided during a read operation of another (selected) memory cell. For example, the access transistor 202A or 402A and the control gate transistor 202B or 402B of the unselected memory cell can be de-asserted, thereby blocking current flow, for example, instead of being in a half-selected state in the 2T configuration without switches.

[0053] Figures 5A-5B An example arrangement of WL, BL, CG, write select lines and read select lines connected to different memory cells 502 in a 64x64 memory array is shown. Figures 5A-5B The memory array can be of different sizes, not limited to a 64x64 memory array. Each memory cell 502 may include, in conjunction with, a memory array. Figure 2 and Figure 4At least one similar component or configuration of the memory cells 200, 400. Schematic diagram 500A may illustrate memory cell 502 during write or programming mode. During programming mode, the gate voltage (VG) of the gate transistor in memory cell 502 may be controlled by or set to the voltage of CG, which may be configured to be approximately half (or a small portion) of the voltage applied to BL. Therefore, unselected memory cells may be subjected to less BL stress, for example, when BL is asserted (e.g., set to a relatively high voltage) to program selected memory cells.

[0054] Schematic diagram 500B may illustrate memory cell 502 during read mode. In read mode, the VG of the control gate transistor can be controlled by WL, for example, depending on the voltage of WL. For unselected memory cells, the control gate transistor can be de-asserted by de-asserting WL (e.g., setting it to a low state below 0V or a predefined voltage). For selected memory cells, the control gate transistor can be asserted by applying a voltage of WL to the gate terminal of the control gate transistor, for example, VG can be substantially equal to the WL voltage. In this case, leakage in the unselected memory cell can be mitigated during read mode by de-asserting (or keeping the de-asserted) access transistor and control gate transistor in the unselected memory cell.

[0055] Figure 6 Illustrations are shown according to some embodiments Figure 1 An example schematic diagram of an eFuse cell (e.g., memory cell 600) having a p-channel metal-oxide-semiconductor (PMOS) switch in a memory array. Memory cell 600 may be one of the memory cells 103 in memory array 102. Memory cell 600 may include components combined with... Figures 2-5B The memory cell 600 may be one or more components or arrangements similar to or different from at least one of the memory cells 200, 400 or 502 (but not limited to). The memory cell 600 may be implemented in the memory array 102 as a supplement to or replacement of the memory cell 200.

[0056] Memory cell 600 may include transistors 602A-D (e.g., sometimes referred to as transistor 602) and a resistor element 604. Resistor element 604 may be at least similar to or different from resistor element 204 used for OTP programming. Transistors 602A-D may include access transistor 602A, control gate transistor 602B, read select transistor 602C, and write select transistor 602D. Access transistor 602A and control gate transistor 602B may be similar to transistors 202A-B of memory cell 200. In this case, read select transistor 602C and write select transistor 602D may be implemented using PMOS transistors. For PMOS transistors, each of the read and write select transistors 602C-D can be asserted by applying a corresponding predefined voltage at the gate terminal via the read / write select line, and deasserted by terminating or not applying the predefined voltage at the gate terminal. The operation of memory cell 600 during read or write modes may be similar to or combined with... Figures 2-5B At least one of them is described.

[0057] Figure 7 Illustrations are shown according to some embodiments Figure 1 An example schematic diagram of an eFuse cell (e.g., memory cell 700) with hybrid switching in a memory array. Memory cell 700 may be one of the memory cells 103 in memory array 102. Memory cell 700 may include one or more components or arrangements that are similar to or different from the combination Figures 2-6 The memory cell 200, 400, 502, or 600 described in at least one of the following (but not limited to) memory cells. The memory cell 700 may be implemented in the memory array 102 as a supplement to or replacement of the memory cell 200.

[0058] Memory cell 700 may include transistors 702A-D (e.g., sometimes referred to as transistor 702) and a resistive element 704. Resistive element 704 may be at least similar to or different from resistive element 204. Transistors 702A-D may be similar to transistors 202A-D, for example, including access transistor 702A, control gate transistor 702B, read select transistor 702C, and write select transistor 702D. In some configurations, read select transistor 702C and write select transistor 702D may be different types of transistors (e.g., a hybrid switch). For example, read select transistor 702C may be a PMOS transistor, and write select transistor 702D may be an NMOS transistor, or vice versa. A mode select line (e.g., labeled "RW") may be connected to the gate terminals of read and write select transistors 702C-D via different switches to assert one of transistors 702C-D and deassert the other.

[0059] For example, using read select transistor 702C as a PMOS transistor and write select transistor 702D as an NMOS transistor, memory cell 700 can operate in write mode by applying a logic "1" or setting a predefined voltage to the mode select line. By applying a predetermined voltage to the gate terminals of read and write select transistors 702C-D, read select transistor 702C can be de-asserted, and write select transistor 702D can be asserted. By terminating or blocking the voltage at the gate terminals of transistors 702C-D (or applying a logic "0"), read select transistor 702C can be asserted, and write select transistor 702D can be de-asserted.

[0060] For example, when the read select transistor 702C is an NMOS transistor and the write select transistor 702D is a PMOS transistor, applying a predetermined voltage at the gate terminal can keep the read and write select transistors 702C-D asserted and deasserted, respectively, while not applying a predetermined voltage at the gate terminal can keep the read and write select transistors 702C-D deasserted and asserted, respectively. The operation of the memory cell 700 during read or write modes can be similar to or combined with... Figures 2-6 At least one of them is described.

[0061] In some implementations, at least one inverter may be used or coupled to the gate terminal of at least one of the read select transistor 202C or write select transistor 202D of the same type. For example, to operate transistors 202C-D (e.g., NMOS transistors) similar to transistors 702C-D (e.g., transistor 702C is a PMOS transistor and transistor 702D is an NMOS transistor), a connection may be implemented, added, or otherwise made to the gate terminal of the read select transistor 202C such that a high signal can be inverted to a low signal and vice versa. In some other configurations, an inverter may be implemented at the gate terminal of the write select transistor 202D. Other types of circuitry or components may be used or implemented to achieve the desired features or functions discussed herein.

[0062] Figure 8 The diagram illustrates the relationship between [various embodiments] and [other embodiments]. Figure 1 An example schematic diagram of an eFuse cell (e.g., memory cell 800) coupled by switches 806A-B in a memory array. Memory cell 800 can be... Figure 1 It is part of the memory array 102 in circuit 100. As an illustrative example, Figure 8Four memory cells 800 may be shown, although more or fewer memory cells 800 may be included as part of circuitry 100. One or more of the memory cells 800 may include one or more components or features similar to at least one of memory cells 103, 200, 400, 502, 600, or 700. Each memory cell 800 may include two transistors, such as corresponding access transistors 802A, 802C, 802E, 802G and corresponding control gate transistors 802B, 802D, 802F, 802H, and a corresponding resistor element 804A-D (e.g., sometimes referred to as resistor element 804).

[0063] For example, resistor 804 can operate similarly to resistor 204. Transistors 802A-H may sometimes be referred to as transistor 802. The corresponding access and control gate transistors 802 can operate similarly to access transistor 202A and gate transistor 202B, respectively. As shown, a first memory cell may include transistors 802A-B and resistor 804A, a second memory cell may include transistors 802C-D and resistor 804B, a third memory cell may include transistors 802E-F and resistor 804C, and a fourth memory cell may include transistors 802G-H and resistor 804D.

[0064] To minimize leakage, for example at least during read mode, one or more switches 806 may be implemented to manage the CG voltage (e.g., manage current flow through the CG). Switches 806 may include one or more logics suitable for controlling the CG. Each switch 806 may be operated or controlled using a control signal from at least a mode select line (RW), for example, implementing features or functions similar to at least memory cell 200 according to at least the RW. Switches 806 may control the CG according to the RW and WL. Corresponding switches 806 may be implemented in corresponding rows of memory array 102, whereby controlling the CG may assert or deasserte one or more corresponding control gate transistors 802B, 802D, 802F, 802H. The CG may extend in a first direction parallel to the WL and perpendicular to the second direction of the BL.

[0065] For example, switch 806 can receive signals from WL and RW. A signal from WL can indicate whether at least one switch 806 in the corresponding row is selected. Switch 806 may not assert CG when there is no signal from WL or when WL is de-asserted. When WL is asserted, switch 806 can determine whether to assert CG by setting a predefined voltage for CG based on or according to RW (e.g., read mode or programming mode). The value or state of RW can indicate read mode or programming mode; for example, read mode is high and programming mode is low, or vice versa. Switch 806 can de-asserte CG during read mode.

[0066] During programming mode, switch 806 can assert CG to assert the gate terminals of one or more control gate transistors 802B, 802D, 802F, 802H. In this case, the corresponding one or more control gate transistors 802B, 802D, 802F, 802H can be deasserted during read mode and asserted during programming mode. By deasserting the control gate transistors 802B, 802D, 802F, 802H for unselected memory cells and / or during read mode (rather than leaving the memory cells in a half-selected state), potential leakage from BL to ground can be minimized or prevented.

[0067] In some configurations, one or more switches 806 can act as read and write select transistors 202C-D (e.g., at least in combination). Figure 2 The above can be implemented as a supplement or alternative to the above. In some configurations, the WL level shifter and CG level shifter (not shown) for controlling CG can be part of or included in the line control circuit 104. For example, switch 806 can be included as part of the line control circuit 104.

[0068] Figure 9 Illustrations are shown according to some embodiments Figure 1 An example schematic diagram of an eFuse cell (e.g., memory cell 900) having three transistors 902A-C in a memory array. Memory cell 900 may be one of the memory cells 103 of memory array 102. Memory cell 900 may include one or more components or features similar to (or different from) at least one of memory cells 103, 200, 400, 502, 600, 700, or 800. Memory cell 900 may include three transistors 902A-C (e.g., sometimes referred to as transistor 902) and a resistive element 904. Resistive element 904 may be similar to (or different from) resistive element 204 used for OTP operation.

[0069] The three transistors 902 may include two access transistors 902A-B and one control gate transistor 902C. The two access transistors 902A-B may be connected in series with the control gate transistor 902C and a resistive element 904. The gate terminals of the two access transistors 902A-B may be connected to WL. The access transistors 902A-B can be controlled based on a signal from WL. For example, each of the two access transistors 902A-B may include at least one coupled to... Figure 2 The access transistor 202A has similar features or functions. Access transistors 902A-B can perform similar operations to each other.

[0070] For example, the control gate transistor 902C may include at least [a combination of] Figure 2 The control gate transistor 202B has similar features or functions. Although shown as an NMOS transistor, transistor 902 can be other types of transistors, such as a PMOS transistor or a combination of NMOS and PMOS transistors. In some implementations, by implementing two access transistors, such as 902A-B, leakage from BL to ground can be minimized, at least during read operations. For example, if memory cell 900 is an unselected memory cell and control gate transistor 902C is asserted by the CG voltage, both access transistors 902A-C can remain in a deasserted state to prevent current from flowing from BL to ground, thereby minimizing or avoiding potential leakage. In some configurations, memory cell 900 may include more than two access transistors 902A-B.

[0071] Figure 10 Illustrations are shown according to some embodiments Figure 1 An example schematic diagram of an eFuse cell (e.g., 1000) comprising multiple access transistors and switches in a memory array. Memory cell 1000 may be one of memory cells 103 in memory array 102. Memory cell 1000 may include one or more components or features similar to (or different from) at least one of memory cells 103, 200, 400, 502, 600, 700, or 800. As shown, memory cell 1000 may include, but is not limited to, transistors 1002A-E (e.g., sometimes referred to as transistor 1002) and resistive element 1004. Resistive element 1004 may be similar to (or different from) resistive element 204 used for OTP operation.

[0072] Transistor 1002 may include, but is not limited to, at least two access transistors 1002A-B, at least one control gate transistor 1002C, at least one read select transistor 1002D, and at least one write select transistor 1002E. The read select transistor 1002D and the write select transistor 1002E may be switches that operate according to the operating mode of the memory cell 1000 (e.g., read or program mode). Although shown as an NMOS transistor, transistor 902 may be other types of transistors, such as a PMOS transistor or a combination of NMOS and PMOS transistors.

[0073] Memory cell 1000 can be configured as a combination similar to memory cells 200 and 900. For example, transistors 1002B-E can be interconnected and operate similarly to transistors 202A-D, respectively. In a further example, another access transistor (e.g., 1002A or 1002B) can be added, for example, similar to having transistors 902A-B. The operation of memory cell 1000 can be similar to the operation of memory cell 200.

[0074] For example, during read mode, read select transistor 1002D can be asserted, and write select transistor 1002E can be deasserted. During programmable mode, read select transistor 1002D can be deasserted, and write select transistor 1002E can be asserted. If memory cell 1000 (or another memory cell in the same row associated with memory cell 1000) is selected, WL can be asserted, thereby at least asserting access transistors 1002A-B (and control gate transistor 1002C during read mode). If memory cell 1000 or the row associated with memory cell 1000 is not selected, WL can be deasserted, thereby deasserting access transistors 1002A-B (and control gate transistor 1002C during read mode). At least during read mode, switches (e.g., read and write select transistors 1002D-E) and multiple access transistors 1002A-B can be used to minimize or prevent leakage from BL to ground.

[0075] It should be noted that the configurations or arrangements of the components of the various memory cells discussed herein may be mixed, combined, or otherwise integrated with each other, for example, as part of a memory cell configuration. In some embodiments, one or more different arrangements of the memory cells discussed herein may be implemented in the same or different memory arrays of one or more memory devices / circuits.

[0076] Figure 11 The following are examples of methods for using in some embodiments. Figures 1-10A flowchart of an example method 1100 for improving leakage tolerance is provided, illustrating how a memory device (e.g., device or circuit 100) including eFuse bit cells (e.g., at least one of memory cells 103, 200, 400, 502, 600, 700, 900, or 1000) can be formed in a stacked structure. The operation of method 1100 can be performed by the components described above, such as, but not limited to, those described above. Figures 1-10 At least one of them, therefore, some of the reference figures used above can be reused in the following discussion of method 1100. Furthermore, it should be understood that method 1100 has been simplified, therefore, it can be... Figure 1 Additional operations are provided before, during, and after method 1100. And only a few other operations may be briefly described here. It should also be noted that alternative operations may be provided as... Figure 11 This is part of method 1100.

[0077] Method 1100 begins with operation 1102, forming corresponding first portions of a plurality of memory cells (e.g., 103, 200, etc.) along the main surface of a semiconductor substrate. The first portion of each memory cell may include / contain an access transistor (e.g., at least one of 202A, 402A, etc.), a control gate transistor (e.g., at least one of 202B, 402B, etc.), a read select transistor (e.g., at least one of 202C, 402C, etc.), and a write select transistor (e.g., at least one of 202D, 402D, etc.). Each memory cell may include or correspond to an one-time programmable (OTP) memory cell. In some configurations, one or more memory cells may include multiple access transistors, and are not limited to a single access transistor.

[0078] Method 1100 continues to operation 1104, forming a corresponding second portion of a memory cell in one or more of a plurality of metallization layers disposed on the main surface. The second portion of each memory cell may include a resistive element (e.g., at least one of 204, 404, etc.). The resistive element may include or correspond to a fuse configured to store data. For OTP operation, the resistive element may fuse after programming, thereby producing a (permanent) resistance change representing the stored data.

[0079] Method 1100 continues to operation 1106, forming a plurality of word lines, BLs, read select lines, write select lines, and control gate lines in one or more metallization layers. Lines for connecting to one or more components of a memory cell within a column can be formed. In some embodiments, method 1100 may include forming a plurality of BLs, a plurality of read select lines, a plurality of write select lines, and a plurality of control gate lines (e.g., CGs) in one or more metallization layers in a memory device for connection to corresponding memory cells within a memory array (e.g., memory cells arranged in columns and rows). For example, memory cells may form a column spanning multiple rows, for example, at least as... Figure 4 As shown.

[0080] Method 1100 may include connecting WL to the gate terminals of the access transistors of the memory cell. Method 1100 may include connecting BL to the respective first source / drain terminals of a resistive element of the memory cell. Method 1100 may include connecting a read select line to the respective gate terminal of the read select transistor of the memory cell. Method 1100 may include connecting a write select line to the respective gate terminal of the write select transistor of the memory cell. Method 1100 may include connecting a control gate line to a respective source / drain terminal of the write select transistor of the memory cell.

[0081] Method 1100 may include connecting WL to respective first source / drain terminals of the read select transistors of the memory cell. Method 1100 may include connecting each of the corresponding second source / drain terminals of the read select transistors to the first source / drain terminal of a corresponding write select transistor in the memory cell. Method 1100 may include connecting the second source / drain terminal of the read select transistor and the first source / drain terminal of the write select transistor of each memory cell to the gate terminal of the gate select transistor of the corresponding memory cell.

[0082] For each memory cell, an access transistor, a control gate transistor, and a resistive element may be connected in series with each other. Method 1100 may include connecting the gate terminal of the access transistor and the gate terminal of the control gate transistor to the first and second source / drain terminals of the read select transistor, respectively. Method 1100 may include connecting the gate terminal of the control gate transistor and a corresponding one of CG to the first and second source / drain terminals of the write select transistor, respectively.

[0083] In various configurations, the access transistor, control gate transistor, and resistive element can be connected between ground voltage and BL (or a corresponding one of the BLs in the memory array). In some implementations, when a corresponding memory cell is selected for programming (e.g., programming mode) by at least one of the corresponding assertion word lines, the read select transistor can be turned off or de-asserted by a corresponding one of the read select lines (e.g., de-asserting the read select line or setting a relatively low voltage or no voltage on the read select line), while the write select transistor can be turned on or asserted by a corresponding one of the write select lines (e.g., asserting the write select line or setting a predefined voltage on the write select line). For example, when asserting the write select transistor and de-asserting the read select transistor, the corresponding voltages present on the gate terminal of the control gate transistor and CG can be substantially equal to each other. After de-asserting the read select transistor, the asserted WL can be disconnected from the gate terminal of the gate select transistor.

[0084] In some implementations, when a corresponding memory cell is selected for reading by asserting at least one corresponding word line, the read select transistor can be turned on or asserted by the corresponding one of the read select lines (e.g., asserting the read select line), and the write select transistor can be turned off or de-asserted by the corresponding one of the write select lines (e.g., de-asserting the write select line). For example, when the read select transistor is asserted and the write select transistor is de-asserted, the corresponding voltages present at the gate terminal of the control gate transistor and the corresponding WL can be substantially equal to each other. After de-asserting the write select transistor, CG can be disconnected from the gate terminal of the gate select transistor.

[0085] The read select line (WL) may extend along the first direction, while the read select line (CG), read select line (BL), and write select line (WC) may extend along a second direction perpendicular to the first direction. In some other configurations, one or more of the read select line (CG), read select line, or write select line may extend along the first direction. These lines may extend in other non-restrictive directions.

[0086] In some configurations, method 1100 may form a memory device including a first decoder, a second decoder, and at least one level shifter. The first decoder (e.g., a WL decoder) may be configured to receive and decode a first portion of an address signal. The second decoder (e.g., a BL decoder) may be configured to receive and decode a second portion of the address signal. At least one level shifter (e.g., a WL, BL, CG level shifter, etc.) may be configured to adjust the voltage in at least one of the WLs, at least one of the BLs, at least another of the CGs, at least one of the write select lines, or at least one of the read select lines, etc. The first decoder may be configured to select one or more WLs based on the first portion of the address signal. The second decoder may be configured to select one or more BLs based on the second portion of the address signal.

[0087] In some configurations, the read select transistor and the write select transistor can have the same conductivity type, such as n-type or p-type. In other configurations, the read select transistor and the write select transistor can have different conductivity types, such as a mixture of n-type and p-type transistors. In this configuration, the gate terminals of the read and write select transistors can be connected to a select line (e.g., a mode select line). For example, by asserting the mode select line, one of the read or write select transistors can be asserted, and the other can be deasserted. Similarly, by deasserting the mode select line, one of the read or write select transistors can be deasserted, and the other can be asserted. When the mode select line is asserted, which of the read or write select transistors is asserted can be based on the configuration of the memory cell.

[0088] Figure 12 A flowchart of an example method 1200 for operating a memory device (e.g., device or circuit 100) according to some embodiments is shown, the memory device including Figures 1-10 The eFuse bit cells in the stacked structure (e.g., at least one of memory cells 103, 200, 400, 502, 600, 700, 900, or 1000) are used to improve leakage tolerance. The operation of method 1200 can be performed by the components described above, such as, but not limited to, those described above. Figures 1-10 At least one of them, therefore, some of the reference figures used above can be reused in the following discussion of method 1200. Furthermore, it should be understood that method 1200 has been simplified, therefore, it can be... Figure 1 Additional operations are provided before, during, and after method 1200. And only a few other operations may be briefly described here. It should also be noted that alternative operations may be provided as... Figure 12 This is part of method 1200.

[0089] Method 1200 begins with operation 1202, selecting a memory cell from a plurality of memory cells (e.g., 103, 200, etc.). The selected memory cell can be programmed or read. Each memory cell may include an access transistor (e.g., at least one of 202A, 402A, etc.), a control gate transistor (e.g., at least one of 202B, 402B, etc.), a resistive element (e.g., at least one of 204, 404, etc.), a read select transistor (e.g., at least one of 202C, 402C, etc.), and a write select transistor (e.g., at least one of 202D, 402D, etc.), all electrically coupled to each other. For example, the access transistor, control gate transistor, and resistive element may be connected in series between a ground voltage and a corresponding BL (of the plurality of BLs). The gate terminal of the access transistor and the gate terminal of the control gate transistor may be connected to the first and second source / drain terminals of the read select transistor, respectively. The gate terminal of the control gate transistor and the corresponding control gate line may be connected to the first and second source / drain terminals of the write select transistor, respectively. The gate terminal of the access transistor and the first source / drain terminal of the read select transistor can be connected to the corresponding WL (among multiple WLs).

[0090] Method 1200 continues to operation 1204, asserting the read select transistor and deasserting the write select transistor during read mode / operation. The read select transistor can be asserted via the read select line, for example, by applying a predefined voltage to the read select line to enable the read select transistor. The write select transistor can be deasserted via the write select line, for example, by not applying voltage to the write select line, thereby disabling the write select transistor. When the read select transistor is deasserted and the write select transistor is asserted, a first voltage at the corresponding control gate line can be applied to the gate terminal of the control gate transistor. During the write operation, WL can be disconnected from the gate terminal of the gate select transistor.

[0091] Method 1200 continues to operation 1206, during write mode, deasserting the read select transistor and asserting the write select transistor. The read select transistor can be deasserted via the read select line, and the write select transistor can be asserted via the write select line. When the read select transistor is asserted and the write select transistor is deasserted, a second voltage on the corresponding WL can be applied at the gate terminal of the control gate transistor. The gate control line can be disconnected from the gate terminal of the gate select transistor during the read operation, thereby minimizing or avoiding leakage during the read operation of another (selected) memory cell.

[0092] In one aspect of this disclosure, a memory device is disclosed. The memory device includes a plurality of memory cells, each of the plurality of memory cells including an access transistor, a control gate transistor, a resistive element, a read select transistor, and a write select transistor; a plurality of word lines; a plurality of control gate lines; a plurality of bit lines; a plurality of read select lines; and a plurality of write select lines; wherein, for each of the plurality of memory cells, the access transistor, the control gate transistor, and the resistive element are connected in series with each other, the gate terminal of the access transistor and the gate terminal of the control gate transistor are respectively connected to the first source / drain terminal and the second source / drain terminal of the read select transistor, and the gate terminal of the control gate transistor and a corresponding control gate line are respectively connected to the first source / drain terminal and the second source / drain terminal of the write select transistor.

[0093] In some embodiments, each of the plurality of memory cells includes a one-time programmable memory cell.

[0094] In some embodiments, the gate terminal of the access transistor is connected to a corresponding word line.

[0095] In some embodiments, the access transistor, the control gate transistor, and the resistive element are connected between a ground voltage and a corresponding bit line.

[0096] In some embodiments, when a corresponding memory cell to be programmed is selected by asserting at least one corresponding word line, the read select transistor is turned off by the corresponding read select line, and the write select transistor is turned on by the corresponding write select line.

[0097] In some embodiments, the corresponding voltages present on the gate terminal of the control gate transistor and on the control gate line are substantially equal to each other.

[0098] In some embodiments, when a corresponding memory cell to be read is selected by asserting at least one of the corresponding word lines, the read select transistor is turned on by the corresponding read select line, and the write select transistor is turned off by the corresponding write select line.

[0099] In some embodiments, the corresponding voltages present on the gate terminal of the control gate transistor and on the corresponding word line are substantially equal to each other.

[0100] In some embodiments, word lines extend in a first direction, and control gate lines, bit lines, read select lines, and write select lines extend in a second direction perpendicular to the first direction.

[0101] In some embodiments, the memory device further includes: a first decoder configured to receive and decode a first portion of an address signal; a second decoder configured to receive and decode a second portion of the address signal; and at least one level shifter configured to adjust the voltage in at least one word line, at least one bit line, at least one control gate line, at least one write select line, or at least one read select line, wherein the first decoder is configured to select one or more word lines based on the first portion of the address signal, and the second decoder is configured to select one or more bit lines based on the second portion of the address signal.

[0102] In some embodiments, the read select transistor and the write select transistor have the same conductivity type.

[0103] In another aspect of this disclosure, a memory device is disclosed. The memory device includes a plurality of memory cells, each memory cell including an access transistor, a control gate transistor, a resistive element, a read select transistor, and a write select transistor, wherein the plurality of memory cells are respectively coupled to a plurality of word lines and are commonly coupled to a bit line, a read select line, a write select line, and a control gate line.

[0104] In some embodiments, a plurality of memory cells are arranged along a first direction, bit lines, read select lines, write select lines and control gate lines extend along the first direction, and word lines extend along a second direction perpendicular to the first direction.

[0105] In some embodiments, when one of a plurality of memory cells to be programmed is selected by asserting at least one corresponding word line, the read select line is de-asserted and the write select line is asserted such that the corresponding voltages present on the gate terminal of the gate select transistor and on the gate select line are equal to each other.

[0106] In some embodiments, the assertion word line is disconnected from the gate terminal of the gate select transistor.

[0107] In some embodiments, when one of a plurality of memory cells to be read is selected by asserting at least one corresponding word line, the read select line is asserted and the write select line is deasserted such that the corresponding voltages present at the gate terminal of the gate select transistor and the corresponding word line are equal to each other.

[0108] In some embodiments, the control gate line is disconnected from the gate terminal of the gate select transistor.

[0109] In another aspect of this disclosure, a method for operating a memory device is disclosed. The method includes selecting a memory cell from a plurality of memory cells, each memory cell including an access transistor, a control gate transistor, a resistive element, a read select transistor, and a write select transistor electrically coupled to each other; during a read mode: asserting a read select transistor via a read select line; and deasserting a write select transistor via a write select line; during a write mode: deasserting a read select transistor via a read select line; and asserting a write select transistor via a write select line.

[0110] In some embodiments, the access transistor, the control gate transistor, and the resistive element are connected in series between a ground voltage and a corresponding bit line; the gate terminal of the access transistor and the gate terminal of the control gate transistor are respectively connected to the first source / drain terminal and the second source / drain terminal of the read select transistor; the gate terminal of the control gate transistor and the corresponding control gate line are respectively connected to the first source / drain terminal and the second source / drain terminal of the write select transistor; and the gate terminal of the access transistor and the first source / drain terminal of the read select transistor are connected to the corresponding word line.

[0111] In some embodiments, when an assertion read select transistor is canceled and an assertion write select transistor is canceled, a first voltage at the corresponding control gate line is applied to the gate terminal of the control gate transistor; and when an assertion read select transistor is canceled and an assertion write select transistor is canceled, a second voltage at the corresponding word line is applied to the gate terminal of the control gate transistor.

[0112] As used herein, the terms “about” and “approximately” generally refer to the value of a given quantity that can vary depending on the specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term “about” can refer to a given quantity of value, for example, varying within a range of 10-30% of the value (e.g., +10%, ±20%, or ±30% of the value).

[0113] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them within this disclosure without departing from its spirit and scope.

Claims

1. A memory device, comprising: A plurality of memory cells, each of the plurality of memory cells including an access transistor, a control gate transistor, a resistive element, a read select transistor, and a write select transistor; Multiple character lines; Multiple control gate lines; Multiple bit lines; Multiple read selection lines; as well as Multiple write select lines, In each of the plurality of memory cells, the access transistor, the control gate transistor, and the resistive element are connected in series with each other. The gate terminal of the access transistor and the gate terminal of the control gate transistor are respectively connected to the first source / drain terminal and the second source / drain terminal of the read select transistor. The gate terminal of the control gate transistor and a corresponding one of the control gate lines are respectively connected to the first source / drain terminal and the second source / drain terminal of the write select transistor.

2. The memory device according to claim 1, wherein, The access transistor, the control gate transistor, and the resistive element are connected between the ground voltage and a corresponding one of the bit lines.

3. The memory device according to claim 1, wherein, When a corresponding memory cell to be programmed is selected by asserting at least one of the corresponding word lines, the read select transistor is turned off by the corresponding one of the read select lines, and the write select transistor is turned on by the corresponding one of the write select lines.

4. The memory device according to claim 3, wherein, The corresponding voltages present on the gate terminal of the control gate transistor and on the control gate line are substantially equal to each other.

5. The memory device according to claim 1, wherein, When a corresponding memory cell to be read is selected by asserting at least one of the corresponding word lines, the read select transistor is turned on by the corresponding one of the read select lines, and the write select transistor is turned off by the corresponding one of the write select lines.

6. The memory device according to claim 1, wherein, The word line extends in a first direction, and the control gate line, the bit line, the read select line, and the write select line extend in a second direction perpendicular to the first direction.

7. The memory device according to claim 1, further comprising: The first decoder is configured to receive and decode the first part of the address signal; The second decoder is configured to receive and decode a second portion of the address signal; as well as At least one level shifter is configured to adjust the voltage in at least one of the word lines, at least one of the bit lines, at least one of the control gate lines, at least one of the write select lines, or at least one of the read select lines. The first decoder is configured to select one or more word lines based on a first portion of the address signal, and the second decoder is configured to select one or more bit lines based on a second portion of the address signal.

8. A memory device, comprising: Multiple memory cells, each of which includes an access transistor, a control gate transistor, a resistive element, a read select transistor, and a write select transistor. The plurality of memory cells are coupled to a plurality of word lines, and are jointly coupled to a bit line, a read select line, a write select line and a control gate line.

9. The memory device according to claim 8, wherein, The plurality of memory cells are arranged along a first direction, the bit lines, the read select lines, the write select lines and the control gate lines extend along the first direction, and the word lines extend along a second direction perpendicular to the first direction.

10. A method of operating a memory device, comprising: Selecting a memory cell from a plurality of memory cells, the memory cell comprising an access transistor, a control gate transistor, a resistive element, a read select transistor, and a write select transistor electrically coupled to each other; During read mode: the read select transistor is asserted via the read select line; and the write select transistor is deasserted via the write select line; as well as During write mode: the read select transistor is de-asserted via the read select line; and the write select transistor is asserted via the write select line.

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