Memory device and method of accessing the same

Abstract

Embodiments of the present invention provide a memory device that divides memory subarrays by an IO control system and address decoders to shorten the length of subarray word lines and bit lines to improve access speed. The memory device can include a plurality of macros having four memory subarrays including word lines and bit lines, a first address decoder located between and connected to word lines of two upper memory subarrays, a second address decoder located between and connected to word lines of two lower memory subarrays, and an IO control system, the two upper memory subarrays and the first address decoder being located on a first side of the IO control system, the two lower memory subarrays and the second address decoder being located on a second side of the IO control system opposite the first side. Embodiments of the present invention also provide a method of accessing a memory device.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to the semiconductor field, and more specifically, to storage devices and methods of accessing them. Background Technology

[0002] Integrated circuits, such as static random access memory (SRAM) devices, typically consist of arrays of memory cells. The array of memory cells is arranged as rows of word lines and columns of bit lines. To initiate access to a memory cell, word lines are connected to an address decoder, such as a word line select circuit, while bit lines are connected to input / output (I / O) circuitry. Summary of the Invention

[0003] An embodiment of the present invention provides a memory device, comprising: a first macro, including: a first memory subarray; a second memory subarray separated from the first memory subarray in a first direction; a third memory subarray; a fourth memory subarray separated from the third memory subarray in the first direction; a first address decoder located between the first memory subarray and the second memory subarray in the first direction; a second address decoder located between the third memory subarray and the fourth memory subarray in the first direction; and a first input / output (IO) control system located between the first address decoder and the second address decoder in a second direction intersecting the first direction, wherein the first IO control system is configured to access the first memory subarray and the second memory subarray through the first address decoder, and to access the third memory subarray and the fourth memory subarray through the second address decoder; and a second macro, including: a fifth memory subarray abutting against the third memory subarray in the second direction; and a sixth memory subarray. A third address decoder is located between the fifth and sixth memory subarrays in the first direction; a fourth address decoder is located between the seventh and eighth memory subarrays in the first direction; and a second I / O control system is located between the third and fourth address decoders in the second direction, wherein the second I / O control system is configured to access the fifth and sixth memory subarrays through the third address decoder and to access the seventh and eighth memory subarrays through the fourth address decoder, wherein the memory devices include a total number of bit lines, and the first macro and the second macro allocate the total number of bit lines such that the first macro includes a first portion of the total number of bit lines, and the second macro includes a second portion of the total number of bit lines.

[0004] Another embodiment of the present invention provides a method for accessing a memory device, comprising: determining a memory cell; determining a word line and a bit line of the memory cell; activating a first memory subarray, a second memory subarray, a third memory subarray, a fourth memory subarray, a fifth memory subarray, a sixth memory subarray, a seventh memory subarray, or an eighth memory subarray to access the memory cell according to the word line and the bit line of the memory cell; and wherein, according to the word line and the bit line of the memory cell, a first input / output I / O control system activates the first memory subarray, the second memory subarray, the third memory subarray, or the fourth memory subarray, or a second I / O control system activates the fifth memory subarray, the sixth memory subarray, the seventh memory subarray, or the eighth memory subarray. Another embodiment of the present invention provides a storage device comprising: a plurality of macros, each of which includes: a macro array of memory cells including four memory subarrays; a first address decoder located between two upper memory subarrays of the four memory subarrays; a second address decoder located between two lower memory subarrays of the four memory subarrays; an input / output (I / O) control system positioned such that the two upper memory subarrays and the first address decoder are located on a first side of the I / O control system, while the two lower memory subarrays and the second address decoder are located on a second side of the I / O control system relative to the first side, wherein the I / O control system includes: an I / O interface configured to interface with external components; a global I / O circuit connected to a plurality of bit lines of the four memory subarrays and configured to access the bit lines; and a global control circuit configured to control the global I / O circuit and one or both of the first address decoder and the second address decoder. Attached Figure Description

[0005] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0006] Figure 1A This is a cell diagram of an exemplary storage device according to embodiments of the present disclosure;

[0007] Figure 1B This is a cell diagram of an exemplary access loop path of a storage device according to an embodiment of the present disclosure;

[0008] Figure 1C This is a cell diagram of another exemplary storage device according to an embodiment of the present disclosure;

[0009] Figure 1D This is a cell diagram of an exemplary access loop path of another storage device according to an embodiment of the present disclosure;

[0010] Figure 2 This is a circuit diagram of the storage device in FIG1 according to an embodiment of the present disclosure;

[0011] Figure 3 According to embodiments of this disclosure Figure 1A and Figure 1C Cell diagrams of other exemplary aspects of storage devices;

[0012] Figure 4A According to embodiments of this disclosure Figure 1A and Figure 1C A unit diagram of an exemplary I / O control system;

[0013] Figure 4B According to embodiments of this disclosure Figure 1A and Figure 1C A unit diagram of an exemplary IO control system;

[0014] Figure 4C According to embodiments of this disclosure Figure 1A and Figure 1C A cell diagram of an exemplary access path;

[0015] Figure 5 According to embodiments of this disclosure Figure 1A and Figure 1C Waveform diagrams of exemplary signals generated by the internal components;

[0016] Figure 6 Access according to embodiments of this disclosure Figure 1A and Figure 1C A flowchart of an exemplary method for a storage device;

[0017] Figure 7 This is a flowchart of an exemplary storage device method according to an embodiment of the present disclosure. Detailed Implementation

[0018] This invention provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0020] Storage devices, such as static random access memory (SRAM) devices, have memory cells arranged in columns and rows. In a further example, each memory cell may include 6 transistors, 8 transistors, or 10 transistors connected between an upper reference potential and a lower reference potential (usually ground), such that one of the two storage nodes can be occupied by the information to be stored, while complementary information is stored in the other storage node.

[0021] To initiate access to memory cells, rows of memory cells are connected to an address decoder (e.g., a row decoder, word line decoder) via word lines. Additionally, columns of memory cells are connected to an input / output (I / O) block via bit lines. Therefore, the bit lines of each column of a memory array are coupled to multiple memory cells located in the corresponding column, and each memory cell in the corresponding column is located in a different row and coupled to a corresponding word line. Typically, the bit lines extend along a first direction (parallel to a first axis), while the word lines extend along a second direction perpendicular to the first direction (parallel to a second axis).

[0022] I / O blocks, such as I / O control systems, can be connected to control systems that implement the control logic of the memory architecture. For example, the global I / O circuitry of an I / O block can be connected to a global control system that implements the control logic of the memory devices.

[0023] Memory device access speed can be limited by the size of the memory array, for example, because access speed is affected by the number of memory cells per word line. As process technology advances to more advanced levels, and high-speed and high-bandwidth applications require wider bandwidth I / O, there may be a need to increase the speed of memory devices. Exemplary applications include artificial intelligence applications, central processing unit (CPU) applications (e.g., CPU-side cache), and similar applications that can use 7nm chips (N7), 5nm chips (N5), 3nm chips (N3), 2nm chips (N2), and so on. Speed ​​improvements in memory devices are influenced by word line resistance-capacitance (RC). While access speeds can increase with I / O bandwidth and application complexity, there are limitations.

[0024] To improve access speed, a memory array may include multiple memory subarrays, each with fewer memory cells in each corresponding word line and / or bit line, compared to a single memory array with the same overall size and equivalent number of memory cells. Therefore, access time (e.g., TCD) and cycle time (e.g., TCYC) can be improved using the disclosed embodiments. To form subarrays, the memory may include multiple macroarrays, each macroarray having a memory array composed of memory subarrays. Each macroarray may include two central address decoders, each located between two subarrays and connected to the word lines of the corresponding subarrays. Because the address decoders are central decoders, their placement effectively reduces the word line length of the subarrays (i.e., fewer memory cells per word line in the subarray), lowering the word line RC.

[0025] In a further development, the two memory subarrays in the macro are located on the first side of the I / O block, while the other two memory subarrays in the macro are located on the second side of the I / O block opposite the first side. This presents a folded architecture. The folded architecture shortens the bit line length, shortens the word line length (e.g., because the subarrays in the macro can share all memory cells), eliminates the need for global bit lines, improves memory performance, and so on. In certain examples, read bit lines can be fly read bit lines to reduce bit line RC.

[0026] Memory devices can include multiple macros to further reduce word line and / or bit line lengths by having more memory subarrays sharing the number of memory cells. For example, a memory device can include two macros, where each subarray word line has 64 memory cells and each bit line has 32 memory cells. In other examples, a memory device can include four macros, where each subarray word line has 32 memory cells and each bit line has 32 memory cells. Therefore, a folded architecture using macros can halve the word line length (i.e., from 128 memory cells to 64 memory cells), while increasing the memory device from two macros to four macros halves the word line length (i.e., from 64 memory cells to 32 memory cells). When word line cell loading doubles, the word line RC increases by approximately four times (i.e., doubled resistance multiplied by doubled capacitance equals a fourfold increase in word line RC). Therefore, a macro architecture for a memory device can significantly reduce word line RC (i.e., from 4RC to 1RC by implementing the memory device with two macros). For example, assuming a given word line latency is approximately 20% of the access time latency, a quarter word line latency will reduce access time latency by 15%. This accelerates access time and cycle time, for instance, when memory macros employ high-bandwidth I / O in high-speed memory applications. Shorter word line and / or bit line lengths can also improve signal transmission speed in addition to increasing access speed.

[0027] Each macro has an independent I / O block. For example, the word lines in the first and second macros of a storage device are independent of each other and can be enabled simultaneously or separately. This shortens the memory access path and allows multiple access operations to occur concurrently. In a particular example, when the number of data bits is less than the number of bits in the macro, only one macro's word line (e.g., the upper macro) is enabled. When the number of data bits is more than the number of bits in the macro, both macros' word lines (e.g., the upper and lower macros) are enabled.

[0028] During access operations, all memory subarrays can be accessed simultaneously, selecting bit lines from the upper subarray and bit lines from the lower subarray. The macro memory architecture enables startup control of the left and right I / O blocks to further conserve startup power. As the number of central address decoders increases, the area used by the decoders increases. However, when the number of I / O blocks is large, the area implementing the central address decoder can be significantly smaller than the area implementing non-central decoders, allowing for a reduction in the size of the memory device.

[0029] Figure 1A This is a cell diagram of an exemplary storage device 100. The storage device 100 includes multiple memory subarrays 102, multiple address decoders 104, and multiple I / O control systems 110.

[0030] Memory device 100 stores data that can be used by computing devices. For example, memory device 100 may be an SRAM device, which uses latch circuitry, such as flip-flops, to store data for each bit. Furthermore, the data is stored statically and does not require updates as needed by dynamic random access memory (DRAM). Memory subarray 102 may be an SRAM array employing multiple SRAM memory cells. However, within the scope of this disclosure, memory subarray 102 may be implemented as any memory cell array (e.g., DRAM, MRAM, RRAM, etc.). For example, memory subarray 102 may be implemented as a read-only memory (ROM) array, a logic N-type metal-oxide-semiconductor (NMOS) array, a logic P-type metal-oxide-semiconductor (PMOS) array, or a combination thereof.

[0031] The memory device 100 may include any number of macros to reduce the length of word lines and / or bit lines of the memory subarrays 102. Each macro may include four memory subarrays 102, two address decoders 104, and an I / O control system 110. A first address decoder 104 is located between two upper memory subarrays 102, and a second address decoder 104 is located between two lower memory subarrays 102. Thus, the first address decoder 104 separates the two upper memory subarrays 102 in a first direction (e.g., vertical), while the second address decoder 104 separates the two lower memory subarrays 102 in the same first direction. The first address decoder 104 and the two upper memory subarrays 102 are located on a first side of the I / O control system 110, while the second address decoder 104 and the two lower memory subarrays 102 are located on a second side of the I / O control system 110 relative to the first side. Thus, the I / O control system 110 separates the elements on the first side from the elements on the second side in a second direction perpendicular to the first direction (e.g., horizontal).

[0032] Figure 1AThe exemplary storage device 100 shown includes a first macro 120 (e.g., an upper macro) and a second macro 122 (e.g., a lower macro). The first macro 120 includes an address decoder 104a between upper memory subarrays 102a and 102b, an address decoder 104b between upper memory subarrays 102a and 102b, a address decoder 104b between lower memory subarrays 102c and 102d, and an I / O control system 110a. The upper memory subarrays 102a, 102b, and address decoder 104a are located on a first side of the I / O control system 110a, and the lower memory subarrays 102c, 102d, and address decoder 104b are located on a second side of the I / O control system 110a. The second macro 122 includes an address decoder 104c between the upper memory subarray 102e and the upper memory subarray 102f, an address decoder 104d between the upper memory subarray 102e and the upper memory subarray 102f, a lower memory subarray 102g and the lower memory subarray 102h, an address decoder 104d between the lower memory subarray 102g and the lower memory subarray 102h, and an I / O control system 110b. The upper memory subarray 102e, the upper memory subarray 102f, and the address decoder 104c are located on the first side of the I / O control system 110b, and the lower memory subarray 102g, the lower memory subarray 102h, and the address decoder 104d are located on the second side of the I / O control system 110b. The arrangement of the first macro 120 and the second macro 122 makes the memory subarray 102c, memory subarray 102d and address decoder 104b adjacent to (e.g., abutting) the memory subarray 102e, memory subarray 102f and address decoder 104c.

[0033] The I / O control system 110 and the address decoder 104 are operable to access memory cells in the memory subarray 102 using access paths, such as performing write or read operations. In some embodiments, the access path may include an address input signal to select a word line (i.e., an input signal from the I / O control system 110 and operated by the address decoder 104) and a data path to read or write data to a memory cell (i.e., the memory cell is accessed by the I / O control system 110 via a bit line).

[0034] Figure 1BAn exemplary access path 150 of storage device 100 is shown. For example, memory cells of memory subarray 102a are accessed via access path 150a (e.g., data is read from or written to memory cells). Similarly, memory cells of memory subarray 102d are accessed via access path 150b, memory cells of memory subarray 102f are accessed via access path 150c, and memory cells of memory subarray 102g are accessed via access path 150d. Any memory cell of any memory subarray 102 can be accessed via access path 150.

[0035] The maximum and average length of access path 150, as described above, is shorter than other configurations of a single memory array or memory subarray with an equivalent number of memory cells because the first macro 120 and the second macro 122 have shorter word lines and / or bit lines. The shorter word lines and / or bit lines may be due to multiple macros, independent I / O control system 110, central address decoder 104, the folded architecture of macros 120 and 122, and the memory subarray 102 having fewer memory cells per corresponding word line and / or bit line compared to a single memory array. The shorter access path 150 improves the speed of reading or writing data to memory cells in the memory device.

[0036] Because the I / O control system 110a operates independently of the I / O control system 110b, multiple access paths can be used simultaneously to perform multiple access operations. For example, the I / O control system 110a can perform an operation using access path 150a or access path 150b, while the I / O control system 110b can perform an operation using access path 150c or access path 150d.

[0037] Figure 1C This is a cell diagram of another exemplary storage device 100. Figure 1CThe exemplary storage device 100 shown includes a first macro 120, a second macro 122, a third macro 124, and a fourth macro 126. The third macro 124 includes upper memory subarrays 102i and 102j, an address decoder 104e located between upper memory subarrays 102i and 102j, lower memory subarrays 102k and 102l, an address decoder 104f located between lower memory subarrays 102k and 102l, and an I / O control system 110c. The upper memory subarrays 102i and 102j and the address decoder 104e are located on a first side of the I / O control system 110c, while the lower memory subarrays 102k and 102l and the address decoder 104f are located on a second side of the I / O control system 110c. The fourth macro 126 includes upper memory subarrays 102m and 102n, an address decoder 104g located between upper memory subarrays 102m and 102n, lower memory subarrays 102o and 102p, an address decoder 104h located between lower memory subarrays 102o and 102p, and an I / O control system 110d. Upper memory subarrays 102m and 102n and the address decoder 104g are located on the first side of the I / O control system 110d, while lower memory subarrays 102o and 102p and the address decoder 104h are located on the second side of the I / O control system 110d. The arrangement of the first macro 120, the second macro 122, the third macro 124, and the fourth macro 126 is such that memory subarrays 102c, 102d, and address decoder 104b are adjacent to memory subarrays 102e, 102f, and 104c; memory subarrays 102g, 102h, and 104d are adjacent to memory subarrays 102i, 102j, and 104e; and memory subarrays 102k, 102l, and 104f are adjacent to memory subarrays 102m, 102n, and 104g.

[0038] Storage device 100 may include any number of macros to reduce the length of word lines and / or bit lines, for example, depending on the access speed requirements or other required operating characteristics of storage device 100. The lengths of the bit lines and word lines of exemplary storage device 100 will be detailed below.

[0039] Figure 1D Showing Figure 1CThe exemplary access path 150 of the storage device 100 is shown. In addition to access paths 150a, 150b, 150c, and 150d for accessing memory cells in the first macro 120 and the second macro 122, there may also be an access path 150 for accessing memory cells in the third macro 124 and the fourth macro 126. For example, memory cells of memory subarray 102j are accessed via access path 150e, memory cells of memory subarray 102l are accessed via access path 150f, memory cells of memory subarray 102m are accessed via access path 150g, and memory cells of memory subarray 102o are accessed via access path 150h. Any memory cell of any memory subarray 102 can be accessed via access path 150.

[0040] Figure 1C The maximum length and average length of the access path 150 of the storage device 100 shown, and similarly described above, can be compared with those having the same total number of memory cells. Figure 1A and Figure 1B The illustrated memory device is shorter because the memory cells are further distributed between the third macro 124 and the fourth macro 126. The reduced word line and / or bit line lengths are likely due to the multiple macros, the independent I / O control system 110, the central address decoder 104, the folded architecture of macros 120 and 122, and the fewer memory cells per corresponding word line and / or bit line compared to a single memory array. The shorter access paths 150 improve the speed of reading and writing data to the memory cells of the memory device.

[0041] Because I / O control system 110a operates independently of I / O control system 110b, multiple access paths can be used simultaneously to perform multiple access operations concurrently. For example, I / O control system 110a can use access path 150a or access path 150b to perform an operation, while I / O control system 110b uses access path 150c or access path 150d to perform an operation, while I / O control system 110c uses access path 150e or access path 150f to perform an operation, and while I / O control system 110d uses access path 150g or access path 150h to perform an operation.

[0042] Figure 2 An exemplary memory cell 200 of the storage device 100 is shown. In the example shown, the memory cell 200 is located above and below the I / O control system 110. For example, the upper memory cell 200 may be part of memory subarray 102a, while the lower memory cell 200 may be part of memory subarray 102c. Therefore, to illustrate the memory cell 200 present in each memory subarray 102, Figure 2The example shown only shows a portion of the memory device 100. The memory cell 200 shown includes 6 transistors, but in other examples, the memory cell 200 of the memory subarray 102 may include more or fewer transistors.

[0043] Memory cell 200 is connected to word line 202, bit line (BL) 204a, and complementary bit line (BLB) 204b. Word line 202 is connected to a corresponding address decoder 104, and bit line 204a and complementary bit line 204b are connected to I / O control system 110. I / O control system 110 may include a data input terminal 210 for receiving data to access memory cell 200, such as receiving data to write to memory subarray 102. I / O control system 110 may also include an output terminal 212 for outputting data, such as outputting data read from memory subarray 102.

[0044] Memory cell 200 includes NMOS transistors 206a, 206b, 206c, and 206d, and PMOS transistors 208a and 208b. NMOS transistors 206c and 208a are coupled to each other and located between an upper reference potential (e.g., supply voltage VDD) and a lower reference potential (e.g., ground) to form a first inverter. Similarly, NMOS transistors 206d and 208b are coupled between the upper and lower reference potentials to form a second inverter. These two inverters are cross-coupled to each other. NMOS transistor 206a acts as an access transistor, connecting the output of the first inverter to bit line 204a. Similarly, NMOS transistor 206b acts as an access transistor, connecting the output of the second inverter to complementary bit line 204b. Word line 202 is connected to the gate terminals of access transistors 206a and 206b to selectively couple the output of the inverter to bit line 204a and complementary bit line 204b during read / write operations. For example, during a write operation, the inverter drives the voltage levels of bit line 204a and complementary bit line 204b.

[0045] The cross-coupled inverters of memory cell 200 provide two stable voltage states, denoted as logic values ​​0 and 1. Metal-oxide-semiconductor field-effect transistors (MOSFETs) are typically used as transistors in memory cell 200. In some embodiments, memory cell 200 may be implemented using more or fewer than six transistors.

[0046] Figure 3 This is a unit diagram of other aspects of the storage device 100. Specifically, Figure 3Macros 300 (e.g., first macro 120, second macro 122, etc.) are shown. Each of the memory subarrays 102 of macros 300 (e.g., memory subarrays 102a, 102b, 102c, 102d, 102e, 102f, 102g, and 102h, or similar) includes a plurality of memory cells 200 arranged in an array having a row-column configuration. Each column has bit lines 204a and complementary bit lines 204b, respectively coupled to the memory cells 200 disposed in that row, and each row has word lines 202. Each memory cell 200 in a column is arranged in a different row and coupled to a corresponding (different) word line 202. Thus, each memory cell 200 is coupled to the bit lines 204a and complementary bit lines 204b of a column and the word line 202 of a row in one of the memory subarrays 102. In some embodiments, bit lines 204a and complementary bit lines 204b are arranged vertically parallel, while word lines 202 are arranged horizontally parallel (i.e., perpendicular to bit lines 204a and complementary bit lines 204b). Bit lines 204a and complementary bit lines 204b of the memory subarray 102 extend directly to the I / O control system 110 so that the I / O control system 110 selects a column (e.g., bit lines 204a and / or complementary bit lines 204b) during access operations and other operations. Word lines 202 of the memory subarray 102 extend directly to the address decoder 104 so that the corresponding address decoder 104 selects word lines 202 when performing access operations.

[0047] In a specific paradigm, Figure 1AThe memory device 100 shown comprises memory subarrays 102a, 102b, 102c, 102d, 102e, 102f, 102g, and 102h, forming a memory array with a total of 256 bit lines (e.g., 256 bit lines 204a and 256 complementary bit lines 204b). Each of the memory subarrays 102a, 102b, 102c, 102d, 102e, 102f, 102g, and 102h can have 64 bit lines to form the overall size of the 256-bit memory array. Therefore, the memory device 100 has the desired overall size and fewer memory cells 200 per word line (e.g., 64 memory cells instead of 256 memory cells). In some embodiments, memory subarrays 102a, 102b, 102c, 102d, 102e, 102f, 102g, and 102h may have 32 word lines, resulting in each subarray having an array of 32×64 memory cells 200. In other examples, the sizes of memory subarrays 102a, 102b, 102c, 102d, 102e, 102f, 102g, and 102h may differ (i.e., they may have different numbers of memory cells 200). This includes instances where each memory subarray 102 is the same size in some examples, and different sizes in others.

[0048] In a specific paradigm, for Figure 1CThe memory device 100 shown comprises memory subarrays 102a, 102b, 102c, 102d, 102e, 102f, 102g, 102h, 102i, 102j, 102k, 102l, 102m, 102n, 102o, and 102p, forming a memory array with a total of 256 bit lines (e.g., 256 bit lines 204a and 256 complementary bit lines 204b). Each of memory subarrays 102a, 102b, 102c, 102d, 102e, 102f, 102g, 102h, 102i, 102j, 102k, 102l, 102m, 102n, 102o, and 102p can have 32 bit lines to form an overall size of a memory array with 256 bit lines. Therefore, the memory device 100 has the desired overall size while having fewer memory cells 200 per word line (e.g., 32 memory cells instead of 256 memory cells). For example, compared to... Figure 1A The storage device 100 shown, Figure 1C The memory device 100 shown has half the number of memory cells 200 in each bit line because the additional memory subarrays 102i, 102j, 102k, 102l, 102m, 102n, 102o, and 102p allow for further allocation of the total number of memory cells 200. Therefore, Figure 1C The storage device 100 shown may have a higher capacity than Figure 1A The storage device 100 shown has a faster access speed (e.g., a quarter word line RC).

[0049] In some embodiments, memory subarrays 102a, 102b, 102c, 102d, 102e, 102f, 102g, 102h, 102i, 102j, 102k, 102l, 102m, 102n, 102o, and 102p may have 32 word lines, so each subarray has a 32-by-32 array of memory cells 200. In other examples, the memory subarrays 102a, 102b, 102c, 102d, 102e, 102f, 102g, 102h, 102i, 102j, 102k, 102l, 102m, 102n, 102o, and 102p may have different sizes (i.e., different numbers of memory cells 200), including some examples where each subarray has the same size, and other examples where the subarrays have different sizes.

[0050] Figure 4A and Figure 4B This is a unit diagram of the I / O control system 110 of the storage device 100. The I / O control system 110 includes an I / O interface 402, a global I / O circuit 404, and a global control circuit 406. Figure 4B An exemplary configuration of the components of the I / O control system 110, the memory subarray 102, and the address decoder 104 is shown.

[0051] The I / O control system 110 has a first side 410 (or upper side) and a second side 412 (or lower side) relative to the first side 410. The first side 410 receives bit lines (e.g., bit line 204a and complementary bit line 204b) from a plurality of memory subarrays 102. For example, the first side 410 receives bit lines from memory subarrays 102a and 102b. The second side 412 receives bit lines (e.g., bit line 204a and complementary bit line 204b) from a plurality of memory subarrays 102. For example, the second side 412 receives bit lines from memory subarrays 102c and 102d. Therefore, the memory device 100 provides a folded memory array arrangement by horizontally extending through a macro to allocate the location of I / O control blocks of the memory subarrays 102, and by segmenting the folded memory architecture of the memory device 100. In the folded arrangement, the I / O control system 110 receives bit lines directly from the memory subarray 102, allowing the bit line length to be shortened to approximately half compared to the conventional arrangement where bit lines extend to I / O blocks located at one end of the memory array. The address decoder 104 is also centrally located, extending vertically to divide the two corresponding memory subarrays 102 and connecting to the word lines of the corresponding memory subarray 102. Multiple I / O control systems 110 and address decoders 104 are arranged to access multiple memory subarrays 102, allowing the word line and / or bit line lengths of the memory subarrays 102 to be shorter than in other memory array configurations, thus improving access speed.

[0052] I / O interface 402 interfaces with components external to memory device 100. For example, I / O interface 402 may receive signals requesting access to memory device 100, such as read or write operations, and may also transmit signals, such as data read from memory subarray 102. I / O interface 402 may be configured to process electrical signals, level shifting, electrostatic discharge protection, buffering, protocol conversion, and / or similar functions. Global I / O circuitry 404 may interface with I / O interface 402 and memory subarray 102 for access operations. Global I / O circuitry 404 includes bit line discharge elements, a sense amplifier for reading data stored in memory cell 200, a write driver for writing data to memory cell 200, and an output latch, and similar components. Global I / O circuitry 404 may be connected to the bit lines of memory subarray 102 to read and write data in memory cell 200.

[0053] Global control circuitry 406 can use input signals (e.g., chip-level input signals) received from I / O interface 402 to generate appropriate internal signals to perform the requested operation. Global control circuitry 406 can be connected to a corresponding I / O interface 402, a corresponding global I / O circuitry 404, and a corresponding address decoder 104 to output signals or otherwise control (e.g., coordinate) the behavior of elements to perform the requested operation. Global I / O circuitry 404 is configured to receive or otherwise determine column addresses (e.g., specific bit lines) to access the relevant operation and access the corresponding bit line to perform the relevant operation (e.g., activating one or more access transistors coupled to the bit line). In an exemplary embodiment, the elements of global I / O circuitry and / or I / O control system 110 include a bit line decoder for selecting the corresponding bit line.

[0054] Address decoder 104 is configured to receive a row address (e.g., a specific word line) to access the corresponding word line at that row address to perform a related operation (e.g., activating one or more access transistors coupled to the word line). For example, in a read operation, I / O control system 110 may decode the selected bit line based on the received bit line address, while address decoder 104 may decode the selected word line based on the received word line address.

[0055] Various components of the I / O control system 110 can be shared among the memory cells 200 of the memory subarray 102. This further reduces the area required to implement the disclosed memory device 100. This optimizes the performance of the memory device 100 and the components connected to it, and can reduce redundancy of the components in the I / O control system 110. In some examples, the global I / O circuitry 404 and / or the global control circuitry 406 may be local circuitry, operating based on signals received from global circuitry located elsewhere (e.g., outside the memory device 100).

[0056] Figure 4C According to the disclosed embodiments Figure 1A and Figure 1C A cell diagram of an exemplary access path 150 in an I / O control system. Access path 150 may include a path originating from I / O interface 402 (e.g., receiving an address), through global control circuitry 406, to address decoder 104 (e.g., identifying word lines), to a specific memory cell on the identified word line and bit line, to global I / O circuitry connected to the bit line, and back to I / O interface 402. Any memory cell in memory subarray 102 may be accessed using a similar access path 150.

[0057] Figure 5This is a waveform diagram 500 of exemplary signals generated by elements within the storage device 100. Waveform diagram 500 includes a line upper signal 502 for the word lines of an upper macro (e.g., first macro 120) and a line lower signal 504 for the word lines of a lower macro (e.g., second macro 122). During a first standby time 510, no word lines are activated, and the line upper signal 502 and line lower signal 504 are at a logic low level. During a first access event time 512, only the upper word line is activated, and the line upper signal 502 is at a logic high level. In some exemplary embodiments, when the number of data bits in an access operation (e.g., a write operation) is less than the number of bits in the macro, only one word line of a macro (e.g., first macro 120) is activated. The number of bits associated with the first access event time 512 may therefore be less than the number of memory cells in the first macro 120. During the second standby time 514, no word line is activated, and the signal 502 above the word line and the signal 504 below the word line are at the logic low level.

[0058] At the second access event time 516, both word lines are activated, with signal 502 above the word lines and signal 504 below the word lines at logic high level. In some exemplary embodiments, when there are more data bits than macro bits, word lines in both macros (e.g., the upper first macro 120 and the lower second macro 122) are activated. The number of bits associated with the second access event time 516 may therefore be greater than the number of memory cells in the first macro 120. Various macros can perform access operations in different orders, combinations, times, and / or similar ways described above.

[0059] Figure 6 This is a flowchart of an exemplary method 600 for accessing storage device 100. Method 600 includes operations 610, 620, and 630. In some embodiments, some or all of the operations of method 600 may be performed by some or more elements of storage device 100.

[0060] In operation 610, a decision is made to access a memory cell. For example, one or more macro-level I / O control systems 110 receive signals (e.g., requests to perform an access operation). The access operation can be a write operation, a read operation, and / or something similar described above. In some embodiments, I / O interface 402 receives signals to perform an access operation from an external device.

[0061] In operation 620, the word lines and bit lines of the memory cell are determined. For example, the I / O control system 110 and the address decoder 104 determine the word lines and bit lines of the memory cell. In a particular embodiment, the corresponding global control circuit 406 passes an address input signal (e.g., a received signal) to the corresponding address decoder 104, and the address decoder 104 selects the word line corresponding to the address input signal. The corresponding global I / O circuit 404 may receive or otherwise determine the row address used to determine the corresponding bit line. For example, the global I / O circuit 404 receives the address input signal and selects the bit line corresponding to the address input signal.

[0062] In operation 630, memory subarray 102 is activated to access memory cells. For example, I / O control system 110 and address decoder 104 activate memory subarray 102, which includes memory cells (e.g., based on word lines and bit lines of the memory cells). Accessing memory cells may include reading data stored in the memory cells, writing data to the memory cells, and / or similar actions described above. In a particular embodiment, memory cells may be accessed using access path 150.

[0063] In the example, the first I / O control system (e.g., I / O control system 110a) is configured to: activate a first memory subarray (e.g., memory subarray 102a) when the word line of a memory cell is in the first word line interval and the bit line of the memory cell is in the first bit line interval; activate a second memory subarray (e.g., memory subarray 102b) when the word line of a memory cell is in the first word line interval and the bit line of the memory cell is in the second bit line interval; activate a third memory subarray (e.g., memory subarray 102c) when the word line of a memory cell is in the second word line interval and the bit line of the memory cell is in the first bit line interval; and activate a fourth memory subarray (e.g., memory subarray 102d) when the word line of a memory cell is in the second word line interval and the bit line of the memory cell is in the second bit line interval. The second I / O control system (e.g., I / O control system 110b) is configured to: activate the fifth memory subarray (e.g., memory subarray 102e) when the word line of the memory cell is in the third word line interval and the bit line of the memory cell is in the third bit line interval; activate the sixth memory subarray (e.g., memory subarray 102f) when the word line of the memory cell is in the third word line interval and the bit line of the memory cell is in the fourth bit line interval; activate the seventh memory subarray (e.g., memory subarray 102g) when the word line of the memory cell is in the fourth word line interval and the bit line of the memory cell is in the third bit line interval; and activate the eighth memory subarray (e.g., memory subarray 102h) when the word line of the memory cell is in the fourth word line interval and the bit line of the memory cell is in the fourth bit line interval.

[0064] In a specific embodiment, the first character line interval is from character line 1 to character line 32; the second character line interval is from character line 33 to character line 64; the third character line interval is from character line 65 to character line 96; and the fourth character line interval is from character line 97 to character line 128. Additionally, the first bit line interval is from bit line 1 to bit line 64; the second bit line interval is from bit line 65 to bit line 128; the third bit line interval is from bit line 129 to bit line 192; and the fourth bit line interval is from bit line 193 to bit line 256.

[0065] In one example, a first address decoder (e.g., address decoder 104a) is located between a first memory subarray and a second memory subarray, a second address decoder (e.g., address decoder 104b) is located between a third memory subarray and a fourth memory subarray, a third address decoder (e.g., address decoder 104c) is located between a fifth memory subarray and a sixth memory subarray, and a fourth address decoder (e.g., address decoder 104d) is located between a seventh memory subarray and an eighth memory subarray. The first I / O control system is positioned such that the first memory subarray, the second memory subarray, and the first address decoder are located on a first side of the first I / O control system, while the third memory subarray, the fourth memory subarray, and the second address decoder are located on a second side of the first I / O control system relative to the first side. The second I / O control system is positioned such that the fifth memory subarray, the sixth memory subarray, and the third address decoder are located on a first side of the second I / O control system, while the seventh memory subarray, the eighth memory subarray, and the fourth address decoder are located on a second side of the second I / O control system relative to the first side.

[0066] In some examples, method 600 further includes receiving multiple bits of data for storage; when the multiple bits of data are less than the number of memory cells in the first memory subarray, the second memory subarray, the third memory subarray, and the fourth memory subarray, activating multiple word lines in one or both of the first word line interval and the second word line interval to store the multiple bits within one or more of the first memory subarray, the second memory subarray, the third memory subarray, and the fourth memory subarray; and when the multiple bits of data are more than the number of memory cells in the first memory subarray, the second memory subarray, the third memory subarray, and the fourth memory subarray, activating multiple word lines in (i) any one of the first word line interval and the second word line interval, and (ii) any one of the third word line interval and the fourth word line interval, to store the multiple bits within one or more of the first memory subarray, the second memory subarray, the third memory subarray, and the fourth memory subarray, and one or more of the fifth memory subarray, the sixth memory subarray, the seventh memory subarray, and the eighth memory subarray.

[0067] Figure 7This is a flowchart of an exemplary storage device method 700. Method 700 includes operations 710, 720, 730, and 740. In some embodiments, some or all of the operations of method 700 may be performed by some or more elements of storage device 100.

[0068] In operation 710, a macro with memory subarray 102 is provided, for example... Figure 1A or Figure 1C The storage device 100 shown.

[0069] In operation 720, the address decoder 104 and the I / O control system 110 are located between the memory subarrays 102. For example, the address decoder is located between the memory subarrays 102 and connected to the word lines of the memory subarrays, while the I / O control system 110 is located between the upper memory subarray 102 and the corresponding address decoder 104 and the lower memory subarray 102 and the corresponding address decoder 104.

[0070] In operation 730, bit lines are received from memory subarray 102. For example, I / O control system 110 receives bit lines corresponding to memory subarray 102 in a macro. The bit lines of the upper memory subarray 102 can be connected to a first side 410 of I / O control system 110, while the bit lines of the lower memory subarray 102 can be connected to a second side 412 of I / O control system 110.

[0071] In operation 740, access operations are performed to access memory cells 200 of storage device 100. For example, the I / O control system 110 operates to read data from or write data to a subset of memory cells 200, and to output and receive data from external devices.

[0072] In a particular embodiment, a method of forming a memory device includes forming multiple macros that allocate the number of bit lines. For example, the memory device has two macros, each with 128 bit lines, forming a memory array with a total of 256 bit lines. The macros allocate the number of bit lines, creating shorter access paths to increase access speed. Forming macros may include forming memory subarrays with an I / O control system and an address decoder that divides the memory subarrays into four subarrays. For example, the upper address decoder may be located in the middle of the two upper memory subarrays, and the lower address decoder may be located in the middle of the two lower memory subarrays. The I / O control system may be located between the upper elements (e.g., the upper address decoder and the upper memory subarrays) and the lower elements (e.g., the lower address decoder and the lower memory subarrays). The address decoders divide the memory subarrays in a first direction, while the I / O control system divides the memory subarrays in a second direction. The macros may be directly adjacent to each other.

[0073] The disclosed examples provide a memory device 100 with shortened bit lines and word lines to improve memory performance (e.g., access speed). In an exemplary embodiment, the memory device includes: a first macro (e.g., first macro 120), a first macro array including memory cells, the first macro array including a first memory subarray (e.g., memory subarray 102a), a second memory subarray (e.g., memory subarray 102b), a third memory subarray (e.g., memory subarray 102c), and a fourth memory subarray (e.g., memory subarray 102d), wherein each of the first, second, third, and fourth memory subarrays includes a plurality of word lines and a plurality of bit lines; and a first address decoder (e.g., address decoder 104a), located between the first and second memory subarrays and connected to the first memory subarray. The word lines of the first memory subarray and the word lines of the second memory subarray; a second address decoder (e.g., address decoder 104b) located between the third and fourth memory subarrays and connected to the word lines of the third and fourth memory subarrays; a first I / O control system (e.g., I / O control system 110a) positioned such that the first memory subarray, the second memory subarray, and the first address decoder are located on a first side of the first I / O control system, while the third memory subarray, the fourth memory subarray, and the second address decoder are located on a second side of the first I / O control system relative to the first side; wherein the first I / O control system is connected to the bit lines of each of the first, second, third, and fourth memory subarrays.

[0074] The memory device further includes a second macro (e.g., second macro 122), comprising: a second macro array of memory cells, the second macro array including a fifth memory subarray (e.g., memory subarray 102e), a sixth memory subarray (e.g., memory subarray 102f), a seventh memory subarray (e.g., memory subarray 102g), and an eighth memory subarray (e.g., memory subarray 102h), wherein each of the fifth, sixth, seventh, and eighth memory subarrays includes a plurality of word lines and a plurality of bit lines; a third address decoder (e.g., address decoder 104c), located between the fifth and sixth memory subarrays and connected to the word lines of the fifth memory subarray and the eighth memory subarray. The word lines of the six memory subarrays; a fourth address decoder (e.g., address decoder 104d) located between the seventh and eighth memory subarrays and connected to the word lines of the seventh and eighth memory subarrays; a second I / O control system (e.g., I / O control system 110b) positioned such that the fifth, sixth, and third address decoders are on a first side of the second I / O control system, while the seventh, eighth, and fourth address decoders are on a second side of the second I / O control system relative to the first side; and bit lines of the second I / O control system connected to each of the fifth, sixth, seventh, and eighth memory subarrays.

[0075] In some examples, the memory device further includes: a third macro (e.g., third macro 124), comprising: a third macro array of memory cells, the third macro array including a ninth memory subarray (e.g., memory subarray 102i), a tenth memory subarray (e.g., memory subarray 102j), an eleventh memory subarray (e.g., memory subarray 102k), and a twelfth memory subarray (e.g., memory subarray 102l), wherein each of the ninth, tenth, eleventh, and twelfth memory subarrays includes a plurality of word lines and a plurality of bit lines; a fifth address decoder (e.g., ground... Address decoder 104e is located between the ninth and tenth memory subarrays and connected to the word lines of the ninth and tenth memory subarrays; a sixth address decoder (e.g., address decoder 104f) is located between the eleventh and twelfth memory subarrays and connected to the word lines of the eleventh and twelfth memory subarrays; a third I / O control system (e.g., I / O control system 110c) is positioned such that the ninth, tenth, and fifth address decoders are located on the first side of the third I / O control system, while the eleventh and twelfth memory subarrays are located on the first side. The memory subarray and the sixth address decoder are located on the second side of the third I / O control system relative to the first side; wherein the third I / O control system is connected to the bit lines of each of the ninth, tenth, eleventh, and twelfth memory subarrays; the fourth macro (e.g., fourth macro 126) includes: a fourth macro array of memory cells, the fourth macro array including a thirteenth memory subarray (e.g., memory subarray 102m), a fourteenth memory subarray (e.g., memory subarray 102n), a fifteenth memory subarray (e.g., memory subarray 102o), and a sixteenth memory subarray (e.g., memory subarray 102o). Memory subarray 102p), wherein each of the thirteenth, fourteenth, fifteenth, and sixteenth memory subarrays includes multiple word lines and multiple bit lines; a seventh address decoder (e.g., address decoder 104g) is located between the thirteenth and fourteenth memory subarrays and connected to the word lines of the thirteenth and fourteenth memory subarrays; an eighth address decoder (e.g., address decoder 104h) is located between the fifteenth and sixteenth memory subarrays and connected to the word lines of the fifteenth and sixteenth memory subarrays.A fourth I / O control system (e.g., I / O control system 110d) is positioned such that the thirteenth memory subarray, the fourteenth memory subarray, and the seventh address decoder are located on a first side of the fourth I / O control system, while the fifteenth memory subarray, the sixteenth memory subarray, and the eighth address decoder are located on a second side of the fourth I / O control system relative to the first side; and wherein the fourth I / O control system is connected to bit lines of each of the thirteenth, fourteenth, fifteenth, and sixteenth memory subarrays.

[0076] In other examples, the method includes: determining a memory cell to be accessed; determining the word line and bit line of the memory cell; activating a first memory subarray, a second memory subarray, a third memory subarray, a fourth memory subarray, a fifth memory subarray, a sixth memory subarray, a seventh memory subarray, or an eighth memory subarray to access the memory cell according to the word line and bit line of the memory cell, wherein: a first I / O control system: activates the first memory subarray when the word line of the memory cell is within the first word line interval and the bit line of the memory cell is within the first bit line interval; activates the second memory subarray when the word line of the memory cell is within the first word line interval and the bit line of the memory cell is within the second bit line interval; activates the third memory subarray when the word line of the memory cell is within the second word line interval and the bit line of the memory cell is within the first bit line interval; activates the fourth memory subarray when the word line of the memory cell is within the second word line interval and the bit line of the memory cell is within the first bit line interval; activates the fifth memory subarray when the word line of the memory cell is within the first word line interval and the bit line of the memory cell is within the second bit line interval; activates the sixth memory subarray when the word line of the memory cell is within the second word line interval and the bit line of the memory cell is within the first bit line interval. When the bit line of a memory cell is within the first bit line interval, the third memory subarray is activated; when the word line of a memory cell is within the second word line interval and the bit line of a memory cell is within the second bit line interval, the fourth memory subarray is activated; the second I / O control system: when the word line of a memory cell is within the third word line interval and the bit line of a memory cell is within the third bit line interval, the fifth memory subarray is activated; when the word line of a memory cell is within the third word line interval and the bit line of a memory cell is within the fourth bit line interval, the sixth memory subarray is activated; when the word line of a memory cell is within the fourth word line interval and the bit line of a memory cell is within the third bit line interval, the seventh memory subarray is activated; and when the word line of a memory cell is within the fourth word line interval and the bit line of a memory cell is within the fourth bit line interval, the eighth memory subarray is activated.

[0077] In another embodiment, the memory device includes a plurality of macros, each macro including: a macro array of memory cells including four memory subarrays, each of the four memory subarrays including a plurality of word lines and a plurality of bit lines; a first address decoder located between two of the upper memory subarrays and connected to the word lines of the two upper memory subarrays; a second address decoder located between two of the lower memory subarrays and connected to the word lines of the two lower memory subarrays; an input / output (IO) control system positioned such that the two upper memory subarrays and the first address decoder are located on a first side of the IO control system, and the two lower memory subarrays and the second address decoder are located on a second side of the IO control system opposite to the first side, wherein the IO control system includes: an IO interface configured to interface with external components; global IO circuitry connected to the bit lines of the four memory subarrays and configured to access the bit lines; and global control circuitry configured to control the global IO circuitry and one or both of the first and second address decoders.

[0078] In one embodiment, the memory device includes a first macro, comprising: a first macro array of memory cells, the first macro array including a first memory subarray, a second memory subarray, a third memory subarray, and a fourth memory subarray, wherein each of the first, second, third, and fourth memory subarrays includes a plurality of word lines and a plurality of bit lines; a first address decoder located between the first and second memory subarrays and connected to the word lines of the first and second memory subarrays; a second address decoder located between the third and fourth memory subarrays and connected to the word lines of the third and fourth memory subarrays; and a first I / O control system positioned such that the first, second, and third memory subarrays and the first address decoder are located on a first side of the first I / O control system, while the third, fourth, and second address decoders are located on a second side of the first I / O control system relative to the first side; wherein the first I / O control system is connected to each of the first, second, third, and fourth memory subarrays. A bit line; a second macro, comprising: a second macro array of memory cells, the second macro array including a fifth memory subarray, a sixth memory subarray, a seventh memory subarray, and an eighth memory subarray, wherein each of the fifth memory subarray, the sixth memory subarray, the seventh memory subarray, and the eighth memory subarray includes a plurality of word lines and a plurality of bit lines; a third address decoder located between the fifth memory subarray and the sixth memory subarray and connected to the word lines of the fifth memory subarray and the sixth memory subarray; a fourth address decoder located between the seventh memory subarray and the eighth memory subarray and connected to the word lines of the seventh memory subarray and the eighth memory subarray; a second I / O control system positioned such that the fifth memory subarray, the sixth memory subarray, and the third address decoder are located on a first side of the second I / O control system, while the seventh memory subarray, the eighth memory subarray, and the fourth address decoder are located on a second side of the second I / O control system relative to the first side; and wherein the second I / O control system is connected to the bit lines of each of the fifth memory subarray, the sixth memory subarray, the seventh memory subarray, and the eighth memory subarray.The memory device may further include a third macro, comprising: a third macro array of memory cells, the third macro array including a ninth memory subarray, a tenth memory subarray, an eleventh memory subarray, and a twelfth memory subarray, wherein each of the ninth, tenth, eleventh, and twelfth memory subarrays includes a plurality of word lines and a plurality of bit lines; a fifth address decoder located between the ninth and tenth memory subarrays and connected to the word lines of the ninth and tenth memory subarrays; a sixth address decoder located between the eleventh and twelfth memory subarrays and connected to the word lines of the eleventh and twelfth memory subarrays; a third I / O control system positioned such that the ninth, tenth, and fifth address decoders are located on a first side of the third I / O control system, while the eleventh, twelfth, and sixth address decoders are located on a second side of the third I / O control system relative to the first side; wherein the third I / O control system is connected to the bit lines of each of the ninth, tenth, eleventh, and twelfth memory subarrays; and a fourth macro. It includes: a fourth macroarray of memory cells, the fourth macroarray including a thirteenth memory subarray, a fourteenth memory subarray, a fifteenth memory subarray, and a sixteenth memory subarray, wherein each of the thirteenth, fourteenth, fifteenth, and sixteenth memory subarrays includes multiple word lines and multiple bit lines; a seventh address decoder, located between the thirteenth and fourteenth memory subarrays and connected to the word lines of the thirteenth and fourteenth memory subarrays; and an eighth address decoder, located between the fifteenth and tenth memory subarrays. The word lines of the six memory subarrays are connected to and between the word lines of the fifteenth and sixteenth memory subarrays; a fourth I / O control system is positioned such that the thirteenth, fourteenth, and seventh address decoders are located on a first side of the fourth I / O control system, while the fifteenth, sixteenth, and eighth address decoders are located on a second side of the fourth I / O control system relative to the first side; and wherein the fourth I / O control system is connected to the bit lines of each of the thirteenth, fourteenth, fifteenth, and sixteenth memory subarrays.

[0079] In other embodiments, the memory device includes a first macro, comprising a first memory subarray; a second memory subarray separated from the first memory subarray in a first direction; a third memory subarray separated from the first memory subarray in a second direction; a fourth memory subarray separated from the third memory subarray in a first direction; a first address decoder located in the first direction between the first and second memory subarrays; a second address decoder located in the first direction between the third and fourth memory subarrays; and a first I / O control system located in the second direction between the first and second address decoders; and a second macro, comprising a fifth memory subarray; a sixth memory subarray separated from the fifth memory subarray in a first direction; a seventh memory subarray separated from the fifth memory subarray in a second direction; an eighth memory subarray separated from the seventh memory subarray in a first direction; a third address decoder located in the first direction between the fifth and sixth memory subarrays; a fourth address decoder located in the first direction between the seventh and eighth memory subarrays; and a second I / O control system located in the second direction between the third and fourth address decoders. In an exemplary embodiment, the second I / O control system is connected to the bit lines of each of the fifth, sixth, seventh, and eighth memory subarrays. In some embodiments, no I / O control system is located between the second and third address decoders in the second direction.

[0080] In a particular embodiment, a storage device includes: a first macro array comprising memory cells, the first macro array including: a first memory subarray 102a-d; a second memory subarray; a third memory subarray; and a fourth memory subarray; a first address decoder 104a located in a first direction between the first memory subarray and the second memory subarray; a second address decoder 104b located in the first direction between the third memory subarray and the fourth memory subarray; and a first I / O control system 110a positioned such that the first memory subarray, the second memory subarray, and the first address decoder are located on a first side of the first I / O control system in a second direction intersecting the first direction, while the third memory subarray, the fourth memory subarray, and the second address decoder are located on a first side of the first I / O control system. A second side of an I / O control system relative to a first side; a second macro, comprising a second macro array of memory cells, the second macro array including: a fifth memory subarray; a sixth memory subarray; a seventh memory subarray; and an eighth memory subarray; a third address decoder located in a first direction between the fifth and sixth memory subarrays; a fourth address decoder located in a first direction between the seventh and eighth memory subarrays; and a second I / O control system 110a positioned such that the fifth, sixth, and third address decoders are located in a second direction on a first side of the second I / O control system, while the seventh, eighth, and fourth address decoders are located on a second side of the second I / O control system relative to the first side.

[0081] In some embodiments, a method includes forming a memory device comprising a total number of bit lines. The operation of forming the memory device includes forming a plurality of macros, wherein the macros allocate the total number of bit lines such that each macro includes a portion of the total number of bit lines. The operation of forming the plurality of macros includes: forming a macro array of memory cells comprising four memory subarrays; forming a first address decoder located between two upper memory subarrays of the four memory subarrays; forming a second address decoder located between two lower memory subarrays of the four memory subarrays; and forming an I / O control system such that the two upper memory subarrays and the first address decoder are located on a first side of the I / O control system, and the two lower memory subarrays and the second address decoder are located on a second side of the I / O control system opposite to the first side. In an exemplary embodiment, the I / O control system includes: an I / O interface configured to interface with external components; global I / O circuitry connected to the bit lines of the four memory subarrays and configured to access a single bit line; and global control circuitry configured to control the global I / O circuitry and one or both of the first and second address decoders.

[0082] In other embodiments, a memory device includes: a plurality of macros, each macro including: a macro array of memory cells including four memory subarrays, each of the four memory subarrays including a plurality of word lines and a plurality of bit lines; a first address decoder located between two upper memory subarrays of the four memory subarrays and connected to the word lines of the two upper memory subarrays; a second address decoder located between two lower memory subarrays of the four memory subarrays and connected to the word lines of the two lower memory subarrays; an I / O control system positioned such that the two upper memory subarrays and the first address decoder are located on a first side of the I / O control system, and the two lower memory subarrays and the second address decoder are located on a second side of the I / O control system opposite to the first side, wherein the I / O control system includes: an I / O interface configured to interface with external components; global I / O circuitry connected to the bit lines of the four memory subarrays and configured to access a bit line; and global control circuitry configured to control the global I / O circuitry and one or both of the first and second address decoders.

[0083] In some embodiments, a method for accessing a memory device includes: determining to access a memory cell; determining a word line of the memory cell and a bit line of the memory cell; activating a first memory subarray, a second memory subarray, a third memory subarray, a fourth memory subarray, a fifth memory subarray, a sixth memory subarray, a seventh memory subarray, or an eighth memory subarray to access the memory cell according to the word line and bit line of the memory cell, wherein: a first I / O control system: activates the first memory subarray when the word line of the memory cell is within a first word line interval and the bit line of the memory cell is within a first bit line interval; activates the second memory subarray when the word line of the memory cell is within the first word line interval and the bit line of the memory cell is within a second bit line interval; activates the second memory subarray when the word line of the memory cell is within the second word line interval; and activates the third memory subarray when the word line of the memory cell is within the second word line interval. A second I / O control system: when the word line of a memory cell is within a third word line interval and the bit line of the memory cell is within a third bit line interval, a third memory subarray is started; when the word line of a memory cell is within a second word line interval and the bit line of the memory cell is within a second bit line interval, a fourth memory subarray is started; a second I / O control system: when the word line of a memory cell is within a third word line interval and the bit line of the memory cell is within a third bit line interval, a fifth memory subarray is started; when the word line of a memory cell is within a third word line interval and the bit line of the memory cell is within a fourth bit line interval, a sixth memory subarray is started; when the word line of a memory cell is within a fourth word line interval and the bit line of the memory cell is within a third bit line interval, a seventh memory subarray is started; and when the word line of a memory cell is within a fourth word line interval and the bit line of the memory cell is within a fourth bit line interval, an eighth memory subarray is started.

[0084] In one embodiment, the storage device includes: a first macro, comprising: a first memory subarray; a second memory subarray separated from the first memory subarray in a first direction; a third memory subarray; a fourth memory subarray separated from the third memory subarray in the first direction; a first address decoder located between the first memory subarray and the second memory subarray in the first direction; a second address decoder located between the third memory subarray and the fourth memory subarray in the first direction; and a first input / output (IO) control system located between the first address decoder and the second address decoder in a second direction intersecting the first direction, wherein the first IO control system is configured to access the first memory subarray and the second memory subarray through the first address decoder, and to access the third memory subarray and the fourth memory subarray through the second address decoder; and a second macro, comprising: a fifth memory subarray abutting against the third memory subarray in the second direction; a first... A sixth memory subarray, abutting against a fourth memory subarray in a second direction and separated from a fifth memory subarray in a first direction; a seventh memory subarray; an eighth memory subarray, separated from the seventh memory subarray in a first direction; a third address decoder, located between the fifth and sixth memory subarrays in a first direction; a fourth address decoder, located between the seventh and eighth memory subarrays in a first direction; and a second I / O control system, located between the third and fourth address decoders in a second direction, wherein the second I / O control system is configured to access the fifth and sixth memory subarrays via the third address decoder and to access the seventh and eighth memory subarrays via the fourth address decoder, wherein the memory devices include a total number of bit lines, and a first macro and a second macro allocate the total number of bit lines such that the first macro includes a first portion of the total number of bit lines, and the second macro includes a second portion of the total number of bit lines.

[0085] In some embodiments, the positions of the first and second macros are such that the third, fourth, and second memory subarrays and the second address decoder are adjacent to the fifth, sixth, and third memory subarrays and the third address decoder. In some embodiments, each of the first, second, third, fourth, fifth, sixth, seventh, and eighth memory subarrays includes 64 bit lines. In some embodiments, the memory device further includes: a third macro, comprising: a first macro array of memory cells, the first macro array including a ninth memory subarray, a tenth memory subarray, an eleventh memory subarray, and a twelfth memory subarray; a fifth address decoder located in a first direction between the ninth and tenth memory subarrays; a sixth address decoder located in the first direction between the eleventh and twelfth memory subarrays; and a third I / O control system positioned such that the ninth, tenth, and fifth address decoders are located on a first side of the third I / O control system in a second direction, while the eleventh, twelfth, and sixth address decoders are located in the second direction relative to the first side of the third I / O control system. A second side; a fourth macro, comprising: a second macro array of memory cells, the second macro array including a thirteenth memory subarray, a fourteenth memory subarray, a fifteenth memory subarray and a sixteenth memory subarray; a seventh address decoder located in a first direction between the thirteenth memory subarray and the fourteenth memory subarray; an eighth address decoder located in the first direction between the fifteenth memory subarray and the sixteenth memory subarray; and a fourth I / O control system positioned such that the thirteenth memory subarray, the fourteenth memory subarray and the seventh address decoder are located in a second direction on a first side of the fourth I / O control system, while the fifteenth memory subarray, the sixteenth memory subarray and the eighth address decoder are located in a second direction on a second side of the fourth I / O control system relative to the first side. In some embodiments, each of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, and sixteenth memory subarrays includes 32 bit lines. In some embodiments, the second and third macros are positioned such that the seventh, eighth, and fourth address decoders are adjacent to the ninth, tenth, and fifth address decoders.In some embodiments, the first I / O control system and the second I / O control system are configured to independently access corresponding memory subarrays to access the memory subarrays simultaneously and separately. In some embodiments, each of the first I / O control system and the second I / O control system includes: an I / O interface configured to interface with external components; a global I / O circuit configured to access a single bit line; and a global control circuit configured to control the global I / O circuit and one or more of a first address decoder, a second address decoder, a third address decoder, and a fourth address decoder. In some embodiments, the storage device is configured to: receive a plurality of bits of data for storage; when the number of bits of data is less than a number of memory cells in the first, second, third, and fourth memory subarrays, store the bits into one or more of the first, second, third, and fourth memory subarrays; and when the number of bits of data is greater than the number of memory cells in the first, second, third, and fourth memory subarrays, store the bits into one or more of the first, second, third, and fourth memory subarrays, and one or more of the fifth, sixth, seventh, and eighth memory subarrays.In some embodiments, the memory device is configured to: determine access to a memory cell; determine a word line and a bit line of the memory cell; activate a first memory subarray, a second memory subarray, a third memory subarray, a fourth memory subarray, a fifth memory subarray, a sixth memory subarray, a seventh memory subarray, or an eighth memory subarray to access the memory cell according to the word line and bit line of the memory cell, wherein: the first I / O control system is configured to: activate the first memory subarray when the word line of the memory cell is within a first word line interval and the bit line of the memory cell is within a first bit line interval; activate the second memory subarray when the word line of the memory cell is within the first word line interval and the bit line of the memory cell is within a second bit line interval; activate the third memory subarray when the word line of the memory cell is within the second word line interval and the bit line of the memory cell is within a second bit line interval; activate the fourth memory subarray when the word line of the memory cell is within the second word line interval and the bit line of the memory cell is within a first bit line interval; activate the fifth memory subarray when the word line of the memory cell is within the second word line interval and the bit line of the memory cell is within a second bit line interval; activate the sixth memory subarray when the word line of the memory cell is within the second word line interval and the bit line of the memory cell is within a second bit line interval; activate the seventh memory subarray when the word line of the memory cell is within the second word line interval and the bit line of the memory cell is within a second bit line interval; activate the eighth memory subarray when the word line of the memory cell is within the second word line interval and the bit line of the memory cell is within a second bit line interval; activate the ninth memory subarray when the word line of the memory cell is within the second word line interval and the bit line of the memory cell is within a second bit line interval; activate the eleventh memory subarray when the word line of the memory cell is within the first word line interval and the bit line of the memory cell is within the second bit line interval; activate the eleventh memory subarray when the word line of the memory cell is within the second word line interval and the bit When the bit line of a memory cell is within the first bit line interval, a third memory subarray is activated; when the word line of a memory cell is within the second word line interval and the bit line of a memory cell is within the second bit line interval, a fourth memory subarray is activated; the second I / O control system is configured to: activate a fifth memory subarray when the word line of a memory cell is within the third word line interval and the bit line of a memory cell is within the third bit line interval; activate a sixth memory subarray when the word line of a memory cell is within the third word line interval and the bit line of a memory cell is within the fourth bit line interval; activate a seventh memory subarray when the word line of a memory cell is within the fourth word line interval and the bit line of a memory cell is within the third bit line interval; and activate an eighth memory subarray when the word line of a memory cell is within the fourth word line interval and the bit line of a memory cell is within the fourth bit line interval. In some embodiments, the memory cells of the first, second, third, fourth, fifth, sixth, seventh, and eighth memory subarrays are configured to be accessed via access paths.

[0086] In another embodiment, a method for accessing a memory device includes: determining to access a memory cell; determining a word line and a bit line of the memory cell; and activating a first memory subarray, a second memory subarray, a third memory subarray, a fourth memory subarray, a fifth memory subarray, a sixth memory subarray, a seventh memory subarray, or an eighth memory subarray to access the memory cell based on the word line and the bit line of the memory cell, wherein a first input / output (IO) control system activates the first memory subarray, the second memory subarray, the third memory subarray, or the fourth memory subarray, or a second IO control system activates the fifth memory subarray, the sixth memory subarray, the seventh memory subarray, or the eighth memory subarray, based on the word line and the bit line of the memory cell.

[0087] In some embodiments, the operation of the first I / O control system activating the first memory subarray, the second memory subarray, the third memory subarray, or the fourth memory subarray, or the operation of the second I / O control system activating the fifth memory subarray, the sixth memory subarray, the seventh memory subarray, or the eighth memory subarray, includes: the first I / O control system: activating the first memory subarray when the word line of a memory cell is within a first word line interval and the bit line of the memory cell is within a first bit line interval; activating the second memory subarray when the word line of a memory cell is within the first word line interval and the bit line of the memory cell is within a second bit line interval; activating the third memory subarray when the word line of a memory cell is within the second word line interval and the bit line of the memory cell is within the first bit line interval. The memory subarray is configured as follows: A fourth memory subarray is activated when the word line of a memory cell is within the second word line interval and the bit line of a memory cell is within the second bit line interval; A second I / O control system is configured as follows: A fifth memory subarray is activated when the word line of a memory cell is within the third word line interval and the bit line of a memory cell is within the third bit line interval; A sixth memory subarray is activated when the word line of a memory cell is within the third word line interval and the bit line of a memory cell is within the fourth bit line interval; A seventh memory subarray is activated when the word line of a memory cell is within the fourth word line interval and the bit line of a memory cell is within the third bit line interval; and An eighth memory subarray is activated when the word line of a memory cell is within the fourth word line interval and the bit line of a memory cell is within the fourth bit line interval. In some embodiments, wherein: the first word line interval is a first word line to a thirty-second word line; the second word line interval is a thirty-third word line to a sixty-fourth word line; the third word line interval is a sixty-fifth word line to a ninety-sixth word line; the fourth word line interval is a ninety-seventh word line to a one hundred and twenty-eighth word line; the first bit line interval is a first bit line to a sixty-fourth bit line; the second bit line interval is a sixty-fifth bit line to a one hundred and twenty-eighth bit line; the third bit line interval is a one hundred and twenty-ninth bit line to a one hundred and ninety-second bit line; and the fourth bit line interval is a one hundred and ninety-third bit line to a two hundred and fifty-sixth bit line. In some embodiments, a first address decoder is located between a first memory subarray and a second memory subarray; a second address decoder is located between a third memory subarray and a fourth memory subarray; a third address decoder is located between a fifth memory subarray and a sixth memory subarray; and a fourth address decoder is located between a seventh memory subarray and an eighth memory subarray.In some embodiments, the first I / O control system is positioned such that the first memory subarray, the second memory subarray, and the first address decoder are located on a first side of the first I / O control system, while the third memory subarray, the fourth memory subarray, and the second address decoder are located on a second side of the first I / O control system relative to the first side; and the second I / O control system is positioned such that the fifth memory subarray, the sixth memory subarray, and the third address decoder are located on a first side of the second I / O control system, while the seventh memory subarray, the eighth memory subarray, and the fourth address decoder are located on a second side of the second I / O control system relative to the first side. In some embodiments, the access method further includes: receiving a plurality of bits of data for storage; when the number of bits of data is less than a number of memory cells in the first memory subarray, the second memory subarray, the third memory subarray, and the fourth memory subarray, activating a plurality of word lines in one or two of the first word line intervals and the second word line intervals to store the bits into one or more of the first memory subarray, the second memory subarray, the third memory subarray, and the fourth memory subarray; and when the number of bits of data is greater than the number of memory cells in the first memory subarray, the second memory subarray, the third memory subarray, and the fourth memory subarray, activating (i) a plurality of word lines in either the first word line interval and the second word line interval, and (ii) a plurality of word lines in either the third word line interval and the fourth word line interval, to store the bits into one or more of the first memory subarray, the second memory subarray, the third memory subarray, and the fourth memory subarray, and one or more of the fifth memory subarray, the sixth memory subarray, the seventh memory subarray, and the eighth memory subarray.

[0088] In another embodiment, the storage device includes: a plurality of macros, each of which includes: a macro array of memory cells including four memory subarrays; a first address decoder located between two upper memory subarrays of the four memory subarrays; a second address decoder located between two lower memory subarrays of the four memory subarrays; and an input / output (I / O) control system positioned such that the two upper memory subarrays and the first address decoder are located on a first side of the I / O control system, while the two lower memory subarrays and the second address decoder are located on a second side of the I / O control system relative to the first side, wherein the I / O control system includes: an I / O interface configured to interface with external components; a global I / O circuit connected to a plurality of bit lines of the four memory subarrays and configured to access a bit line; and a global control circuit configured to control the global I / O circuit and one or both of the first and second address decoders.

[0089] In some embodiments, each of the four memory subarrays includes 64 bit lines. In some embodiments, each of the four memory subarrays includes 32 bit lines. In some embodiments, the storage device is configured to: receive a plurality of bits of data for storage; store bits into one or more of the four memory subarrays when the number of bits of data is less than a number of memory cells in the four memory subarrays of the first macro; and store bits into one or more of the four memory subarrays of the first macro and one or more of the four memory subarrays of the second macro when the number of bits of data is greater than a number of memory cells in the four memory subarrays of the first macro. In some embodiments, the storage device is configured to: determine access to a memory cell; determine a word line and a bit line of the memory cell; and activate a word line of the four memory subarrays to access the memory cell according to the word line and the bit line of the memory cell.

[0090] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them without departing from the spirit and scope of this disclosure.

Claims

1. A memory device, comprising: The first macro and the second macro, where... The first macro includes: First memory subarray; The second memory subarray is separated from the first memory subarray in a first direction; Third memory subarray; The fourth memory subarray is separated from the third memory subarray in the first direction; A first address decoder is located between the first memory subarray and the second memory subarray in the first direction; A second address decoder is located between the third memory subarray and the fourth memory subarray in the first direction; and The first input / output (IO) control system is located between the first address decoder and the second address decoder in a second direction intersecting the first direction. The first I / O control system is configured to access the first memory subarray and the second memory subarray through the first address decoder, and to access the third memory subarray and the fourth memory subarray through the second address decoder; and The second macro includes: The fifth memory subarray abuts against the third memory subarray in the second direction; The sixth memory subarray abuts against the fourth memory subarray in the second direction and is separated from the fifth memory subarray in the first direction; Seventh memory subarray; The eighth memory subarray is separated from the seventh memory subarray in the first direction; The third address decoder is located between the fifth memory subarray and the sixth memory subarray in the first direction; A fourth address decoder is located between the seventh memory subarray and the eighth memory subarray in the first direction; and The second I / O control system is located between the third address decoder and the fourth address decoder in the second direction. The second I / O control system is configured to access the fifth and sixth memory subarrays via the third address decoder, and to access the seventh and eighth memory subarrays via the fourth address decoder. The memory device includes a total number of bit lines, and the first macro and the second macro allocate the total number of bit lines such that the first macro includes a first portion of the total number of bit lines, and the second macro includes a second portion of the total number of bit lines.

2. The storage device of claim 1, wherein the positions of the first macro and the second macro are such that the third memory subarray, the fourth memory subarray, and the second address decoder are adjacent to the fifth memory subarray, the sixth memory subarray, and the third address decoder.

3. The memory device of claim 1, wherein each of the first memory subarray, the second memory subarray, the third memory subarray, the fourth memory subarray, the fifth memory subarray, the sixth memory subarray, the seventh memory subarray, and the eighth memory subarray comprises 64 bit lines.

4. The memory device of claim 1, further comprising: The third and fourth macros, among which, The third macro includes: A first macro array of memory cells, the first macro array including a ninth memory subarray, a tenth memory subarray, an eleventh memory subarray and a twelfth memory subarray; The fifth address decoder is located between the ninth memory subarray and the tenth memory subarray in the first direction; A sixth address decoder is located between the eleventh memory subarray and the twelfth memory subarray in the first direction; and The third I / O control system is positioned such that the ninth memory subarray, the tenth memory subarray, and the fifth address decoder are located on the first side of the third I / O control system in the second direction, while the eleventh memory subarray, the twelfth memory subarray, and the sixth address decoder are located on the second side of the third I / O control system relative to the first side in the second direction. The fourth macro includes: The second macroarray of memory cells includes a thirteenth memory subarray, a fourteenth memory subarray, a fifteenth memory subarray, and a sixteenth memory subarray; The seventh address decoder is located between the thirteenth memory subarray and the fourteenth memory subarray in the first direction; An eighth address decoder is located between the fifteenth and sixteenth memory subarrays in the first direction; and The fourth I / O control system is positioned such that the thirteenth memory subarray, the fourteenth memory subarray, and the seventh address decoder are located on the first side of the fourth I / O control system in the second direction, while the fifteenth memory subarray, the sixteenth memory subarray, and the eighth address decoder are located on the second side of the fourth I / O control system relative to the first side in the second direction.

5. A method for accessing a storage device, comprising: Determines the memory location to access; Determine the word lines and bit lines of the memory cell; Activate the first memory subarray, the second memory subarray, the third memory subarray, the fourth memory subarray, the fifth memory subarray, the sixth memory subarray, the seventh memory subarray, or the eighth memory subarray to access the memory cell according to the word line and the bit line of the memory cell; as well as The first input / output I / O control system activates the first memory subarray, the second memory subarray, the third memory subarray, or the fourth memory subarray, or the second I / O control system activates the fifth memory subarray, the sixth memory subarray, the seventh memory subarray, or the eighth memory subarray, based on the word line and the bit line of the memory cell.

6. The method for accessing a storage device according to claim 5, wherein the operation of the first I / O control system activating the first memory subarray, the second memory subarray, the third memory subarray, or the fourth memory subarray, or the operation of the second I / O control system activating the fifth memory subarray, the sixth memory subarray, the seventh memory subarray, or the eighth memory subarray, comprises: First IO control system: When the word line of the memory cell is within the first word line interval and the bit line of the memory cell is within the first bit line interval, the first memory subarray is started. When the word line of the memory cell is within the first word line interval and the bit line of the memory cell is within the second bit line interval, the second memory subarray is started. When the word line of the memory cell is within the second word line interval and the bit line of the memory cell is within the first bit line interval, the third memory subarray is started. When the word line of the memory cell is within the second word line interval and the bit line of the memory cell is within the second bit line interval, the fourth memory subarray is started. Second IO control system: When the word line of the memory cell is within the third word line interval and the bit line of the memory cell is within the third bit line interval, the fifth memory subarray is activated. When the word line of the memory cell is within the third word line interval and the bit line of the memory cell is within the fourth bit line interval, the sixth memory subarray is activated. When the word line of the memory cell is within the fourth word line interval and the bit line of the memory cell is within the third bit line interval, the seventh memory subarray is started. as well as The eighth memory subarray is activated when the word line of the memory cell is within the fourth word line interval and the bit line of the memory cell is within the fourth bit line interval.

7. The method for accessing a storage device according to claim 6, wherein: The first character line interval is from the first character line to the thirty-second character line; The second character line interval is from the thirty-third character line to the sixty-fourth character line; The third character line interval is from the sixty-fifth character line to the ninety-sixth character line; The fourth character line interval is from the ninety-seventh character line to the one hundred and twenty-eighth character line; The first bit line interval is from the first bit line to the sixty-fourth bit line; The second bit line interval is from the 65th bit line to the 128th bit line; The third bit line interval is from bit line 129 to bit line 192; and The fourth bit line interval is from bit line 193 to bit line 256.

8. A storage device comprising: Multiple macros, each of which includes: The macroarray of memory cells includes four memory subarrays; The first address decoder is located between the two upper memory subarrays of the four memory subarrays; The second address decoder is located between the two lower memory subarrays of the four memory subarrays; An input / output (I / O) control system is positioned such that the two upper memory subarrays and the first address decoder are located on a first side of the I / O control system, while the two lower memory subarrays and the second address decoder are located on a second side of the I / O control system relative to the first side, wherein the I / O control system includes: The IO interface is configured to interface with external components; Global I / O circuitry, connected to multiple bit lines of the four memory subarrays, and configured as access bit lines; and A global control circuit is configured to control the global I / O circuit and one or both of the first address decoder and the second address decoder.

9. The memory device of claim 8, wherein each of the four memory subarrays comprises 64 bit lines.

10. The memory device of claim 8, wherein each of the four memory subarrays comprises 32 bit lines.

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