Opto-electric hybrid storage device and data processing method thereof

Abstract

This application discloses a hybrid optoelectronic storage device and its data processing method, relating to the field of storage technology. The device includes a data processor and a storage regeneration circuit connected via an optical fiber delay line. The storage regeneration circuit receives the optical signal output from the optical fiber delay line, converts the optical signal into message data, and then converts the message data back into an optical signal based on an electrical signal before sending it back to the optical fiber delay line, allowing the message data to circulate in a loop formed by the two. The data processor receives a data processing request and sends it along with data processing information to the storage regeneration circuit. The storage regeneration circuit determines the target data matching the data processing request from the circulating message data and sends the received data processing result back to the requesting end. This application solves the noise accumulation problem in related optical buffering devices, eliminating noise accumulation during optical signal buffering, and overcoming the limitation of buffering time by not being limited by noise accumulation in the number of cycles.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to an optoelectronic hybrid storage device and its data processing method. Background Technology

[0002] Optical signal buffering utilizes the propagation delay of optical signals in the transmission medium to temporarily store data. Related technologies employ fiber optic ring buffering, consisting of a fiber optic ring, optical switch, coupler, and amplifier. However, this method accumulates noise during the cyclic transmission of the optical signal, resulting in limited buffering time and complex system control.

[0003] Therefore, eliminating accumulated noise in optical buffer devices is a technical problem that needs to be solved by those skilled in the art.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] This application provides a hybrid optoelectronic storage device and its data processing method, which can solve the problem of noise accumulation in optical buffer devices. There is no noise accumulation during the optical signal buffering process, thereby realizing that the number of cycles is not limited by noise accumulation and breaking through the buffering time limit.

[0006] To solve the above-mentioned technical problems, this application provides the following technical solution: This application provides a hybrid optoelectronic storage device, comprising: This includes a data processor and storage regeneration circuitry connected via fiber optic delay lines; The storage and regeneration circuit receives the optical signal output by the optical fiber delay line, converts the optical signal into message data, and uses the message data as the basic electrical signal to convert it back into an optical signal and send it to the optical fiber delay line, so that the message data is cyclically transmitted in the loop formed by the storage and regeneration circuit and the optical fiber delay line. The data processor is configured as follows: A data processing request is received, and the data processing request and data processing information are sent to the storage regeneration circuit. The storage regeneration circuit determines the target data that matches the data processing request from the cyclic message data, and sends the received data processing result to the data processing request end.

[0007] This application also provides a data processing method applied to the aforementioned optoelectronic hybrid storage device, comprising: Transmit optical signals in an optical fiber delay line; The storage and regeneration circuit receives the optical signal output from the optical fiber delay line, converts the optical signal into message data, and uses the message data as the basic electrical signal to convert it back into an optical signal and send it to the optical fiber delay line, so that the message data is cyclically transmitted in the loop formed by the storage and regeneration circuit and the optical fiber delay line. When the data processor receives a data processing request, it sends the data processing request and data processing information to the storage regeneration circuit, and uses the storage regeneration circuit to determine the target data that matches the data processing request from the cyclic message data. Send the data processing results to the data processing request end.

[0008] The advantages of the technical solution provided in this application are as follows: the storage and regeneration circuit receives the optical signal output from the fiber optic delay line and converts it into message data. Then, it regenerates the optical signal based on this message data and injects it into the fiber optic delay line. This allows the data to be transmitted in the loop as an optical signal and regenerated in the form of an electrical signal upon returning to the storage and regeneration circuit. Each cycle completes a reassembly of the message data in the electrical domain before re-emitting the optical signal. The optical signal transmitted in the loop is always driven by the newly generated electrical signal, rather than directly amplifying and forwarding the received optical signal. This cuts off the accumulation path of spontaneous emission noise introduced by the optical amplifier in the optical domain during multiple cycles, eliminates the positive feedback between the increase in the number of cycles and noise superposition, and makes the buffer time no longer limited by noise accumulation. It also eliminates the need for time synchronization control of the optical switch, simplifying the control circuit. The data processor uses the address information in the message data as a matching basis, locates the target data in the cyclic message data through the storage and regeneration circuit, and performs write or read operations. This enables address-based random read / write operations in a continuously cyclically streaming message sequence, providing real-time high-throughput streaming read / write capabilities. It is suitable for AI caching scenarios that require large-volume streaming storage and retrieval. Furthermore, the data processing methods of hybrid optoelectronic storage devices offer corresponding advantages.

[0009] The technical features mentioned above, those to be mentioned below, and those shown individually in the accompanying drawings can be arbitrarily combined, provided that the combined technical features are not contradictory. All feasible combinations of features are technical contents explicitly described in this application. Any one of the multiple sub-features contained in the same statement can be applied independently, without necessarily being applied together with other sub-features.

[0010] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this application. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 A schematic diagram of the hardware framework of the optoelectronic hybrid storage device provided in this application; Figure 2 A schematic diagram of a custom message for a hybrid optoelectronic ring buffer provided in this application; Figure 3 This is a schematic diagram of the internal processing of the storage regeneration circuit provided in this application; Figure 4 Another schematic diagram of the optoelectronic hybrid storage device provided in this application; Figure 5 A schematic diagram illustrating the control command data parsing and response workflow provided in this application; Figure 6 A flowchart illustrating the data processing method provided in this application. Detailed Implementation

[0013] To enable those skilled in the art to better understand the technical solutions of this application, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. The terms "first," "second," "third," "fourth," etc., used in the specification and the aforementioned drawings are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. The term "exemplary" means "serving as an example, embodiment, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as superior to or better than other embodiments.

[0014] In optical communication systems, optical signal buffering is a crucial step in enabling all-optical packet switching and optical burst switching. Optical signal buffering utilizes the propagation delay of optical signals in the transmission medium to temporarily store data. Its basic working principle involves modulating the data to be buffered onto an optical carrier, allowing the optical signal to enter a fiber delay line or a loop composed of optical fibers for transmission. The purpose of data buffering is achieved by controlling the residence time of the optical signal in the transmission path.

[0015] The relevant technology employs fiber optic ring buffering to buffer optical signals. This technology achieves delayed storage of the optical signal by introducing it into a fiber optic ring for cyclic transmission. The implementation of fiber optic ring buffering combines components such as fiber optic rings, optical switches, couplers, and amplifiers. Some solutions further utilize multi-ring control to achieve various delay adjustments.

[0016] However, in this type of all-optical caching architecture, the signal needs to be amplified by an optical amplifier to compensate for transmission loss after each cycle. While amplifying the signal, the optical amplifier inevitably introduces spontaneous emission noise. This noise accumulates and is amplified again with each cycle, forming cumulative noise that is difficult to eliminate. This cumulative noise directly degrades signal quality, preventing the optical signal from being properly recovered after a finite number of cycles, thus strictly limiting the upper limit of the caching time, typically only in the millisecond range. Furthermore, to achieve multi-level delay combinations, this type of solution requires high-precision time synchronization, accurate optical switching, and conflict scheduling control, making system control extremely complex. In addition, its application scenarios are limited; for example, it can only store data, not modify it, lacking general caching capabilities and in-memory computing capabilities.

[0017] In view of this, this application converts the optical signal output from the fiber optic delay line into message data through a storage and regeneration circuit, and then converts the message data back into an optical signal based on the electrical signal before sending it to the fiber optic delay line. This allows the message data to be cyclically transmitted within a loop formed by the storage and regeneration circuit and the fiber optic delay line. The data processor sends data processing requests and information to the storage and regeneration circuit, which then determines the target data matching the data processing request from the cyclic message data. Because the optical signal undergoes photoelectric conversion and electro-optic conversion regeneration processes in each cycle, noise accumulation caused by direct cyclic amplification of the optical signal in the fiber optic loop is avoided, thus breaking through the upper limit of buffer time. Simultaneously, data location and access are achieved using message addresses, eliminating the need for precise time synchronization control of the optical switch, simplifying the control circuit. Furthermore, since the message data is continuously cyclically transmitted in the loop, the data processor can perform address matching and data reading / writing in real time during the message data flow, realizing streaming read / write operations. Various non-limiting embodiments of this application are described in detail below with reference to the accompanying drawings and specific implementation details.

[0018] Please see first. Figure 1 This application provides a hybrid optoelectronic storage device that may include a data processor 2 and a storage regeneration circuit 1 connected via an optical fiber delay line. The storage regeneration circuit 1 receives the optical signal output from the optical fiber delay line, converts the optical signal into message data, and uses the message data as a base electrical signal to re-convert it into an optical signal before sending it back to the optical fiber delay line. This allows the message data to be cyclically transmitted within a loop formed by the storage regeneration circuit 1 and the optical fiber delay line. The regenerated electrical signal replaces the direct cyclic transmission of the optical signal, eliminating accumulated noise in the loop. The data processor 2 is configured to: receive a data processing request; send the data processing request and data processing information to the storage regeneration circuit 1; determine the target data matching the data processing request from the cyclic message data using the storage regeneration circuit 1; and send the received data processing result to the data processing request end.

[0019] The basic mechanism of the optoelectronic hybrid ring buffer in this application is to construct the buffered data into N custom messages. These N custom messages are cyclically forwarded in the optical fiber delay line and the storage regeneration circuit 1. When writing is needed, the corresponding message is found according to the buffer address, and the corresponding content is modified. When reading is needed, the corresponding buffer message is found according to the read address, and the corresponding data is read. For example, such as... Figure 2 As shown in two consecutive custom message formats, the address corresponding to cached data 0 is n, the cache address corresponding to cached data 1 is n+1, the cache address corresponding to cached data 2 is n+2, ..., the cache address corresponding to cached data m is n+m. In the next message, the cache address corresponding to cached data m+1 is n+m+1, ..., the cache address corresponding to cached data 2m is n+2m.

[0020] In this embodiment, the fiber optic delay line is a section of optical fiber of a predetermined length, in which optical signals propagate at a finite speed. The propagation time is determined by both the fiber length and the speed of light, thus providing buffering time for the data. The storage and regeneration circuit 1 is an electrical signal processing device located between the two ends of the fiber optic delay line. Its input end receives the optical signal emitted from the fiber optic delay line through a photodetector, and its output end converts the electrical signal into an optical signal and injects it into the fiber optic delay line through a laser driver or electro-optic modulator. Message data refers to a data structure organized according to a preset format. Each message data includes address information and data content. The address information uniquely identifies the position of the message data in the cyclic sequence, while the data content is the actual cached payload data. The basic electrical signal refers to a driving electrical signal generated by a modulation circuit based on each bit of the message data. The waveform parameters of this driving electrical signal are entirely determined by the bit sequence of the message data, rather than shaping or copying the electrical signal obtained by directly amplifying the received optical signal after photoelectric conversion. The storage and regeneration circuit 1 receives the optical signal output from the fiber optic delay line, converts the optical signal into an electrical signal through a photodetector, and then recovers the message data from the electrical signal according to a preset frame synchronization method. The recovery process may include, for example, clock recovery, frame delimiting, and code block decoding to obtain complete message data. The storage and regeneration circuit 1 does not directly use this message data to drive the electro-optical converter; instead, it stores it in an internal buffer unit. Using this message data as new source data, it regenerates the driving electrical signal, driving the electro-optical converter to generate a new optical signal that is sent to the fiber delay line. This process ensures that the optical signal injected into the fiber delay line always originates from the message data regenerated in the electrical domain, rather than being a forwarding or amplification of the received optical signal in the optical domain.

[0021] The data processor 2 can be either a processor executing a data processing computer program stored in a non-volatile storage medium, or a circuit implemented using a hardware description language, logic synthesis, and physical implementation to perform corresponding data processing functions. A data processing request is a command message sent from outside the data processor 2 to the data processor. This message can be sent from outside the entire device or from the storage regeneration circuit 1. Its content indicates the type of operation to be performed, along with the address and data information associated with that operation. Data processing information is a set of parameters extracted by the data processor from the data processing request and passed to the storage regeneration circuit, such as read address, write address, and data to be written. Target data refers to the data content or address information of the message data in the cyclic message data whose address information matches the address carried in the data processing request. The data processor 2 receives the externally sent data processing request, parses the operation type and address information contained in the request, and sends the parsed data processing information to the storage regeneration circuit. During the cyclic flow of message data, the storage regeneration circuit compares the address in the data processing information with the address of the currently flowing message data. When they match, it performs a read or write operation on the message data and returns the operation result to the data processor. The data processor assembles the received operation result into a data processing result and sends it to the requesting end that initially issued the data processing request.

[0022] The technical problem solved and the technical effect achieved in this embodiment are as follows: In the all-optical caching scheme, the optical signal needs to undergo power compensation through an optical amplifier every time it cycles. The spontaneous emission noise introduced by the optical amplifier while amplifying the signal continuously accumulates with the number of cycles, leading to rapid deterioration of signal quality and severely limited caching time. In this embodiment, the storage regeneration circuit first converts the optical signal into an electrical signal and restores it to message data in each cycle. Then, based on this message data, it re-drives the electro-optical conversion to generate a new optical signal. The optical signal injected into the fiber delay line in each cycle is regenerated from digital message data in the electrical domain. Optical domain noise cannot be transmitted across cycles, fundamentally cutting off the noise accumulation path, so that the caching time is no longer limited by the number of cycles. Simultaneously, the data processor locates the target data in the cyclically streaming message sequence using address matching, realizing random access by address, extending the optical cache from a simple data temporary storage to a general-purpose caching device with read / write addressing capabilities.

[0023] Based on the above embodiments, this embodiment further refines the workflow of the storage regeneration circuit 1, which may include the following: The system receives optical signals emitted from the fiber optic delay line, converts the optical signals into electrical signals, recovers message data from the electrical signals, and stores it. It then retrieves target message data from the stored message data. If the address information in the target message data matches the address information corresponding to the data to be read, the data content in the target message data is output as the data to be read. Similarly, it retrieves target message data from the stored message data. If the address information in the target message data matches the address information corresponding to the data to be written, the data to be written is written to the storage location corresponding to the target message data to update the stored message data. Based on the stored message data or the updated message data, it regenerates the driving electrical signal, converts the driving electrical signal into an optical signal, and sends it to the fiber optic delay line, ensuring that the optical signal transmitted to the fiber optic delay line is regenerated based on the stored message data.

[0024] In this embodiment, the storage regeneration circuit 1 receives the optical signal emitted from the optical fiber delay line. For example, the optical signal can be converted into an electrical signal using any device with photoelectric conversion capabilities, such as a photodetector. The electrical signal refers to the current or voltage change signal generated after the optical signal is photodetected; its waveform reflects the intensity change of the optical signal. The storage regeneration circuit 1 extracts clock information from this electrical signal through a clock data recovery circuit, performs serial-to-parallel conversion and frame synchronization detection, locates the start boundary of the message, and recovers the message data. The recovered message data is written into the internal buffer of the storage regeneration circuit 1 for storage.

[0025] When data reading is required, the storage regeneration circuit 1 retrieves one of the message data from the cache, which is defined as the target message data in this embodiment. The retrieval method can be to intercept the currently output message data from the output port of the cache unit, or to select the corresponding message data from the cache unit according to its address. The storage regeneration circuit 1 compares the address information in the target message data with the read address corresponding to the data to be read. The data to be read refers to the payload content expected by the read request. If the address information matches the read address, the target message data is identified as the required message, and its data content is output to the data processor as the data to be read. Address matching is implemented through a hardware comparator, which compares the message address field bit by bit with the value in the read address register and outputs a matching signal.

[0026] When data writing is required, the storage regeneration circuit 1 retrieves one of the message data from the cache, defined in this embodiment as the target message data, and compares the address information in the target message data with the write address corresponding to the data to be written. If the addresses match, the storage regeneration circuit overwrites the data to be written into the storage location corresponding to the data content in the target message data, thereby updating the stored message data. The updated message data replaces the original message data and is stored in the original location in the cache unit.

[0027] The storage and regeneration circuit 1, based on currently stored message data or newly written message data, selects the corresponding message data via a data selector and sends it to the electro-optic conversion drive circuit. The drive circuit generates a modulation electrical signal, i.e., a drive electrical signal, based on the bit sequence of the message data. This drive electrical signal drives an electro-optic modulator or a direct modulator laser to convert the drive electrical signal into an optical signal, which is then sent to the fiber optic delay line. Therefore, the optical signal transmitted to the fiber optic delay line is always regenerated based on the currently stored digital message data in the storage and regeneration circuit, rather than directly amplifying the received optical signal before forwarding.

[0028] The technical problem solved and the technical effects achieved in this embodiment are as follows: In an optical buffer loop, write and read operations require accurate location of target data within a high-speed streaming data sequence. The storage regeneration circuit first stores the recovered message data into the buffer unit, and then completes the read / write location on the storage side using address information comparison. This ensures that both read and write operations are performed on the digital message data in the electrical domain, and the address matching accuracy is guaranteed by a digital comparator, unaffected by dispersion and jitter in optical signal transmission. Simultaneously, write operations directly modify message data in the buffer or the streaming path, and read operations directly extract data from the buffer or the streaming path. The read / write response latency is determined only by the hardware processing latency of the matching logic, not by the loop's full cycle latency, significantly shortening the read / write access latency.

[0029] Furthermore, based on the above embodiments, this embodiment also defines the internal structure of the storage regeneration circuit 1, which may include a photoelectric converter, a loop buffer, a read controller, a write controller, and an electro-optical converter. After each cycle of transmission in the optical fiber delay line, the optical signal is converted into message data by the storage regeneration circuit 1, and then converted back into an optical signal by the storage regeneration circuit 1 for transmission to the optical fiber delay line. Correspondingly, from the moment the optical signal emitted from the output end of the optical fiber delay line is received by the photoelectric converter until the electro-optical converter emits a new optical signal and re-enters the optical fiber delay line, a complete signal regeneration process is completed. Each cycle undergoes complete processing of photoelectric conversion, message recovery, buffer read / write, and electro-optical conversion, which may include the following: like Figure 3As shown, the storage regeneration circuit 1 includes a photoelectric converter that receives the optical signal output from the fiber optic delay line and converts the optical signal into an electrical signal; a cyclic buffer connected to the photoelectric converter that stores the recovered message data and outputs the stored message data in a first-in-first-out order; an electro-optic converter connected to the cyclic buffer that generates a drive electrical signal based on the message data obtained from the cyclic buffer, converts the drive electrical signal into an optical signal, and sends it to the fiber optic delay line; a read controller connected to the data path between the cyclic buffer and the photoelectric converter that, according to the data read request sent by the data processor 2, extracts the target message data corresponding to the data read request from the flowing message data, matches the address information in the target message data with the read address, and sends the data content in the target message data to the data processor 2 when the address matches; and a write controller connected to the data path between the electro-optic converter and the cyclic buffer that, according to the data write request sent by the data processor 2, writes the data to be written to the corresponding position in the flowing message data, and sends the updated message data to the electro-optic converter.

[0030] The photoelectric converter, for example, can consist of a photodetector and a transimpedance amplifier. It receives the optical signal output from the fiber optic delay line, converts the intensity change of the optical signal into a current signal, and then converts it into a voltage signal via the transimpedance amplifier, outputting it to subsequent circuits as an electrical signal. The circular buffer, connected to the photoelectric converter, is a hardware unit that implements cyclic storage and sequential output of message data. Internally, the circular buffer contains logic circuitry for recovering message data from the electrical signal, including a clock recovery circuit and a frame synchronization circuit. The recovered message data is written sequentially into the storage array within the circular buffer according to the recovery time order. The circular buffer can output the stored message data in a first-in, first-out (FIFO) order; that is, the first message data stored is read out first and sent to the next processing stage. The storage depth of the circular buffer determines the upper limit of the number of messages that can reside in the electrical domain simultaneously.

[0031] The read controller is connected to the data path between the cyclic buffer and the photoelectric converter. The data path refers to the circuit path through which message data flows from the output port of the photoelectric converter to the input port of the cyclic buffer. The read controller receives data read requests sent by the data processor, which carry a read address. As message data flows along the data path, the read controller intercepts the currently passing message data and compares its address information with the read address. The interception method can be to synchronously copy the message data on the data path to the read controller's comparison register, while the original message data continues to be transmitted along the data path unaffected. When the address matching signal is valid, the read controller extracts the data content from the message data and sends it to the data processor via the data bus. The read controller does not block the normal cyclic transmission of message data.

[0032] The write controller is connected to the data path between the cyclic buffer and the electro-optic converter. The write controller receives write requests from the data processor, which carry a write address and the data to be written. As the message data flows from the photoelectric converter to the electro-optic converter after being recovered and buffered, the write controller monitors the address information of the currently flowing message data and matches it with the write address. When the address matches, the write controller replaces the corresponding bit field of the data content in the message data with the data to be written, generating updated message data. The updated message data then replaces the old data at the corresponding position and is sent to the electro-optic converter for electro-optic conversion. The electro-optic converter is connected to the cyclic buffer and may include, for example, a laser driver or electro-optic modulator and its driving circuit. The electro-optic converter retrieves message data from the cyclic buffer and controls the driving circuit to generate a corresponding modulation current or modulation voltage according to the bit sequence of the message data. This drives the laser or electro-optic modulator to convert the electrical signal into an optical signal. The intensity or phase change of the optical signal reflects the bit information of the message data, and the optical signal is then coupled and sent to the fiber optic delay line.

[0033] The technical problem solved and the technical effect achieved in this embodiment are as follows: In the all-optical caching schemes of related technologies, the circulation, reading, writing, and control of optical signals are all completed in the optical domain by optical switches and optical couplers, resulting in high control complexity and difficulty in achieving precise address addressing. This embodiment divides the electrical domain processing after photoelectric conversion into a cyclic buffer, a read controller, a write controller, and an electro-optical converter. The read and write controllers are respectively set on the inlet and outlet data paths of the cyclic buffer. Read operations are intercepted when the message enters the cyclic buffer, and write operations are modified when the message leaves the cyclic buffer. The read and write paths are independent and do not block each other. The read and write controllers only access the message data at the moment of address matching; at other times, the message data is smoothly streamed between the cyclic buffer and the electro-optical converter, realizing the coordinated work of cyclic transmission and read / write operations without requiring precise time synchronization and optical switch switching control.

[0034] Furthermore, after power-on reset, the storage regeneration circuit 1 enters the initialization state. In this state, it does not respond to external read / write requests, but instead establishes a cyclically transmitted message data stream within the loop. Specifically, in the initialization state, the write controller determines the number of messages based on the transmission length of the fiber optic delay line and the capacity of the cyclic buffer, and generates a corresponding number of buffered messages. The write controller generates buffered messages, which are converted into optical signals by the electro-optic converter and sent to the fiber optic delay line. After the buffered messages are transmitted through the fiber optic delay line and return to the storage regeneration circuit 1 to complete one cycle, the storage regeneration circuit 1 enters the working state and begins to respond to the read / write data processing requests from the data processor 2.

[0035] The transmission length of the fiber optic delay line determines the one-way delay of the optical signal propagating within it. This delay, combined with the message duration that the cyclic buffer can store, determines the total number of messages the entire loop can accommodate. Buffered messages are message data generated by the write controller during the initialization phase according to a preset message format, and their format is completely consistent with the message data cyclically generated during normal operation. In other words, buffered messages refer to the message data pre-generated during the initialization phase, which includes a message address and data content. The message data in the above embodiment is complete electrical domain data cyclically generated in the loop during the operation phase, also including a message address and data content. The message address identifies the sequential position of the message in the buffered message sequence, and the data content can be filled with a preset default value or all zeros during initialization. The write controller sequentially outputs the generated buffered messages to the electro-optic converter. The electro-optic converter converts each buffered message into a corresponding optical signal and sends it to the fiber optic delay line. Buffered messages propagate along the fiber optic delay line as optical signals. At the output of the delay line, they are received by a photoelectric converter and converted back into electrical signals. These signals are then either transmitted through the read controller or bypassed by the read controller and returned to the write controller via a cyclic buffer. Once the first batch of buffered messages has completed a full cycle of transmission through the fiber optic delay line and returned to the storage regeneration circuit, the entire loop is filled with cyclically transmitted messages. The storage regeneration circuit then switches from the initialization state to the operating state and begins responding to read and write data processing requests sent by the data processor.

[0036] The technical problem solved and the technical effect achieved in this embodiment are as follows: Before the optical buffer loop starts working, the fiber delay line is in an idle state and there are no valid messages. Directly receiving read / write requests will not be able to locate the target data. Through message generation and loop filling operations in the initialization state, the write controller generates a structured buffer message sequence in the electrical domain. After one loop, messages are being transmitted at all points in the loop. When entering the working state, read / write requests for any address initiated by the data processor can find the corresponding message in the current loop message sequence to perform the operation, ensuring that the buffer device provides real-time read / write services.

[0037] Furthermore, in the initialization state, the write controller generates cached messages according to a preset order of message addresses, with free code blocks filling the gaps between adjacent cached messages. The preset order of message addresses refers to the arrangement of the values ​​in the message address field according to a predetermined rule, which is pre-configured based on application requirements. The preset order can be an ascending order, where the message address of the first generated cached message is the base address, and the message address of each subsequent generated cached message increases by a fixed step. The preset order can also be other arrangements defined according to a specific application scenario. A free code block is a specific code pattern that does not carry valid data and is used to provide a time interval between adjacent messages. The specific code pattern of the free code block can be preset, allowing the receiving end to distinguish between free code blocks and valid message data. The cache space for read and write operations by the data processor 2 can be determined based on the number of messages, the number of free code blocks between messages, and the internal framing overhead of the messages. The internal framing overhead of the messages refers to the fields and bits occupied in each message besides the actual data content available for reading and writing, including but not limited to the message address field, frame synchronization field, and check field. The buffer space is calculated by multiplying the total number of messages by the number of bits in the data content portion of each message. This is equivalent to the net payload remaining after deducting the occupancy of all idle code blocks and the framing overhead of all messages from the total loop transmission capacity.

[0038] The technical problem solved and the technical effect achieved in this embodiment are as follows: There are intervals between messages transmitted in a loop, and each message contains addresses and framing overhead. If the effective data area and the overhead area are not distinguished, the available cache capacity obtained by the data processing end will be inconsistent with the actual available storage space. By specifying the preset generation order of message addresses, filling the gaps between messages with free code blocks, and determining the effective cache space based on the number of messages, the number of free code blocks, and the framing overhead, the data processing end can accurately obtain the actual available capacity of the cache device. This facilitates upper-layer applications in arranging read and write operations according to the actual capacity, avoiding data overwriting or loss due to exceeding the effective cache space.

[0039] To make the storage regeneration circuit 1 of this application clearer to those skilled in the art, this embodiment also provides an exemplary embodiment of the storage regeneration circuit 1. The circular buffer can use a FIFO (First In First Out) method to buffer data, and may include the following: Storage regeneration circuit 1 is used to implement new data writing, stored data regeneration, and data reading. After power-on reset, storage regeneration circuit 1 first enters the hardware initialization state. In the hardware initialization state, it does not respond to external write or read requests, but instead generates multiple ring-shaped fly-through buffer messages according to the buffer space size. The buffer message format is as follows: Figure 2As shown, the messages are generated sequentially by the write controller. Each message contains a cache base address, so the message order reflects the address order. This order can be incremental or a special order specific to other applications. Cache messages are filled with free code blocks at configured intervals. The generated data is converted from electrical signals to optical pulse signals via electro-optical conversion and sent to the fiber optic delay line. After transmission for a period of time, it is converted back to electrical signals via photoelectric conversion, passed through the read controller, and written to the circular buffer. Once the configured circular buffer read threshold is reached, the data is read from the circular buffer and then passed through again, undergoing data writing, electro-optical conversion, and so on, continuously forwarding the cached messages. After generating cached messages according to the buffer size and completing one cycle, the module enters normal operation. The write and read controllers record the base address and offset address of the messages being forwarded in real time, thus obtaining the cache address corresponding to the currently flowing cached message data. Upon receiving a read request, the read controller compares the read request address with the cache address corresponding to the currently flowing cached data, i.e., the base address and the offset address within the data packet. If the addresses match, the data is read and sent to the read processor. Upon receiving a write request, the write controller compares the write request address with the cache address corresponding to the currently flowing cached data. If the addresses match, the write data is written to the corresponding position in the cached data packet, generating a new cached data packet which is then forwarded to the next-level electro-optical processing module. Simultaneously, a write completion acknowledgment is sent to the write processor.

[0040] Furthermore, this embodiment also defines the processing procedure of the data processor 2 for data read requests and data write requests, which may include the following: Data processor 2 is configured to: receive data read requests; send the data read request and read address to storage regeneration circuit 1 to determine the target message data matching the read address in the cyclic message data; and, upon receiving the target message data, send the target message data to the data read request end. It also receives data write requests; sends the data write request, the data to be written, and the write address to storage regeneration circuit 1 to determine the target cache address matching the write address in the cache addresses corresponding to the cyclic message data, and writes the data to be written to the target cache address; and, upon receiving write response information, sends the write response information to the data write request end.

[0041] In this system, a data read request is a read command sent from an external or internal processing unit to data processor 2. The read address is the address value carried in the data read request, specifying the location of the data to be read in the cache space. The target message data is the message data in the storage regeneration circuit whose message address matches the read address. The data read request end refers to the source end that initiates the data read request. After receiving the data read request, the data processor parses the read address from the request and sends the data read request and read address as data processing information to the storage regeneration circuit. The storage regeneration circuit compares the message address of the currently flowing message data with the read address using an address comparison circuit. When the comparison result matches, it determines the target message data and sends it back to the data processor. After receiving the target message data, the data processor forwards it to the data read request end, completing one read operation.

[0042] A write request is a write command sent to the data processor from external or internal processing units. The data to be written is the valid data carried in the write request that needs to be stored in the cache space. The write address is the address value specifying the destination location for the write operation. The write acknowledgment information is an acknowledgment signal returned by the storage regeneration circuit to the data processor after completing the write operation. The write requesting end is the source end that initiates the write request. After receiving the write request, the data processor parses the write address and the data to be written from the request and sends the write request, the data to be written, and the write address together as data processing information to the storage regeneration circuit. The storage regeneration circuit, in the cyclically transmitted message data, locates the target cache address that matches the message address and the write address through an address comparison circuit, and overwrites the data content field corresponding to that target cache address with the data to be written. After the write is completed, the storage regeneration circuit returns the write acknowledgment information to the data processor, which then sends this write acknowledgment information to the write requesting end to confirm the write operation is complete.

[0043] The technical problem solved and the technical effect achieved in this embodiment are as follows: the characteristic of the circular buffer is that data flows continuously with the loop, and is not fixed at a certain storage address waiting to be read. After the data processor 2 sends the read address to the storage regeneration circuit, the storage regeneration circuit intercepts the data according to the address matching at the moment the message flows through, so that the read operation does not need to wait for the target data to flow to a specific position, but will inevitably encounter the message corresponding to the target address and complete the reading within one cycle. The maximum read wait delay does not exceed one cycle, ensuring deterministic read delay. When performing a write operation in the circular buffer, the modified message data continues to be transmitted on the loop, and it is necessary to ensure that the write timing is synchronized with the message flow. The data processor sends the write address and the data to be written to the storage regeneration circuit together, and the storage regeneration circuit performs the write replacement at the moment the target message flows through the write controller, so that the updated message data seamlessly replaces the old message data and continues to circulate in the loop, and the write operation does not interrupt the normal circulation of the loop.

[0044] Furthermore, for scenarios requiring in-memory computing functionality, this embodiment also includes a data calculator in the optoelectronic hybrid storage device, such as... Figure 4 As shown, a data calculator can be either a processor executing in-memory arithmetic programs stored in non-volatile storage media, whereby the in-memory arithmetic program is a set of instruction codes used to perform data operations within a hybrid optoelectronic storage device; or a circuit that implements corresponding arithmetic functions, written in a hardware description language and obtained through logic synthesis and physical implementation. To facilitate the description of the data calculation process of the data calculator, this embodiment refines the data processor 2 into a write processor responsible for handling write requests and a read processor responsible for handling read requests. The data calculator is configured to: receive a calculation request that instructs to perform a calculation operation on source message data at at least one source address and write the calculation result to the destination address; extract the source address from the calculation request and send the source address to the read processor; obtain the source message data from the storage regeneration circuit 1 through the read processor and read the source data content from the source message data as the data to be calculated; perform corresponding calculation processing on the data to be calculated according to the calculation request and generate the calculation result; send the calculation result and the destination address to the write processor; write the calculation result as the data content to the message data corresponding to the destination address through the write processor and output the message data after writing the calculation result to the storage regeneration circuit 1; receive the write completion response information returned by the write processor and generate a calculation completion response.

[0045] When executed by the data calculator, the data calculator completes data processing according to the operation type and operand addresses indicated by the calculation command. The calculation request is a message containing operation instructions, the source addresses participating in the operation, and the destination address for storing the result. This message instructs that source message data at at least one source address be used as an operand to perform the specified operation, and the operation result be written to the destination address. Source message data refers to message data stored in the cache space whose message address matches the source address in the calculation request. Source data content is the payload carried by the data content field in the source message data. Data to be processed is data extracted from the source message data and awaiting processing by the calculation unit. Operation processing can include numerical or logical operations. Numerical operations include addition, subtraction, and multiplication; logical operations include bitwise AND, bitwise OR, and bitwise XOR; and operations such as finding the maximum, minimum, and average values ​​can also be performed.

[0046] The write processor is used to collect data write requests and provide corresponding responses. The write data sources for the write processor include write command requests from external sources and write calculation result requests from the data calculator. Upon receiving a write request, the write processor sends the write request, write address, and write data to the write controller in storage regeneration circuit 1. After completing the write operation, storage regeneration circuit 1 sends a write completion response. Upon receiving the write completion response, the write processor sends it to the data processor 2 (control command data parsing and response) or the data calculator, according to the corresponding write request source. The read processor is used to collect data read requests and provide corresponding responses. The read request sources for the read processor include read command requests from external sources and read data requests from the data calculator. Upon receiving a read request, the read processor sends the read request and read address to the read controller in storage regeneration circuit 1. After completing the read operation, storage regeneration circuit 1 sends the read data to the read processor. Upon receiving the read response, the read processor sends it to the data processor 2 (control command data parsing and response) or the data calculator, according to the corresponding read request source.

[0047] In this embodiment, after the data calculator receives a calculation request, the calculation request can be sent by the data processor 2, which handles control command data parsing and response. The data processor extracts the source address from the request and sends one or more source addresses to the read processor. The read processor performs a read operation based on the source address, retrieves the corresponding source message data from the storage regeneration circuit, extracts the source data content from the source message data, and returns the extracted source data content as the data to be calculated to the data calculator. The data calculator performs the corresponding calculation processing on the data to be calculated according to the calculation type indicated in the calculation request, generating the calculation result. Subsequently, the data calculator sends the calculation result and the destination address to the write processor. The write processor performs a write operation based on the destination address, writes the calculation result as the data content to be written into the message data corresponding to the destination address, and sends the message data after writing the calculation result back to the storage regeneration circuit to continue the loop. After completing the write operation, the write processor returns a write completion response to the data calculator, which then generates a calculation completion response, completing one in-memory calculation operation.

[0048] The technical problem solved and the technical effects achieved in this embodiment are as follows: Related caching devices require reading data from the cache and transmitting it to an external computing unit during data processing, and then writing the result back after the processing is complete. This data transfer process consumes a significant amount of bandwidth and time. This embodiment integrates the computing function into a data calculator within the data processor. The data calculator directly obtains the message data content located at the source address through the read processor and writes the calculation result back to the destination address through the write processor. The data involved in the calculation always flows within the optoelectronic hybrid storage device, without needing to be transferred to an external processing unit. This shortens the data transmission path from the cache to the computing unit, reduces the occupation of external data bandwidth, and allows the read and write processors to concurrently respond to the data calculator's requests, completing both read and write operations within one cycle, thus improving the overall throughput of in-memory computing. The optoelectronic hybrid caching device possesses high-speed in-memory computing capabilities. Compared to pure optical caching, it breaks through the time limit of optical caching, has a simple control circuit, and is particularly suitable for artificial intelligence caching scenarios requiring large-volume streaming storage and reading, and simple linear computing capabilities.

[0049] Furthermore, the data processor 2 also has command parsing and response functions. These functions are used to identify and distribute externally input control commands. The process of the data processor 2 performing command type identification and distribution is as follows: It receives external control commands and identifies their command type; when the command type is a write command, it sends the write address and the data to be written as data processing information, along with the data write request, to the data processor 2. After the write operation is completed, it generates a write response and sends the response to the data write request end; when the command type is a read command, it sends the read address and read length as data processing information, along with the data read request, to the data processor 2. After the read operation is completed, it generates a read completion response and sends the response and target message data to the data read request end; when the command type is a calculation command, it sends the calculation information to the data processor. After the calculation is completed, it generates a calculation completion response and sends the response and the calculation result to the calculation request end.

[0050] External control commands are command messages input through an external interface. The message format includes fields to distinguish the command type. Command types include write commands, read commands, and computation commands. A write command instructs data to be written to a cache space at a specified address; a read command instructs data to be read from a cache space at a specified address; and a computation command instructs data to be processed at a specified address and the result stored at the destination address.

[0051] like Figure 5 As shown, after receiving an external control command, data processor 2 parses the command type field. When identified as a write command, it extracts the write address and the data to be written from the command, and sends these as data processing information, along with the data write request, to the storage regeneration circuit for processing. After the storage regeneration circuit completes the write operation and returns a write acknowledgment signal, the data processor generates write acknowledgment information and sends it to the requesting end that initially issued the write command. When identified as a read command, it extracts the read address and read length from the command, and sends these as data processing information, along with the data read request, to the storage regeneration circuit. After the storage regeneration circuit completes the read operation and returns the target message data, the data processor generates read completion acknowledgment information and sends it, along with the read target message data, to the requesting end that initially issued the read command. When identified as a calculation command, it extracts calculation information from the command. The calculation information includes the source operand address, destination address, and operation type. The data processor sends the calculation information to the data calculator for processing. After the data calculator completes the calculation and returns the result, the data processor generates a calculation completion response and sends the response and the result together to the requesting end that originally issued the calculation command.

[0052] The technical problem solved and the technical effects achieved in this embodiment are as follows: the optoelectronic hybrid storage device provides three types of services: write, read, and compute, requiring a unified command interface for external requesting parties to interact. By setting up command parsing and response functions, the data processor automatically classifies and routes input commands according to type fields. Write commands are distributed to the write data path of the storage regeneration circuit, read commands are distributed to the read data path of the storage regeneration circuit, and compute commands are distributed to the data calculator, avoiding the interface complexity caused by external requesting parties interacting with multiple internal modules separately. Simultaneously, the data processor uniformly encapsulates the completion responses for various operations, requiring external requesting parties to only face a unified command interaction point, reducing the complexity of system integration.

[0053] Finally, please see Figure 6 This application also provides a data processing method for the optoelectronic hybrid storage device described in any of the above embodiments. In some embodiments of this method, the following steps may be included: S601: Transmits optical signals in an optical fiber delay line.

[0054] S602: The storage and regeneration circuit receives the optical signal output from the fiber optic delay line, converts the optical signal into message data, and uses the message data as the basic electrical signal to convert it back into an optical signal before sending it to the fiber optic delay line, so that the message data is transmitted cyclically in the loop formed by the storage and regeneration circuit and the fiber optic delay line.

[0055] S603: When the data processor receives a data processing request, it sends the data processing request and data processing information to the storage regeneration circuit, and uses the storage regeneration circuit to determine the target data that matches the data processing request in the cyclic message data.

[0056] S604: Send the data processing result to the data processing request end.

[0057] As can be seen from the above, in the optical buffering method of this embodiment, the optical signal is transmitted cyclically in the optical fiber delay line. Each cycle undergoes a signal regeneration process involving photoelectric conversion and electro-optical conversion, combining optical domain transmission with electrical domain regeneration. The optical domain provides a stable propagation delay as a buffering time reference, while the electrical domain completes the recovery, reading, writing, and regeneration of message data. This overcomes the upper limit of the number of cycles caused by noise accumulation in the optical domain, allowing the buffering time to be extended as needed. Simultaneously, the data processor locates the target data in the cyclically streaming message sequence through address matching, unifying write and read operations into an address-addressing process for the target message. This enables random read / write access to data in the optical buffer, expanding the application scenarios of optical buffering.

[0058] It should be noted that there is no strict order of execution for the steps in this application. As long as they conform to a logical order, these steps can be executed simultaneously or in a certain preset order. Figure 6 This is just an illustrative example and does not mean that this is the only possible execution order.

[0059] This application also provides a corresponding apparatus for the data processing method, further enhancing the practicality of the method. The apparatus can be described from both a functional module perspective and a hardware perspective. The data processing apparatus provided in this application is described below. This apparatus is used to implement the data processing method provided in this application. In this embodiment, the data processing apparatus may include or be divided into one or more functional modules. These one or more functional modules may be stored in a storage medium and executed by one or more processors, or they may be performed by one or more dedicated hardware circuits. The following description will specifically introduce the functions of each module in this embodiment. The data processing apparatus described below and the data processing method described above can be referred to and correspond to each other.

[0060] From the perspective of functional modules, a structural diagram of the data processing device of the optoelectronic hybrid storage device in one specific embodiment is shown. The device may include: The signal transmission module is used to transmit optical signals in an optical fiber delay line; The message data loop module is used to receive the optical signal output from the fiber optic delay line through the storage and regeneration circuit, convert the optical signal into message data, and use the message data as the basic electrical signal to convert it back into an optical signal and send it to the fiber optic delay line, so that the message data is circulated and transmitted in the loop formed by the storage and regeneration circuit and the fiber optic delay line. The data processing module is used to send the data processing request and data processing information to the storage and regeneration circuit when the data processor receives a data processing request. The storage and regeneration circuit then uses the data processing module to determine the target data that matches the data processing request from the cyclic message data. The results feedback module is used to send the data processing results to the data processing request end.

[0061] The data processing apparatus for the optoelectronic hybrid storage device mentioned above is described from the perspective of functional modules. Furthermore, this application also provides an electronic device, described from a hardware perspective. This electronic device includes a memory and a processor. The memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above-described embodiments of the data processing method for the optoelectronic hybrid storage device.

[0062] It is understood that if the data processing method of the optoelectronic hybrid storage device in the above embodiments is implemented as a software functional unit and sold or used as an independent product, it can be stored in a non-volatile storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the related technology, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of this application. The aforementioned storage medium includes, but is not limited to, various media capable of storing program code, such as: USB flash drive, mobile hard disk, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, register, hard disk, multimedia card, card-type memory (e.g., SD or DX memory), magnetic memory, removable disk, CD-ROM, magnetic disk, or optical disk. Based on this, this application also provides a non-volatile storage medium storing a computer program, which, when executed by a processor, performs the steps of the data processing method of the optoelectronic hybrid storage device as described in any of the above embodiments.

[0063] It is understood that if the data processing method of the optoelectronic hybrid storage device in the above embodiments is implemented as a software functional unit and sold or used as an independent product, the computer software product may not need to be stored in a physical storage medium. For example, it can be directly transmitted to a computer or other device with information processing capabilities via a wired or wireless network to execute all or part of the steps of the methods in the various embodiments of this application. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the related technology, or all or part of the technical solution, can be embodied in the form of a software product. Based on this, this application also provides a computer program product storing a computer program, which, when executed by a processor, performs the steps of the data processing method of the optoelectronic hybrid storage device as described in any of the above embodiments.

[0064] The foregoing has provided a detailed description of an optoelectronic hybrid storage device and its data processing method. The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. Whether the units and algorithm steps of the various examples described in the disclosed embodiments are executed in electronic hardware or computer software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, and such implementations should not be considered beyond the scope of this application. Several improvements and modifications can be made to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A hybrid optoelectronic storage device, characterized in that, This includes a data processor and storage regeneration circuitry connected via fiber optic delay lines; The storage and regeneration circuit receives the optical signal output by the optical fiber delay line, converts the optical signal into message data, and uses the message data as the basic electrical signal to convert it back into an optical signal and send it to the optical fiber delay line, so that the message data is cyclically transmitted in the loop formed by the storage and regeneration circuit and the optical fiber delay line. The data processor is configured as follows: A data processing request is received, and the data processing request and data processing information are sent to the storage regeneration circuit. The storage regeneration circuit determines the target data that matches the data processing request from the cyclic message data, and sends the received data processing result to the data processing request end.

2. The optoelectronic hybrid storage device according to claim 1, characterized in that, The storage regeneration circuit: Receive the optical signal emitted from the optical fiber delay line, convert the optical signal into an electrical signal, recover the message data from the electrical signal, and store it; Obtain target message data from stored message data. If the address information in the target message data matches the address information corresponding to the data to be read, then output the data content in the target message data as the data to be read. Obtain target message data from the stored message data. If the address information in the target message data matches the address information corresponding to the data to be written, write the data to be written to the storage location corresponding to the target message data to update the stored message data. Based on the stored or updated message data, a driving electrical signal is regenerated, and the driving electrical signal is converted into an optical signal and sent to the optical fiber delay line, so that the optical signal transmitted to the optical fiber delay line is regenerated based on the stored message data.

3. The optoelectronic hybrid storage device according to claim 1, characterized in that, After each cycle of transmission in the optical fiber delay line, the optical signal is converted into message data by the storage and regeneration circuit, and then converted back into an optical signal by the storage and regeneration circuit for transmission to the optical fiber delay line. The storage and regeneration circuit includes: A photoelectric converter receives the optical signal output from the optical fiber delay line and converts the optical signal into an electrical signal; A circular buffer, connected to the photoelectric converter, stores the recovered message data and outputs the stored message data in a first-in-first-out order; An electro-optical converter, connected to the cyclic buffer, generates a driving electrical signal based on the message data obtained from the cyclic buffer, and converts the driving electrical signal into an optical signal before sending it to the optical fiber delay line; The read controller is connected to the data path between the loop buffer and the photoelectric converter. According to the data read request sent by the data processor, it extracts the target message data corresponding to the data read request from the flowing message data, matches the address information in the target message data with the read address, and sends the data content in the target message data to the data processor when the address matches. The write controller is connected to the data path between the electro-optical converter and the circular buffer. According to the data write request sent by the data processor, it writes the data to be written to the corresponding position in the message data flowing through it, and sends the updated message data to the circular buffer.

4. The optoelectronic hybrid storage device according to claim 3, characterized in that, The storage regeneration circuit enters an initialization state after power-on reset. In the initialization state: The write controller determines the number of packets based on the transmission length of the optical fiber delay line and the capacity of the circular buffer, and generates a corresponding number of buffered packets, each of which contains a packet address and data content. The write controller stores the cached message into the circular buffer. The cached message is converted into an optical signal by the electro-optic converter and then sent to the optical fiber delay line. After the cached message is transmitted through the optical fiber delay line and returned to the storage regeneration circuit to complete one cycle, the storage regeneration circuit enters the working state and begins to respond to the read and write data processing requests of the data processor.

5. The optoelectronic hybrid storage device according to claim 4, characterized in that, The write controller generates the cached messages according to a preset order of message addresses, and fills the gaps between adjacent cached messages with free code blocks; The cache space for the data processor to perform read and write operations is determined based on the number of messages, the number of free code blocks between messages, and the framing overhead within the messages.

6. The optoelectronic hybrid storage device according to claim 1, characterized in that, The data processor is also configured to: Receive external control commands and identify the command type of the external control commands; When the command type is a write command, the write address and the data to be written are sent to the data processor along with the data write request as the data processing information. After the write operation is completed, a write response is generated and sent to the data write request end. When the command type is a read command, the read address and read length are used as the data processing information and sent to the data processor along with the data read request. After the read operation is completed, a read completion response is generated and the read completion response and target message data are sent to the data read request end. When the command type is a calculation command, the calculation information is sent to the data calculator. After the calculation is completed, a calculation completion response is generated, and the calculation completion response and the calculation result are sent to the calculation request end.

7. The optoelectronic hybrid storage device according to claim 1, characterized in that, The data processing request is a data read request, and the data processor is configured as follows: Receive data read request; The data read request and read address are sent to the storage regeneration circuit to determine the target message data that matches the read address in the cyclic message data; Upon receiving the target message data, the target message data is sent to the data read request terminal.

8. The optoelectronic hybrid storage device according to claim 1, characterized in that, The data processing request is a data write request, and the data processor is configured as follows: Receive data write request; The data write request, the data to be written, and the write address are sent to the storage regeneration circuit to determine the target cache address that matches the write address from the cache addresses corresponding to the cyclic message data, and the data to be written is written to the target cache address. Upon receiving a write response message, the write response message is sent to the data write request end.

9. The optoelectronic hybrid storage device according to any one of claims 1 to 8, characterized in that, The data processor includes a write processor and a read processor, and also includes a data calculator, which is configured as follows: A calculation request is received that instructs the execution of a computational operation on source message data at at least one source address and writes the computation result to the destination address. The source address is extracted from the computation request and sent to the read processor. The read processor obtains the source message data from the storage regeneration circuit and reads the source data content from the source message data as the data to be computed. Based on the computation request, perform corresponding computational processing on the data to be computed and generate computational results; The calculation result and the target address are sent to the write processor, which writes the calculation result as data content into the message data corresponding to the target address, and outputs the message data after writing the calculation result to the storage regeneration circuit. Receive the write completion response information returned by the write processor and generate a calculation completion response.

10. A data processing method, characterized in that, Applied to the optoelectronic hybrid storage device as described in any one of claims 1 to 9, comprising: Transmit optical signals in an optical fiber delay line; The storage and regeneration circuit receives the optical signal output from the optical fiber delay line, converts the optical signal into message data, and uses the message data as the basic electrical signal to convert it back into an optical signal and send it to the optical fiber delay line, so that the message data is cyclically transmitted in the loop formed by the storage and regeneration circuit and the optical fiber delay line. When the data processor receives a data processing request, it sends the data processing request and data processing information to the storage regeneration circuit, and uses the storage regeneration circuit to determine the target data that matches the data processing request from the cyclic message data. Send the data processing results to the data processing request end.

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