Phase change memory

Abstract

This application provides a phase-change memory (PCM) including a memory array and peripheral circuitry coupled to the memory array. The memory array includes multiple first address lines, multiple second address lines, and multiple PCM cells. The peripheral circuitry includes: a temperature sensing circuit configured to output a first signal, the first signal including digital information corresponding to the current temperature; a selection circuit configured to sequentially select one of multiple first compensation parameters as a first output compensation parameter; an arithmetic circuit configured to receive the first signal and the first output compensation parameter, and output a second signal, the second signal including digital information corresponding to an adjustment voltage; and a first conversion circuit coupled to the first and second address lines, configured to receive a reference voltage and the second signal, and output a third signal, the third signal including analog information corresponding to a compensation target voltage. This application can reduce the area of ​​the PCM.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a phase-change memory. Background Technology

[0002] Phase-change random access memory (PCRAM) bridges the performance gap between dynamic random access memory (DRAM) and flash memory, offering advantages such as high-speed read speeds, high erase / write cycles, non-volatility, small device size, low power consumption, and resistance to strong shocks and radiation, leading to its widespread use. With the increasing demand for wider operating temperature ranges and larger storage capacities of PCRAM, more voltage and current are required, necessitating temperature compensation. Achieving more precise energy control to ensure optimal read / write performance at various temperatures has become a pressing technical challenge. Summary of the Invention

[0003] This application provides a phase-change memory that can reduce the area of ​​the phase-change memory.

[0004] This application provides a phase-change memory (PCM) comprising a memory array and peripheral circuitry coupled to the memory array. The memory array includes multiple first address lines, multiple second address lines, and multiple PCM cells. The peripheral circuitry includes: a temperature sensing circuit configured to output a first signal; the first signal including digital information corresponding to the current temperature; a selection circuit configured to sequentially select one of multiple first compensation parameters as a first output compensation parameter; the first compensation parameter including first slope information corresponding to multiple temperature ranges, used for temperature compensation of a target voltage; an arithmetic circuit configured to receive the first signal and the first output compensation parameter, and output a second signal; the second signal including digital information corresponding to an adjustment voltage; the adjustment voltage being a voltage for temperature compensation of the target voltage; and a first conversion circuit coupled to the first and second address lines, configured to receive a reference voltage and the second signal, and output a third signal; the third signal including analog information corresponding to the compensation target voltage; the compensation target voltage being the voltage after temperature compensation of the target voltage.

[0005] In some embodiments, the first conversion circuit is configured to: provide a first compensation target voltage to the first address line according to the corresponding third signal during the set operation, the reset operation, or the read operation; and provide a second compensation target voltage to the second address line according to the corresponding third signal; the second compensation target voltage is less than the first compensation target voltage.

[0006] In some embodiments, the first conversion circuit includes a first digital-to-analog converter, a voltage regulator, and a first voltage follower; the first digital-to-analog converter is configured to receive a reference voltage and a second signal, and output a first analog signal; the first analog signal includes analog information corresponding to a compensation target voltage; the voltage regulator is configured to receive the first analog signal and output a second analog signal; the second analog signal is amplified information of the first analog signal; the first voltage follower is configured to receive the second analog signal and output a third signal.

[0007] In some embodiments, the temperature sensing circuit includes a bandgap reference circuit and a temperature sensor; the bandgap reference circuit is configured to output a positive temperature coefficient voltage and a reference voltage; the temperature sensor is configured to receive the positive temperature coefficient voltage and the reference voltage, sense the current temperature, and output a first signal.

[0008] In some embodiments, the peripheral circuit further includes a second conversion circuit; a selection circuit, further configured to sequentially select one of a plurality of second compensation parameters as a second output compensation parameter; the second compensation parameters include second slope information corresponding to a plurality of temperature ranges respectively, used for temperature compensation of the target current; an arithmetic circuit, further configured to receive a first signal and a second output compensation parameter, and output a fourth signal; the fourth signal includes digital information corresponding to the adjustment current; the adjustment current is the current for temperature compensation of the target current; the second conversion circuit, coupled to a second address line, and configured to receive a reference current and the fourth signal, and output a fifth signal; the fifth signal includes analog information corresponding to the compensation target current; the compensation target current is the current after temperature compensation of the target current.

[0009] In some embodiments, the target current includes a set current, the compensated target current includes a compensated set current, and the compensated set current is the current after temperature compensation of the set current according to the current temperature; the second conversion circuit is configured to: provide a compensated set current to the second address line according to the corresponding fifth signal during the set operation; or, the target current includes a reset current, the compensated target current includes a compensated reset current, and the compensated reset current is the current after temperature compensation of the reset current according to the current temperature; the second conversion circuit is configured to: provide a compensated reset current to the second address line according to the corresponding fifth signal during the reset operation; or, the target current includes a read current, the compensated target current includes a compensated read current, and the compensated read current is the current after temperature compensation of the read current according to the current temperature; the second conversion circuit is configured to: provide a compensated read current to the second address line according to the corresponding fifth signal during the read operation.

[0010] In some embodiments, the second conversion circuit includes a second digital-to-analog converter, a second voltage follower, and an output device; the second digital-to-analog converter is configured to receive a reference current and a fourth signal, and output a third analog signal; the third analog signal includes analog information corresponding to the compensation target current; the second voltage follower is configured to receive the third analog signal and output a fourth analog signal; the output device is configured to receive the fourth analog signal and output a fifth signal.

[0011] In some embodiments, the arithmetic circuit includes an arithmetic section and an output section; the arithmetic section is configured to receive a first signal and a first output compensation parameter, and output a first digital signal; the first digital signal includes digital information corresponding to an adjustment amount of the adjustment voltage; the output section is configured to receive the first digital signal and a second digital signal, and output a second signal; the second digital signal includes digital information corresponding to a reference amount of the adjustment voltage; the second signal includes digital information corresponding to the sum of the adjustment amount and the reference amount.

[0012] In some embodiments, the multiple temperature ranges are multiple consecutive temperature ranges; the arithmetic part includes a multiplier and a first adder; the arithmetic part is configured to: perform temperature compensation on the target voltage based on the first slope information corresponding to the temperature range, to obtain the correspondence between the temperature in each temperature range and the corresponding compensation target voltage; and output a second signal according to the first signal and the correspondence between the temperature in the temperature range where the current temperature is located and the corresponding compensation target voltage.

[0013] In some embodiments, the output section includes a latch and a second adder; the latch is configured to latch a first digital signal and a second digital signal; the second adder is configured to sum the first digital signal and the second digital signal.

[0014] In various embodiments of this application, a time-division multiplexing arithmetic circuits are used. The arithmetic circuits perform serial calculations on multiple target voltages to achieve temperature compensation for multiple target voltages and obtain multiple corresponding compensated target voltages. Compared with the method that occupies a large area due to parallel operation of multiple arithmetic circuits, the embodiments of this application can reduce the area of ​​the phase change memory. Attached Figure Description

[0015] Figure 1 A block diagram of a memory system provided in an embodiment of this application; Figure 2 A block diagram of an exemplary memory including a storage array and peripheral circuitry provided for embodiments of this application; Figure 3 One of the block diagrams of an exemplary memory array and an exemplary peripheral circuit provided for embodiments of this application; Figure 4 One of the three-dimensional schematic diagrams of a phase-change memory provided in an embodiment of this application; Figure 5 A second three-dimensional schematic diagram of a phase-change memory provided in an embodiment of this application; Figure 6 A schematic diagram of pulses during each operation process of the phase-change memory unit provided in the embodiments of this application; Figure 7 A schematic diagram of the peripheral circuit for voltage-temperature compensation provided in an embodiment of this application; Figure 8 A schematic diagram of the storage array and some peripheral circuits coupled to the storage array provided in the embodiments of this application; Figure 9 A schematic diagram of an arithmetic circuit provided in an embodiment of this application; Figure 10 A schematic diagram of the first conversion circuit provided in an embodiment of this application; Figure 11 A schematic diagram of the peripheral circuit for voltage temperature compensation and current temperature compensation provided in the embodiments of this application; Figure 12 A schematic diagram of the second conversion circuit provided in an embodiment of this application; Figure 13 A schematic diagram illustrating temperature compensation for multiple temperature ranges provided in the embodiments of this application; Figure 14 A block diagram of a readable storage medium provided in an embodiment of this application. Detailed Implementation

[0016] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0017] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0018] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0019] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0020] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0022] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0023] This application provides a system comprising: a host and a memory system coupled to the host (see reference). Figure 1 The system can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. The host can be the processor of the electronic device, such as a central processing unit (CPU) or a system-on-a-chip (SoC), where the SoC can be, for example, an application processor (AP). The host can be configured to send data to or receive data from the memory system.

[0024] Figure 1 A block diagram of a memory system provided in an embodiment of this application.

[0025] refer to Figure 1 This application provides a memory system 100, which includes: a memory 300; the memory 300 includes a phase change memory; and a memory controller 200, which is coupled to the memory 300 and configured to control the memory 300.

[0026] In some embodiments, the memory controller 200 may control the overall operation of the memory system 100, such as write operations, read operations, and refresh operations. In some embodiments, the memory controller 200 is configured to store data in the memory 300, or to read data stored in the memory 300.

[0027] In some embodiments, the memory controller 200 is also configured to handle error checking and correction (ECC) of data read from or written to the memory 300. In some embodiments, the memory controller 200 may also be configured to manage various functions relating to data stored or to be stored in the memory, including but not limited to logical-to-physical address translation, bad block management, garbage collection, wear leveling, etc.

[0028] In some embodiments, memory 300 may include one of phase-change random access memory, resistive random access memory (RRAM), magnetic random access memory (MRAM), and nanotube random access memory (NRAM).

[0029] In some embodiments, the memory controller 200 is also configured to store various information required for the operation of the memory system 100 (e.g., metadata information and mapping tables) into volatile memory. Figure 1 (Not shown), and memory 300 can be accessed based on information stored in volatile memory. In some embodiments, the volatile storage device may include dynamic random access memory, static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), or double-data-rate fourth generation synchronous dynamic random access memory (DDR4 SDRAM).

[0030] Figure 2 A block diagram of an exemplary memory including a storage array and peripheral circuitry, provided for embodiments of this application.

[0031] refer to Figure 2 The memory 300 may include a memory array 301 and peripheral circuitry 302 coupled to the memory array 301. In some embodiments, the peripheral circuitry 302 is configured to control the overall operation of the memory 300, such as write operations, read operations, and refresh operations. In some embodiments, the peripheral circuitry 302 is configured to store data in the memory array 301, or to read data stored in the memory array 301.

[0032] Figure 3 Block diagrams of exemplary memory arrays and exemplary peripheral circuits provided for embodiments of this application.

[0033] refer to Figure 3The memory 300 may include a memory array 301 and peripheral circuitry coupled to the memory array 301. In some embodiments, the memory array 301 may include word lines WL, bit lines BL, and memory cells 301a formed between the word lines WL and BL; the memory cells 301a are located at the intersection between the word lines WL and BL and are coupled to the word lines WL and BL. In some embodiments, the peripheral circuitry may be configured to apply word line voltages to selected word lines WL and bit line voltages to selected bit lines BL, operating the memory cells 301a of the memory array 301. In some embodiments, the peripheral circuitry may include: control logic 312, an address register 314, a voltage generator 310, a row decoder / word line driver 308, a page buffer / sensor amplifier circuit 304, a column decoder / bit line driver 306, and a data register / data I / O 316.

[0034] Page buffer / sensor amplifier circuit 304 can be configured to read data from memory array 301 and program (write) data to memory array 301 according to control signals from control logic 312. In one example, page buffer / sensor amplifier 304 can store programming data (write data) to be programmed into a page of memory array 301. In another example, page buffer / sensor amplifier 304 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, page buffer / sensor amplifier 304 can also sense a low-power signal representing a data bit stored in the memory cell from the selected bit line and amplify a small voltage swing to a recognizable logic level during a read operation. In some embodiments, page buffer / sensor amplifier 304 may include a comparator (e.g., a voltage comparator) for comparing a voltage signal (e.g., a read voltage) with a reference voltage signal. Column decoder / bit line driver 306 can be configured to be controlled by control logic 312 and select one or more memory cells and bit lines. Column decoder / bit line driver 306 can be further configured to drive the selected bit line. The column decoder / bit line driver 306 may be further configured to drive the bit lines using a bit line voltage generated from the voltage generator 310. The column decoder / bit line driver 306 may be a binary data storage device for storing bits. In some embodiments, the column decoder / bit line driver 306 may include a read data latch to store read data.

[0035] The data register / data I / O 316 may be coupled to the page buffer / sensor amplifier 304, and / or coupled to the column decoder / bit line driver 306, and is configured to route data input from the data bus 318 to the desired memory cell of the memory array 301, and to route data output from the desired memory cell to the data bus 318.

[0036] The row decoder / word line driver 308 can be configured to be controlled by control logic 312 and to select one or more memory cells and word lines of the memory array 301. The row decoder / word line driver 308 can be further configured to drive the selected word lines. The row decoder / word line driver 308 can be further configured to drive the word lines using word line voltages generated from voltage generator 310.

[0037] The voltage generator 310 can be configured to be controlled according to control signals from the control logic 312 and to generate word line voltages, bit line voltages and reference voltages to be supplied to the memory array 301.

[0038] Control logic 312 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each of the peripheral circuits. Control logic 312 is configured to receive a clock signal ( Figure 3 (Not shown), command signal CMD, address signal ( Figure 3 (Not shown) and data signal DQ, wherein command signal CMD is received via command bus 320; and data signal DQ is received via data bus 318. In some embodiments, control logic 312 may be implemented by a microprocessor, microcontroller (also known as a micro controller unit (MCU)), digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), programmable logic device (PLD), state machine, gating logic, discrete hardware circuitry, and other suitable hardware, firmware, and / or software configured to perform the various functions described.

[0039] In some embodiments, memory 300 may be phase-change random access memory (PCM), and memory cells 301a of memory array 301 may be PCM cells. In some embodiments, the PCM has a transistorless crosspoint architecture, which positions the PCM cells between intersecting (e.g., perpendicular) word lines and bit lines. The word lines and bit lines may be made of a conductive material with constant linewidth (Line / Space, L / S) formed after a patterning process. The PCM cells may include stacked gating elements and PCM elements.

[0040] In this document, the first direction, the second direction, and the third direction intersect each other (e.g., are orthogonal). The first direction can be understood as the extension direction of the first address line, the second direction as the extension direction of the second address line, and the third direction as the stacking direction of each layer / component of the phase-change memory cell. For example, the first direction is represented by the X direction in the attached figure; the second direction is represented by the Y direction in the attached figure; and the third direction is represented by the Z direction in the attached figure. Any two of the X, Y, and Z directions are orthogonal to each other.

[0041] Figure 4 This is one of the three-dimensional schematic diagrams of a phase-change memory provided in an embodiment of this application.

[0042] refer to Figure 4 In some embodiments, the phase-change memory includes word line WL, phase-change memory cell 301-0, and bit line BL stacked sequentially from bottom to top; the phase-change memory cell 301-0 includes a first electrode 3011, a gating element 3012, a second electrode 3013, a phase-change memory element 3014, and a third electrode 3015 stacked sequentially from bottom to top.

[0043] In some embodiments, the word line WL and bit line BL are made of conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, conductive nitrides, or any combination thereof. The word line WL and bit line BL may have the same conductive material or different conductive materials. Exemplarily, the word line WL and bit line BL are made of tungsten.

[0044] In some embodiments, the first electrode 3011, the second electrode 3013, and the third electrode 3015 are electrode layers in a phase-change memory cell, used for conducting electrical signals. It should be noted that... Figure 4 The electrode layers, designated by different reference numerals in the accompanying drawings, are merely for distinguishing differences in the location of the electrode layers and are not necessarily used to describe a specific order or sequence. In some embodiments, the materials of the first electrode 3011, the second electrode 3013, and the third electrode 3015 may be the same or different. The materials of the first electrode 3011, the second electrode 3013, and the third electrode 3015 may include amorphous carbon, such as α-phase carbon.

[0045] In some embodiments, the material of the gating element 3012 may include: an octagonal threshold switching (OTS) material, such as ZnaTeb, GeaTeb, NbaOb, or SiaAsbTec, where a, b, and c represent stoichiometric coefficients.

[0046] In some embodiments, the phase change memory element 3014 is made of a chalcogenide-based phase change material. Exemplarily, the phase change memory element 3014 is made of a binary phase change material, such as GaSb, InSb, InSe, Sb₂Te₃, Sb₇Te₃, GeTe, etc. Exemplarily, the phase change memory element 3014 is made of a ternary phase change material, such as Ge₂Sb₂Te₅, Ge₁Sb₄Te₇, InSbTe, GaSeTe, etc. Exemplarily, the phase change memory element 3014 is made of a quaternary phase change material, such as AgInSbTe, GeTeSbS, GeTeInGa, etc.

[0047] Figure 5 This is a second three-dimensional schematic diagram of a phase-change memory provided in an embodiment of this application. Figure 5 The phase-change memory shown can be understood as a three-dimensional phase-change memory, which can consist of multiple Figure 4 The phase change memory shown is stacked together.

[0048] In some embodiments, the phase-change memory includes an upper storage structure 301-U and a lower storage structure 301-D stacked sequentially from bottom to top. The lower storage structure 301-D includes a word line WL, a phase-change memory cell 301-1, and a bit line BL stacked sequentially from bottom to top. The phase-change memory cell 301-1 includes a first electrode 3011, a gating element 3012, a second electrode 3013, a phase-change memory element 3014, and a third electrode 3015 stacked sequentially from bottom to top. The upper storage structure 301-U is located above the lower storage structure 301-D and includes a bit line BL, a phase-change memory cell 301-2, and a word line WL stacked sequentially from bottom to top. The phase-change memory cell 301-2 includes a first electrode 3011, a gating element 3012, a second electrode 3013, a phase-change memory element 3014, and a third electrode 3015 stacked sequentially from bottom to top. The materials for the word line WL, bit line BL, first electrode 3011, gating element 3012, second electrode 3013, phase change memory element 3014, and third electrode 3015 can be referenced. Figure 4 The relevant embodiments will be understood from here, and will not be repeated. It is understood that the bit line BL of the upper memory structure 301-U and the bit line BL of the lower memory structure 301-D can be understood as a common bit line.

[0049] Figure 4 and Figure 5 The word line WL and bit line BL in the phase-change memory shown can also be understood by interchanged positions. In practical applications, by activating the selected word line and the selected bit line, the phase-change memory cell connected to both the selected word line and the selected bit line can be selected.

[0050] Figure 6This is a pulse diagram illustrating the various operational processes of the phase-change memory unit provided in the embodiments of this application. It should be noted that... Figure 6 The voltage pulses shown are only used to illustrate the principle of the transition between the crystalline and amorphous states of the phase change material in the phase change memory cell. The actual pulses in each operation process of the phase change memory cell can be based on... Figure 6 The principle of the voltage pulse shown is adapted accordingly. For example, Figure 6 The voltage pulse for the SET operation shown is a voltage plateau, but in practice it can also be multiple voltage plateaus in a stepped pattern. For example, Figure 6 The voltage pulses of the RESET operation shown above the melting temperature TM exhibit a curve of rising and then falling, and may actually include a voltage plateau.

[0051] refer to Figure 6In some embodiments, phase change memory (PCM) utilizes the crystalline and amorphous properties of the phase change material in the PCM cell to store data. Different electrical pulses are used to induce a rapid and reversible phase transition between the amorphous and crystalline states of the PCM. During the transition between the crystalline and amorphous states of the PCM in the PCM cell, different pulses (e.g., light pulses, electrical pulses) can be used to control the heating of the PCM. In one optional implementation, a long and medium-intensity programming pulse (also known as a Set Pulse) is applied to raise the temperature of the phase change material in the phase change memory cell above the crystallization temperature TX but below the melting temperature TM, and this temperature is maintained for a period of time to promote nucleus growth. This allows the phase change material in the phase change memory cell to transition from an amorphous state (corresponding to a high-resistivity state) to a crystalline state (corresponding to a low-resistivity state). The process of changing the phase change material in the phase change memory cell from a high configuration (logic state "0") to a low-resistivity state (logic state "1") is called a set operation, or a write operation. After applying a short and high-intensity reset pulse (also known as a Reset Pulse) to raise the temperature of the phase change material in the phase change memory cell above the melting temperature TM, it is then rapidly cooled. The reset (or erase) operation is a process that enables the phase change material of a phase change memory cell to transition from a crystalline to an amorphous state. This process, where the phase change material changes from a low-resistance state (logic state "1") to a high-resistance state (logic state "0"), is called the reset operation or the erase operation. The reset and set operations are reversible. A phase change memory cell can use the crystalline state of the phase change material to represent binary data "1" and the amorphous state to represent binary data "0". In some embodiments, a short, low-intensity read pulse (also called a read pulse) is applied to keep the temperature of the phase change material far below its crystallization temperature TX, preventing a phase change. The current in the circuit is measured to determine the resistance of the phase change material. Based on the resistance value, the read data is determined to be either "0" or "1". This process is called the read operation (RD). For example, the set operation of the phase change memory needs to be completed at time tSET, the reset operation needs to be completed at time tRESET, and the read operation needs to be completed at time tRD, wherein time tRESET is later than time tRD, and time tSET is later than time tRESET.

[0052] To meet the requirements of two stacked phase-change memory (reference) Figure 5The design requirements of a phase-change memory (PCM) necessitate, for example, six temperature compensation channels. Five of these channels can be used for temperature compensation at five different voltages, and one channel can be used for current temperature compensation. These six channels are connected in parallel and can each perform temperature compensation independently. However, to meet the design requirements of multi-layer (e.g., three or four layers) PCMs, more different voltages and currents are needed. The number of compensation channels increases from six to, for example, seventeen. Using a seventeen-channel parallel temperature compensation system with each channel performing independent temperature compensation is unsuitable because it increases the area of ​​the PCM.

[0053] Figure 7 This is a schematic diagram of the peripheral circuit for voltage and temperature compensation provided in an embodiment of this application. Figure 8 This is a schematic diagram of the storage array and some peripheral circuits coupled to the storage array, provided in an embodiment of this application.

[0054] According to a first aspect of the embodiments of this application, a phase-change memory is provided, with reference to... Figure 7 and Figure 8The phase-change memory 300 includes a memory array 301 and peripheral circuitry 302 coupled to the memory array 301. The memory array 301 includes multiple first address lines (also referred to herein as word lines WL), multiple second address lines (also referred to herein as bit lines BL), and multiple phase-change memory cells 310a. The peripheral circuitry 302 includes: a temperature sensing circuit 324 configured to output a first signal temp_code; the first signal temp_code includes digital information corresponding to the current temperature; and a selection circuit 326 configured to sequentially select one of multiple first compensation parameters (parameter P_0, parameter P_1, ..., parameter P_N-1, parameter P_N) as a first output compensation parameter P_J; the first compensation parameter includes multiple temperature sensing circuitry 310a. The first slope information corresponding to each degree interval is used to perform temperature compensation on the target voltage; the arithmetic circuit 328 is configured to receive the first signal temp_code and the first output compensation parameter P_J, and output the second signal trim_code1; the second signal trim_code1 includes digital information corresponding to the adjustment voltage; the adjustment voltage is the voltage for temperature compensation of the target voltage; the first conversion circuit 330 is coupled to the first address line and the second address line, and is configured to receive the reference voltage VBG and the second signal trim_code1, and output the third signal V_trim; the third signal V_trim includes analog information corresponding to the compensation target voltage; the compensation target voltage is the voltage after temperature compensation of the target voltage. In this embodiment, a time-division multiplexing arithmetic circuit is used. The arithmetic circuit performs serial calculations on multiple target voltages to achieve temperature compensation of multiple target voltages, obtaining multiple corresponding compensation target voltages. Compared with the method that occupies a large area due to parallel operation of multiple arithmetic circuits, this embodiment can reduce the area of ​​the phase change memory.

[0055] refer to Figure 7 In some embodiments, the temperature sensing circuit 324 includes a bandgap reference circuit 324a and a temperature sensor 324b; the bandgap reference circuit 324a is configured to output a positive temperature coefficient voltage VPTAT and a reference voltage VBG; the temperature sensor 324b is configured to receive the positive temperature coefficient voltage VPTAT and the reference voltage VBG, sense the current temperature, and output a first signal temp_code.

[0056] The bandgap reference circuit 324a is used to sum a voltage with a positive temperature coefficient and a voltage with a negative temperature coefficient, whose temperature coefficients cancel each other out, to achieve a reference voltage independent of process and temperature variations. Exemplarily, the bandgap reference circuit 324a includes a bipolar transistor (BJT). Figure 7(Not shown) Based on the fact that the base-emitter voltage VBE of a bipolar transistor has a negative temperature coefficient, and the difference ΔVBE between the base-emitter voltages of two bipolar transistors operating at different current densities has a positive temperature coefficient, by adding these two voltages with opposite temperature coefficients with appropriate weights, the effect of temperature on the output voltage can be canceled out, and a temperature-independent reference voltage can be obtained.

[0057] Temperature sensor 324b is used to sense the current temperature and generate digital information representing the current temperature. Exemplarily, temperature sensor 324b includes a successive approximation analog-to-digital converter (SAR ADC). Figure 7 (Not shown), the SAR ADC is configured to successively approximate the positive temperature coefficient voltage VPTAT with a reference voltage VBG to generate a first signal temp_code, which includes digital information representing the current temperature.

[0058] refer to Figure 7 In some embodiments, the temperature sensor 324b is further configured to output a start signal sta and an end signal fin. The start signal sta is used to instruct the arithmetic circuit 328 to begin receiving the first signal temp_code, and the end signal fin is used to instruct the arithmetic circuit 328 to end receiving the first signal temp_code. In some embodiments, the first signal temp_code includes a p+q bit code, where the high p bits indicate the temperature range of the current temperature, and the low q bits can be directly provided to the arithmetic circuit 328, where p and q are both positive integers. For example, the first signal temp_code can be a thermometer code, such as an 8-bit thermometer code, where the high 3 bits indicate the temperature range of the current temperature, and the low 5 bits can be directly provided to the arithmetic circuit 328.

[0059] Figure 13 This is a schematic diagram illustrating temperature compensation for multiple temperature ranges provided in the embodiments of this application.

[0060] refer to Figure 13In some embodiments, the operating temperature range of the phase-change memory can be divided into multiple temperature ranges. For example, the operating temperature range of the phase-change memory is -20°C to 100°C, divided into 5 temperature ranges. In some embodiments, the high 3 bits of the first signal temp_code are 000, indicating a temperature range of -20°C (excluding) to 4°C; the high 3 bits of the first signal temp_code are 001, indicating a temperature range of 4°C (excluding) to 28°C; the high 3 bits of the first signal temp_code are 010, indicating a temperature range of 28°C (excluding) to 52°C; the high 3 bits of the first signal temp_code are 011, indicating a temperature range of 52°C (excluding) to 76°C; and the high 3 bits of the first signal temp_code are 100, indicating a temperature range of 76°C (excluding) to 100°C. For example, the temperature sensor's code is 160 bits long, with each 32 bits corresponding to a temperature range. For instance, bits 1 to 32 correspond to a temperature range of -20°C (excluding) to 4°C, and bits 129 to 160 correspond to a temperature range of 76°C (excluding) to 100°C.

[0061] refer to Figure 7 In some embodiments, the selection circuit 326 includes a multiplexer. Exemplarily, the multiplexer is an N+1 to 1 type multiplexer, where N is a positive integer. The N+1 input terminals of the N+1 to 1 type multiplexer respectively receive parameters P_0, P_1, ..., P_N-1 and P_N from a plurality of first compensation parameters, and the output terminal outputs the first output compensation parameter P_J.

[0062] In some embodiments, the first compensation parameter can be an empirical value; it can also be a default value configured at the factory of the phase-change memory, which is obtained through extensive simulation experiments before the phase-change memory leaves the factory. In some embodiments, the first compensation parameter is stored in a latch ( Figure 7 (Not shown). In some embodiments, the first compensation parameter includes multiple first slope information corresponding to the number of multiple temperature ranges, and the first slope information is used to perform temperature compensation on the target voltage of the corresponding temperature range. In this way, the coefficient used for temperature compensation can be flexibly controlled for each temperature range.

[0063] refer to Figure 7 and Figure 13For example, taking a phase-change memory (PCM) with an operating temperature range of -20°C to 100°C, divided into 5 temperature ranges, the first slope information corresponding to the temperature range -20°C (excluding) to 4°C is the offset value deta1_max; the first slope information corresponding to the temperature range 4°C (excluding) to 28°C is the offset value deta2_max; the first slope information corresponding to the temperature range 28°C (excluding) to 52°C is the offset value 0; the first slope information corresponding to the temperature range 52°C (excluding) to 76°C is the offset value deta3_max; and the first slope information corresponding to the temperature range 76°C (excluding) to 100°C is the offset value deta4_max. It should be noted that the offset values ​​have a direction; the offset values ​​deta1_max and deta2_max have the same direction. Figure 13 As shown above, the offset values ​​deta3_max and deta4_max are in the same direction. Figure 13 As shown below, the offset values ​​deta2_max and deta3_max are in opposite directions.

[0064] Figure 9 This is a schematic diagram of an arithmetic circuit provided in an embodiment of this application.

[0065] refer to Figure 9 or Figure 7 In some embodiments, the arithmetic circuit 328 includes an arithmetic section 328a and an output section 328b; the arithmetic section 328a is configured to receive a first signal temp_code and a first output compensation parameter P_J, and output a first digital signal data_code1; the first digital signal data_code1 includes digital information corresponding to the adjustment amount of the adjustment voltage; the output section 328b is configured to receive the first digital signal data_code1 and a second digital signal trim_base, and output a second signal trim_code1; the second digital signal trim_base includes digital information corresponding to the reference amount of the adjustment voltage; the second signal trim_code1 includes digital information corresponding to the sum of the adjustment amount and the reference amount.

[0066] refer to Figure 9In some embodiments, the peripheral circuit 302 further includes a channel counter 334; the channel counter 334 is coupled to the selection circuit 326 and the output section 328b, and is configured to receive a clock signal clk and a serial calculation start signal serial_calc_start, and output a control signal serial_calc_control; the selection circuit 326 is configured to receive the control signal serial_calc_control, and output one of the parameters P_0, P_1, ..., P_N-1, P_N among the received multiple first compensation parameters as a first output compensation parameter P_J; the output section 328b is configured to receive the control signal serial_calc_control, and output a second signal trim_code1 after summing the received first digital signal data_code1 and the second digital signal trim_base.

[0067] For example, at a first moment, the selection circuit 326 is configured to receive the control signal `serial_calc_control` and output parameter P_0 from the received plurality of first compensation parameters as the first output compensation parameter P_J. At the first moment, the arithmetic section 328a is configured to receive the first signal `temp_code` and the first output compensation parameter P_J, and at a second moment, outputs the first digital signal `data_code1`; the second moment is later than the first moment. At the second moment, the output section 328b is configured to receive the first digital signal `data_code1` and the second digital signal `trim_base`, and at a third moment, outputs the second signal `trim_code1`; the third moment is later than the second moment. After the second moment, the arithmetic section 328a is in an idle state. After the second moment, the selection circuit 326 can be configured to receive the control signal `serial_calc_control` and output parameter P_1 from the received plurality of first compensation parameters as the first output compensation parameter P_J to the arithmetic section 328a. This improves the utilization rate of the arithmetic section and increases the efficiency of the arithmetic circuit in performing serial calculations.

[0068] refer to Figure 9 In some embodiments, the multiple temperature ranges are multiple consecutive temperature ranges; the arithmetic part 328a includes a multiplier and a first adder; the arithmetic part 328a is configured to: perform temperature compensation on the target voltage based on the first slope information corresponding to the temperature range, to obtain the correspondence between the temperature in each temperature range and the corresponding compensation target voltage; and output a second signal trim_code1 according to the first signal temp_code and the correspondence between the temperature in the temperature range where the current temperature is located and the corresponding compensation target voltage.

[0069] In some embodiments, the arithmetic section 328a is configured to: starting from the lowest temperature range among multiple temperature ranges, starting from the highest temperature range among multiple temperature ranges, starting from an intermediate temperature range among multiple temperature ranges towards the lowest temperature range, or starting from an intermediate temperature range among multiple temperature ranges towards the highest temperature range, sequentially perform temperature compensation on the target voltage based on the first slope information corresponding to each temperature range, thereby obtaining the correspondence between the temperature in each temperature range and the corresponding compensation target voltage. Thus, compared to methods that can only start temperature compensation from the highest temperature range among multiple temperature ranges, this embodiment of the application can use any temperature range among multiple temperature ranges as the starting temperature range for temperature compensation, which is advantageous for expanding the operating temperature range of the phase-change memory.

[0070] refer to Figure 9 In some embodiments, the output section 328b includes a latch and a second adder; the latch is configured to latch a first digital signal data_code1 and a second digital signal trim_base; the second adder is configured to sum the first digital signal data_code1 and the second digital signal trim_base.

[0071] Figure 10 This is a schematic diagram of the first conversion circuit provided in an embodiment of this application.

[0072] refer to Figure 10 or Figure 7 In some embodiments, the first conversion circuit 330 includes a first digital-to-analog converter 330a, a voltage regulator 330b, and a first voltage follower 330c; the first digital-to-analog converter 330a is configured to receive a reference voltage VBG and a second signal trim_code1, and output a first analog signal V_1; the first analog signal V_1 includes analog information corresponding to the compensation target voltage; the voltage regulator 330b is configured to receive the first analog signal V_1 and output a second analog signal V_2; the second analog signal V_2 includes amplified information of the first analog signal V_1; the first voltage follower 330c is configured to receive the second analog signal and output a third signal V_trim.

[0073] refer to Figure 10In some embodiments, the first conversion circuit 330 further includes a reference voltage source 330d; the reference voltage source 330d is configured to receive a reference voltage VBG and output an amplified signal VBG_1 of the reference voltage VBG; the first digital-to-analog converter 330a is configured to receive the amplified signal VBG_1 of the reference voltage VBG and a second signal trim_code1, and output a first analog signal V_1; the first power supply terminal of the reference voltage source 330d receives voltage VCC, and the second power supply terminal receives voltage VSS, wherein voltage VCC is greater than voltage VSS; the first power supply terminal of the regulator 330b receives voltage VPH, and the second power supply terminal receives voltage VSS, wherein voltage VPH is greater than voltage VSS; wherein voltage VPH is greater than voltage VCC.

[0074] refer to Figure 10 or Figure 7 In some embodiments, the first conversion circuit 330 is configured to: provide a first compensation target voltage to the first address line according to the corresponding third signal V_trim, and provide a second compensation target voltage to the second address line according to the corresponding third signal V_trim during the set operation, reset operation, or read operation; the second compensation target voltage is less than the first compensation target voltage. In this embodiment, the first compensation target voltage can be understood as a positive voltage greater than the first reference voltage, and the second compensation target voltage can be understood as a negative voltage less than the second reference voltage. The first reference voltage can be understood as voltage VSS. Voltage VSS can be set according to specific circumstances, for example, 0V, less than 0V (e.g., -0.5V), or greater than 0V (e.g., 0.5V). The second reference voltage can be understood as voltage VSS. Voltage VSS can be set according to specific circumstances, for example, 0V, less than 0V (e.g., -0.5V), or greater than 0V (e.g., 0.5V). The first reference voltage and the second reference voltage can be the same or different. For example, the first reference voltage and the second reference voltage are the same and both are 0V.

[0075] For example, during a read operation, taking the storage of data "1" by a phase-change memory element, a positive voltage is applied to the first address line and a negative voltage is applied to the second address line. After the gating element is turned on, the phase-change memory cell coupled between the first and second address lines is turned on. Since the phase-change memory cell is turned on, a current path is formed between the first and second address lines. The sensing circuit coupled to the second address line senses the voltage change of the second address line and latches the corresponding data "1". Taking the storage of data "0" by a phase-change memory element, a positive voltage is applied to the first address line and a negative voltage is applied to the second address line. After the gating element is turned on, the phase-change memory cell coupled between the first and second address lines is not turned on. Since the phase-change memory cell is not turned on, no current path is formed between the first and second address lines. The sensing circuit coupled to the second address line senses that the voltage of the second address line has not changed and latches the corresponding data "0".

[0076] Similarly, during the set operation, the voltage applied to the first address line can be referenced. Figure 6 To understand the SET-related content, a negative voltage is applied to the second address line.

[0077] Similarly, during the reset operation, the voltage applied to the first address line can be referenced. Figure 6 To understand the RESET-related content, a negative voltage is applied to the second address line.

[0078] refer to Figure 7 In some embodiments, the first conversion circuit 330 is configured to provide N+1 paths for voltage temperature compensation based on the corresponding N+1 third signals V_trim. This increases the number of paths for voltage temperature compensation while reducing the area of ​​the phase-change memory. It should be noted that the area corresponding to the increased number of paths for voltage temperature compensation is negligible compared to the area reduction of the arithmetic circuitry achieved by using time-division multiplexing arithmetic circuitry.

[0079] For example, the first conversion circuit 330 is configured to provide voltages VGWL_REG0, VGWL_REG1, VGWL_REG2, VGWL_REG3, VGWL_REG4, and VGWL_REG5 to the regulators corresponding to six different global word lines based on the six corresponding third signals V_trim. For example, the first conversion circuit 330 is configured to provide positive voltages VPR1 and VPR2 to two different word lines based on the two corresponding third signals V_trim. For example, the first conversion circuit 330 is configured to provide negative voltages VNR1 and VNR2 to two different word lines based on the two corresponding third signals V_trim. For example, the first conversion circuit 330 is configured to provide a power supply voltage VOSC_power to the oscillator based on one corresponding third signal V_trim. For example, the first conversion circuit 330 is configured to provide a corresponding power supply voltage VNRH1 and a power supply voltage VNSRH to the current source according to the corresponding two third signals V_trim; wherein the power supply voltage VNRH1 is used to generate the current source of current I_SET, and the power supply voltage VNSRH is used to generate the current sources of current I_SET, current I_RESET, and current I_RD.

[0080] Figure 11 A schematic diagram of the peripheral circuit for voltage temperature compensation and current temperature compensation provided in the embodiments of this application.

[0081] refer to Figure 11 and Figure 8 In some embodiments, the peripheral circuit 302 further includes a second conversion circuit 332; the selection circuit 326 is further configured to sequentially select one of a plurality of second compensation parameters (parameter P_0, parameter P_1, ..., parameter P_M-1, parameter P_M) as a second output compensation parameter P_I; the second compensation parameter includes second slope information corresponding to a plurality of temperature ranges, used for temperature compensation of the target current; the arithmetic circuit 328 is further configured to receive a first signal temp_code and a second output compensation parameter P_I, and output a fourth signal trim_code2; the fourth signal trim_code2 includes digital information corresponding to the adjustment current; the adjustment current is the current for temperature compensation of the target current; the second conversion circuit 332 is coupled to a second address line and is configured to receive a reference current I_ref and the fourth signal trim_code2, and output a fifth signal I_trim; the fifth signal I_trim includes analog information corresponding to the compensation target current; the compensation target current is the current after temperature compensation of the target current.

[0082] refer to Figure 11 and Figure 8 In some embodiments, the selection circuit 326 includes a multiplexer. Exemplarily, the multiplexer is an M+N+2 to 1 type multiplexer, where M and N are both positive integers. The N+1 inputs of the M+N+2 to 1 type multiplexer respectively receive parameters P_0, P_1, ..., P_N-1, and P_N from a plurality of first compensation parameters. The M+1 inputs respectively receive parameters P_0, P_1, ..., P_M-1, and P_M from a plurality of second compensation parameters. The output terminal outputs the second output compensation parameter P_I.

[0083] In some embodiments, the second compensation parameter can be an empirical value; it can also be a default value configured at the factory of the phase-change memory, which is obtained through extensive simulation experiments before the phase-change memory leaves the factory. In some embodiments, the second compensation parameter is stored in a latch ( Figure 7 (Not shown). In some embodiments, the second compensation parameter includes multiple second slope information corresponding to the number of multiple temperature ranges. The second slope information is used to perform temperature compensation on the target current of the corresponding temperature range. Specific examples of the second slope information can be understood by referring to the above description of the first slope information, and will not be repeated here.

[0084] Figure 12 This is a schematic diagram of the second conversion circuit provided in an embodiment of this application.

[0085] refer to Figure 12 In some embodiments, the second conversion circuit 332 includes a second digital-to-analog converter 332a, a second voltage follower 332b, and an output device 332c; the second digital-to-analog converter 332a is configured to receive a reference current I_ref and a fourth signal trim_code2, and output a third analog signal V_3; the third analog signal V_3 includes analog information corresponding to the compensation target current; the second voltage follower 332b is configured to receive the third analog signal V_3 and output a fourth analog signal V_4; the output device 332c is configured to receive the fourth analog signal V_4 and output a fifth signal I_trim.

[0086] For example, the second digital-to-analog converter 332a includes a current mirror structure, which includes transistors M0, M1, ..., Mn. The branch containing transistor M0 outputs a current equal to 1 times the current I0, the branch containing transistor M1 outputs a current equal to 2 times the current I0, and the branch containing transistor Mn outputs a current equal to 2 times the current I0. n The current I0 is multiples of the current. The number of bits in the fourth signal trim_code2 can be n+1 bits. The first to the n+1th bits are used to control the gates of transistors MO, M1, ..., Mn, respectively.

[0087] refer to Figure 12 In some embodiments, a portion of the second conversion circuit 332 is located in the first semiconductor structure 300a, and another portion is located in the second semiconductor structure 300b, with the first semiconductor structure 300a and the second semiconductor structure 300b bonded together. The first semiconductor structure 300a includes a portion of the peripheral circuitry, and the second semiconductor structure 300b includes the entire memory array and another portion of the peripheral circuitry. Exemplarily, the second digital-to-analog converter 332a and the second voltage follower 332b are located in the first semiconductor structure 300a, and the output device 332c is located in the second semiconductor structure 300b. This closer proximity of the output device to the memory array reduces the length of the connection lines between the output device and the bit lines, which is beneficial for providing stable current to the bit lines and avoiding current transmission losses and instability associated with longer connection lines.

[0088] refer to Figure 11 and Figure 8 In some embodiments, the second conversion circuit 332 is configured to provide M+1 corresponding paths for current-temperature compensation based on the corresponding M+1 fifth signals I_trim. This increases the number of paths for current-temperature compensation while reducing the area of ​​the phase-change memory. It should be noted that the area corresponding to the increased number of paths for current-temperature compensation is negligible compared to the area reduction of the arithmetic circuitry achieved by using time-division multiplexing arithmetic circuitry.

[0089] refer to Figure 11 and Figure 8 In some embodiments, the second conversion circuit 332 is configured to provide independent compensation read currents for the second address lines during set, reset, and read operations. This overcomes the drawbacks of providing a single compensation read current for the second address lines during set, reset, and read operations (e.g., using the compensation set current as the adjustment coefficient sacrifices the accuracy of the compensation reset current). In this embodiment, providing independent compensation read currents for the second address lines during set, reset, and read operations ensures accurate reading of the compensation set current, compensation reset current, and supplementary read current, achieving more precise energy control and guaranteeing optimal read / write performance at various temperatures.

[0090] refer to Figure 11 and Figure 8In some embodiments, the target current includes a set current, the compensated target current includes a compensated set current, and the compensated set current is the current after temperature compensation of the set current according to the current temperature; the second conversion circuit 332 is configured to provide a compensated set current to the second address line according to the corresponding fifth signal during the set operation. Exemplarily, the second conversion circuit 332 is configured to provide compensated set currents I_SET1 and I_SET2 to the second address line according to two corresponding fifth signals I_trim, where the compensated set currents I_SET1 and I_SET2 are different. In some embodiments, the target current includes a reset current, the compensated target current includes a compensated reset current, and the compensated reset current is the current after temperature compensation of the reset current according to the current temperature; the second conversion circuit 332 is configured to provide a compensated reset current to the second address line according to the corresponding fifth signal during the reset operation. Exemplarily, the second conversion circuit 332 is configured to provide a compensated set current I_RESET to the second address line according to one corresponding fifth signal I_trim. In some embodiments, the target current includes the read current, and the compensated target current includes the compensated read current, which is the current after temperature compensation of the read current according to the current temperature. The second conversion circuit 332 is configured to provide a compensated read current to the second address line according to the corresponding fifth signal during the read operation. For example, the second conversion circuit 332 is configured to provide a compensated set current I_RD to the second address line according to a corresponding fifth signal I_trim. Thus, compared to providing a single compensated read current to the second address line during the set, reset, and read operations, in this embodiment, independent compensated read currents are provided to the second address line during the set, reset, and read operations respectively, achieving more precise energy control and ensuring optimal read / write performance at various temperatures.

[0091] For example, in a two-layer stacked phase-change memory (reference) Figure 5 The circuit has six temperature compensation channels, five of which can be used for temperature compensation of five different voltages, and one channel can be used for current temperature compensation. The six temperature compensation channels are connected in parallel and can each perform temperature compensation independently. The total area of ​​the temperature compensation circuit is Aμm. 2 The average area of ​​a single-channel temperature compensation circuit is Bμm. 2 For example, in a four-layer stacked phase-change memory (not shown) provided in this application embodiment, there are 17 temperature compensation channels. Twelve of these channels can be used for temperature compensation of 12 different voltages, and five of these channels can be used for temperature compensation of 5 different currents. The 17 temperature compensation channels are connected in parallel and perform temperature compensation using a time-division multiplexing arithmetic circuit for serial calculation. The total area of ​​the temperature compensation circuit is A μm.2 One-quarter of the average area of ​​a single-channel temperature compensation circuit is Bμm. 2 1 / 10 of.

[0092] According to a second aspect of the present application, a method for operating a phase-change memory (PCM) is provided. The PCM includes a memory array and peripheral circuitry coupled to the memory array. The memory array includes multiple first address lines, multiple second address lines, and multiple PCM cells. The method for operating the PCM includes: a temperature sensing circuit of the peripheral circuitry outputting a first signal; the first signal including digital information corresponding to the current temperature; a selection circuit of the peripheral circuitry sequentially selecting one of multiple first compensation parameters as a first output compensation parameter; the first compensation parameter including first slope information corresponding to multiple temperature ranges, used for temperature compensation of a target voltage; an arithmetic circuit of the peripheral circuitry receiving the first signal and the first output compensation parameter, and outputting a second signal; the second signal including digital information corresponding to an adjustment voltage; the adjustment voltage being a voltage for temperature compensation of the target voltage; a first conversion circuit of the peripheral circuitry coupled to the first address lines and the second address lines, receiving a reference voltage and the second signal, and outputting a third signal; the third signal including analog information corresponding to the compensation target voltage; the compensation target voltage being the voltage after temperature compensation of the target voltage.

[0093] In some embodiments, the operation method of the phase-change memory includes: during a set operation, a reset operation, or a read operation, the first conversion circuit provides a first compensation target voltage to the first address line according to a corresponding third signal, and provides a second compensation target voltage to the second address line according to a corresponding third signal; the second compensation target voltage is less than the first compensation target voltage.

[0094] In some embodiments, the first conversion circuit includes a first digital-to-analog converter, a voltage regulator, and a first voltage follower; the operation method of the phase-change memory includes: the first digital-to-analog converter receiving a reference voltage and a second signal, and outputting a first analog signal; the first analog signal includes analog information corresponding to a compensation target voltage; the voltage regulator receiving the first analog signal and outputting a second analog signal; the second analog signal is amplified information of the first analog signal; the first voltage follower receiving the second analog signal and outputting a third signal.

[0095] In some embodiments, the temperature sensing circuit includes a bandgap reference circuit and a temperature sensor; the operation method of the phase change memory includes: the bandgap reference circuit outputting a positive temperature coefficient voltage and a reference voltage; the temperature sensor receiving the positive temperature coefficient voltage and the reference voltage, sensing the current temperature and outputting a first signal.

[0096] In some embodiments, the peripheral circuit further includes a second conversion circuit; the operation method of the phase-change memory further includes: a selection circuit sequentially selecting one of a plurality of second compensation parameters as a second output compensation parameter; the second compensation parameter includes second slope information corresponding to a plurality of temperature ranges respectively, used for temperature compensation of the target current; an arithmetic circuit receives a first signal and a second output compensation parameter, and outputs a fourth signal; the fourth signal includes digital information corresponding to the adjustment current; the adjustment current is the current for temperature compensation of the target current; the second conversion circuit is coupled to a second address line, and receives a reference current and the fourth signal, and outputs a fifth signal; the fifth signal includes analog information corresponding to the compensation target current; the compensation target current is the current after temperature compensation of the target current.

[0097] In some embodiments, the target current includes a set current, the compensated target current includes a compensated set current, and the compensated set current is the current after temperature compensation of the set current according to the current temperature; the phase-change memory operation method includes: during the set operation, the second conversion circuit provides a compensated set current to the second address line according to the corresponding fifth signal; or, the target current includes a reset current, the compensated target current includes a compensated reset current, and the compensated reset current is the current after temperature compensation of the reset current according to the current temperature; the phase-change memory operation method includes: during the reset operation, the second conversion circuit provides a compensated reset current to the second address line according to the corresponding fifth signal; or, the target current includes a read current, the compensated target current includes a compensated read current, and the compensated read current is the current after temperature compensation of the read current according to the current temperature; the phase-change memory operation method includes: during the read operation, the second conversion circuit provides a compensated read current to the second address line according to the corresponding fifth signal.

[0098] In some embodiments, the second conversion circuit includes a second digital-to-analog converter, a second voltage follower, and an output device; the operation method of the phase-change memory includes: the second digital-to-analog converter receiving a reference current and a fourth signal, and outputting a third analog signal; the third analog signal includes analog information corresponding to the compensation target current; the second voltage follower receiving the third analog signal and outputting a fourth analog signal; and the output device receiving the fourth analog signal and outputting a fifth signal.

[0099] In some embodiments, the arithmetic circuit includes an arithmetic section and an output section; the operation method of the phase-change memory includes: the arithmetic section receiving a first signal and a first output compensation parameter, and outputting a first digital signal; the first digital signal includes digital information corresponding to the adjustment amount of the adjustment voltage; the output section receiving the first digital signal and a second digital signal, and outputting a second signal; the second digital signal includes digital information corresponding to the reference amount of the adjustment voltage; the second signal includes digital information corresponding to the sum of the adjustment amount and the reference amount.

[0100] In some embodiments, the multiple temperature ranges are multiple consecutive temperature ranges; the arithmetic part includes a multiplier and a first adder; the operation method of the phase-change memory includes: the arithmetic part starting from the lowest temperature range among the multiple temperature ranges or starting from the highest temperature range among the multiple temperature ranges, sequentially performing temperature compensation on the target voltage based on the first slope information corresponding to each temperature range, to obtain the correspondence between the temperature in each temperature range and the corresponding compensation target voltage; and outputting a second signal according to the first signal and the correspondence between the temperature in the current temperature range and the corresponding compensation target voltage.

[0101] In some embodiments, the output section includes a latch and a second adder; the operation method of the phase-change memory includes: the latch latching a first digital signal and a second digital signal; and the second adder summing the first digital signal and the second digital signal.

[0102] According to a third aspect of the present application, a memory system is provided, the memory system comprising: a memory, including any phase-change memory as provided in the first aspect, or a phase-change memory applied according to any operating method provided in the second aspect; and a memory controller, coupled to the memory and configured to control the memory.

[0103] In this embodiment, the memory and memory controller of the memory system can be referred to the above. Figure 1 The relevant descriptions can be used for understanding, and will not be repeated here. The storage array and peripheral circuitry of the phase-change memory can be referred to the above. Figure 2 , Figure 3 , Figure 7 , Figure 8 and Figure 11 To understand the relevant descriptions, refer to the descriptions of phase-change memory cells in the memory array. Figure 4 and Figure 5 The relevant descriptions will be understood and will not be repeated here.

[0104] Figure 14 A block diagram of a readable storage medium provided in an embodiment of this application. (See reference...) Figure 14 According to a fourth aspect of the present application, a readable storage medium 400 is provided, which stores a computer program 410. When the computer program 410 is executed, it can implement any of the phase-change memory operation methods provided in the second aspect.

[0105] For example, the phase-change memory includes a memory array and peripheral circuitry coupled to the memory array; the memory array includes multiple first address lines, multiple second address lines, and multiple phase-change memory cells; the operation method of the phase-change memory includes: a temperature sensing circuit of the peripheral circuitry outputs a first signal; the first signal includes digital information corresponding to the current temperature; a selection circuit of the peripheral circuitry sequentially selects one of multiple first compensation parameters as a first output compensation parameter; the first compensation parameter includes first slope information corresponding to multiple temperature ranges, used for temperature compensation of the target voltage; an arithmetic circuit of the peripheral circuitry receives the first signal and the first output compensation parameter, and outputs a second signal; the second signal includes digital information corresponding to the adjustment voltage; the adjustment voltage is the voltage for temperature compensation of the target voltage; a first conversion circuit of the peripheral circuitry is coupled to the first address lines and the second address lines, and receives a reference voltage and the second signal, and outputs a third signal; the third signal includes analog information corresponding to the compensation target voltage; the compensation target voltage is the voltage after temperature compensation of the target voltage.

[0106] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0107] The above description is only a preferred embodiment of this application and does not limit the scope of protection of this application. All equivalent structural transformations made under the inventive concept of this application using the content of this application specification and drawings, or direct / indirect applications in other related technical fields, are included within the scope of protection of this application.

Claims

1. A phase change memory, characterized by, The system includes a memory array and peripheral circuitry coupled to the memory array; the memory array includes multiple first address lines, multiple second address lines, and multiple phase-change memory cells; the peripheral circuitry includes: A temperature sensing circuit is configured to output a first signal; the first signal includes digital information corresponding to the current temperature. The selection circuit is configured to sequentially select one of a plurality of first compensation parameters as a first output compensation parameter; the first compensation parameter includes first slope information corresponding to a plurality of temperature ranges respectively, which is used to perform temperature compensation on the target voltage. An arithmetic circuit is configured to receive the first signal and the first output compensation parameter, and output a second signal; the second signal includes digital information corresponding to an adjustment voltage; the adjustment voltage is a voltage used for temperature compensation of the target voltage; A first conversion circuit, coupled to the first address line and the second address line, is configured to receive a reference voltage and the second signal, and output a third signal; the third signal includes analog information corresponding to a compensation target voltage; the compensation target voltage is the voltage after temperature compensation of the target voltage.

2. The phase change memory of claim 1, wherein, The first conversion circuit is configured as follows: During the set operation, reset operation, or read operation, a first compensation target voltage is provided to the first address line according to the corresponding third signal, and a second compensation target voltage is provided to the second address line according to the corresponding third signal; the second compensation target voltage is less than the first compensation target voltage.

3. The phase change memory of claim 1, wherein, The first conversion circuit includes a first digital-to-analog converter, a voltage regulator, and a first voltage follower; The first digital-to-analog converter is configured to receive the reference voltage and the second signal, and output a first analog signal; the first analog signal includes analog information corresponding to the compensation target voltage; The voltage regulator is configured to receive the first analog signal and output a second analog signal; the second analog signal is amplified information of the first analog signal. The first voltage follower is configured to receive the second analog signal and output the third signal.

4. The phase change memory of claim 3, wherein, The temperature sensing circuit includes a bandgap reference circuit and a temperature sensor; The bandgap reference circuit is configured to output a positive temperature coefficient voltage and the reference voltage; The temperature sensor is configured to receive the positive temperature coefficient voltage and the reference voltage, sense the current temperature, and output the first signal.

5. The phase change memory of claim 1, wherein, The peripheral circuit also includes a second conversion circuit; The selection circuit is further configured to sequentially select one of a plurality of second compensation parameters as a second output compensation parameter; the second compensation parameter includes second slope information corresponding to a plurality of temperature ranges respectively, for temperature compensation of the target current; The arithmetic circuit is further configured to receive the first signal and the second output compensation parameter, and output a fourth signal; the fourth signal includes digital information corresponding to the adjustment current; the adjustment current is the current used for temperature compensation of the target current; The second conversion circuit is coupled to the second address line and is configured to receive the reference current and the fourth signal, and output the fifth signal; The fifth signal includes analog information corresponding to the target compensation current; The target current for compensation is the current after temperature compensation of the target current.

6. The phase change memory of claim 5, wherein, The target current includes a set current, the compensated target current includes a compensated set current, and the compensated set current is the current after temperature compensation of the set current based on the current temperature; the second conversion circuit is configured to: During the set operation, the compensation set current is provided to the second address line according to the corresponding fifth signal; or, The target current includes a reset current, and the compensated target current includes a compensated reset current, wherein the compensated reset current is the current after temperature compensation of the reset current based on the current temperature; The second conversion circuit is configured as follows: During the reset operation, the compensation reset current is provided to the second address line according to the corresponding fifth signal; or, The target current includes the reading current, and the compensated target current includes the compensated reading current, wherein the compensated reading current is the current after temperature compensation of the reading current based on the current temperature; The second conversion circuit is configured as follows: During the read operation, the compensation read current is provided to the second address line according to the corresponding fifth signal.

7. The phase change memory of claim 5, wherein, The second conversion circuit includes a second digital-to-analog converter, a second voltage follower, and an output unit; The second digital-to-analog converter is configured to receive the reference current and the fourth signal, and output a third analog signal; the third analog signal includes analog information corresponding to the compensation target current; The second voltage follower is configured to receive the third analog signal and output a fourth analog signal; The output device is configured to receive the fourth analog signal and output the fifth signal.

8. The phase change memory of claim 1, wherein, The arithmetic circuit includes an arithmetic section and an output section; The arithmetic section is configured to receive the first signal and the first output compensation parameter, and output a first digital signal; the first digital signal includes digital information corresponding to the adjustment amount of the adjustment voltage; The output section is configured to receive the first digital signal and the second digital signal, and output the second signal; the second digital signal includes digital information corresponding to the reference amount of the adjustment voltage; the second signal includes digital information corresponding to the sum of the adjustment amount and the reference amount.

9. The phase change memory of claim 8, wherein, The plurality of temperature ranges are multiple consecutive temperature ranges; the arithmetic section includes a multiplier and a first adder; the arithmetic section is configured as follows: Based on the first slope information corresponding to the temperature range, temperature compensation is performed on the target voltage to obtain the correspondence between the temperature in each temperature range and the corresponding compensation target voltage. Based on the first signal and the correspondence between the temperature within the temperature range where the current temperature is located and the corresponding compensation target voltage, the second signal is output.

10. The phase change memory of claim 8, wherein, The output section includes a latch and a second adder; The latch is configured to latch the first digital signal and the second digital signal; The second adder is configured to sum the first digital signal and the second digital signal.

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