Discharge circuit, control circuit and its control method, memory, memory system
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-08
- Publication Date
- 2026-08-11
Smart Images
Figure CN122551850A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a control circuit for a memory, a memory, a memory system, a control method for a memory, and a discharge circuit for a memory. Background Technology
[0002] During the continuous execution of different operations in a memory, the voltage required for the word lines may vary. For example, the voltage required for the word lines in a previous operation may be greater than the voltage required for a subsequent operation. Therefore, it is necessary to discharge the voltage reached by the word lines in the previous operation between the two operations. Summary of the Invention
[0003] In a first aspect, some embodiments of this disclosure provide a control circuit for a memory. The control circuit includes a discharge terminal, a clamping unit, a first switching unit, and a power supply branch; the clamping unit is coupled to the word line of the memory; the first switching unit is coupled between the clamping unit and the discharge terminal and is configured to be in an on state from a first time moment to a second time moment, connecting the word line to the discharge terminal, and discharging the voltage of the word line from a first voltage to a target voltage; the power supply branch is coupled to the word line and is configured to provide a second voltage to the word line after the second time moment; wherein the target voltage is less than or equal to the second voltage.
[0004] In an exemplary embodiment, the clamping unit includes a diode-connected MOS transistor, wherein the drain and gate of the diode-connected MOS transistor are coupled.
[0005] In an exemplary embodiment, the diode-connected MOS transistor is an NMOS transistor or a PMOS transistor.
[0006] In an exemplary embodiment, the voltage at the discharge terminal is less than or equal to the difference between the second voltage and the threshold voltage of the diode-connected MOS transistor.
[0007] In an exemplary embodiment, the clamping unit includes a diode and / or a resistor.
[0008] In an exemplary embodiment, the first switch unit is further configured to: in response to the controlled terminal of the first switch unit receiving a first control signal, the first switch unit is in an open state from a first time moment to a second time moment, and in a closed state before the first time moment and after the second time moment.
[0009] In an exemplary embodiment, the first switching unit includes a first transistor, the first electrode of the first transistor is coupled to a clamping unit, the second electrode of the first transistor is coupled to a discharge terminal, and the control terminal of the first transistor is configured to receive a first control signal.
[0010] In an exemplary embodiment, the control circuit further includes a protection transistor coupled between the clamping unit and the first transistor, the protection transistor providing overvoltage protection for the first transistor.
[0011] In an exemplary embodiment, the first transistor is an NMOS transistor, and the protection transistor is an NMOS transistor.
[0012] In an exemplary embodiment, the power supply branch is further configured to provide a first voltage to the word line before the first moment.
[0013] In an exemplary embodiment, the power supply branch includes a first voltage generator and a second switching unit. The first voltage generator is configured to provide a first voltage; the second switching unit is coupled between the first voltage generator and a word line and is configured to be in an on state before a first moment and in a off state after a first moment in response to the controlled terminal of the second switching unit receiving a first enable signal.
[0014] In an exemplary embodiment, the second switching unit includes a second transistor, the first terminal of which is coupled to a first voltage generator, the second terminal of which is coupled to a word line, and the control terminal of the second transistor is configured to receive a first enable signal.
[0015] In an exemplary embodiment, the power supply branch further includes a second voltage generator and a third switching unit. The second voltage generator is configured to provide a second voltage; the third switching unit is coupled between the second voltage generator and a word line and is configured to be in a closed state before a second time moment and in an open state after the second time moment in response to the controlled terminal of the third switching unit receiving a second enable signal.
[0016] In an exemplary embodiment, the second switching unit includes a third transistor, the first terminal of which is coupled to a second voltage generator, the second terminal of which is coupled to a word line, and the control terminal of the third transistor is configured to receive a second enable signal.
[0017] In an exemplary embodiment, the control circuit further includes a NOR gate, the input of which is configured to receive a first enable signal and a second enable signal, and the output of which is coupled to the control terminal of the first transistor and configured to output a first control signal.
[0018] In an exemplary embodiment, the control circuit further includes a fourth switching unit coupled between the word line and the clamping unit, and configured such that: in response to the controlled terminal of the fourth switching unit receiving a second control signal, the fourth switching unit is in an on state from a first time moment to a second time moment.
[0019] In an exemplary embodiment, the first voltage is the programming voltage, and the second voltage is the reading voltage, wherein the programming voltage is greater than the reading voltage.
[0020] Secondly, some embodiments of this disclosure provide a memory including a memory cell array and peripheral circuitry. The memory cell array includes memory cells and word lines coupled to the memory cells. The peripheral circuitry is coupled to the memory cell array and includes the control circuitry mentioned in any of the above embodiments.
[0021] In an exemplary embodiment, the memory is a dynamic random access memory.
[0022] Thirdly, some embodiments of this disclosure provide a memory system. This memory system includes the memory mentioned in any of the above embodiments and a controller. The controller is coupled to the memory and is used to control the memory to store data.
[0023] Fourthly, some embodiments of this disclosure provide a method for controlling a memory. The memory includes: a discharge terminal, a clamping unit, a first switching unit, and a power supply branch. The clamping unit is coupled to the word line of the memory, the first switching unit is coupled between the clamping unit and the discharge terminal, and the power supply branch is coupled to the word line. The method for controlling the memory includes: controlling the first switching unit to be in an on state from a first time moment to a second time moment, so that the word line is connected to the discharge terminal, and the voltage of the word line discharges from a first voltage to a target voltage; after the second time moment, controlling the power supply branch to provide a second voltage to the word line; wherein the target voltage is less than or equal to the second voltage.
[0024] In an exemplary embodiment, controlling the first switch unit to be in an on state from a first moment to a second moment includes: in response to the controlled terminal of the first switch unit receiving a first control signal, the first switch unit is in an on state from the first moment to the second moment; wherein, the control method further includes: in response to the controlled terminal of the first switch unit receiving the first control signal, the first switch unit is in a closed state before the first moment and after the second moment.
[0025] In an exemplary embodiment, the control method further includes: controlling the power supply branch to provide a first voltage to the word line before a first moment.
[0026] Fifthly, some embodiments of this disclosure provide a discharge circuit for a memory. The discharge circuit includes a discharge terminal, a diode-connected NMOS transistor, and a first switching unit. The diode-connected NMOS transistor is coupled to a word line of the memory; the first switching unit is coupled between the diode-connected NMOS transistor and the discharge terminal, and is configured to be in an on state from a first time moment to a second time moment, connecting the word line to the discharge terminal, and discharging the voltage of the word line from a first voltage to a target voltage.
[0027] In an exemplary embodiment, the drain and gate of a diode-connected NMOS transistor are coupled.
[0028] In an exemplary embodiment, the target voltage is the sum of the voltage at the discharge terminal and the threshold voltage of the diode-connected NMOS transistor. Attached Figure Description
[0029] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:
[0030] Figure 1 This is a circuit diagram of the memory provided in an embodiment of this disclosure;
[0031] Figure 2 This is a circuit diagram of a storage unit provided in an embodiment of this disclosure;
[0032] Figure 3 This is a circuit diagram of the control circuit of the memory provided in an embodiment of this disclosure;
[0033] Figure 4 This is a waveform diagram of the control circuit of the memory provided in the embodiment of this disclosure during operation;
[0034] Figures 5A to 5C This is a circuit diagram of the clamping unit provided in an embodiment of this disclosure;
[0035] Figure 6 This is a schematic block diagram of a system with a memory system provided in an embodiment of this disclosure;
[0036] Figure 7 This is a flowchart illustrating a memory control method provided in an embodiment of this disclosure; and
[0037] Figure 8 This is a circuit diagram of the discharge circuit of the memory provided in an embodiment of this disclosure. Detailed Implementation
[0038] To better understand this disclosure, various aspects of this disclosure will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this disclosure and are not intended to limit the scope of this disclosure in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.
[0039] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence.
[0040] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this disclosure, the word "may" is used to mean "one or more embodiments of this disclosure." And the term "exemplary" is intended to refer to an example or illustration.
[0041] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that, unless expressly stated in this disclosure, terms as defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.
[0042] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this disclosure are not limited to the order in which they are described, but can be performed in any order or in parallel.
[0043] Furthermore, when the term “connection” or “linkage” is used in this disclosure, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.
[0044] Figure 1 This is a circuit diagram of the memory provided in an embodiment of this disclosure. Figure 2 This is a circuit diagram of a storage unit provided in an embodiment of this disclosure.
[0045] like Figure 1 and Figure 2As shown, memory 100 may include a memory cell array 110 and peripheral circuitry 120 coupled to the memory cell array 110. The memory cell array 110 may include a plurality of memory cells MC. The plurality of memory cells MC may be arranged in a two-dimensional array having rows and columns. Exemplarily, the memory cells MC may be implemented as memory cells of the Dynamic Random Access Memory (DRAM) type, and memory 100 may be referred to as DRAM. Thus, the memory cells MC may include a transistor T and a capacitor C coupled in series. For example, one of the source or drain terminals of transistor T is coupled to a first electrode of capacitor C, and a second electrode of capacitor C is coupled to ground. Capacitor C may store binary information based on different stored charges. Transistor T may act as a switch to access the binary information stored in capacitor C.
[0046] It should be noted that the memory cell MC can also be implemented as any suitable type of memory cell, such as PCM (Phase Change Memory), RRAM (Resistive Random Access Memory), FRAM (Ferroelectric Random Access Memory). Each of these types of memory cells can include a memory node and a transistor for accessing the binary information stored in the memory node. For example, for a PCM type memory cell, the memory node can be a chalcogenide material element, and binary information storage can be achieved based on a current-induced reversible transition between amorphous and polycrystalline states. For example, for an RRAM type memory cell, the memory node can be a metal-oxide material element, and binary information storage can be achieved based on a change in the conductive material state caused by current. For example, for an FRAM type memory cell, the memory node can be a ferroelectric material element, and binary information storage can be achieved based on the switching of the ferroelectric material between two polarization states under an external electric field.
[0047] The memory cell array 110 may further include word lines WL and bit lines BL. Word lines WL can be used to couple a row of memory cells MC to peripheral circuitry 120 (e.g., word line driver 124). Bit lines BL can be used to couple a column of memory cells MC to peripheral circuitry 120 (e.g., bit line driver 122). When the memory cells MC are implemented as DRAM-type memory cells, each word line WL can be coupled to the gate of a transistor T in the corresponding row of memory cells MC. Each bit line BL can be coupled to either the drain or source of a transistor T in the corresponding column of memory cells MC.
[0048] In some implementations, peripheral circuitry 120 may include digital, analog, and / or mixed-signal circuitry to support the functionality of memory cell array 110. For example, peripheral circuitry 120 may include bit line driver 122, word line driver 124, and control circuitry 200 (see reference 120). Figure 3 ) and other functional circuits composed of active and / or passive semiconductor devices.
[0049] The following explanation uses memory 100 as a DRAM memory, i.e., memory cell MC is implemented as a DRAM type memory cell, as an example to illustrate the programming and reading operation principles of memory 100.
[0050] In some implementations, the storage cell MC distinguishes between two states based on whether or not the capacitor C stores charge, thereby representing stored information "1" or "0". For example, if the capacitor C has no stored charge, it means that the capacitor C stores data logic "0"; if the capacitor C has stored charge, it means that the capacitor C stores data logic "1".
[0051] When the memory 100 is operating in normal mode, for programming operations, firstly, a programming voltage can be provided to the corresponding word line WL based on the row address, turning on the transistor T of the memory cell MC in the target row. Next, based on the column address, the charge on the corresponding bit line BL can flow into the capacitor C of the memory cell MC in the target column and the target row, which is coupled to the bit line BL, thereby programming the original data logic "0" in capacitor C to data logic "1"; or, based on the column address, the charge in the capacitor C in the target column and the target row can flow to the corresponding bit line BL, thereby programming the original data logic "1" in capacitor C to data logic "0". For reading operations, firstly, the corresponding bit line BL can be pre-charged based on the column address. Then, a read voltage can be provided to the corresponding word line WL based on the row address, turning on the transistor T of the memory cell MC in the target row, so that capacitor C shares the charge with the bit line BL. By judging whether the voltage of the bit line BL rises or falls, the data stored in capacitor C is read as logic "0" or logic "1".
[0052] When the memory 100 operates in One-Time Programmable (OTP) mode, the programming voltage supplied to the corresponding word line WL during programming is greater than the reading voltage supplied to the corresponding word line WL during reading. During consecutive programming and reading operations, the voltage required for the word line WL is provided by different voltage generators. After the programming operation, the larger programming voltage needs to be discharged to meet the voltage requirements of the word line WL in subsequent reading operations. If the target voltage reached by the programming voltage discharge is too large, and the pull-down capability of the circuit providing the reading voltage is weak, it is difficult to quickly reach the required reading voltage for the word line WL, thus affecting the accuracy of subsequent reading operations.
[0053] In view of this, the present disclosure provides a control circuit for a memory. A first switching unit controls the discharge of a first voltage (e.g., a programming voltage) to a target voltage from a first time point to a second time point, ensuring that the target voltage is less than or equal to a second voltage (e.g., a read voltage) required by the word line after the second time point. Based on the strong pull-up capability of the circuit used to provide the second voltage, after the second voltage is provided to the word line, the voltage on the word line can quickly reach the second voltage from the target voltage, thereby meeting the voltage requirements of the word line during the read operation and improving the accuracy of the read operation. Furthermore, a clamping unit can clamp the voltage on the word line at the target voltage during the discharge process, preventing the word line voltage from becoming too low and facilitating a rapid rise in the voltage from the target voltage to the second voltage.
[0054] This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.
[0055] Figure 3 This is a circuit diagram of the control circuit of the memory provided in an embodiment of this disclosure. Figure 4 This is a waveform diagram of the control circuit of the memory provided in the embodiment of this disclosure during operation. Figures 5A to 5C This is a circuit diagram of the clamping unit provided in an embodiment of this disclosure. For example, the memory control circuit 200 (hereinafter referred to as control circuit 200) may be... Figure 1 A portion of the peripheral circuit 120 is shown.
[0056] like Figure 3 and Figure 4As shown, the control circuit 200 may include a discharge terminal 210, a clamping unit 220, a first switching unit 230, and a power supply branch 240. The clamping unit 220 is coupled to the word line WL. The first switching unit 230 is coupled between the clamping unit 220 and the discharge terminal 210 and is configured to be in an on state from a first time t1 to a second time t2, connecting the word line WL to the discharge terminal 210, and discharging the voltage of the word line WL from a first voltage V1 to a target voltage Vtarget. The power supply branch 240 is coupled to the word line WL and is configured to provide a second voltage V2 to the word line WL after the second time t2. The target voltage Vtarget is less than the second voltage V2. For example, the first voltage V1 may be the programming voltage required to program the word line WL in OTP operation mode. The second voltage V2 may be the read voltage required to read the word line WL in OTP operation mode. The programming voltage may be greater than the read voltage. For example, the programming voltage may be approximately 6.5V, and the read voltage may be approximately 2V.
[0057] It should be noted that the voltage Vdischarge at the discharge terminal 210 can be less than the first voltage V1 and can be provided by any suitable voltage source. Furthermore, Figure 4 An example is shown where the target voltage Vtarget is less than the second voltage V2. In other examples, the target voltage Vtarget may be equal to the second voltage V2.
[0058] In the memory control circuit 200 provided in this disclosure, a first switching unit 230 controls the discharge of a first voltage V1 (e.g., programming voltage) to a target voltage Vtarget from a first time t1 to a second time t2, ensuring that the target voltage Vtarget is less than or equal to the second voltage V2 (e.g., read voltage) required by the word line WL after the second time t2. Due to the strong pull-up capability of the circuit used to provide the second voltage V2, after providing the second voltage V2 to the word line WL, the voltage on the word line WL can quickly reach the second voltage V2 from the target voltage Vtarget, thereby meeting the voltage requirement of the word line WL during the read operation and improving the accuracy of the read operation. Furthermore, the clamping unit 220 can clamp the voltage on the word line WL at the target voltage Vtarget during the discharge process, preventing the voltage on the word line WL from becoming too low and helping the voltage on the word line WL to quickly reach the second voltage V2 from the target voltage Vtarget.
[0059] In some embodiments, clamping unit 220 may include a diode-connected MOS transistor M5. The drain D and gate G of the diode-connected MOS transistor M5 are coupled. Thus, the drain and gate potentials of the diode-connected MOS transistor are the same, allowing the MOS transistor to operate in the saturation region and act as a load.
[0060] In some implementations, such as Figure 3 and Figure 5A As shown, the diode-connected MOS transistor M5 can be an NMOS transistor or a PMOS transistor. In some examples, such as... Figure 3 As shown, when the diode-connected MOS transistor M5 is an NMOS transistor, the drain (D) and gate (G) of the diode-connected MOS transistor M5 can be coupled to the word line WL, and the source (S) of the diode-connected MOS transistor M5 can be coupled to the discharge terminal 210. When an NMOS transistor is selected for the diode-connected MOS transistor M5, the NMOS transistor has the characteristics of high electron mobility, fast switching speed, and low conduction loss, which helps to improve the discharge speed without increasing the area overhead. In other examples, such as Figure 5A As shown, when the diode-connected MOS transistor M5 is a PMOS transistor, the drain D and gate G of the diode-connected MOS transistor M5 can be coupled to the discharge terminal 210, and the source S of the diode-connected MOS transistor M5 can be coupled to the word line WL. In this embodiment, when the clamping unit 220 uses the diode-connected MOS transistor M5, it is compatible with CMOS process technology and has a simple structure.
[0061] In other implementations, such as Figure 5B As shown, clamping unit 220 may also include a diode. For example, the anode of the diode is coupled to the word line WL, and the cathode of the diode is coupled to the discharge terminal 210. In some other embodiments, such as Figure 5C As shown, the clamping unit 220 may further include a resistor. The two ends of this resistor are coupled between the word line WL and the discharge terminal 210. In this embodiment, both the diode and the resistor can function as a load. In some embodiments, when the diode-connected MOS transistor M5 can be an NMOS transistor or a PMOS transistor, the voltage Vdischarge at the discharge terminal 210 is less than or equal to the difference between the second voltage V2 and the threshold voltage Vth5 of the diode-connected MOS transistor M5. In other words, the voltage Vdischarge at the discharge terminal 210, the second voltage V2, and the threshold voltage Vth5 of the diode-connected MOS transistor M5 can satisfy: Vdischarge - V2 ≤ Vth5. The threshold voltage Vth5 of the diode-connected MOS transistor M5 depends on its physical structure and materials, and the second voltage V2 can be a preset voltage value. For example, the voltage at the discharge terminal 210 is approximately 1.05V. By reasonably setting the voltage Vdischarge of the discharge terminal 210, the voltage on the word line WL can be clamped at the target voltage Vtarget during the discharge process, so that the voltage on the word line WL is not too small, which helps the voltage on the word line WL to quickly reach the second voltage V2 from the target voltage Vtarget.
[0062] In some implementations, such as Figure 3 and Figure 4 As shown, the first switching unit 230 is further configured to: in response to the controlled terminal of the first switching unit 230 receiving the first control signal CS1, the first switching unit 230 is in an on state from a first time t1 to a second time t2, and in a off state before the first time t1 and after the second time t2. For example, the first control signal CS1 may be a low-level signal before the first time t1 and after the second time t2, and a high-level signal before the first time t1 and the second time t2. When the first control signal CS1 is a high-level signal, the first control signal CS1 is valid.
[0063] In some embodiments, the first switching unit 230 may include a first transistor M1. The first terminal of the first transistor M1 is coupled to the clamping unit 220, the second terminal of the first transistor M1 is coupled to the discharge terminal 210, and the control terminal of the first transistor M1 is configured to receive a first control signal CS1. When the clamping unit 220 is a diode-connected NMOS transistor M5, the first terminal of the first transistor M1 is coupled to the source of the diode-connected NMOS transistor M5.
[0064] In some implementations, the first transistor M1 may be an NMOS transistor. For example, before the first time t1 and after the second time t2, the control terminal of the first transistor M1 receives a low-level first control signal CS1, causing the first transistor M1 to be in the off state. Before the second time t2, the first transistor M1 receives a high-level first control signal CS1, causing the first transistor M1 to be in the on state.
[0065] It should be noted that the first terminal of the first transistor M1 can be the source of the first transistor M1, and the second terminal of the first transistor M1 can be the drain of the first transistor M1. Alternatively, the first terminal of the first transistor M1 can also be the drain of the first transistor M1, and the second terminal of the first transistor M1 can also be the source of the first transistor M1. The source and drain of the first transistor M1 are interchangeable.
[0066] In some implementations, such as Figure 3 As shown, the control circuit 200 may further include a protection transistor M6. The protection transistor M6 may be coupled between the clamping unit 220 and the first transistor M1, and provides overvoltage protection for the first transistor M1. If the clamping unit 220 is a diode-connected NMOS transistor M5, the protection transistor M6 is coupled between the source of the diode-connected NMOS transistor M5 and the first terminal of the first transistor M1. As an example, the protection transistor M6 may be an NMOS transistor.
[0067] In some implementations, during the discharge process, the control terminal of the protection transistor M6 is configured to receive a bias voltage Vpp, causing the protection transistor M6 to be in the on state.
[0068] In some implementations, such as Figure 3 and Figure 4 As shown, the power supply branch 240 is also configured to provide a first voltage V1 to the word line WL before the first time t1. For example, the power supply branch 240 provides the first voltage V1 to the word line WL from the zero time t0 to the first time t1, causing the voltage on the word line WL to rise to the first voltage V1.
[0069] In some implementations, such as Figure 3 and Figure 4 As shown, the power supply branch 240 may include a first voltage generator 241 and a second switching unit 250. The first voltage generator 241 may be configured to provide a first voltage V1. The second switching unit 250 is coupled between the first voltage generator 241 and the word line WL, and is configured to be in an on state before a first time t1 and in a off state after a first time t1 in response to the controlled terminal of the second switching unit 250 receiving a first enable signal EN1. For example, the first enable signal EN1 may be a different level signal before and after the first time t1. Specifically, the first enable signal EN1 may be a high level signal before the first time t1 and a low level signal after the first time t1. When the first enable signal EN1 is a high level signal, the first enable signal EN1 is active.
[0070] In some embodiments, the second switching unit 250 may include a second transistor M2. The first terminal of the second transistor M2 is coupled to the first voltage generator 241, and the second terminal of the second transistor M2 is coupled to the word line WL. The control terminal of the second transistor M2 is configured to receive a first enable signal EN1. For example, before a first time t1, the control terminal of the second transistor M2 receives a high-level first enable signal EN1, causing the second transistor M2 to be in a conducting state. After the first time t1, the second transistor M2 receives a low-level first enable signal EN1, causing the second transistor M2 to be in a cutoff state.
[0071] It should be noted that the first terminal of the second transistor M2 can be the source of the second transistor M2, and the second terminal of the second transistor M2 can be the drain of the second transistor M2. The first terminal of the second transistor M2 can also be the drain of the second transistor M2, and the second terminal of the second transistor M2 can also be the source of the second transistor M2. The source and drain of the second transistor M2 are interchangeable.
[0072] In some implementations, such as Figure 3 and Figure 4 As shown, the power supply branch 240 also includes a second voltage generator 242 and a third switching unit 260. The second voltage generator 242 can be configured to provide a second voltage V2. The third switching unit 260 can be coupled between the second voltage generator 242 and the word line WL, and can be configured to be in a closed state before the second time t2 and in an open state after the second time t2 in response to the controlled terminal of the third switching unit 260 receiving a second enable signal EN2. For example, the second enable signal EN2 can be a different level signal before and after the second time t2. Specifically, the second enable signal EN2 is a low level signal before the second time t2 and a high level signal after the second time t2. When the second enable signal EN2 is a high level signal, the second enable signal EN2 is active.
[0073] In some embodiments, the third switching unit 260 includes a third transistor M3. The first terminal of the third transistor M3 is coupled to the second voltage generator 242, and the second terminal of the third transistor M3 is coupled to the word line WL. The control terminal of the third transistor M3 is configured to receive a second enable signal EN2. For example, before the second time t2, the control terminal of the third transistor M3 receives a low-level second enable signal EN2, causing the third transistor M3 to be in a cutoff state. After the second time t2, the third transistor M3 receives a high-level second enable signal EN2, causing the third transistor M3 to be in a conducting state.
[0074] It should be noted that the first terminal of the third transistor M3 can be the source of the third transistor M3, and the second terminal of the third transistor M3 can be the drain of the third transistor M3. Alternatively, the first terminal of the third transistor M3 can also be the drain of the third transistor M3, and the second terminal of the third transistor M3 can also be the source of the third transistor M3. The source and drain of the third transistor M3 are interchangeable.
[0075] In some implementations, such as Figure 3As shown, the control circuit 200 may further include a NOR gate 270. The inputs of the NOR gate 270 are configured to receive a first enable signal EN1 and a second enable signal EN2. The output of the NOR gate 270 is coupled to the control terminal of the first transistor M1 and can be configured to output a first control signal CS1. The NOR gate 270 can be used to implement a logic NOR function. Specifically, the output of the NOR gate 270 is high only when all inputs are low-level signals. When one or more inputs of the NOR gate 270 are high-level signals, its output is low-level. Thus, before the first time t1, if the first enable signal EN1 is high and the second enable signal EN2 is low, the first control signal CS1 output via the NOR gate 270 is low. From the first time t1 to the second time t2, if both the first enable signal EN1 and the second enable signal EN2 are low, the first control signal CS1 output via the NOR gate 270 is high. After the second time t2, the first enable signal EN1 is a low-level signal and the second enable signal EN2 is a high-level signal. Then the first control signal CS1 output through the NOR gate 270 is a low-level signal.
[0076] In the above embodiment, when both the first enable signal EN1 and the second enable signal EN2 are low-level signals, the first voltage generator 241 and the second voltage generator 242 are not connected to the word line WL. At this time, the first control signal CS1, gated by the first enable signal EN1 and the second enable signal EN2, can connect the word line WL to the discharge terminal 210 through the first switching unit 230 (e.g., the first transistor M1), thereby preventing the word line WL from being simultaneously connected to the first voltage generator 241, the second voltage generator 242, and the discharge terminal 210, which helps to improve the reliability of the control circuit 200.
[0077] In some embodiments, the control circuit 200 may further include a fourth switching unit 280. The fourth switching unit 280 may be coupled between the WL word line and the clamping unit 220, and may be configured to be in an on state from a first time t1 to a second time t2 in response to the controlled terminal of the fourth switching unit 280 receiving a second control signal CS2. Optionally, the fourth switching unit 280 may also be configured to be in a off state before the first time t1 and after the second time t2 in response to the controlled terminal of the fourth switching unit 280 receiving the second control signal CS2.
[0078] In some embodiments, the fourth switching unit 280 may include a fourth transistor M4. The first terminal of the fourth transistor M4 is coupled to the clamping unit 220, and the second terminal of the fourth transistor M4 is coupled to the word line WL. The control terminal of the fourth transistor M4 is configured to receive a second control signal CS2. For example, before the first time t1, the control terminal of the fourth transistor M4 receives a low-level second control signal CS2, causing the fourth transistor M4 to be in a cutoff state. From the first time t1 to the second time t2, the control terminal of the fourth transistor M4 receives a high-level second control signal CS2, causing the fourth transistor M4 to be in a conduction state. After the second time t2, the fourth transistor M4 receives a low-level second control signal CS2, causing the fourth transistor M4 to be in a cutoff state.
[0079] It should be noted that the first terminal of the fourth transistor M4 can be the source of the fourth transistor M4, and the second terminal of the fourth transistor M4 can be the drain of the fourth transistor M4. Alternatively, the first terminal of the fourth transistor M4 can also be the drain of the fourth transistor M4, and the second terminal of the fourth transistor M4 can also be the source of the fourth transistor M4. The source and drain of the fourth transistor M4 are interchangeable.
[0080] In the above embodiment, the fourth switching unit 280 (e.g., the fourth transistor M4) can be used to control the word line WL and the discharge terminal 210 to be connected. The additional provision of the fourth switching unit 280, based on the first switching unit 230, can increase the reliability of the control circuit 200.
[0081] The following is combined Figure 3 and Figure 4 The working process of the control circuit 200 is explained.
[0082] The time period from time zero t0 to time one t1 is the programming operation period. Specifically, the first enable signal EN1 is a high-level signal, and the second transistor M2 is in the on state. The word line WL is connected to the first voltage generator 241. The first voltage generator 241 provides the first voltage V1 to the word line WL. The second enable signal EN2 is a low-level signal, and the third transistor M3 is in the off state. The word line WL is not connected to the second voltage generator 242. The high-level first enable signal EN1 and the low-level second enable signal EN2 serve as input signals to the NOR gate 270, and the output of the NOR gate 270 outputs a low-level first control signal CS1. Controlled by the first control signal CS1, the first transistor M1 is in the off state. At the same time, the second control signal CS2 is also a low-level signal. Controlled by the second control signal CS2, the fourth transistor M4 is also in the off state. The word line WL is not connected to the discharge terminal 210.
[0083] The time period from the first time point t1 to the second time point t2 is the discharge operation period. Specifically, the first enable signal EN1 is a low-level signal, and the second transistor M2 is in the off state. The word line WL is not connected to the first voltage generator 241. The second enable signal EN2 is a low-level signal, and the third transistor M3 is in the off state. The word line WL is not connected to the second voltage generator 442. The low-level first enable signal EN1 and the low-level second enable signal EN2 serve as input signals to the NOR gate 270, and the output of the NOR gate 270 outputs a high-level first control signal CS1. Controlled by the first control signal CS1, the first transistor M1 is in the on state. At the same time, the second control signal CS2 is also a high-level signal. Controlled by the second control signal CS2, the fourth transistor M4 is in the on state. The word line WL is connected to the discharge terminal 210. The voltage of word line WL drops from the first voltage V1 until it reaches the target voltage Vtarget, and is clamped at the sum of the voltage Vdischarge at the discharge terminal 210 and the threshold voltage Vth5 of the fifth transistor M5.
[0084] The time period from the second time t2 to the third time t3 is the read operation period. Specifically, the first enable signal EN1 is a low-level signal, and the second transistor M2 is in the off state. The word line WL is not connected to the first voltage generator 241. The second enable signal EN2 is a high-level signal, and the third transistor M3 is in the on state. The word line WL is connected to the second voltage generator 242. The second voltage generator 242 provides the second voltage V2 to the word line WL. When the target voltage is less than the second voltage V2, due to the strong pull-up capability of the second voltage generator 422, the voltage of the word line WL quickly reaches the second voltage V2 from the target voltage Vtarget. When the target voltage is equal to the second voltage V2, under the action of the second voltage generator 422, the voltage of the word line WL maintains the target voltage Vtarget (i.e., the second voltage V2). The low-level first enable signal EN1 and the high-level second enable signal EN2 serve as the input signals of the NOR gate 270, and the output of the NOR gate 270 outputs a low-level first control signal CS1. Controlled by the first control signal CS1, the first transistor M1 is in the off state. Simultaneously, the second control signal CS2 is also at a low level. Controlled by the second control signal CS2, the fourth transistor M4 is in the off state. The word line WL is not connected to the ground terminal 210.
[0085] This disclosure also provides a memory. For example... Figures 1 to 4As shown, the memory 100 may include a memory cell array 110 and peripheral circuitry 120. The memory cell array 110 may include memory cells MC and word lines WL. The peripheral circuitry 120 is coupled to the memory cell array 110, and the peripheral circuitry 120 may include the control circuitry 200 in any of the above embodiments. Since the memory 100 includes the control circuitry 200 in any of the above embodiments of this disclosure, the memory 100 may have the same beneficial effects as the control circuitry 200, which will not be described again here.
[0086] In some implementations, memory 100 may be DRAM memory. For example, DRAM memory may include multiple DRAM-type memory cells. For instance, memory 100 may operate in OTP mode.
[0087] In other embodiments, the memory 100 may also be one of PCM memory, RRAM memory, and FRAM memory. For example, each of the above-mentioned memories may include a PCM type memory cell, an RRAM type memory cell, and an FRAM type memory cell, respectively.
[0088] This disclosure also provides a memory system. Figure 6 This is a schematic block diagram of a system with a memory system provided in an embodiment of this disclosure.
[0089] like Figure 6 As shown, system 10 can be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a memory system 10 located therein). Figure 6 As shown, system 10 may include a host 14 and a memory system 11, the memory system 11 having one or more memories 12 and a controller 13. The host 14 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 14 may be configured to send or receive data to and from the memory 12.
[0090] Memory 12 may include the memory described in any embodiment of this disclosure (e.g., memory 100). According to some embodiments, controller 13 is coupled to memory 12 and host 14 and configured to control memory 12. Controller 13 can manage data stored in memory 12 and communicate with host 14. Controller 13 may be configured to control operations of memory 12, such as read, erase, and program operations. Controller 13 may communicate with external devices (e.g., host 14) according to a specific communication protocol.
[0091] This disclosure also provides a method for controlling a memory in some embodiments. The memory may include a discharge terminal, a clamping unit, a first switching unit, and a power supply branch. The clamping unit is coupled to the word line of the memory, the first switching unit is coupled between the clamping unit and the discharge terminal, and the power supply branch is coupled to the word line. Figure 7 This is a flowchart illustrating the memory control method provided in an embodiment of this disclosure. Figure 7 As shown, the memory control method 300 (hereinafter referred to as control method 300) may include the following steps.
[0092] S310 controls the first switching unit to be in the open state from the first moment to the second moment, so that the word line is connected to the discharge terminal, and the voltage of the word line is discharged from the first voltage to the target voltage.
[0093] S320, after the second moment, controls the power supply branch to provide a second voltage to the word line, wherein the target voltage is less than or equal to the second voltage.
[0094] According to the control method 300 provided in this disclosure embodiment, a first voltage (e.g., programming voltage) is discharged to a target voltage from a first time moment to a second time moment via a first switching unit, such that the target voltage is less than or equal to a second voltage (e.g., read voltage) required by the word line after the second time moment. Based on the strong pull-up capability of the circuit used to provide the second voltage, after the second voltage is provided to the word line, the voltage on the word line can quickly reach the second voltage from the target voltage, thereby meeting the voltage requirements of the word line in the read operation and improving the accuracy of the read operation. Furthermore, the clamping unit can clamp the voltage on the word line at the target voltage during the discharge process, preventing the word line voltage from becoming too low and helping the voltage on the word line to quickly reach the second voltage from the target voltage.
[0095] In some embodiments, controlling the first switching unit to be in an on state from a first time moment to a second time moment, so that the word line is connected to the discharge terminal, may include: in response to the controlled terminal of the first switching unit receiving a first control signal, the first switching unit is in an on state from the first time moment to the second time moment. Furthermore, the control method 300 may also include: in response to the controlled terminal of the first switching unit receiving the first control signal, the first switching unit is in a off state before the first time moment and after the second time moment. The specific process of turning the first switching unit on and off has been described in detail in the control circuit section and will not be repeated here.
[0096] In some embodiments, the control method 300 may further include: before the first moment, controlling the power supply branch to provide a first voltage to the word line. The specific process of the power supply circuit providing voltage to the word line has been described in detail in the control circuit section and will not be repeated here.
[0097] Some embodiments of this disclosure also provide a discharge circuit for a memory. Figure 8 This is a circuit diagram of the discharge circuit of the memory provided in an embodiment of this disclosure.
[0098] like Figure 8 As shown, the memory discharge circuit 400 (hereinafter referred to as discharge circuit 400) includes a discharge terminal 410, a diode-connected NMOS transistor M5, and a first switching unit 430. The diode-connected NMOS transistor M5 is coupled to the memory word line WL. The first switching unit 430 is coupled between the diode-connected NMOS transistor M5 and the discharge terminal 410, and is configured to be in the on state from a first time moment to a second time moment, so that the word line WL is connected to the discharge terminal 410, and the voltage of the word line WL is discharged from the first voltage to the target voltage.
[0099] It should be noted that the voltage at the discharge terminal 410 may be less than the first voltage and may be provided by any suitable voltage source.
[0100] According to the discharge circuit 400 provided in the embodiments of this disclosure, the voltage of word line WL is controlled by the first switching unit 430 to discharge from the first voltage to the target voltage. During the discharge process, the diode-connected NMOS transistor M5 has the characteristics of high electron mobility, fast switching speed and low conduction loss, which helps to improve the discharge speed and does not increase the area overhead.
[0101] In some implementations, the drain and gate of the diode-connected NMOS transistor M5 are coupled. Thus, the drain and gate potentials of the diode-connected MOS transistor are the same, allowing the MOS transistor to operate in the saturation region and function as a load.
[0102] In some implementations, the target voltage is the sum of the voltage at the discharge terminal and the threshold voltage of the diode-connected NMOS transistor. The threshold voltage of the diode-connected MOS transistor M5 depends on parameters such as its physical structure and materials. By appropriately setting the voltage at the discharge terminal, the voltage of the word line WL can be clamped at the target voltage during discharge, allowing for flexible adjustment of the target voltage.
[0103] In some embodiments, the first switching unit 430 may include a first transistor M1. The first terminal of the first transistor M1 is coupled to the source of a diode-connected NMOS transistor M5, the second terminal of the first transistor M1 is coupled to a discharge terminal 410, and the control terminal of the first transistor M1 is configured to receive a first control signal CS1.
[0104] In some implementations, such as Figure 8 As shown, the discharge circuit 400 may further include a protection transistor M6. The protection transistor M6 may be coupled between the diode-connected NMOS transistor M5 and the first transistor M1, and the protection transistor M6 provides overvoltage protection for the first transistor M1.
[0105] The above description is merely an illustration of the embodiments of this disclosure and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features disclosed in this disclosure that have similar functions.
Claims
1. A control circuit for a memory, comprising: Discharge terminal; Clamping units are coupled to the word lines of the memory; A first switching unit is coupled between the clamping unit and the discharge terminal and is configured to be in an on state from a first moment to a second moment, so that the word line is connected to the discharge terminal and the voltage of the word line is discharged from a first voltage to a target voltage. as well as A power supply branch, coupled to the word line, is configured to provide a second voltage to the word line after the second moment; Wherein, the target voltage is less than or equal to the second voltage.
2. The control circuit according to claim 1, wherein, The clamping unit includes a diode-connected MOS transistor, wherein the drain and gate of the diode-connected MOS transistor are coupled.
3. The control circuit according to claim 2, wherein, The diode-connected MOS transistor is either an NMOS transistor or a PMOS transistor.
4. The control circuit according to claim 3, wherein, The voltage at the discharge terminal is less than or equal to the difference between the second voltage and the threshold voltage of the diode-connected MOS transistor.
5. The control circuit according to claim 1, wherein, The clamping unit includes a diode and / or a resistor.
6. The control circuit according to any one of claims 1 to 5, wherein, The first switching unit is also configured to: In response to the first control signal being received by the controlled terminal of the first switch unit, the first switch unit is in the open state from the first time to the second time, and in the closed state before the first time and after the second time.
7. The control circuit according to claim 6, wherein, The first switching unit includes a first transistor, the first terminal of the first transistor is coupled to the clamping unit, the second terminal of the first transistor is coupled to the discharge terminal, and the control terminal of the first transistor is configured to receive the first control signal.
8. The control circuit according to claim 7, wherein, The control circuit also includes: A protection transistor is coupled between the clamping unit and the first transistor, and the protection transistor provides overvoltage protection for the first transistor.
9. The control circuit according to claim 8, wherein, The first transistor is an NMOS transistor, and the protection transistor is an NMOS transistor.
10. The control circuit according to claim 7, wherein, The power supply branch is also configured to provide the first voltage to the word line before the first moment.
11. The control circuit according to claim 7, wherein, The power supply branch includes: A first voltage generator is configured to provide the first voltage; and The second switching unit, coupled between the first voltage generator and the word line, is configured such that, in response to the controlled terminal of the second switching unit receiving a first enable signal, the second switching unit is in an on state before the first moment and in a off state after the first moment.
12. The control circuit according to claim 11, wherein, The second switching unit includes a second transistor, the first terminal of which is coupled to the first voltage generator, the second terminal of which is coupled to the word line, and the control terminal of the second transistor is configured to receive the first enable signal.
13. The control circuit according to claim 11, wherein, The power supply branch also includes: A second voltage generator is configured to provide the second voltage; and A third switching unit, coupled between the second voltage generator and the word line, is configured such that, in response to the controlled terminal of the third switching unit receiving a second enable signal, the third switching unit is in a closed state before the second time moment and in an open state after the second time moment.
14. The control circuit according to claim 13, wherein, The second switching unit includes a third transistor, the first terminal of which is coupled to the second voltage generator, the second terminal of which is coupled to the word line, and the control terminal of the third transistor is configured to receive the second enable signal.
15. The control circuit according to claim 13, wherein, The control circuit also includes: The NOR gate has its input configured to receive the first enable signal and the second enable signal, and its output coupled to the control terminal of the first transistor and configured to output the first control signal.
16. The control circuit according to any one of claims 1 to 5, wherein, The control circuit also includes: A fourth switching unit, coupled between the word line and the clamping unit, is configured such that, in response to the controlled terminal of the fourth switching unit receiving a second control signal, the fourth switching unit is in an on state from the first time moment to the second time moment.
17. The control circuit according to any one of claims 1 to 5, wherein, The first voltage is the programming voltage, and the second voltage is the reading voltage, wherein the programming voltage is greater than the reading voltage.
18. A memory comprising: A memory cell array, comprising memory cells and word lines coupled to the memory cells; The peripheral circuitry is coupled to the memory cell array and includes the control circuitry as described in any one of claims 1 to 17.
19. The memory according to claim 18, wherein, The memory is a dynamic random access memory.
20. A memory system, comprising: The memory as described in claim 18 or 19; as well as A controller, coupled to the memory, is used to control the memory to store data.
21. A method for controlling a memory, wherein, The memory includes a discharge terminal, a clamping unit, a first switching unit, and a power supply branch. The clamping unit is coupled to the word line of the memory, the first switching unit is coupled between the clamping unit and the discharge terminal, and the power supply branch is coupled to the word line. The control method includes: Controlling the first switching unit to be in the ON state from a first moment to a second moment connects the word line to the discharge terminal, causing the voltage of the word line to discharge from a first voltage to a target voltage; and After the second moment, control the power supply branch to provide a second voltage to the word line; Wherein, the target voltage is less than or equal to the second voltage.
22. The control method according to claim 21, wherein, Controlling the first switching unit to be in the on state from the first moment to the second moment includes: In response to the first control signal being received by the controlled terminal of the first switch unit, the first switch unit is in the open state from the first time moment to the second time moment; The control method further includes: In response to the first control signal being received by the controlled terminal of the first switching unit, the first switching unit is in a closed state before the first time and after the second time.
23. The control method according to claim 21 or 22, wherein, The control method further includes: Before the first moment, the power supply branch is controlled to provide the first voltage to the word line.
24. A discharge circuit for a memory, comprising: Discharge terminal; A diode-connected NMOS transistor coupled to the word line of the memory; as well as The first switching unit is coupled between the diode-connected MOS transistor and the discharge terminal, and is configured to be in the on state from the first moment to the second moment, so that the word line is connected to the discharge terminal, and the voltage of the word line discharges from the first voltage to the target voltage.
25. The discharge circuit according to claim 23, wherein, The drain and gate of the diode-connected NMOS transistor are coupled.
26. The discharge circuit according to claim 23, wherein, The target voltage is the sum of the voltage at the discharge terminal and the threshold voltage of the diode-connected NMOS transistor.