Memory device using two encoding levels to store data in ternary cells

Abstract

This application relates to a memory device that stores data in ternary units using two coding levels. Systems, methods, and apparatuses related to the memory device for storing data are also included. In one method, the memory device includes at least one memory array having ternary memory units. A controller stores data in pairs of the ternary units. Each value in the data is stored by writing it to a pair of corresponding units using a first coding level. The controller defines special values ​​and identifies examples of the special values ​​in the data. For each identified special value, a second coding level is used to store additional bits.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 757,103, filed February 11, 2025, the entire disclosure of which is hereby incorporated herein by reference. Technical Field

[0003] At least some of the embodiments disclosed herein generally relate to memory devices, and more specifically (but not limited to) to memory devices that use two coding levels to store data in memory cells. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, a binary device has two states, typically represented by logic "1" or logic "0". In other systems, more than two states can be stored. To access stored information, components of the electronic device can read or sense the stored states in the memory device. To store information, components of the electronic device can write to or program the states in the memory device.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), and so on. Memory devices can be volatile or non-volatile. Non-volatile memory cells can maintain their stored logic state for a long time, even without external power. Volatile memory cells lose their stored state over time unless they are periodically refreshed by an external power source.

[0006] A storage device is an example of a memory device. A typical computer storage device has a controller that receives data access requests from a host computer and performs programmed computational tasks to execute the requests in a manner specific to the media and structure configured in the storage device. In one example, the memory controller manages the data stored in the memory and communicates with the computer device. In some examples, the memory controller is in a solid-state drive (SSD) used in media used in mobile devices, laptops, or digital cameras.

[0007] Firmware can be used to operate the memory controller of a specific storage device. In one instance, a computer system or device communicates with the memory controller when reading data from or writing data to the memory device.

[0008] Memory devices typically store data in memory cells. In some cases, memory cells exhibit non-uniform, variable electrical characteristics, which can arise from various factors including statistical process variations, cyclic events (such as read or write operations on memory cells), or drift (such as changes in the resistance of chalcogenide alloys).

[0009] In one instance, reading a dataset (e.g., codewords, pages) is performed by determining the read voltage (e.g., an estimated median of threshold voltages) of the memory cells storing the dataset. In some cases, the memory device may include an array of PCM cells arranged in a 3D architecture, such as a crosspoint architecture for storing datasets. The PCM cells in the crosspoint architecture may represent a first logic state (e.g., logic 1, set state) associated with a first set of threshold voltages or a second logic state (e.g., logic 0, reset state) associated with a second set of threshold voltages. In some cases, data may be stored using encoding (e.g., error correction coding (ECC)) to recover data from errors in the data stored in the memory cells.

[0010] For variable resistance memory cells (such as PCM cells), one of several states (such as resistance states) can be set. For example, a memory cell can be programmed to one of two states (such as logic 1 or 0), depending on whether the cell is programmed to a resistance higher or lower than a certain level. As an additional example, various variable resistance memory cells can be programmed to one of several different states corresponding to multiple data states, such as 10, 01, 00, 11, 111, 101, 100, 1010, 1111, 0101, 0001, etc.

[0011] The state of a variable-resistance memory cell can be determined by sensing the current through the cell in response to an applied interrogation voltage (e.g., reading). The sensed current, which changes based on the cell's resistance, can indicate the cell's state (e.g., binary data stored in the cell). The resistance of a programmed variable-resistance memory cell can drift over time (e.g., shift). Resistance drift can lead to erroneous sensing of the variable-resistance memory cell (e.g., determining that the cell is in a state other than its programmed state, and other problems).

[0012] For example, a PCM cell can be programmed to a reset state (amorphous) or a set state (crystalline). A reset pulse (e.g., a pulse used to program the cell to the reset state) may contain a relatively high current pulse applied to the cell over a relatively short period of time, causing the phase change material of the cell to melt and cool rapidly, resulting in a relatively small amount of crystallization. Conversely, a set pulse (e.g., a pulse used to program the cell to the set state) may contain a relatively low current pulse applied to the cell over a relatively long time interval and at a slower quenching rate, resulting in increased crystallization of the phase change material.

[0013] A programming signal can be applied to a selected memory cell to program the cell to a target state. A read signal can be applied to a selected memory cell to read the cell (e.g., to determine the state of the cell). For example, the programming signal and the read signal can be current and / or voltage pulses. Summary of the Invention

[0014] One aspect of this application relates to an apparatus comprising: a memory array including ternary units; and at least one controller configured to store data in the ternary units, wherein a portion of the data corresponding to a defined value is stored using two encoding levels, and another remaining portion of the data is stored using one encoding level.

[0015] Another aspect of this application relates to a system comprising: a memory configured to store user data; and a controller configured to: identify the location of a specific value in the user data; and associate a corresponding additional bit with each identified location.

[0016] Another aspect of this application relates to a system comprising: at least one processing device; and at least one memory containing instructions configured to instruct the at least one processing device to: adjust the proportion of special values ​​in data; and use ternary unit pairs to store each special value and corresponding extra bits. Attached Figure Description

[0017] The embodiments are illustrated in the accompanying drawings by way of example rather than limitation, wherein similar reference element symbols indicate similar elements.

[0018] Figure 1 A memory device is shown that accesses a memory array when performing a read or write operation, according to some embodiments.

[0019] Figure 2 A memory array having memory cells accessed using a common word line is shown according to some embodiments.

[0020] Figure 3 Examples of memory cells including selection devices according to some embodiments are shown.

[0021] Figure 4 A memory device is shown according to one embodiment, which is configured with a read manager to access memory cells in a memory array.

[0022] Figure 5 A memory cell having a bit line driver and a word line driver configured to apply voltage is shown according to one embodiment.

[0023] Figure 6An exemplary normal quantile (NQ) plot is shown to represent the statistical distribution of the threshold voltages of memory cells.

[0024] Figure 7 An exemplary three-dimensional memory array structure with word lines configured in a comb-like structure is shown according to some embodiments.

[0025] Figure 8 An encoding table for storing data using a pair of ternary units is shown according to some embodiments.

[0026] Figure 9 An encoding table for storing data using an encoding level is shown according to some embodiments.

[0027] Figure 10 This illustrates an encoding table, according to some embodiments, for storing data corresponding to defined values ​​using two encoding levels.

[0028] Figure 11 This demonstrates how a data stream is encoded according to some embodiments to use two encoding levels to store additional bits.

[0029] Figure 12 The demonstration shows scanning a data stream according to some embodiments to identify special values ​​used to store additional bits using two coding levels.

[0030] Figure 13 The examples demonstrate how, according to some embodiments, the storage density of memory cells with various levels per cell can be improved by using two coding-level storage extra bits.

[0031] Figure 14 The examples demonstrate an exemplary improvement in the storage density of ternary cells by using two extra bits of code-level storage, according to some embodiments.

[0032] Figure 15 This document demonstrates a method for storing user data using ternary unit pairs, according to some embodiments. Detailed Implementation

[0033] The following disclosure describes various embodiments of a memory device that uses two coding levels to store data in memory cells (e.g., cells that each store data in three or more states or levels). In one embodiment, data is stored using ternary cell pairs. In one example, the memory cells are chalcogenide memory cells. Each pair of ternary cells is programmed according to a coding scheme that uses two coding levels to increase storage density. This implementation stores additional bits.

[0034] Memory storage typically uses power-of-2 encoding. In one instance, a memory cell has two data states or levels. This memory cell has a density of 1 bit per cell. To increase storage density, memory cells with higher powers of 2 encoding using multiple data states or levels can be used. For example, a memory cell could have 4 states or levels.

[0035] However, in some cases, memory technology may not be reliable enough for operations at densities of four levels per cell or higher. For example, the standard deviation (σ) of the threshold voltage distribution of a memory cell may be too large for a particular memory technology, and four levels cannot be reliably used. In such cases, a non-power-of-two encoding scheme can be used. For example, a ternary memory cell with three states or levels per cell (e.g., L0, L1, L2) can be used to store data. For example, each ternary cell can be programmed to have one of three different threshold voltages.

[0036] Because each unit uses 3 levels of encoding that is not based on powers of 2, this can lead to some technical problems during implementation. For example, memory density is suboptimal because the encoding scheme has some redundancy during encoding. Redundancy can be tolerated to simplify the design of the encoding circuit system. However, this leads to inefficient memory storage.

[0037] For example, non-power-of-two encoded circuit systems are complex to construct and require a suboptimal cell density for simplicity. This implies an area overhead matching the page dimension. For instance, in the case of three levels per cell, it might be simpler to store three bits of code in two cells. However, if this is done, only eight of the nine states or level combinations provided by two memory cells (e.g., L2 / L1, L0 / L2, etc.) will be used. This leads to technical problems of inefficient use of layout area and storage resources.

[0038] To address the aforementioned and other technical problems, the memory device uses ternary cell pairs to store data. In one embodiment, each pair provides nine levels of combinations. Three-bit combinations of data are stored. Each three-bit combination is stored using a pair of cells. Eight distinct values ​​(e.g., 0, 1, 2, 3, 4, 5, 6, 7) can be stored, each mapped to a combination at the cell level.

[0039] Nine levels are used to encode three bits, providing a redundant level combination that is not used in a single level of the aforementioned three-bit encoding. To improve storage density, this redundant level combination is associated with a defined value. The defined value can be arbitrarily chosen from eight values. The defined value is stored using two encoding levels.

[0040] For example, the defined value can be selected as 4 by the controller. Two of the nine level combinations are mapped to the defined value. These two level combinations are mapped to the value of the extra bits stored (e.g., 0 or 1). Values ​​of data that are not the defined value are stored using one first encoding level. Various 3-bit combinations of all values ​​except the defined value are stored using the method described above. However, if the 3-bit combination equals the defined value, then a total of four bits are stored (the 3-bit combination plus the extra bits).

[0041] It should be noted that the terms "defined value" and "special value" are used to describe the various embodiments described herein. The terms "defined value" and "special value" are generally used interchangeably herein.

[0042] In one embodiment, the memory device uses chalcogenide cells to store data. The controller stores user data in the cells. User data corresponding to defined values ​​(e.g., special value 4) is stored using two encoding levels. Other remaining user data (e.g., values ​​0, 1, 2, 3, 5, 6, 7) is stored using one encoding level.

[0043] In one embodiment, the controller identifies the location of a specific value in user data received from the host device. The controller associates a corresponding extra bit with each identified location. The controller uses a first encoding level to store user data at the identified location and a second encoding level to store the corresponding extra bit.

[0044] In one embodiment, the system includes at least one processing device and at least one memory containing instructions configured to instruct the at least one processing device to: adjust the scale of special values ​​in data; and use ternary unit pairs to store each special value and corresponding additional bits. For example, the scale is changed by inverting all bits of a selected incoming codeword. The controller scans the data upon receipt to determine the scale adjustment.

[0045] At least some of the embodiments described herein offer various advantages. For example, using two-level encoding to store data in ternary cells compensates for previously lost bit / cell density and associated area overhead.

[0046] At least some embodiments herein relate to memory devices using bipolar operation on memory arrays. In one example, a bipolar selection voltage is used to select memory cells of the memory array. In one example, the memory cells are arranged in a crosspoint architecture. In one example, each memory cell is formed using a single selection device. In one example, the selection device comprises a chalcogenide material that switches (e.g., abruptly) when a sufficient voltage is applied across the memory cell.

[0047] The memory device may, for example, store data used by a host device (such as the computing device of an autonomous vehicle or another computing device that accesses data stored in the memory device). In one example, the memory device is a solid-state drive installed in an electric vehicle.

[0048] In some cases, the memory device may include an array of memory cells arranged in a three-dimensional (3D) architecture (e.g., a crosspoint architecture) to store a dataset. Memory cells in the crosspoint architecture may, for example, represent a first logic state (e.g., logic 1, set state) associated with a first set of threshold voltages or a second logic state (e.g., logic 0, reset state) associated with a second set of threshold voltages.

[0049] In other embodiments, the memory cells may be arranged in a three-dimensional (3D) vertical architecture. The 3D vertical architecture may include memory cells located at the intersection of a vertical access line (e.g., a bit line strut) and each of a plurality of second access lines (e.g., word lines) formed in a horizontal plane or layer parallel to each other.

[0050] More generally, integrated circuit memory cells (such as cross-point memory or memory cells in a 3D vertical array) can be programmed to store data through their states under voltages applied across the memory cell. For example, if a memory cell is configured or programmed to allow a large current to flow through the memory cell at a voltage within a predefined voltage range, then the memory cell is considered to be configured or programmed to store a first bit value (e.g., 1 or 0); otherwise, the memory cell stores a second bit value (e.g., 0 or 1).

[0051] Optionally, the memory cell can be configured or programmed to store more than one data bit by, for example, having a threshold voltage in one of more than two separate voltage regions.

[0052] A threshold voltage for a memory cell causes it to switch rapidly or abruptly (e.g., for chalcogenide memory cells) or jump from a non-conductive state to a conductive state when the voltage applied across the memory cell increases above the threshold voltage. The non-conductive state allows a small leakage current to pass through the memory cell; in contrast, the conductive state allows current exceeding the threshold amount to pass through. Therefore, memory devices can use sensors (e.g., sensing amplifiers) to detect changes or determine the conductive / non-conductive state of the memory device under one or more applied voltages to assess or classify the threshold voltage level of the memory cell and thus assess or classify its stored data.

[0053] Threshold voltages configured / programmed in different voltage zones of a memory cell can be used to represent different data values ​​stored in the memory cell. For example, the threshold voltage of a memory cell can be programmed in any of four predefined voltage zones; and each zone can be used to represent the bit value of a different 2-bit data item. Therefore, given a 2-bit data item, one of the four voltage zones can be selected based on the mapping between the 2-bit data item and the voltage zone; and the threshold voltage of the memory cell can be adjusted, programmed, or configured in the selected voltage zone to represent or store the given 2-bit data item. To retrieve, identify, or read a data item from a memory cell, one or more read voltages can be applied across the memory cell to determine which of the four voltage zones contains the threshold voltage of the memory cell. Identification of the voltage zone containing the threshold voltage of the memory cell provides information about the 2-bit data item that has been stored, programmed, or written to the memory cell.

[0054] In one embodiment, the memory device has a memory array comprising memory cells (e.g., chalcogenide memory cells in a vertically integrated crosspoint memory array). The memory device includes a bias circuitry system to apply voltage to the memory cells during read, write, and / or other operations. In one example, the bias circuitry system includes a decoder to direct the applied voltage to word lines, gate lines, and / or digital lines. During a read operation, a sensing circuitry system of the memory device is used to read the logic state of the memory cells. In some cases, a sensing circuitry system is used during write operations (e.g., to adjust the write voltage).

[0055] It should be noted that the terms "digital line" and "bit line" are used to describe the various embodiments described herein. The terms "digital line" and "bit line" are generally used interchangeably herein.

[0056] In one instance, the controller receives a command (e.g., from a host device) to read data at first and second addresses (e.g., addresses provided by the host along with a command). The first address corresponds to a first memory cell in the memory array, the second address corresponds to a second memory cell in the memory array, and the first and second memory cells are accessed using a common word line. In one instance, the first and second memory cells are located in the same block of the memory array.

[0057] In response to a received command, the controller uses a bias circuitry to bias the word line voltage to an initial voltage (e.g., the voltage at the start of a read voltage ramp for the controller's read algorithm). The controller then causes the sensing circuitry to read a first memory cell. This read operation involves increasing the word line voltage by an amount from the initial voltage during the ramp.

[0058] In one example, the word line idle mode voltage is ground or 0 volts. During the selection phase, the word line voltage decreases to an initial voltage of -2 volts (-2 V). The read voltage then scales up in increments of, for example, -0.2 volts (-0.2 V) until a final maximum read voltage is reached. In one example, this maximum read voltage corresponds to the time when the controller determines that conditions are met (e.g., minimum read error rate reached, several or a certain proportion of data memory cells switched, and / or several reference or mode cells switched).

[0059] Figure 1 A memory device is shown that accesses a memory array when performing read or write operations, according to some embodiments. Memory device 101 includes a memory array 102 having data units 110 (and optionally mode units). Data units 110 typically store data (e.g., user data stored for host device 126). Access to the memory array 102 is managed by controller 120.

[0060] The controller 120 includes an encoding circuitry 112 for encoding and decoding data written to and read from the data unit 110. In one embodiment, the data is stored using ternary units 105. For example, a 3-bit combination is stored using a pair of memory units 105 according to a mapping provided by an encoding table.

[0061] In one embodiment, the encoding circuitry 112 encodes user data received from the host device 126 (e.g., data provided with a write command). Various values ​​of the user data are stored using a first encoding level. The first encoding level corresponds to the state or level of a pair of ternary units. These values ​​of the user data corresponding to a specific value (e.g., 4) may be associated with additional bits that can be stored using a second encoding level. The second encoding level corresponds to a combination of levels of ternary unit pairs to correspond to the specific value. This combination of levels of the specific value corresponds to a redundant combination of levels of ternary unit pairs, which can be combined to store the value of the additional bits.

[0062] In one embodiment, controller 120 receives a read command from host device 126. In response to receiving the read command, controller 120 reads data from multiple partitions of memory array 102 in parallel. For example, data is read from each of the partitions using a streaming mode.

[0063] In one embodiment, the encoding circuitry 112 decodes user data (e.g., data requested by a read command from the host device 126) stored in the ternary unit 105. The encoding circuitry 112 is used to decode data stored in the ternary unit 105 corresponding to the address provided with the read command. In one embodiment, the encoding circuitry 112 uses an encoding table stored in memory 118 to perform encoding / decoding.

[0064] In one example, address mapping 104 is stored in memory 118 and associates addresses in memory array 102 with physical nodes / features (e.g., word lines, gate lines, sense nodes, etc.) of memory array 102. In one example, address mapping 104 stores data indicating which data cells 110 are accessed using a common node (e.g., a common word line). Controller 120 uses this data to determine whether to use streaming mode or default mode (e.g., random mode) to access data cells 110.

[0065] The controller 120 reads data from memory cells, for example, using a common word line (not shown) of the memory array 102. The controller 120 then sends the read data to the host device 126.

[0066] In one embodiment, memory device 101 uses a reference mode to select a read voltage for performing a read operation (e.g., when operating in default / random and / or streaming modes). The mode unit typically stores various reference modes (e.g., a known all-one (1) mode). For example, two reference modes are associated with each codeword or block stored in data unit 110.

[0067] In one example, during a read operation for reading a codeword, controller 120 reads a reference pattern associated with the codeword. For instance, controller 120 counts the number of pattern cells that abruptly change during the read. Based on the number of abrupt changes, controller 120 selects a read voltage for reading the codeword. In one example, the read voltage is the current voltage applied to the pattern cell when a threshold number of cells abruptly change.

[0068] In one embodiment, when a read operation is performed, the bias circuitry system 124 applies a voltage to the mode cell. In one example, the bias circuitry system 124 includes word line and bit line drivers (not shown) to bias the word lines and bit lines of the memory array 102.

[0069] Controller 120 determines which mode cells are switched. In one instance, controller 120 determines that the number of memory cells that are switched in mode (e.g., limit or abrupt) is greater than a threshold.

[0070] Sensing circuitry 122 is used to read the mode unit and data unit 110. In one example, sensing circuitry 122 includes a sensing amplifier for sensing characteristics associated with memory cells of memory array 102. These characteristics may be, for example, voltage and / or current associated with a selected memory cell.

[0071] In one embodiment, based on the number of mode units to be switched, the controller 120 determines the initial read voltage to be used when reading from the data unit 110 associated with the mode unit (e.g., user data).

[0072] The controller 120 includes one or more processing devices 116 and a memory 118. In one example, the memory 118 stores firmware executed by the processing device 116 to select and apply read voltages.

[0073] The memory controller 120 may use the bias circuitry 124 to generate voltages for applying read and other voltages (e.g., initial read and read retries). The bias circuitry 124 may also generate voltages for applying write voltages to the data cells 110 and / or mode cells as part of a programming operation. The bias circuitry 124 may be used to generate read voltages for read operations performed on the memory array 102 (e.g., in response to a read command from the host device 126).

[0074] Sensing circuitry 122 can be used to sense the state of each memory cell in memory array 102. In one example, sensing circuitry 122 includes a sensing amplifier for detecting the current caused by applying various voltages to the memory cells in memory array 102. In one example, biasing circuitry 124 applies a read voltage to either data cell 110 or mode cell. Sensing circuitry 122 senses the current associated with each of the data cell 110 or mode cell caused by the applied read voltage.

[0075] In one instance, if the sensing circuitry 122 determines that the current for a memory cell is greater than a fixed threshold (e.g., a predetermined current level), then the memory controller 120 determines that the memory cell has been switched (e.g., abruptly switched).

[0076] In one embodiment, memory controller 120 receives a write command from host device 126. The write command is accompanied by data to be written to memory array 102 (e.g., user data of host device 126). In response to receiving the write command, controller 120 initiates a programming operation.

[0077] In one embodiment, controller 120 uses a counter to count the number of data or mode cells that abruptly change when a read voltage is applied. The data stored in the counter can be used as part of the evaluation when determining the read voltage to be applied. This stored data can optionally be used in combination with errors caused by ECC errors when reading data during the selection of a read voltage (e.g., a read retry voltage).

[0078] In one example, controller 120 may use a write voltage (e.g., a write pulse) during a write or programming operation to write logic state to a memory cell, such as data cell 110 or mode cell. The write pulse can be applied to select a memory cell by providing a first voltage to a bit line and a second voltage to a word line. Circuitry coupled to access lines that can be coupled to the memory cell may be used to provide the write voltage (e.g., access line drivers included in decoder circuitry). The circuitry may be controlled by internal control signals provided by control logic (e.g., controller 120). The resulting voltage applied to the memory cell is the difference between the first and second voltages. In some embodiments, the write pulse may be of the same duration as the read pulse. In some embodiments, the duration is 10 to 50 ns. In some embodiments, the duration is 1 to 100 ns. In some embodiments, the duration is 1 ns to 1 microsecond.

[0079] In one instance, the polarity of the read or write pulse can be either a first polarity or a second polarity. For example, a write pulse can apply a voltage to the memory cell with a first polarity (e.g., the bit line at 6 V and the word line at 0 V).

[0080] In one example, circuitry coupled to the access lines that can be coupled to the memory cell is used to provide read pulses (e.g., access line drivers included in decoder circuitry). The circuitry may be controlled by internal control signals provided by control logic (e.g., controller 120). The read voltage or pulse may be a voltage applied to the memory cell over a period of time (e.g., 10 to 50 ns, 1 to 100 ns, 1 ns to 1 microsecond). In some embodiments, the read pulse may be a square pulse. In some embodiments, the read pulse may be a ramp, i.e., a linearly increasing voltage may be applied across the memory cell.

[0081] In one instance, after being accessed (e.g., selected), a memory cell can be read or sensed by a sensing component (e.g., sensing circuitry 122) to determine the memory cell's storage state. For example, a voltage can be applied to the memory cell (using word lines and bit lines), and the presence of the resulting current can depend on the applied voltage and the memory cell's threshold voltage. In some cases, more than one voltage can be applied. Additionally, if the applied voltage does not cause current flow, other voltages can be applied until current is detected by the sensing component. By evaluating the voltage that causes current flow, the storage logic state of the memory cell can be determined. In some cases, the voltage magnitude can ramp up until current flow is detected (e.g., the memory cell is turned on, activated, conducts current, or becomes active). In other cases, predetermined voltages can be applied sequentially until current is detected. Similarly, current can be applied to the memory cell, and the magnitude of the voltage used to generate the current can depend on the memory cell's resistance or threshold voltage.

[0082] In some cases, memory cells (e.g., PCM cells) contain materials that can change their crystalline configuration (e.g., between a crystalline phase and an amorphous phase), and this change in crystalline configuration determines the threshold voltage of the memory cell used to store information. In other cases, memory cells contain materials that maintain a crystalline configuration (e.g., an amorphous phase), which can exhibit a variable threshold voltage for storing information.

[0083] The sensing component may include various transistors or amplifiers to detect and amplify signal differences. The detected logic state of the memory cell can then be output as an output through a column decoder. In some cases, the sensing component may be part of either a column decoder or a row decoder.

[0084] Figure 2 A memory array 150 is shown according to some embodiments, having memory cells accessed using a common word line 160. For example, memory cells 170 and 172 are accessed sequentially using the same common word line 160. In one example, memory cell 170 uses a first set of digital lines (not shown) for a first read operation, and then memory cell 172 uses a second set of digital lines (not shown) for a second read operation immediately following the first read operation.

[0085] Memory cells 170 and 172 are examples of data cell 110. A bias circuit system 152 biases access lines 156 to access various memory cells in the memory array 150. For example, access lines 156 include word lines (e.g., word line 160) and digital lines (not shown). The bias circuit system 152 may be similar to bias circuit system 124.

[0086] In one embodiment, during a read operation, memory cells 172 and 174 are sequentially accessed using access line 156. Sensing circuitry 154 senses the state of memory cell 172 for a first read operation and senses the state of memory cell 174 for a second read operation. Sensing node 162 is coupled to each of memory cells 172 and 174. Sensing circuitry 154 senses the state of sensing node 162 when reading memory cell 172 or 174. Sensing circuitry 154 may be similar to sensing circuitry 122.

[0087] In one embodiment, the bias circuitry 152 applies a voltage when performing a read and / or write operation. A controller (not shown) (e.g., controller 120) receives commands associated with a first and a second address, wherein the first address corresponds to a first memory cell 170 of the memory array 150 and the second address corresponds to a second memory cell 172 of the memory array 150.

[0088] The controller determines (e.g., using address mapping 104) that the first and second memory cells use at least one common node (e.g., word line 160) for access. In response to receiving a command, the bias circuitry system 152 biases at least one access line 156 for accessing the first memory cell 170 to an initial state in preparation for reading or writing to the first memory cell 170.

[0089] After biasing the access lines to their initial state, the controller reads or writes to the first memory cell 170. Following the read or write to the first memory cell 170, the biasing circuitry 152 biases the access lines to their initial state in preparation for reading or writing to the second memory cell 172. The controller then reads or writes to the second memory cell 172. In one example, the read data is sent to the host device 126.

[0090] Figure 3 Examples of memory units 402 including selection devices according to some embodiments are shown. In one example, the selection device 410 includes a chalcogenide. Memory unit 402 is an example of data unit 110.

[0091] The top electrode 408 conductively connects the selector 410 to the bit line 404, and the bottom electrode 412 conductively connects the selector 410 to the word line 406. In one example, electrodes 408 and 412 are formed of carbon material.

[0092] In one example, the selection device 410 includes a chalcogenide (e.g., a chalcogenide material and / or a chalcogenide alloy). The threshold voltage nature of the selection device may be based on the voltage polarity applied to the memory cell.

[0093] In one instance, a logic state can be written to memory cell 402, which may correspond to one or more data bits. The logic state can be read from or written to the memory cell by applying voltages of different polarities at different voltage and / or current values. The read and write protocol can utilize different threshold voltages of the selection device caused by different polarities. In other words, when the memory cell is a self-selecting memory cell implemented using a selector / memory device, the selection device 410 can serve as both a selection element and a storage element for cell 402.

[0094] Figure 4 A memory device 130 is shown, according to one embodiment, configured with a read manager 113 to access memory cells in a memory array. Memory device 130 is an example of memory device 101. Figure 4 In this context, memory device 130 includes an array 133 of memory cells (e.g., memory cell 103). Memory cell 103 is an instance of data cell 110.

[0095] In one instance, array 133 may be referred to as a chip; and a memory device (e.g., 130) may have one or more chips. Different chips may operate in parallel within the memory device (e.g., 130).

[0096] For example, Figure 4 The memory device 130 described herein may have a cross-point memory having at least an array 133 of memory cells (e.g., 103). In another example, Figure 4 The memory device 130 described herein may have a 3D vertical architecture having at least an array 133 of memory cells (e.g., 103).

[0097] In some implementations, the crosspoint memory uses a memory cell 103 having elements (e.g., a single element) that serve as both a selector device and a memory device. For example, the memory cell 103 may use a monolithic alloy with variable threshold capability. Read / write operations on this memory cell 103 can be based on limiting the memory cell 103 to simultaneously suppress other cells in a subthreshold bias, in a manner similar to read / write operations on memory cells having a first element stacked together as a selector device and a second element stacked together as a phase-change memory device. The selector device that can be used to store information may be referred to as a selector / memory device.

[0098] Figure 4 The memory device 130 includes a controller 131 that operates bit line driver 137 and word line driver 135 to access individual memory cells (e.g., 103) in the array 133.

[0099] For example, each memory cell (e.g., 103) in array 133 can be accessed via a voltage driven by a pair of bit line drivers 147 and word line drivers 145, such as Figure 5 The explanation is as follows.

[0100] Controller 131 includes a read manager 113 configured to decode user data that has been stored using two encoding levels of storage (e.g., as described above). In one instance, the user data is stored in a ternary unit 105.

[0101] In one embodiment, the read manager 113 further determines one or more read voltages for reading data units based on data obtained from patterns of applying voltage to mode units. The read manager 113 may be implemented, for example, via logic circuitry and / or microcode / instructions. For instance, during a read retry, the read manager 113 uses a read voltage having an amount greater than the read voltage previously used to read memory units (e.g., 103). The increase in read voltage may be based on reading mode units (e.g., abrupt changes in counting mode units). The read voltage with the increased amount applied to the memory unit (e.g., 103) may be sufficient to obtain error-free data from the memory unit (e.g., 103).

[0102] Figure 5 A memory cell 103 is shown according to one embodiment, having a bit line driver 147 and a word line driver 145 configured to apply a voltage (e.g., a ramp). For example, the memory cell 103 may be... Figure 4 Typical memory cell 103 in memory cell array 133.

[0103] Figure 5 The bit line driver 147 and word line driver 145 are controlled by the read manager 113 of the controller 131 to selectively apply one or more voltages to the memory cell 103. The bit line driver 147 and word line driver 145 can apply voltages of different polarities to the memory cell 103.

[0104] For example, when a voltage of a certain polarity (e.g., positive polarity) is applied, bit line driver 147 drives a positive voltage relative to ground on bit line 141 connected to a row of memory cells in array 133; and word line driver 145 drives a negative voltage relative to ground on word line 143 connected to a column of memory cells in array 133.

[0105] When a voltage of opposite polarity (e.g., negative) is applied, bit line driver 147 drives a negative voltage on bit line 141; and word line driver 145 drives a positive voltage on word line 143.

[0106] Memory cell 103 is located in both the row connected to bit line 141 and the column connected to word line 143. Therefore, memory cell 103 experiences the voltage difference between the voltage driven by bit line driver 147 on bit line 141 and the voltage driven by word line driver 145 on word line 143.

[0107] Generally, when the voltage driven by the bit line driver 147 is higher than the voltage driven by the word line driver 145, the memory cell 103 experiences a voltage of one polarity (e.g., positive polarity); and when the voltage driven by the bit line driver 147 is lower than the voltage driven by the word line driver 145, the memory cell 103 experiences a voltage of the opposite polarity (e.g., negative polarity).

[0108] In some embodiments, memory cell 103 is a self-selecting memory cell implemented using a selector / memory device. The selector / memory device has chalcogenides (e.g., chalcogenide materials and / or chalcogenide alloys). For example, the chalcogenide material may comprise a chalcogenide glass, such as (for example) an alloy of selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), and silicon (Si). The chalcogenide material may primarily comprise selenium (Se), arsenic (As), and germanium (Ge) and is referred to as a SAG alloy. The SAG alloy may comprise silicon (Si) and is referred to as a SiSAG alloy. In some embodiments, the chalcogenide glass may contain additional elements, each in atomic or molecular form, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F).

[0109] The selector / memory device has a top side and a bottom side. A top electrode is formed on the top side of the selector / memory device for connection to bit line 141; and a bottom electrode is formed on the bottom side of the selector / memory device for connection to word line 143. For example, the top and bottom electrodes may be formed of carbon material. For example, the chalcogenide material of memory cell 103 may be in the form of a crystalline atomic configuration or an amorphous atomic configuration. The threshold voltage of memory cell 103 may depend on the ratio of the crystalline material to the amorphous material in memory cell 103. The ratio may vary under various conditions (e.g., currents of different magnitudes and directions flowing through memory cell 103).

[0110] The self-selecting memory cell 103, having a selector / memory device, can be programmed to have a threshold voltage window. The threshold voltage window can be created by applying programming pulses of opposite polarity to the selector / memory device. For example, the memory cell 103 can be biased to have a positive voltage difference between the two sides of the selector / memory device, or alternatively, a negative voltage difference between the same two sides of the selector / memory device. When a positive voltage difference is considered positive polarity, a negative voltage difference is considered negative polarity. Reads can be performed with a given / fixed polarity. When programmed, the memory cell has a low threshold (e.g., lower than a reset cell or a cell programmed to have a high threshold), such that during a read operation, the read voltage can cause the programmed cell to abruptly change and thus become conductive, while the reset cell remains non-conductive.

[0111] For example, to program the voltage threshold of memory cell 103, bit line driver 147 and word line driver 145 can drive voltage pulses to memory cell 103 with a polarity (e.g., positive) to cause a sudden change in memory cell 103, making memory cell 103 conductive. When memory cell 103 is conductive, bit line driver 147 and word line driver 145 continue to drive programming pulses to change the threshold voltage of memory cell 103 toward the voltage region representing the data or bit value stored in memory cell 103.

[0112] In one embodiment, controller 131 may be configured in an integrated circuit having multiple layers of memory cells. Each layer may be sandwiched between a layer of bit lines and a layer of word lines; and the memory cells in a layer may be arranged in an array 133. A layer may have one or more arrays or slabs. Memory cells in adjacent layers may share a layer of bit lines (e.g., 141) or a layer of word lines (e.g., 143). Bit lines are arranged to run parallel in one direction within their layer; and word lines are arranged to run parallel in another direction orthogonal to the bit lines within their layer. Each of the bit lines is connected to a row of memory cells in the array; and each of the word lines is connected to a column of memory cells in the array. Bit line driver 137 is connected to the bit lines in the layer; and word line driver 135 is connected to the word lines in the layer. Thus, a typical memory cell 103 is connected to both bit line driver 147 and word line driver 145.

[0113] In one embodiment, the threshold voltage of a typical memory cell 103 is configured high enough that the magnitude of the voltage applied across the memory cell 103 is insufficient to cause the memory cell 103 to become conductive when only one of its bit line drivers 147 and word line drivers 145 is driven with a voltage of either polarity while the other voltage driver keeps the corresponding line grounded. Therefore, addressing the memory cell 103 can be performed by operating / selecting the memory cell 103 via both its bit line drivers 147 and word line drivers 145 with driving voltages of opposite polarity relative to ground. Other memory cells connected to the same word line driver 145 can be deselected by keeping the corresponding bit line grounded by their respective bit line drivers; and other memory cells connected to the same bit line driver can be deselected by keeping the corresponding word line grounded by their respective word line drivers.

[0114] A group of memory cells (e.g., 103) connected to a common word line driver 145 can be selected to operate in parallel with their respective word line drivers (e.g., 147) at a voltage level of one polarity while the word line driver 145 is also at a voltage level of the opposite polarity. Similarly, a group of memory cells connected to a common bit line driver 147 can be selected to operate in parallel with their respective word drivers (e.g., 145) at a driving voltage of one polarity while the bit line driver 147 is also at a driving voltage of the opposite polarity.

[0115] At least some examples are disclosed herein with reference to crosspoint memory having self-selecting memory cells. Other types of memory cells and / or memories may also be used. For example, memory cells and / or flash memory cells each having a selector device and a phase-change memory device may also be used in at least some embodiments. Additionally or alternatively, the memory may have a different architecture, such as a 3D vertical architecture.

[0116] Figure 6 Exemplary normal quantile (NQ) plots are shown to represent the statistical distribution of threshold voltages of memory cells (e.g., 171, 173, 182, 184). In one example, the memory cell is data cell 110. When the probability distribution of threshold voltages programmed into a region (e.g., 171) is a normal distribution (also known as a Gaussian distribution), its normal quantile (NQ) plot is considered to be a straight line (e.g., distribution 171).

[0117] The self-selectable memory cell (e.g., 103) may have a threshold voltage of negative polarity and a threshold voltage of positive polarity. When the magnitude of the voltage applied to the memory cell 103 with either polarity increases to the threshold voltage of the corresponding polarity, the memory cell (e.g., 103) switches (e.g., abruptly) from a non-conductive state to a conductive state.

[0118] The threshold voltage for the negative polarity of memory cell 103 and the threshold voltage for the positive polarity of memory cell 103 may have different values. A memory cell programmed to have a large value of positive threshold voltage may have a small value of negative threshold voltage; and a memory cell programmed to have a small value of positive threshold voltage may have a large value of negative threshold voltage.

[0119] For example, a memory cell may be programmed to represent a value (e.g., 1) based on a small positive threshold voltage of distribution 184; and therefore, its threshold voltage may represent the same value (e.g., 1) based on a large negative value of distribution 173. Alternatively, a memory cell may be programmed to represent another value (e.g., 0) based on a large positive threshold voltage of distribution 182; and therefore, its threshold voltage may represent the same value (e.g., 0) based on a smaller negative value of distribution 171.

[0120] Therefore, to determine whether memory cell 103 stores a value (e.g., 1) or another value (e.g., 0), read manager 113 can read memory cell 103 with positive or negative polarity. If the threshold voltage of memory cell 103 has a large number of positive values ​​according to distribution 182, then it stores another value (e.g., 0); otherwise, it stores a value (e.g., 1). Similarly, if the threshold voltage of memory cell 103 has a large number of negative values ​​according to distribution 173, then it stores a value (e.g., 1); otherwise, it stores another value (e.g., 0).

[0121] The threshold voltage distribution of a memory cell can change after a read. For example, in positive polarity, a read can cause the high-value distribution 182 to shift down and / or cause the low-value distribution 184 to shift down.

[0122] Similarly, in negative polarity, reading can cause the high magnitude distribution 173 to shift down and / or cause the low magnitude distribution 171 to shift down.

[0123] Figure 7 Exemplary three-dimensional memory array structures with word lines configured in a comb-like structure are shown according to some embodiments. The memory arrays and memory cells described herein are not limited to use in planar architectures (e.g., where cells are located at the intersections of word lines (WL) and bit lines (BL) at different levels). Alternatively, the method can also be used in vertical architectures (e.g., where vertical BL pillars intersect with horizontal WL planes).

[0124] Examples of vertical architectures that can be used in conjunction with the embodiments described in this disclosure are in Figure 7 The description continues. As described, the memory array includes memory cells 1102 and 1103. Each memory cell 1102 and 1103 can be selected using word lines (e.g., 1106, 1107, or 1108) and digital lines (e.g., 1110). Memory cells 1102 and 1103 are... Figure 1 An instance of data unit 110.

[0125] In one embodiment, each word line extends in one of a plurality of horizontal planes of word lines 1106, 1107, 1108 that are vertically stacked above a semiconductor substrate (not shown). Each digital line or bit line (e.g., 1110) includes a pillar 1104. Each pillar 1104 extends vertically away from the semiconductor substrate. Each memory cell 1102, 1103 is located on the side of one of the pillars 1104.

[0126] In one embodiment, the memory array has a vertical array architecture comprising vertical bit lines (e.g., vertical struts 1104) or digital lines intersecting multiple horizontal layers of word lines (e.g., even-number lines 1106 and odd-number lines 1107). Each layer is configured with two forked word line combs, such that each bit line or digital line forms two cells 1102, 1103 at each location within the layer. In one example, even-number lines 1106 and odd-number lines 1107 are forked into a comb-like structure, as illustrated.

[0127] Figure 8 An encoding table is shown according to some embodiments for storing data using a pair of ternary units (e.g., unit A and unit B). Unit A stores data in one of three data states or levels 802. Unit B stores data in one of three data states or levels 804. Units A and B are examples of ternary unit 105. In one example, controller 120 programs each of the memory unit pair as one of three levels.

[0128] Memory cells are used to store 3-bit combinations. Each 3-bit combination corresponds to one of eight decimal values ​​806 (e.g., 0, 1, 2, 3, 4, 5, 6, 7). For example, the decimal value 2 is stored by the level combination L1 / L2.

[0129] One of the decimal values ​​is chosen as the special value for implementing the two-level encoding. In one instance, the special value is chosen as 4. Level combination 810 is a redundant level combination. The encoding table represents the single-level encoding of values ​​other than the special value.

[0130] For special values, either combination 810 or combination 812 can be used to store this data. For example, an extra bit can be stored, the value of which is represented by one of combination 810 or 812 programmed into the memory cell. Therefore, when storing user data corresponding to a special value, a total of 4 bits (e.g., 3 bits representing the value 4 plus 1 extra bit) can be stored, instead of the total of 3 bits stored as for other values ​​of user data.

[0131] In other embodiments, different decimal values ​​(e.g., 3 or 7) may be selected as special values. Furthermore, the encoding table may use a combination of levels from more than two memory cells. Additionally and / or alternatively, more than three levels may be used in the memory cells.

[0132] In one example, the encoding / decoding table uses 2 units and 3 levels (9 combinations) to encode 3 bits (2 3=8 different combinations). Redundancy level combination 810 is not used to store these 8 different combinations (there are no corresponding coded combinations). However, the decoded value corresponding to a specific value is associated with this redundancy level combination. It should be noted that choosing a base value equal to the adjacent cell value (e.g., 4) can reduce errors in error-prone situations. For example, cell content drift can be preserved by 3 base bits.

[0133] In one instance, during encoding / decoding by the encoding circuit system 112, the combined value of the extra bits is selected as L0L0 or L0L1.

[0134] In one embodiment, codewords in user data can be balanced to ensure a fixed bit distribution.

[0135] Figure 9 An encoding table for storing data using an encoding level is shown according to some embodiments. Units A and B are programmed as illustrated to various level combinations to store decimal values ​​corresponding to 3-bit combinations. These decimal values ​​are... Figure 9 The letter "X" usually indicates the position. Therefore, generally, each position in the encoding table stores a 3-bit combination.

[0136] In the case of special value 4, unit A is programmed as level L0. Unit B is programmed as level L0 at encoding table position 902 or as level L1 at encoding table position 904. At this first encoding level, programming as level L0 or L1 indicates storing the special value 4 from user data.

[0137] In other embodiments, the encoding table positions can be varied arbitrarily as needed. It is not required that the special value position 904 and the redundancy level combination position 902 be adjacent in the table. In one instance, the special value (position 902) may also be in different positions (not L0L0).

[0138] In one instance, if controller 120 identifies a special value 4 in the user data, then controller 120 may selectively determine whether to store the extra bits associated with the special value 4.

[0139] Figure 10 An encoding table is shown according to some embodiments for storing data corresponding to defined or special values ​​using two encoding levels. Specifically, the encoding table shows the encoding of additional bits stored in association with a special value already identified in the data to be stored. For example, the encoding table provides the encoding of the additional bits corresponding to the special value 4 at position 902 or 904. The stored binary value of the additional bits is indicated by programming unit B as level L0 at position 1002 or level L1 at position 1004. Thus, four bits corresponding to the special value can be stored. The value of a 3-bit combination is represented by the first encoding level, such as... Figure 9 The value of the fourth bit is represented by the second coding level, as shown in the image. Figure 10 It is displayed in the middle.

[0140] Figure 11 This demonstrates encoding a data stream according to some embodiments to store additional bits using two encoding levels. The data stream contains a basic payload 1130 to be stored in a memory array. In one example, the basic payload 1130 is user data received from a host device 126.

[0141] The data stream contains various values, such as 1133. The locations of special values ​​in the data stream are identified (e.g., by the controller). For example, locations 1134, 1136, 1138, and 1140 correspond to the special value 4. The controller can determine which of these locations to store an extra bit. The extra bit is stored by encoding a second-level combination of a pair of ternary units at each location.

[0142] For example, extra bit 1150 has a value of 0. The controller confirms the use of level combination 1160 to program a pair of ternary units.

[0143] For example, extra bit 1152 has the value 1. The controller confirms changing level combination 1162 to level combination 1164 to represent the stored value 1.

[0144] The method described above can be used for each additional bit to be stored in association with a special value identified in the basic payload 1130. In this way, an additional payload 1132 can also be stored in addition to the basic payload 1130.

[0145] In one instance, all positions of the special value "4" in the user data are identified. An extra bit is associated with each special value. If the extra bit is "0", then the original position is preserved: "4" & 0. L0L1. If the extra bit is "1", then choose the substitution position: "4" & 1 L0L0.

[0146] In one embodiment, the amount of data in the extra payload 1132 depends on the number of special values ​​in the user data. In some cases, the controller may guarantee the presence of several of these special values ​​within the user data (e.g., a page). Otherwise, the extra bits may vary from 0 to 33% (e.g., randomly) (in the case of 3 / 2 encoding).

[0147] The number or extent of special values ​​in user data can be adjusted using various techniques. In one instance, data balancing can be used. In one instance, perfect balancing of special values ​​guarantees a fixed and predetermined amount of additional payload (1132).

[0148] Alternatively, the controller can scan the coded values ​​and select a distribution of the number of targets that guarantees specific values.

[0149] In some embodiments, the controller may also use user data imbalance to change the distribution (e.g., for some memory technologies, it may be desirable to reduce the number of cells in the critical level value).

[0150] In one instance, because the amount of extra payload data depends on the number of special values ​​(e.g., 4), perfectly balanced messages allow the controller to predict the extra payload from the outset.

[0151] In one embodiment, if the additional payload is a variable, then the controller can manage this variability.

[0152] In some cases, fixed additional payload can be easier to implement and more reliable. Fixed-weight codewords are a more general case of balanced codewords. For example, consider a three-state technique with states A, B, and C. A balanced codeword has 33% of its bits in state A, 33% in state B, and 33% in state C. A fixed-weight codeword has 40% of its bits in state A, 40% in state B, and 20% in state C. In some cases, this approach is convenient in terms of additional bits, and it also allows the controller to know the additional payload from the outset without requiring additional bits.

[0153] In one instance, the number of 1s and 0s in the codeword is unknown. The controller can add combinations of 1s and / or 0s to balance the distribution of each bit in the codeword. In one instance, the state of bits in the codeword can be toggled. This toggling can be tracked using additional bits.

[0154] In one embodiment, a balancing algorithm used by the controller can adjust user data so that the data to be stored has a specific value that increases in quantity or number. This allows for better use of additional payload.

[0155] In some cases, user data may contain all 0s or all 1s in the codeword. Memory devices (such as NAND devices) may implement codeword scrambling to avoid having all 0s or all 1s in the codeword.

[0156] In one embodiment, the controller implements an algorithm to guarantee or ensure the statistical proportions of special values ​​and codewords. This contrasts with the use of a fixed method.

[0157] In some embodiments, the controller may define special values ​​to use a specific distribution of data states in the memory cells. For example, the proportion of a particular data state can be increased by defining special values. These special values ​​can be dynamically selected by the controller during operation. For example, after scanning user data, the controller may select the special values ​​to be used for encoding that data.

[0158] In one embodiment, the encoding scheme maps multiple data bits (e.g., 3 data bits) to 2 ternary units (e.g., denoted as unit i and unit j). For ease of reference, the 3 data bits are represented as x, y, and z. The x bit can be in the most significant bit position, the y bit can be in the middle bit position, and the z bit can be in the least significant bit position. Using the encoding scheme allows the memory device to reduce the number of ternary units in state A (relative to states B and C). Using the encoding scheme allows the memory device to reduce the number of ternary units in state B (relative to states A and C). And using the encoding scheme allows the memory device to reduce the number of ternary units in state C (relative to states A and B).

[0159] The memory device can receive a sequence of data bits for storage in a cell array (e.g., a ternary cell array). The memory device can logically or physically divide the data bits into combinations of (x, y, z) bits for use according to an encoding scheme (e.g., ...). Figure 8 The encoding table is used to map data bits to corresponding ternary unit pairs. In other words, the memory device can assign data bits to groups of x, y, and z bits. Each combination of (x, y, z) bits can be mapped to a pair of corresponding ternary unit states based on the encoding scheme. For example, if (x0, y0, z0) = (1, 1, 1), then the combination (x0, y0, z0) can be mapped to state A (unit j) and state B (unit i).

[0160] In one embodiment, the memory device may divide a data sequence into two groups of data bits. In this case, the data sequence may be divided into a first group of data bits consisting of x bits and a second group of data bits consisting of y bits and z bits.

[0161] After dividing the data sequence into bit groups, the memory device can generate a codeword from the x bit group. For example, the memory device can generate a parity bit (denoted as p) based on the x bit group (e.g., via ECC encoding) and can combine the parity bit and the x bit group into a codeword (e.g., codeword (x)).

[0162] After generating the codeword (x), the memory device can balance the codeword (x) in the binary domain to achieve a target distribution of ternary units in state B (linked to the x bits). For example, the memory device can (e.g., using Knuth or quantized Knuth balancing) invert one or more of the x bits in the codeword (x) to achieve a target distribution of logic values ​​(e.g., 50% 1, 50% 0) associated with the overall target distribution of state B in the data sequence (e.g., 25% state B). After the balancing process, the codeword (x) may contain one or more inverted x bits (denoted as x') and / or one or more inverted parity bits (denoted as p').

[0163] In one embodiment, a fixed-weight codeword may refer to a codeword associated with a fixed distribution of programmable states. In other words, a fixed-weight codeword may be a codeword that, when stored in ternary units, results in a fixed (e.g., set) number of ternary units in each state. The weight of the codeword may refer to the distribution of programmable states associated with the codeword. To properly weight the codewords (this may be called a balanced codeword), the memory device may map the bits in the codeword to blocks and employ a balancing process in which the blocks are inverted (e.g., one at a time) until a weighting is achieved (e.g., until the codeword is balanced). To ensure that the original logic value of the balanced codeword can be accurately recovered during subsequent read operations, the memory device may explicitly or implicitly store balance information bits indicating which blocks of data were inverted during the balancing process. During a read operation, the memory device may reference the balance information bits such that the memory device can un-invert the correct blocks of bits (e.g., bits inverted during the balancing process) before the data bits from the codeword are returned to the requesting device.

[0164] Balancing codewords before storage allows the memory device (e.g., using controller 120) to implement various techniques to improve the operation of the memory device. The memory device can receive a set of data bits for storage in a ternary cell array. The memory device can divide the data bits (e.g., logically or physically) into subsets of (x, y, z) bits for use according to an encoding scheme (e.g., ... Figures 9 to 10 The encoding table is stored in corresponding ternary unit pairs. In other words, the memory device can assign data bits to groups of x, y, and z bits. If the number of x bits differs from the number of y bits (or z bits) (e.g., the difference allows the memory device to minimize the number of ternary units used to store codewords), the memory device can divide the data bits into subsets of (x, y, z) bits and subsets of (y, z) bits (e.g., if there are more y and z bits than x bits) or the memory device can divide the data bits into subsets of (x, y, z) bits and subsets of (x) bits (e.g., if there are more x bits than y and z bits).

[0165] The memory device can form a first sub-message containing a subset of x bits and a second sub-message containing subsets of y and z bits. Forming a sub-message can refer to transmitting the data bits of the sub-message to the ECC encoder for ECC encoding.

[0166] The memory device can generate a first codeword (e.g., codeword (x)) from a first sub-message and a second codeword (e.g., codeword (y, z)) from a second sub-message. The memory device can generate the codeword (x) by encoding the first sub-message with ECC codes (this may include applying ECC codes to x bits of the first sub-message). The codeword (x) may include x bits from a subset and parity bits based on the x bits (denoted as (p(x))).

[0167] The memory device can generate a codeword (y, z) by encoding the second sub-message with ECC code (this may include applying the ECC code to the (y, z) bits of the second sub-message). The codeword (y) may contain (y, z) bits and a parity bit based on the (y, z) bits (denoted as p(y, z)).

[0168] In one embodiment, the memory device may perform a balancing process in which the memory device balances codeword (x) and codeword (y, z). The memory device may balance codeword (x) by inverting one or more blocks of codeword (x). Inverting blocks may refer to inverting the bits of a block (e.g., changing logic 0 to logic 1, and vice versa). The memory device may balance codeword (x) based on an encoding scheme and a target distribution of codeword (x). After inversion, codeword (x) may contain one or more inverted x bits and a parity bit. The memory device may invert the blocks of codeword (x) to achieve a target distribution of states. For example, the memory device may invert the blocks of codeword (x) such that 50% of the bits in codeword (x) are logic 1. Therefore, after the inversion process, 50% of the states associated with codeword (x) may be state A, 25% may be state B, and 25% may be state C (due to the encoding scheme). Therefore, the memory device can invert a portion of the codeword (x) so that the codeword (x) has a fixed weight.

[0169] A memory device can balance a codeword (y, z) by inverting one or more blocks of the codeword (y, z). The memory device can balance the codeword (y, z) based on an encoding scheme and a target distribution of the codeword (y, z). After inversion, the codeword (y, z) may contain one or more inverted y bits, z bits, and parity bits. The memory device can invert the blocks of the codeword (y, z) to achieve a target distribution of states. For example, the memory device can invert the blocks of the codeword (y, z) such that 50% of the states associated with the codeword (y, z) are state B and 50% of the states are state C. Therefore, the memory device can invert a portion of the codeword (y, z) to give the codeword (y, z) a fixed weight.

[0170] After the balanced codeword, the memory device can store the balanced codeword in a ternary cell array (e.g., Figure 1 In the memory array 102). For example, the memory device can store codewords (x) and codewords (y, z) in a set of ternary units according to an encoding scheme. Thus, in one instance, 25% of the ternary units can be in state A, 37.5% of the ternary units can be in state B, and 37.5% of the ternary units can be in state C.

[0171] In some instances, the memory device may add one or more padding bits to a codeword to achieve a target distribution. For example, if less than 50% of the states associated with a codeword (x) are state A, the memory device may add an appropriate number of padding bits set to logic 1 to resolve the difference between the target number of states A and the actual number of states A. The memory device may additionally or alternatively add padding bits to a codeword (y, z) to ensure that the codeword (y, z) is associated with a target number of states B (e.g., equal to 37.5% of the total states). A codeword with a target distribution of states can be said to be precisely weighted, and a codeword without a target distribution (but within a threshold of the target distribution) can be said to be inaccurately weighted. The ability of a memory device to precisely weight codewords using only balancing can be related to the block size used for the codeword, where a smaller block size achieves higher precision relative to a larger block size.

[0172] In some instances, memory devices can optimize or improve the storage process by selecting the number of x, y, and z bits, thereby minimizing or reducing the number of ternary units used to store codewords. For ease of reference, the number of x bits can be referred to as D. X (or the payload of the codeword (x)) and the total number of y bits and z bits can be called D. YZ (or the payload of the codeword (y, z)). Additionally, the total number of parity bits in the codeword (x) can be called P. X Furthermore, the total number of parity bits in the codeword (y, z) can be called P. YZ P X and P YZ The total payload (e.g., D) of codewords (x) and (y, z) can be determined. X +D YZ ), ECC protection level, or both. To reduce the number of ternary units used to store codewords, the memory device may select D... X and D YZ This makes the number of ternary units used to store the codeword (x) (called Q) X The number of ternary units used to store the codeword (y, z) is equal to the number of units (called Q). YZ ).

[0173] In one embodiment, the memory device can balance the codeword (x, y, z) by inverting one or more blocks of the codeword (x, y, z). The memory device can balance the codeword (x, y, z) based on an encoding scheme and a target distribution of the codeword (x, y, z). After inversion, the codeword (x, y, z) may contain one or more inverted x bits, y bits, z bits, and parity bits. The memory device can invert the blocks of the codeword (x, y, z) to achieve the target distribution of states. For example, the memory device can invert the blocks of the codeword (x, y, z) such that 25% of the states associated with the codeword (x) are state A, 37.5% are state B, and 37.5% are state C. Therefore, the memory device can invert a portion of the codeword (x, y, z) such that the codeword (x, y, z) has a fixed weight.

[0174] After the balanced codeword (x, y, z), the memory device can store the balanced codeword in an array of ternary cells. For example, the memory device can store the codeword (x, y, z) in a set of ternary cells according to the encoding scheme. Thus, in one instance, 25% of the ternary cells can be in state A, 37.5% of the ternary cells can be in state B, and 37.5% of the ternary cells can be in state C.

[0175] Figure 12 The diagram illustrates scanning a data stream according to some embodiments to identify special values ​​used to store additional bits using two coding levels. User data stream 1202 is scanned to identify all special values ​​in the user data. Bit combination 1204 (100) is identified as corresponding to special value 4. The controller appends additional bit 1206 (0) to bit combination 1204 and uses level combination 1210 (L0L1) to store all 4 bits. Thus, the 4 bits are stored using two coding levels.

[0176] Bit combination 1208 (110) does not correspond to a special value. Therefore, the controller stores the value corresponding to this bit combination only based on the first coding level. The value is stored as level combination 1212 (L0L2).

[0177] Similar methods are used to identify other special values ​​in user data stream 1202, as described above.

[0178] In one instance, all positions of the special value "4" in the user data are identified. An extra bit is added to each special value. If the extra bit is "0", then the original position is preserved: "4" & 0. L0L1. If the extra bit is "1", then choose the substitution position: "4" & 1 L0L0.

[0179] Figure 13 This demonstrates an exemplary improvement in storage density for memory cells with various levels per cell by using two coding levels to store additional bits, according to some embodiments. Column 1302 indicates the number of levels per cell used for storing data. Column 1304 indicates the maximum theoretical storage density using memory cells of the indicated type.

[0180] Column 1306 indicates the number of bits stored per unit. For example, a 3-bit combination is stored using 2 units. Column 1308 indicates the storage density implemented using only a single coding level. For example, using 2 ternary units to store a 3-bit combination achieves a density of 1.5 bits per unit.

[0181] Column 1310 indicates the storage density achieved using two coding levels for the special values ​​described herein. For example, a density of 1.5625 bits per unit can be achieved when using a pair of ternary units and two coding levels. Column 1312 indicates the percentage improvement in storage density achieved using two coding levels for special values ​​compared to using only one coding level.

[0182] In one instance, storage density can be increased by adding more bits per page of data. In another instance, storage density can be increased by using fewer memory cells for a given number of bits.

[0183] Figure 14 This demonstrates an exemplary improvement in the storage density of ternary cells by using two additional bits stored at the encoding level, according to some embodiments. Column 1402 indicates the number of bits stored per cell. For example, a 3-bit combination is stored using 2 cells. For example, an 11-bit combination is stored using 7 cells. The other columns indicate the same information as described above. Figure 13 Similar data to the column.

[0184] Figure 15 This document demonstrates a method for storing user data using ternary unit pairs, according to some embodiments. For example, Figure 15 The method can be implemented in Figures 1 to 2 In the system.

[0185] Figure 15 The method can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, special-purpose logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executing on the processing device), or a combination thereof. In some embodiments, Figure 15 The method comprises at least part of one or more processing devices (e.g. Figure 1 The controller 120) executes.

[0186] Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0187] In block 1501, scanning the user data received from the host device is part of the write operation. For example, the host device sends a write command to the memory device to store the user data. In one example, controller 120 receives user data from host device 126.

[0188] In box 1503, the distribution of user data is modified based on the results from the scan. For example, the distribution of 1s and 0s in the user data is changed.

[0189] In box 1505, ternary cell pairs are used to store the special values ​​and extra bits of user data. The special values ​​are stored using a first coding level, and the extra bits are stored using a second coding level. The extra bits correspond to the special values. In one instance, the extra bits are added to the special value. In another instance, the extra bits are associated with the special value. In yet another instance, the special values ​​and extra bits are stored using... Figures 9 to 10 It uses an encoding table to store the data.

[0190] In box 1507, ternary cell pairs are used to store the remaining user data that does not contain special values. The remaining user data is stored using only the first coding level.

[0191] In block 1509, the aforementioned stored user data is decoded in response to receiving a read command from the host device. Decoding is performed using encoding tables corresponding to the first and second encoding levels used for storing user data described above. In one example, encoding and decoding are performed by encoding circuitry system 112.

[0192] In some aspects, the technology described herein relates to a device comprising: a memory array including ternary units (e.g., 105); and at least one controller configured to store data in the ternary units, wherein data corresponding to a defined value (e.g., a specific value 4) uses two encoding levels (e.g., ...). Figures 9 to 10 The encoding table is used to store the data, and the remaining data (e.g., values ​​0, 1, 2, 3, 5, 6, 7) is stored using a different encoding level (e.g., a specific encoding table). Figure 8 ).

[0193] In some respects, the techniques described herein relate to a device in which data comprises bit combinations (e.g., binary values ​​represented by 3 bits), the bit combinations corresponding to defined values ​​are stored using two encoding levels, and the other remaining bit combinations are stored using one encoding level.

[0194] In some aspects, the technology described herein relates to a device in which a controller (e.g., 120) is further configured to receive data from a host device (e.g., 126) as part of a write operation requested by the host device.

[0195] In some respects, the techniques described herein relate to a device in which a controller is further configured to select defined values ​​based on the characteristics of the data. In one instance, the characteristics of the data are the distribution of 1s and 0s in the data.

[0196] In some respects, the techniques described herein relate to a device in which data comprises bit combinations, and each bit combination is stored using a pair of ternary units.

[0197] In some respects, the techniques described herein relate to a device in which the first bit combination of data corresponds to a defined value and is stored in first and second ternary units, and the state of each of the first and second ternary units is programmed by a controller based on additional bits to be stored.

[0198] In some respects, the techniques described herein relate to a device in which an additional bit is associated with a combination of the first bit.

[0199] In some aspects, the techniques described herein relate to a device in which a controller is further configured to determine that data contains a first combination representing a defined value, and in response to determining that the data contains the first combination, to apply a second coding level to encode additional bits.

[0200] In some aspects, the techniques described herein relate to a device in which the first bit combination is stored using first and second ternary units, and a second encoding level is applied that includes selecting a first or second state (e.g., state L0 or L1 of cell B) of a first ternary unit of a memory array based on a value represented by an additional bit (e.g., 0 or 1). In one embodiment, the state of a second ternary unit or even both ternary units may be selected.

[0201] In some aspects, the techniques described herein relate to a device in which, for either a first or second state of a first ternary unit, the programmed state of a second ternary unit when storing the first bit combination (e.g., state L0 of unit A) is the same. In one embodiment, both units A and B can be modified by additional bits (it is not necessary for only the first unit to be modified by additional bits).

[0202] In some aspects, the techniques described herein relate to a device in which a controller is further configured to store data using an encoding table that maps multiple data bits in the data to programmable states of ternary unit pairs (e.g., three data bits representing the value 7 are mapped to unit A programmed to state L2 and unit B programmed to state L0).

[0203] In some aspects, the techniques described herein relate to a device in which an encoding table contains combinations of programmable states (e.g., L2 / L0, L1 / L1), and one of the combinations is a redundant combination corresponding to a defined value (e.g., L0 / L0).

[0204] In some aspects, the techniques described herein relate to a method comprising: identifying the location of a particular value in user data; and associating a corresponding additional bit with each identified location.

[0205] In some aspects, the techniques described herein relate to a method that further includes using a first coding level to store user data at an identified location and using a second coding level to store corresponding additional bits.

[0206] In some respects, the techniques described herein involve a method that further comprises, for each additional bit, programming the state of a pair of corresponding ternary units based on the value of the additional bit.

[0207] In some aspects, the techniques described herein relate to a method in which each particular value corresponds to a corresponding bit combination (e.g., 3 bits in a serial data stream), and associating a corresponding additional bit involves adding an additional bit to the bit combination (e.g., adding bit 0 to bit 100 in a user data stream before encoding the data for storage using a pair of ternary units).

[0208] In some respects, the techniques described herein relate to a method that further includes using a pair of ternary units to store each bit combination and corresponding additional bits.

[0209] In some aspects, the techniques described herein involve a method in which user data is a basic payload (e.g., 1130) and additional bits are additional payloads (e.g., 1132).

[0210] In some aspects, the techniques described herein relate to a system comprising: at least one processing means; and at least one memory containing instructions configured to instruct the at least one processing means to: adjust the proportion of special values ​​in data; and use ternary unit pairs to store each special value and corresponding extra bits.

[0211] In some respects, the techniques described herein relate to a system in which adjusting the scaling comprises balancing codewords in data to alter the distribution of at least one programmed state of a ternary unit.

[0212] In some aspects, the techniques described herein relate to a system in which the processing means is further configured to: scan data; change the distribution of the data (e.g., the number of 0s and 1s in the data) based on the scan; and after changing the distribution, encode the data for storage in a ternary unit.

[0213] In some respects, the techniques described herein relate to a system in which the adjustment of the scale involves targeting the number of specific values ​​in the data.

[0214] In some respects, the techniques described herein relate to a system in which data is the base payload and the scaling factor is targeted at the amount of additional payload. In one instance, the amount of additional payload is the number of bits.

[0215] This disclosure includes various apparatuses for performing the above methods and implementing the above systems, including a data processing system for performing these methods and a computer-readable medium containing instructions that, when executed on the data processing system, cause the system to perform these methods.

[0216] The descriptions and figures are illustrative and should not be construed as limiting. Numerous specific details are described to provide a thorough understanding. However, in certain examples, well-known or common details have not been described to avoid obscuring the description. References to one or more embodiments in this disclosure do not necessarily refer to the same embodiment; and such references imply at least one.

[0217] As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediary component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0218] In this specification, references to "an embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. The appearance of the phrase "in an embodiment" in various places in the specification does not necessarily refer to all of the same embodiment, nor is it a single or alternative embodiment mutually exclusive with other embodiments. Furthermore, various features may be exhibited by some embodiments but not others. Similarly, various requirements may be described for some embodiments but not others.

[0219] In this description, various functions and / or operations may be described as being executed or caused by software code for the sake of simplicity. However, those skilled in the art will recognize that such expressions mean that functions and / or operations are caused by the execution of code by one or more processing devices, such as microprocessors, application-specific integrated circuits (ASICs), graphics processors, and / or field-programmable gate arrays (FPGAs). Alternatively or in combination, functions and operations may be implemented using dedicated circuit systems (e.g., logic circuit systems) with or without software instructions. Embodiments may be implemented using hardwired circuit systems with or without software instructions. Therefore, the technology is neither limited to any particular combination of hardware circuit systems and software, nor to any particular source of instructions executed by a computing device.

[0220] While some embodiments may be implemented in full-featured computers and computer systems, various embodiments can be distributed as computing products in various forms and can be applied regardless of the particular type of computer-readable medium that actually causes the distribution.

[0221] At least some of the disclosed aspects may be embodied, at least in part, in software. That is, the technology may be implemented in a computing device or other system in response to its processing device (e.g., a microprocessor) executing a sequence of instructions contained in memory (e.g., ROM, volatile RAM, non-volatile memory, cache, or remote storage device).

[0222] The routines executed to implement the embodiments can be implemented as part of an operating system, middleware, service delivery platform, SDK (Software Development Kit) component, network service, or other specific application, component, program, object, module, or sequence of instructions (sometimes referred to as a "computer program"). The calling interfaces of these routines can be exposed to the software development community as APIs (Application Programming Interfaces). A computer program typically includes one or more instructions that are set at various times in various memories and storage devices in a computer and, when read and executed by one or more processors in the computer, cause the computer to perform operations required to implement the elements involving various aspects.

[0223] Computer-readable media can be used to store software and data that, when executed by a computing device, cause the device to perform various methods. Executable software and data can be stored in various locations, including, for example, ROM, volatile RAM, non-volatile memory, and / or cache. Parts of this software and / or data can be stored in any of these storage devices. Furthermore, data and instructions can be obtained from a centralized server or a peer-to-peer network. Different portions of the data and instructions can be obtained at different times and in different communication sessions or in the same communication session from different centralized servers and / or peer-to-peer networks. Data and instructions can be fully obtained before the application is executed. Alternatively, portions of the data and instructions can be dynamically obtained in a timely manner when execution is required. Therefore, data and instructions do not need to be fully present on the computer-readable media at any given time.

[0224] Examples of computer-readable media include, but are not limited to, recordable and non-recordable media (e.g., volatile and non-volatile memory devices), read-only memory (ROM), random access memory (RAM), flash memory devices, solid-state drive storage media, removable disks, disk storage media, optical storage media (e.g., optical disc read-only memory (CD-ROM), digital versatile disk (DVD), etc.), and others. Computer-readable media can store instructions. Other examples of computer-readable media include, but are not limited to, non-volatile embedded devices using NOR flash or NAND flash architectures. Media used in these architectures may include unmanaged NAND devices and / or managed NAND devices, including, for example, eMMC, SD, CF, UFS, and SSD.

[0225] Generally, non-transitory computer-readable media includes any means of providing (e.g., storing) information in a form accessible by computing devices (e.g., computers, mobile devices, network devices, personal digital assistants, manufacturing tools with controllers, any device having one or more processors, etc.). As used herein, “computer-readable media” may include a single medium or multiple media (e.g., storing one or more sets of instructions).

[0226] In various embodiments, the hardwired circuit system can be combined with software and firmware instructions to implement the technology. Therefore, the technology is neither limited to any particular combination of hardware circuit systems and software, nor to any particular source of instructions executed by a computing device.

[0227] The various embodiments described herein can be implemented using a variety of different types of computing devices. As used herein, examples of "computing device" include, but are not limited to, servers, centralized computing platforms, systems with multiple computing processors and / or components, mobile devices, user terminals, vehicles, personal communication devices, wearable digital devices, electronic kiosks, general-purpose computers, electronic document readers, tablets, laptops, smartphones, digital cameras, home appliances, televisions, or digital music players. Additional examples of computing devices include devices that are part of the so-called "Internet of Things" (IoT). Such "things" may occasionally interact with their owners or administrators who can monitor or modify the settings of these things. In some cases, these owners or administrators act as users regarding the "thing" device. In some instances, a user's primary mobile device (e.g., an iPhone) may act as an administrator server regarding paired "thing" devices worn by the user (e.g., Apple Watches).

[0228] In some embodiments, the computing device may be a computer or a host system, implemented as, for example, a desktop computer, a laptop computer, a web server, a mobile device, or other computing device including memory and processing means. The host system may include or be coupled to a memory subsystem, such that the host system can read data from or write data to the memory subsystem. The host system may be coupled to the memory subsystem via a physical host interface. Generally, the host system may access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or combinations of communication connections.

[0229] In some embodiments, a computing device is a system that includes one or more processing devices. Examples of processing devices may include a microcontroller, a central processing unit (CPU), a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), a system-on-a-chip (SoC), or another suitable processor.

[0230] In one example, the computing device is the controller of the memory system. The controller includes a processing device and a memory containing instructions executed by the processing device to control various operations of the memory system.

[0231] Although some diagrams illustrate several operations in a specific order, operations that do not depend on the order can be reordered, and other operations can be combined or decomposed. While some reorderings or other groupings are specifically mentioned, other groupings will be obvious to those skilled in the art and therefore no exhaustive list of alternatives is provided. Furthermore, it should be recognized that stages can be implemented in hardware, firmware, software, or any combination thereof.

[0232] For example, the disjunctive language of the phrase "at least one of X, Y, or Z" should be understood, in context, to generally indicate that an item, term, etc., can be X, Y, or Z or any combination thereof (e.g., X, Y, and / or Z). Therefore, this disjunctive language generally does not intend and should not imply that some embodiments require at least one X, at least one Y, or at least one Z to be present.

[0233] In the foregoing description, specific exemplary embodiments of this disclosure have been referred to. It should be understood that various modifications may be made to this disclosure without departing from the broader spirit and scope set forth in the appended claims. Therefore, the specification and drawings should be regarded as illustrative rather than limiting.

Claims

1. An apparatus comprising: A memory array comprising ternary units; and At least one controller is configured to store data in the ternary unit, wherein a portion of the data corresponding to a defined value is stored using two encoding levels, and the remaining portion of the data is stored using one encoding level.

2. The device according to claim 1, wherein: The data includes bit combinations, the bit combinations corresponding to the defined values ​​are stored using the two encoding levels, and the other remaining bit combinations are stored using the one encoding level; Each combination is stored using a pair of the aforementioned ternary units; and The controller is further configured to receive the data from the host device as part of a write operation requested by the host device or to select the defined value based on the characteristics of the data.

3. The device according to claim 1, wherein: The first combination of the data corresponds to the defined value and is stored in the first and second ternary units, and the state of each of the first and second ternary units is programmed by the controller based on the additional bits to be stored; and The extra bit is associated with the first bit combination.

4. The device according to claim 1, wherein: The controller is further configured to determine that the data contains a first bit combination representing the defined value and, in response to determining that the data contains the first bit combination, to apply a second encoding level to encode the additional bits; The first bit combination is stored using first and second ternary units, and the application of the second encoding level includes selecting a first or second state of the first ternary unit of the memory array based on the value represented by the additional bits; and For either the first or second state of the first ternary unit, the programming state of the second ternary unit when storing the first bit combination is the same.

5. The device according to claim 1, wherein: The controller is further configured to store the data using an encoding table that maps multiple data bits in the data to programmable states of ternary unit pairs; and The encoding table contains combinations of the programmable states, and one of the combinations is a redundant combination corresponding to the defined value.

6. A system comprising: A memory configured to store user data; and The controller is configured to: Identify the location of special values ​​in the user data; and Associate the corresponding extra bits with each identified position.

7. The system of claim 6, wherein the controller is further configured to: The user data is stored at the identified location using a first coding level. The corresponding extra bits are stored using a second encoding level; and For each extra bit, the state of a pair of corresponding ternary units is programmed based on the value of the extra bit.

8. The system according to claim 6, wherein: The user data is the basic payload, and the extra bits are the additional payload; Each specific value corresponds to a corresponding bit combination, and associating the corresponding extra bit includes adding the extra bit to the bit combination; and The controller is further configured to use a pair of ternary units to store each bit combination and corresponding extra bits.

9. A system comprising: At least one processing device; and At least one memory containing instructions configured to instruct the at least one processing device: Adjust the proportion of special values ​​in the data; and Ternary unit pairs are used to store each special value and its corresponding extra bits.

10. The system according to claim 9, wherein: The user data is the basic payload; The processing device is further configured to scan the data, and based on the scan, change the distribution of the data, and After the distribution is changed, the data is encoded and stored in the ternary unit, and Adjusting the ratio includes: Balance the codewords in the data to change the distribution of at least one programming state of the ternary unit; The target is the number of specific values ​​in the data; or Adjusting the ratio includes targeting the amount of additional payload.

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