Memory device

Abstract

This disclosure provides a memory device. The memory device includes at least one core die and a logic die. The at least one core die provides at least two status signals based on error checking and correction (ECC) operations. The logic die is coupled to at least one core die. The logic die generates a plurality of severity (SEV) signals based on the status signals. The number of status signals is less than the number of SEV signals.

Description

Technical Field

[0001] This disclosure relates to a memory device, and more particularly to a memory device that provides a severity signal. Background Technology

[0002] Figure 1 A schematic diagram of a memory device is shown. Generally, a memory device includes core chips CD1 to CD8 and logic chips LD. Each of the core chips CD1 to CD8 can provide an 8-bit severity (SEV) signal SEV[0] and an 8-bit SEV signal SEV[1] based on error check and correction (ECC) operations. The logic chip LD outputs the sequence severity signal SSEV[0] and the sequence severity signal SSEV[1] to the controller CC.

[0003] It should be noted that each of the eight core dies CD1 to CD8 requires up to 16 channels to transmit the SEV signals SEV[0] and SEV[1]. Each channel has “2” pseudo channels. Each pseudo channel has 2 pins or 2 die-to-die (D2D) interconnects. Each of the core dies CD1 to CD8 requires up to 64 (i.e., 16 × 2 × 2) pins or interconnects. Therefore, the core dies CD1 to CD8 require up to 512 (i.e., 16 × 2 × 2 × 8) pins or interconnects. In other words, the memory device requires 512 vias (e.g., TSVs) to transmit the SEV signals SEV[0] and SEV[1]. Increasing the number of vias used to transmit the SEV signals SEV[0] and SEV[1] increases the design complexity of the memory device.

[0004] Therefore, reducing the number of through holes is one of the key research and development focuses for engineers in this technical field. Summary of the Invention

[0005] This disclosure provides a memory device. The number of vias in at least one core die of the memory device can be reduced.

[0006] In one embodiment of this disclosure, the memory device includes at least one core die and a logic die. The at least one core die provides at least two status signals based on error check and correction (ECC) operations. The logic die is coupled to the at least one core die. The logic die generates multiple severity (SEV) signals based on the status signals. The number of status signals is less than the number of SEV signals.

[0007] To make the foregoing more understandable, several embodiments are described in detail below with reference to the illustrations. Attached Figure Description

[0008] Figure 1 A schematic diagram of a memory device is shown;

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 7 and Figure 8 Schematic diagrams of memory devices according to some embodiments of the present disclosure are shown;

[0010] Figure 5 and Figure 9 A schematic diagram of a front encoder according to some embodiments of the present disclosure is shown;

[0011] Figure 6 A schematic diagram of a severity (SEV) signal generator according to an embodiment of the present disclosure is shown.

[0012] Explanation of icon numbers

[0013] 100, 200, 200', 300, 300': Memory devices

[0014] 110, 210, 210_1~210_8, 310, 310_1~310_8: Core grains

[0015] 120, 220, 320: Logic chips

[0016] 211: Error Correction Code Circuit

[0017] 221, 321: Front encoder

[0018] 2211: Decoder

[0019] 2212: Logic Circuits

[0020] 222: SEV signal generator

[0021] 223: Serializer

[0022] 230: Controller

[0023] AG1, AG2: AND gate

[0024] CC: Controller

[0025] CD1~CD8: Core grains

[0026] ERR_OUT1, ERR_OUT2: Error output signals

[0027] IVT: Inverter

[0028] LD: Logic Diode

[0029] MUX1, MUX2: Multitasking

[0030] OG1, OG2: OR gates

[0031] SEV[0], SEV[1], SEV[0] <0> ~SEV[0] <7> SEV[1] <1> ~SEV[1] <7> SEV signal

[0032] SL1, SL2, SL3, SL4: Logic signals

[0033] SSEV[0], SSEV[1]: Sequence severity signals

[0034] ST1, ST2, ST3: Status signals Detailed Implementation

[0035] Figure 2 A schematic diagram of a memory device 100 according to an embodiment of this disclosure is shown. Please refer to... Figure 2 The memory device 100 includes a core die 110 and a logic die 120. The core die 110 provides at least two status signals based on Error Checking and Correction (ECC) operations. These status signals correspond to the ECC operation results of the core die 110. In this embodiment, taking the core die 110 providing two status signals ST1 and ST2 based on ECC operations as an example, when the logic values ​​of both status signals ST1 and ST2 are first logic values ​​(e.g., low logic value "0"), it indicates that the ECC operation result is error-free (NE). When the logic value of status signal ST1 is a second logic value (e.g., high logic value "1") and the logic value of status signal ST2 is a first logic value, it indicates that the ECC operation result is a correctable error unit (CEs). When the logic value of status signal ST1 is a first logic value and the logic value of status signal ST2 is a second logic value, it indicates that the ECC operation result is a correctable error multiple bit (CEm). When the logic values ​​of both status signals ST1 and ST2 are second logic values, it indicates that the ECC operation result is an uncorrectable error bit (UE). In other embodiments, the core die 110 may also provide more status signals (e.g., three status signals ST1~ST3) based on error checking and correction (ECC) operations, and represent different ECC operation results.

[0036] In this embodiment, logic die 120 generates a severity (SEV) signal SEV[0] based on a state signal. <0> ~SEV[0] <7> and SEV[1] <0> ~SEV[1] <7> In one embodiment, the number of state signals is less than the number of SEV signals SEV[0]. <0> ~SEV[0] <7> and SEV[1] <0> ~SEV[1] <7> The number of state signals. For example, the number of state signals is "2" or "3". SEV signal SEV[0] <0> ~SEV[0] <7> and SEV[1] <0> ~SEV[1] <7> The quantity is "16".

[0037] It should be noted that the core die 110 provides at least two status signals based on the ECC operation to indicate the result of the ECC operation. The logic die 120 then generates multiple SEV signals SEV[0] based on the status signals provided by the core die 110. <0> ~SEV[0] <7> and SEV[1] <0> ~SEV[1] <7> The number of status signals is less than the number of SEV signals. Here, since the logic die can generate multiple SEV signals based solely on the status signals generated by the core die, the core die 110 only needs to be designed with vias (e.g., TSVs) for transmitting status signals, and not vias for transmitting SEV signals. This reduces the number of vias in the core die and lowers the design complexity of the memory device.

[0038] Furthermore, logic die 120 is based on the SEV signal SEV[0]. <0> ~SEV[0] <7> and SEV[1] <0> ~SEV[1] <7> At least one sequence severity signal SSEV[0] and SSEV[1] is generated.

[0039] Figure 3 A schematic diagram of a memory device 200 according to an embodiment of this disclosure is shown. Please refer to... Figure 3 In this embodiment, the memory device 200 includes a core die 210 and a logic die 220. The core die 210 provides status signals ST1 and ST2 based on the results of ECC operations. The logic die 220 includes a front encoder 221 and an SEV signal generator 222. The front encoder 221 is coupled to the core die 210. The front encoder 221 generates error output signals ERR_OUT1 and ERR_OUT2 based on the status signals ST1 and ST2. The SEV signal generator 222 is coupled to the front encoder 221. The SEV signal generator 222 generates an SEV signal SEV[0] based on the error output signals ERR_OUT1 and ERR_OUT2. <0> ~SEV[0] <7> and SEV[1] <0> ~SEV[1] <7> .

[0040] It should be noted that, based on the results of the ECC operation, core die 210 only provides status signals ST1 and ST2, but not the SEV signal SEV[0]. <0> ~SEV[0] <7> and SEV[1] <0> ~SEV[1] <7> For example, each of the two channels used to transmit status signals ST1 and ST2 has two pseudo-channels. Each pseudo-channel has two pins or two die-to-die (D2D) interconnect structures. Therefore, the core die 210 has up to eight (i.e., 2×2×2) pins or interconnect structures. In other words, the core die 210 has eight vias for transmitting status signals ST1 and ST2.

[0041] In addition, logic die 220 also includes a sequencer 223. Sequencer 223 is coupled to SEV signal generator 222. Sequencer 223 operates based on the SEV signal SEV[0]. <0> ~SEV[0] <7> and SEV[1] <0> ~SEV[1] <7> At least one sequence severity signal is generated. In this embodiment, the sequencer 223 generates a sequence based on the SEV signal SEV[0]. <0> ~SEV[0] <7> Generate a sequence severity signal SSEV[0], and based on the SEV signal SEV[1]... <0> ~SEV[1] <7> A sequence severity signal SSEV[1] is generated. The sequencer 223 can receive the SEV signal SEV[0] in parallel. <0> ~SEV[0] <7> and SEV[1] <0> ~SEV[1] <7> And generate sequence severity signals SSEV[0] and SSEV[1]. For example, sequencer 223 can be a parallel-to-sequence converter.

[0042] In this embodiment, the memory device 200 further includes a controller 230. The controller 230 is coupled to the sequencer 223. The controller 230 obtains the ECC operation result of the core die 210 based on the sequence severity signals SSEV[0] and SSEV[1].

[0043] In this embodiment, the core die 210 includes an error correction code circuit 211. The error correction code circuit 211 performs ECC operations on the core die 210 to generate status signals ST1 and ST2. The ECC operations disclosed herein are not limited.

[0044] Figure 4 A schematic diagram of a memory device 200' according to an embodiment of the present disclosure is shown. Please refer to... Figure 3 and Figure 4In this embodiment, the memory device 200' includes core dies 210_1 to 210_8 and logic dies 220. Core dies 210_1 to 210_8 are stacked on top of each other. Each of the core dies 210_1 to 210_8 can be implemented by core die 210. Each of the core dies 210_1 to 210_8 has eight vias for transmitting status signals ST1 and ST2. Therefore, with... Figure 1 Compared to the memory device in the memory device 200', the total number of vias in the core die 210_1 to 210_8 can be reduced from "512" to "64".

[0045] Figure 5 A schematic diagram of a front encoder 221 according to an embodiment of this disclosure is shown. Please refer to... Figure 5 In this embodiment, the front encoder 221 includes a decoder 2211 and a logic circuit 2212. The decoder 2211 generates logic signals SL1 to SL4 in response to the logic values ​​of the status signals ST1 and ST2. The logic circuit 2212 is coupled to the decoder 2211. The logic circuit 2212 generates error output signals ERR_OUT1 and ERR_OUT2 based on the logic signals SL1 to SL3.

[0046] In this embodiment, logic signal SL1 corresponds to the ECC operation result of correctable error units (CEs). Logic signal SL2 corresponds to the ECC operation result of correctable error multiple bits (CEm). Logic signal SL3 corresponds to the ECC operation result of uncorrectable error bits (UE). Logic signal SL4 corresponds to the ECC operation result of no error (NE). Furthermore, the pre-encoder 221 generates error output signals ERR_OUT1 and ERR_OUT2 based on Table 1.

[0047] Table 1:

[0048]

[0049] Based on Table 1, when the logic values ​​of state signals ST1 and ST2 are both first logic values ​​(e.g., low logic value "0"), decoder 2211 generates a logic signal SL4 corresponding to the "NE" state with a second logic value (e.g., high logic value "1"), where each of the logic values ​​of logic signals SL1 to SL3 is a first logic value. When the logic value of state signal ST1 is a second logic value and the logic value of state signal ST2 is a first logic value, decoder 2211 generates a logic signal SL1 corresponding to the "CEs" state with a second logic value, where each of the logic values ​​of logic signals SL2 to SL4 is a first logic value. When the logic value of state signal ST1 is a first logic value and the logic value of state signal ST2 is a second logic value, decoder 2211 generates a logic signal SL2 corresponding to the "CEm" state with a second logic value, where each of the logic values ​​of logic signals SL1, SL3, and SL4 is a first logic value. When the logic values ​​of status signals ST1 and ST2 are both second logic values, decoder 2211 generates a logic signal SL3 with a second logic value corresponding to the "UE" state, while each of the logic values ​​of logic signals SL1, SL2 and SL4 is a first logic value.

[0050] In this embodiment, the decoder 2211 can be implemented by a 2-bit decoder.

[0051] The logic circuit 2212 performs a first OR logic operation on logic signals SL1 and SL2 to generate an error output signal ERR_OUT1, and performs a second OR logic operation on logic signals SL2 and SL3 to generate an error output signal ERR_OUT2.

[0052] In this embodiment, the logic circuit 2212 includes OR gates OG1 and OG2. The first input of OR gate OG1 receives logic signal SL1. The second input of OR gate OG1 receives logic signal SL2. The output of OR gate OG1 outputs an error output signal ERR_OUT1. The first input of OR gate OG2 receives logic signal SL2. The second input of OR gate OG2 receives logic signal SL3. The output of OR gate OG2 outputs an error output signal ERR_OUT2.

[0053] Figure 6 A schematic diagram of a severity (SEV) signal generator according to an embodiment of this disclosure is shown. Please refer to... Figure 6In this embodiment, the SEV signal is SEV[0]. <0> ~SEV[0] <7> The components include the SEV signal SEV[0]. <0> ~SEV[0] <3> The first signal group includes the SEV signal SEV[0]. <4> ~SEV[0] <7> The second signal group. SEV signal SEV[1] <0> ~SEV[1] <7> The components include the SEV signal SEV[1]. <0> ~SEV[1] <3> The first signal group includes the SEV signal SEV[1]. <4> ~SEV[1] <7> The second signal group.

[0054] SEV signal generator 222 provides a first group of signals having a first logic value (e.g., a low logic value "0"), and a second group of signals based on error output signals ERR_OUT1 and ERR_OUT2. Specifically, SEV signal generator 222 provides an SEV signal SEV[0] having a first logic value (e.g., a low logic value "0"). <0> ~SEV[0] <3> and SEV[1] <0> ~SEV[1] <3> The SEV signal generator 222 provides the SEV signal SEV[0] based on the error output signal ERR_OUT1. <4> ~SEV[0] <7> , and provide the SEV signal SEV[1] based on the error output signal ERR_OUT2. <4> ~SEV[1] <7> .

[0055] In one embodiment, the SEV signal generator 222 includes multiplexers MUX1 and MUX2. Multiplexer MUX1 receives a first logic value (e.g., a low logic value "0"), a second logic value (e.g., a high logic value "1"), and an error output signal ERR_OUT1. When the logic value of the error output signal ERR_OUT1 is the first logic value, the SEV signal SEV[0] is generated. <0> ~SEV[0] <7> The logical values ​​are "0, 0, 0, 0, 0, 0, 0, 0". When the logical value of the error output signal ERR_OUT1 is the second logical value, the SEV signal SEV[0] is activated. <0> ~SEV[0] <7> The logical values ​​are "0, 0, 0, 0, 1, 1, 1, 1". The multitasking unit MUX2 receives the first logical value, the second logical value, and the error output signal ERR_OUT2. When the logical value of the error output signal ERR_OUT2 is the first logical value, the SEV signal SEV[1] is activated. <0> ~SEV[1] <7> The logical values ​​are "0, 0, 0, 0, 0, 0, 0, 0". When the logical value of the error output signal ERR_OUT2 is the second logical value, the SEV signal SEV[0] is activated. <0> ~SEV[0] <7> The logical values ​​are "0, 0, 0, 0, 1, 1, 1, 1".

[0056] SEV signal generator 222 provides the SEV signal SEV[0] according to Table 2. <0> ~SEV[0] <7> and SEV[1] <0> ~SEV[1] <7> .

[0057] Table 2:

[0058]

[0059] Therefore, based on Tables 1 and 2, when the logic values ​​of error output signals ERR_OUT1 and ERR_OUT2 are both the first logic value, the SEV signal generator 222 decodes the SEV signal SEV[0] corresponding to the ECC result of "NE". <0> ~SEV[0] <7> and SEV[1] <0> ~SEV[1] <7> When the logic value of the error output signal ERR_OUT1 is the second logic value and the logic value of the error output signal ERR_OUT2 is the first logic value, the SEV signal generator 222 decodes the SEV signal SEV[0] corresponding to the ECC result "CEs". <0> ~SEV[0] <7> and SEV[1] <0> ~SEV[1] <7> When the logic values ​​of error output signals ERR_OUT1 and ERR_OUT2 are both the second logic value, the SEV signal generator 222 decodes the SEV signal SEV[0] corresponding to the ECC result "CEm". <0> ~SEV[0] <7> and SEV[1] <0> ~ SEV[1] <7> When the logic value of the error output signal ERR_OUT1 is the first logic value and the logic value of the error output signal ERR_OUT2 is the second logic value, the SEV signal generator 222 decodes the SEV signal SEV[0] corresponding to the ECC result "UE". <0> ~SEV[0] <7> and SEV[1] <0> ~SEV[1] <7> .

[0060] Figure 7 A schematic diagram of a memory device 300 according to an embodiment of this disclosure is shown. Please refer to... Figure 7In this embodiment, the memory device 300 includes a core die 310 and a logic die 320. The core die 310 provides status signals ST1~ST3 based on the result of ECC operation. For example, the core die 310 provides status signals ST1~ST3 through an ECC circuit. The logic die 320 includes a pre-encoder 321, an SEV signal generator 222, and a sequencer 223. The pre-encoder 321 is coupled to the core die 310. The pre-encoder 321 generates error output signals ERR_OUT1 and ERR_OUT2 based on the status signals ST1~ST3. The SEV signal generator 222 is coupled to the pre-encoder 321. The SEV signal generator 222 generates an SEV signal SEV[0] based on the error output signals ERR_OUT1 and ERR_OUT2. <0> ~SEV[0] <7> and SEV[1] <0> ~SEV[1] <7> .

[0061] It should be noted that, based on the results of the ECC operation, core die 310 only provides status signals ST1~ST3, but not the SEV signal SEV[0]. <0> ~SEV[0] <7> and SEV[1] <0> ~SEV[1] <7> For example, each of the "3" channels used to transmit status signals ST1 to ST3 has 2 pseudo-channels. Each pseudo-channel has 2 pins or 2 die-to-die (D2D) interconnect structures. Therefore, the core die 310 has up to 12 (i.e., 3×2×2) pins or interconnect structures. In other words, the core die 310 has 12 via structures for transmitting status signals ST1 to ST3.

[0062] The memory device 300 also includes a controller 230. The operation of the SEV signal generator 222 is already... Figure 6 The embodiments are clearly explained and will not be repeated here. Controller 230 and sequencer 223 have been described in detail. Figure 3 The embodiments are clearly explained and will not be repeated here.

[0063] Figure 8 A schematic diagram of a memory device 300' according to an embodiment of this disclosure is shown. Please refer to... Figure 7 and Figure 8 In this embodiment, the memory device 300' includes core dies 310_1 to 310_8 and logic dies 320. Core dies 310_1 to 310_8 are stacked on top of each other. Each of the core dies 310_1 to 310_8 can be implemented by core die 310. Each of the core dies 310_1 to 310_8 has 12 vias for transmitting status signals ST1 to ST3. Therefore, with... Figure 1 Compared to memory devices in memory devices, the number of vias in the core chips 310_1 to 310_8 of memory device 300' can be reduced from "512" to "96".

[0064] In this embodiment, the front encoder 321 generates error output signals ERR_OUT1 and ERR_OUT2 based on Table 3.

[0065] Table 3:

[0066]

[0067] In this embodiment, when the ECC operation result is No Error (NE), the logic values ​​of the status signals ST1~ST3 output by the core die are all first logic values, and the front encoder 321 outputs error output signals ERR_OUT1 and ERR_OUT2 with the first logic values. When the ECC operation result is Error Unit (CEs), the logic value of the status signal ST1 output by the core die is different from the logic value of the status signal ST2, and the logic value of the status signal ST3 is the first logic value. The front encoder 321 outputs error output signals ERR_OUT1 with second logic values ​​and error output signals ERR_OUT2 with the first logic value. When the ECC operation result is Correctable Error Multiple (CEm), the logic values ​​of the status signals ST1 and ST2 output by the core die are the second logic values, and the logic value of the status signal ST3 is the first logic value. The front encoder 321 outputs error output signals ERR_OUT1 and ERR_OUT2 with the second logic values. When the ECC operation result is an uncorrectable error bit (UE), the logic values ​​of the status signals ST1~ST3 output by the core die are all the second logic values, and the front encoder 321 outputs an error output signal ERR_OUT1 with the first logic value and an error output signal ERR_OUT2 with the second logic value.

[0068] Therefore, based on Tables 3 and 2, when the logic values ​​of error output signals ERR_OUT1 and ERR_OUT2 are both the first logic value, the SEV signal generator 222 decodes the SEV signal SEV[0] corresponding to the ECC result of "NE". <0> ~SEV[0] <7> and SEV[1] <0> ~SEV[1] <7> When the logic value of the error output signal ERR_OUT1 is the second logic value and the logic value of the error output signal ERR_OUT2 is the first logic value, the SEV signal generator 222 decodes the SEV signal SEV[0] corresponding to the ECC result "CEs". <0> ~SEV[0] <7> and SEV[1] <0> ~SEV[1] <7> When the logic values ​​of error output signals ERR_OUT1 and ERR_OUT2 are both the second logic value, the SEV signal generator 222 decodes the SEV signal SEV[0] corresponding to the ECC result "CEm". <0> ~SEV[0] <7> and SEV[1] <0> ~ SEV[1] <7> When the logic value of the error output signal ERR_OUT1 is the first logic value and the logic value of the error output signal ERR_OUT2 is the second logic value, the SEV signal generator 222 decodes the SEV signal SEV[0] corresponding to the ECC result "UE". <0> ~SEV[0] <7> and SEV[1] <0> ~SEV[1] <7> .

[0069] Figure 9 A schematic diagram of a front encoder 321 according to an embodiment of this disclosure is shown. Please refer to... Figure 9 In this embodiment, the front encoder 321 includes AND gates AG1 and AG2, an inverter IVT, and OR gates OG1 and OG2. The first input of AND gate AG1 receives a status signal ST1. The second input of AND gate AG1 receives a status signal ST2. The input of the inverter IVT receives a status signal ST3. The first input of AND gate AG2 is coupled to the output of the inverter IVT. The second input of AND gate AG2 is coupled to the output of AND gate AG1. The output of AND gate AG2 outputs an error output signal ERR_OUT1. The first input of OR gate OG1 receives the status signal ST1. The second input of OR gate OG1 receives the status signal ST2. The first input of OR gate OG2 receives the status signal ST3. The second input of OR gate OG2 is coupled to the output of OR gate OG1. The output of OR gate OG2 outputs an error output signal ERR_OUT2. Table 3 can be implemented based on AND gates AG1 and AG2, the inverter IVT, and OR gates OG1 and OG2.

[0070] In this embodiment, based on Table 3 and Figure 9When the logic value of the status signal ST3 is the second logic value, the front encoder 321 outputs an error output signal ERR_OUT1 with the first logic value and an error output signal ERR_OUT2 with the second logic value. Therefore, the status signal ST3 corresponds to the "UE" state.

[0071] In view of the above, according to the embodiments disclosed herein, the core die provides at least two status signals based on ECC operation to indicate the result of the ECC operation. The logic die receives the status signals provided by the core die and generates multiple SEV signals based on the status signals. The number of status signals is less than the number of SEV signals. Here, since the core die itself does not generate SEV signals, the core die only needs to be designed with vias (e.g., TSVs) for transmitting status signals, and does not need to be designed with vias for transmitting SEV signals. Therefore, the number of vias in the core die can be reduced, lowering the design complexity of the memory device.

[0072] Various modifications and variations can be made to the disclosed embodiments by those skilled in the art without departing from the scope or spirit of this disclosure. In view of the foregoing, this disclosure is intended to cover modifications and variations falling within the scope of the following claims and their equivalents.

Claims

1. A memory device, comprising: The memory device includes: At least one core die is used to provide at least two status signals based on error checking and correction operations; and A logic die, coupled to the at least one core die, is used to generate the at least two state signals to generate a plurality of severity signals, wherein the number of the at least two state signals is less than the number of the plurality of severity signals.

2. The memory device of claim 1, wherein, The logic grain includes: A front encoder, coupled to the at least one core die, is used to generate a first error output signal and a second error output signal based on the at least two state signals; and A severity signal generator, coupled to the front encoder, is used to generate a plurality of severity signals based on the first error output signal and the second error output signal.

3. The memory device of claim 2, wherein, The logic grain also includes: A sequencer, coupled to the severity signal generator, is used to generate at least one sequence severity signal based on the plurality of severity signals.

4. The memory device of claim 3, wherein, The memory device further includes: A controller, coupled to the sequencer, is used to obtain the error type of the at least one core die based on the at least one sequence severity signal.

5. The memory device according to claim 2, characterized in that: The at least two state signals include a first state signal and a second state signal, and The front encoder includes: A decoder, used to generate a first logic signal, a second logic signal, and a third logic signal in response to the logic values ​​of the first state signal and the second state signal; and A logic circuit, coupled to the decoder, is used to generate the first error output signal and the second error output signal based on the first logic signal, the second logic signal, and the third logic signal.

6. The memory device of claim 5, wherein, The logic circuit performs a first OR logic operation on the first logic signal and the second logic signal to generate the first error output signal, and performs a second OR logic operation on the second logic signal and the third logic signal to generate the second error output signal.

7. The memory device of claim 5, wherein, The logic circuit includes: A first OR gate, wherein the first input of the first OR gate receives the first logic signal, the second input of the first OR gate receives the second logic signal, and the output of the first OR gate outputs the first error output signal; and The second OR gate receives the second logic signal at its first input terminal, receives the third logic signal at its second input terminal, and outputs the second error output signal at its output terminal.

8. The memory device according to claim 5, characterized in that: The first logic signal corresponds to the correct / incorrect unit state. The second logic signal corresponds to a correct / incorrect multi-bit state, and The third logic signal corresponds to the uncorrectable error bit state.

9. The memory device according to claim 8, characterized in that: When the logic value of the first error output signal is the first logic value and the logic value of the second error output signal is the first logic value, the plurality of severity signals indicate an error-free state. When the logic value of the first error output signal is the second logic value and the logic value of the second error output signal is the first logic value, the plurality of severity signals indicate the correct / incorrect unit status. When the logic value of the first error output signal is the second logic value and the logic value of the second error output signal is the second logic value, the plurality of severity signals indicate the correct / error multi-bit state, and When the logic value of the first error output signal is the first logic value and the logic value of the second error output signal is the second logic value, the plurality of severity signals indicate the uncorrectable error bit state.

10. The memory device according to claim 2, characterized in that: The at least two state signals include a first state signal, a second state signal, and a third state signal, and The front encoder generates the first error output signal and the second error output signal based on the first state signal, the second state signal and the third state signal.

11. The memory device of claim 10, wherein, The front encoder includes: A first AND gate, wherein the first input terminal of the first AND gate receives the first state signal, and the second input terminal of the first AND gate receives the second state signal; An inverter, the input of which receives the third state signal; The second AND gate has its first input coupled to the output of the inverter, its second input coupled to the output of the first AND gate, and its output outputs the first error output signal. A first OR gate, wherein the first input terminal of the first OR gate receives the first state signal, and the second input terminal of the first OR gate receives the second state signal; The second OR gate receives the third state signal at its first input terminal, and its second input terminal is coupled to the output terminal of the first OR gate. The output terminal of the second OR gate outputs the second error output signal.

12. The memory device of claim 10, wherein, The third state signal corresponds to the uncorrectable error bit state.

13. The memory device of claim 10, wherein, When the logic value of the first state signal is the first logic value, the logic value of the second state signal is the first logic value, and the logic value of the third state signal is the first logic value, the front encoder outputs a first error output signal having the first logic value and a second error output signal having the first logic value.

14. The memory device of claim 13, wherein, When the logic value of the first state signal is different from the logic value of the second state signal and the logic value of the third state signal is the first logic value, the front encoder outputs a first error output signal with a second logic value and a second error output signal with the first logic value.

15. The memory device of claim 13, wherein, When the logic value of the first state signal is the second logic value, the logic value of the second state signal is the second logic value, and the logic value of the third state signal is the first logic value, the front encoder outputs the first error output signal having the second logic value and the second error output signal having the second logic value.

16. The memory device of claim 13, wherein, When the logic value of the first state signal is the second logic value, the logic value of the second state signal is the second logic value, and the logic value of the third state signal is the second logic value, the front encoder outputs a first error output signal having the first logic value and a second error output signal having the second logic value.

17. The memory device according to claim 10, characterized in that: When the logic value of the first error output signal is the first logic value and the logic value of the second error output signal is the first logic value, the plurality of severity signals indicate an error-free state. When the logic value of the first error output signal is the second logic value and the logic value of the second error output signal is the first logic value, the plurality of severity signals indicate a rectifiable error unit state. When the logic value of the first error output signal is the second logic value and the logic value of the second error output signal is the second logic value, the plurality of severity signals indicate a correctable multi-bit error state, and When the logic value of the first error output signal is the first logic value and the logic value of the second error output signal is the second logic value, the plurality of severity signals indicate an uncorrectable error bit state.

18. The memory device according to claim 2, characterized in that: The multiple severity signals are divided into a first signal group and a second signal group, and The severity signal generator provides the first signal group having a first logic value, and provides the second signal group based on the first error output signal and the second error output signal.

19. The memory device according to claim 1, characterized in that, The at least one core grain includes: An error checking and correction circuit is used to perform the error checking and correction operation of the at least one core die to generate the at least two status signals.

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