3D-raid cross-layer error correction hbm fault avoidance method and system

Abstract

The present application relates to a kind of 3D-RAID cross-layer error correction HBM fault avoidance method and system, it is related to high bandwidth storage technology field, including the parameter configuration and region division to HBM vertical stack structure;The storage area of each layer DRAM chip is divided into data storage area and check storage area;Form three-dimensional check network;Check operation module is carried out parity operation to each three-dimensional odd-even check group in parallel, and synchronous generation check data, obtain updated check data;In three-dimensional check network, the corresponding three-dimensional odd-even check group is positioned, and the read-write request of this fault region is all forwarded through cache unit.The present application effectively solves the problem of local storage unit failure caused by process defects, interlayer interconnection fault etc. during stacking, improves the reliability, fault tolerance and operating stability of HBM.

Description

Technical Field

[0001] This invention relates to the field of high-bandwidth storage technology, and more specifically, to a 3D-RAID cross-layer error correction HBM fault avoidance method and system. Background Technology

[0002] HBM, a high-performance vertically stacked DRAM memory, achieves high-density vertical interconnection of multi-layer DRAM wafers through through-silicon vias (TSVs), realizing ultra-high bandwidth in a very small space. It effectively solves the data transmission bottleneck between the CPU, GPU, and memory, and is widely used in high-end applications such as artificial intelligence, high-performance computing, and servers. Its core structure consists of vertically stacked multi-layer DRAM chips, coupled with buffer dies (logic chips), and inter-layer data interaction is completed through TSVs. Storage capacity and bandwidth increase with the number of stacked layers.

[0003] However, during the manufacturing and long-term operation of HBM, localized failures occur frequently, seriously affecting its reliability and service life. The main causes of failure and the shortcomings of existing technologies are as follows: (1) Causes of failure: The multi-wafer stacking process of HBM is prone to failure of some storage cells due to process defects, quality problems of the wafer itself or stacking alignment deviations. At the same time, the strong coupling of multiple fields of heat, force, electricity and chemistry during long-term operation will cause problems such as uneven filling of TSV, aging of microbumps and poor contact between layers, which will lead to local storage failures and are difficult to avoid by full coverage through traditional single redundancy.

[0004] (2) Existing technical deficiencies: Currently, HBM fault avoidance mainly relies on two methods. One is local redundancy design within a single DRAM wafer, which sets a small number of redundant rows or columns within a single wafer to replace failed units. However, its redundancy is limited. When the proportion of failed units exceeds the redundancy capacity, it will cause the entire HBM module to be scrapped, significantly increasing production costs. Moreover, it cannot achieve cross-layer redundant resource scheduling, resulting in resource waste. The other is traditional two-dimensional dwarf couple check or ECC error correction technology, which only checks the row and column dimensions within a single layer and does not cover the layer dimensions of the vertical stacking of HBM. Its fault tolerance is limited and it cannot cope with cross-layer local faults. In addition, the check data is mostly stored in a centralized manner, which can easily form a "single point of failure". Once the check area fails, the entire error correction mechanism is paralyzed. At the same time, traditional error correction schemes rely on serial logic circuits, resulting in high error correction latency, which can easily affect the normal access bandwidth of HBM and cannot meet the requirements of high-performance scenarios. Currently, there is a lack of a check mechanism that can cover the full dimensions of layer, bank, row, and column, as well as an efficient cross-layer data reconstruction scheme. Summary of the Invention

[0005] The purpose of this invention is to provide a 3D-RAID cross-layer error correction HBM fault avoidance method and system to improve the above-mentioned problems. To achieve the above objective, the technical solution adopted by this invention is as follows: Firstly, this application provides a 3D-RAID cross-layer error correction HBM fault avoidance method, including: The parameters of the HBM vertical stacking structure are configured and the area is divided to determine the number of DRAM chip layers L, the number of banks B in each DRAM chip layer, the number of rows R in each bank, and the number of columns C in each row, thus constructing a four-dimensional storage address system of "layer-bank-row-column". The storage area of ​​each DRAM chip layer is divided into a data storage area and a parity storage area. The parity storage area is evenly distributed to different banks in each layer using a distributed partitioning method. A fault detection module, a parity calculation module, and a data reconstruction module are integrated into the buffer die. Within the three-dimensional space formed by vertically stacked multilayer DRAM chips in HBM, a three-dimensional parity check structure is constructed based on RAID-5 or RAID-6. The three-dimensional parity check groups are divided with "layer-bank-row" as the basic unit. Each parity check group covers four dimensions: layer, bank, row, and column, forming a three-dimensional parity check network. When user data is written to HBM, the parity calculation module performs parity calculations in parallel for each three-dimensional parity check group, and generates parity data synchronously. A distributed storage strategy is adopted to store the parity data in the parity storage area of ​​each layer of DRAM chip, so that the parity data of the same parity group is not stored in the layer and bank where the data unit of the group is located. When user data is modified, an incremental update method is used to recalculate only the parity value corresponding to the modified data to obtain the updated parity data. Based on the updated verification data, the fault detection module monitors the status of storage units in each layer, bank, and row and column in real time. When a local fault is detected, the fault area address is marked and a fault signal is sent to the data reconstruction module. The data reconstruction module locates the corresponding three-dimensional parity check group in the three-dimensional verification network according to the fault area address, calls all intact data units and updated verification data in the check group, reconstructs the failed data of the fault area through parity inverse operation, and temporarily stores the reconstructed data in the cache unit of the buffer die. At the same time, the fault area is marked as failed, and all read and write requests for the fault area are forwarded through the cache unit.

[0006] Preferably, in the three-dimensional parity network: the RAID-5 structure is suitable for single local fault tolerance scenarios, each parity group contains L data units and 1 parity unit, the parity unit is the XOR operation result of all data units in the group, and is stored in a parity storage area of ​​different layer and different bank than the data units in the group using a distributed storage method; the RAID-6 structure is suitable for dual local fault tolerance scenarios, each parity group contains L data units and 2 parity units, the two parity units are generated by XOR operation and even parity operation respectively, and are stored in parity storage areas of different layer and different bank respectively.

[0007] Preferably, in the three-dimensional verification network, the verification storage area of ​​each Bank occupies 5% to 10% of the total storage capacity of the Bank; the distributed storage strategy is as follows: the verification data of the same verification group avoids the layer and Bank where the data unit of the group is located, and is evenly distributed to the verification storage areas of different Banks in other layers for distributed storage.

[0008] Preferably, based on the updated verification data, the fault detection module monitors the storage unit status of each layer, each bank, and each row and column in real time at a period of no more than 10ms through at least one of data read / write verification, TSV interconnection test, and temperature monitoring, with a detection delay of no more than 0.5ns; when a local fault is detected, the layer number, bank number, row number, column number, and fault type of the fault area are marked, and the TSV is a through silicon via.

[0009] Preferably, the data reconstruction module is based on a three-dimensional parity network. It locates the corresponding three-dimensional parity check group based on the fault area address, and calls the intact data units within the group and the aforementioned updated parity data to perform parity inverse operations. The data reconstruction module adopts a hardware-accelerated architecture design, integrating dedicated computing units and a parallel computing architecture. It has a reconstruction processing capability of 16 bytes per cycle, a reconstruction latency of no more than 2ns, and HBM access bandwidth fluctuations of no more than 2% during the reconstruction process. When a single local fault is detected, the corresponding RAID-5 parity check group is called to perform a single parity inverse operation reconstruction. When two local faults are detected, two parity units in the corresponding RAID-6 parity check group are called to perform a double parity inverse operation reconstruction.

[0010] Preferably, the reconstructed data is temporarily stored in the cache unit of the buffer die, and the faulty area is marked as invalid. Therefore, all read and write requests to this faulty area are forwarded through the cache unit, including: If the faulty area is repaired, the data reconstruction module will write the reconstructed data in the cache unit back to the repaired area, synchronously update the corresponding verification data, remove the fault mark and restore the normal use of the area. If the faulty area cannot be repaired, a redundancy switching mechanism is activated to migrate the storage tasks of the faulty area to other intact storage areas in the three-dimensional verification network.

[0011] Preferably, within the three-dimensional space formed by vertically stacked multilayer DRAM chips in HBM, a triple parity check structure is constructed based on RAID-5 or RAID-6. The triple parity check groups are divided using "layer-bank-row" as the basic unit. Each parity group covers four dimensions: layer, bank, row, and column, forming a three-dimensional parity network, including: During the fabrication of HBM stacks to build a three-dimensional verification network, process optimization and adaptation are performed. High-precision TSV etching technology and DRAM wafer bonding alignment technology are combined, and interlayer connectivity testing is added. Interlayer connectivity testing is performed after every two DRAM wafers are stacked to identify and avoid potential interlayer interconnection faults. The TSV is a through silicon via.

[0012] Secondly, this application also provides a 3D-RAID cross-layer error correction HBM fault avoidance system, including: The partitioning module is used to configure parameters and partition regions for the HBM vertical stacking structure, determining the number of DRAM chip layers L, the number of banks B in each DRAM chip layer, the number of rows R in each bank, and the number of columns C in each row, thus constructing a four-dimensional storage address system of "layer-bank-row-column". It divides the storage area of ​​each DRAM chip layer into a data storage area and a parity storage area, with the parity storage area evenly distributed across different banks in each layer using a distributed partitioning method. A fault detection module, a parity calculation module, and a data reconstruction module are integrated into the buffer die. Verification building module: Used to build a three-dimensional parity structure based on RAID-5 or RAID-6 in the three-dimensional space composed of multi-layer DRAM chips vertically stacked in HBM. The three-dimensional parity groups are divided with "layer-bank-row" as the basic unit. Each parity group covers four dimensions: layer, bank, row, and column, forming a three-dimensional parity network. The calculation and update module is used to perform parity operations in parallel for each three-dimensional parity check group when user data is written to HBM, and synchronously generate parity data. A distributed storage strategy is adopted to store the parity data in the parity storage area of ​​each layer of DRAM chip, so that the parity data of the same parity group is not stored in the layer and bank where the data unit of the group is located. When user data is modified, an incremental update method is used to recalculate only the parity value corresponding to the modified data to obtain the updated parity data. Data Reconstruction Module: Based on the updated verification data, the fault detection module monitors the storage unit status of each layer, bank, and row / column in real time. When a local fault is detected, the fault area address is marked and a fault signal is sent to the data reconstruction module. The data reconstruction module locates the corresponding three-dimensional parity check group in the three-dimensional verification network according to the fault area address, calls all intact data units and updated verification data in the check group, and reconstructs the failed data of the fault area through parity inverse operation. The reconstructed data is temporarily stored in the cache unit of the buffer die, and the fault area is marked as failed. Thus, all read and write requests for the fault area are forwarded through the cache unit.

[0013] Preferably, it further includes a redundancy switching module, which is signal-connected to the data reconstruction module. Once the faulty area is repaired, the data reconstruction module writes the reconstructed data from the cache unit back to the repaired area and updates the corresponding verification data, thus removing the fault marker. When a faulty area cannot be repaired, the redundancy switching module migrates the storage tasks of the faulty area to other intact storage areas in the three-dimensional verification network.

[0014] Preferably, it also includes a process optimization and adaptation module: the process optimization and adaptation module is used to combine high-precision TSV etching technology with DRAM wafer bonding alignment technology, and to perform inter-layer connectivity test after every 2 layers are stacked during the wafer stacking process corresponding to the construction of the three-dimensional verification network, so as to troubleshoot inter-layer interconnection faults; the buffer die adopts a process compatible with the existing HBM, and the system as a whole is adapted to HBM2, HBM3 and subsequent generations of vertical stacked DRAM architecture.

[0015] Thirdly, this application also provides a 3D-RAID cross-layer error correction HBM fault avoidance device, comprising: Memory, used to store computer programs; A processor is used to implement the steps of the 3D-RAID cross-layer error correction HBM fault avoidance method when executing the computer program.

[0016] Fourthly, this application also provides a readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the above-described 3D-RAID cross-layer error correction HBM fault avoidance method.

[0017] The beneficial effects of this invention are as follows: This invention utilizes a triple-difference parity overlay layer, bank, row, and column dimensions. The RAID-5 structure can achieve single local fault tolerance, and the RAID-6 structure can achieve double local fault tolerance. It can effectively cope with various local faults that occur during HBM stacking, increasing the HBM failure repair rate from 50% (when the failure rate is 5%) in traditional methods to over 95% (when the failure rate is 15%), significantly reducing the scrap rate of HBM modules and reducing production costs by 60%-70%.

[0018] This invention avoids single points of failure and ensures the stability of the verification mechanism by distributing the verification data; the fault detection delay is ≤0.5ns and the data reconstruction delay is ≤2ns, which can quickly detect and recover faulty data, reduce the risk of data loss, and improve the service life and operational stability of HBM devices. It is especially suitable for scenarios with extremely high data reliability requirements, such as artificial intelligence and high-performance computing.

[0019] This invention utilizes a hardware-accelerated verification and reconstruction mechanism to run in parallel with the normal read and write process of HBM, without occupying normal access bandwidth. The bandwidth fluctuation is ≤2%, ensuring that the high bandwidth advantage of HBM is not affected. At the same time, the solution is compatible with the existing HBM architecture, requiring no large-scale modification of production equipment. It can be directly integrated into the existing production line, has good industrialization prospects and compatibility, and improves the utilization rate of redundant resources by more than 40%.

[0020] This invention combines high-precision TSV etching, bonding alignment technology and interlayer connectivity testing to reduce the initial defect rate and further improve the reliability of HBM. At the same time, the solution can flexibly adjust the division of verification groups and the ratio of verification data storage according to different HBM stacking layers and number of banks, adapting to different specifications of HBM products and having strong versatility.

[0021] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing embodiments of the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the 3D-RAID cross-layer error correction HBM fault avoidance method described in this embodiment of the invention; Figure 2 This is a schematic diagram of the 3D-RAID cross-layer error correction HBM fault avoidance system structure described in this embodiment of the invention; Figure 3 This is a schematic diagram of the 3D-RAID cross-layer error correction HBM fault avoidance device structure described in this embodiment of the invention; Figure 4 This is a schematic diagram of the three-dimensional error checking process of the 3D-RAID cross-layer error correction HBM fault avoidance method described in this embodiment of the invention.

[0024] In the diagram: 701, Partitioning Module; 702, Verification and Construction Module; 703, Calculation and Update Module; 704, Data Reconstruction Module; 705, Redundancy Switching Module; 706, Process Optimization and Adaptation Module; 800, 3D-RAID Cross-Layer Error Correction HBM Fault Avoidance Device; 801, Processor; 802, Memory; 803, Multimedia Component; 804, I / O Interface; 805, Communication Component. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0026] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0027] Example 1:

[0028] To address the shortcomings of existing technologies such as weak fault tolerance for local faults in HBM-stacked DRAM, susceptibility of parity data to single-point failures, and impact on access bandwidth during data reconstruction, this invention provides a method for avoiding local faults in HBM-stacked DRAM based on 3D-RAID and cross-layer error correction. By constructing a RAID-5 / RAID-6 parity check structure within the three-dimensional space of vertically stacked HBMs, parity check is achieved with full-dimensional coverage of layers, banks, rows, and columns. Distributed parity data storage is used to avoid single-point failures. Combined with a hardware-accelerated reconstruction mechanism, cross-layer data recovery is quickly completed when a local fault occurs without affecting the normal access bandwidth of HBMs, thereby improving the reliability and lifespan of HBM devices and reducing production costs.

[0029] This embodiment provides a 3D-RAID cross-layer error correction HBM fault avoidance method.

[0030] See Figure 1 The figure shows that the method includes steps S100, S200, S300 and S400.

[0031] S100. Configure parameters and divide regions for the HBM vertical stacking structure, determine the number of DRAM chip layers L, the number of banks B in each DRAM chip layer, the number of rows R in each bank, and the number of columns C in each row, and construct a four-dimensional storage address system of "layer-bank-row-column"; divide the storage area of ​​each DRAM chip layer into a data storage area and a parity storage area, and distribute the parity storage area evenly to different banks in each layer using a distributed partitioning method; integrate a fault detection module, a parity calculation module, and a data reconstruction module in the buffer die.

[0032] It is understood that step S100 includes S101, S102, and S103, wherein: It should be noted that within the three-dimensional space formed by the vertically stacked multilayer DRAM chips (wafers) of HBM, a 3D-RAID structure based on RAID-5 or RAID-6 is constructed. The parity data is distributed and stored in the non-core storage area of ​​each layer of DRAM chips. Fault detection and cross-layer data reconstruction are realized through hardware acceleration modules. When a fault occurs in a certain layer or a certain local area (bank, row, column), the faulty data is reconstructed by cross-layer parity operation using the distributed storage parity data, so as to quickly avoid local faults. Moreover, the reconstruction process does not occupy normal access bandwidth.

[0033] The specific technical solution is as follows, including the following steps: 1. HBM stacking structure preprocessing (1) Determine HBM stacking parameters: Determine the number of DRAM chip layers in HBM vertical stacking (denoted as L, L≥4, to adapt to the stacking requirements of HBM2 and above), the number of banks in each DRAM chip layer (denoted as B, B≥8), the number of rows in each bank (denoted as R), and the number of columns in each row (denoted as C), forming a four-dimensional storage address system of “layer-bank-row-column”. The address format is defined as “layer number + bank number + row number + column number” to ensure that each storage unit can be uniquely located.

[0034] (2) Divide the storage area: Divide the storage area of ​​each layer of DRAM chip into a data storage area and a parity storage area. The data storage area is used to store the user's original data, and the parity storage area is used to store 3D-RAID parity data. The parity storage area adopts a distributed partitioning method, which does not occupy a single bank or a single area, but is evenly distributed to different banks in each layer. The parity storage area of ​​each bank occupies 5%-10% of the total storage capacity of the bank (which can be adjusted according to the actual fault tolerance requirements), avoiding single point of failure caused by centralized storage of parity data, and does not affect the normal use of the data storage area.

[0035] (3) Interlayer interconnect optimization: Based on the existing TSV vertical interconnect structure of HBM, the interlayer data transmission path is optimized to ensure that the communication delay between each layer of DRAM chip and buffer die is ≤1ns, providing high-speed interconnect support for cross-layer verification and data reconstruction; at the same time, the fault detection module, verification operation module and data reconstruction module are integrated in the buffer die to realize real-time fault detection and fast response. The buffer die adopts a process compatible with the existing HBM, which does not require large-scale modification of the existing stacking process and has good industrialization prospects.

[0036] S200: In the three-dimensional space formed by multi-layer DRAM chips vertically stacked by HBM, a three-dimensional parity structure is constructed based on RAID-5 or RAID-6. The three-dimensional parity groups are divided with "layer-bank-row" as the basic unit. Each parity group covers four dimensions: layer, bank, row, and column, forming a three-dimensional parity network.

[0037] It is understandable that in this step S200, the RAID-5 structure is suitable for single partial fault tolerance scenarios. Each parity group contains L data units and 1 parity unit. The parity unit is the result of the XOR operation of all data units in the group and is stored in a parity storage area of ​​different layer and different bank than the data units in the group using a distributed storage method. The RAID-6 structure is suitable for dual partial fault tolerance scenarios. Each parity group contains L data units and 2 parity units. The two parity units are generated by XOR operation and even parity operation respectively and are stored in parity storage areas of different layer and different bank respectively.

[0038] It should be noted that, based on the three-dimensional stacking space of HBM, the RAID-5 or RAID-6 parity structure is constructed as follows: (1) RAID-5 structure construction (suitable for single local fault tolerance scenarios): Based on the "layer-bank-row" basic unit, a three-dimensional parity check group is constructed. Each parity check group contains L data units and 1 parity check unit, where L is the stacking layer number. Each data unit corresponds to all column data of a certain layer, a certain bank, and a certain row (i.e., a "layer-bank-row" unit). The parity check unit is the XOR operation result (parity check value) of all data units in the group. The parity check unit adopts distributed storage, that is, the parity data of each parity check group is stored in a parity storage area of ​​a different layer and a different bank than the data units in the group, ensuring that the parity data and the corresponding data units are not in the same local area and avoiding simultaneous failure.

[0039] (2) RAID-6 structure construction (suitable for dual partial fault tolerance scenarios): On the basis of RAID-5 structure, an additional parity unit is added to form a parity group of "L data units + 2 parity units"; the two parity units are generated by different parity operation algorithms (such as XOR operation and even parity operation) to achieve fault tolerance for two partial faults (such as simultaneous failure of two layers or simultaneous failure of two different banks), further improving fault tolerance capability; the two parity units also adopt distributed storage and are stored in the parity storage area of ​​different layers and different banks to ensure the reliability of the parity data.

[0040] (3) Full-dimensional coverage design: The verification group is divided into four dimensions: layer, bank, row and column. That is, it not only verifies different layers of data in the same bank and the same row, but also cross-verifies different banks of data in the same layer and the same row, and different rows of data in the same layer and the same bank, forming a three-dimensional verification network. This ensures that when any local area (single layer, single bank, single row / column) fails, the data can be reconstructed through the corresponding verification data. The fault tolerance capability is improved by more than 30% compared with the traditional two-dimensional verification.

[0041] S300. When user data is written to HBM, the parity calculation module performs parity calculations in parallel for each three-dimensional parity check group and generates parity data synchronously. A distributed storage strategy is adopted to store the parity data in the parity storage area of ​​each layer of DRAM chip, so that the parity data of the same parity group is not stored in the layer and bank where the data unit of the group is located. When user data is modified, an incremental update method is adopted to recalculate only the parity value corresponding to the modified data to obtain the updated parity data.

[0042] It is understood that in this step S300, based on the updated verification data, the fault detection module monitors the storage unit status of each layer, each bank, and each row and column in real time at a period of no more than 10ms through at least one of the following methods: data read and write verification, TSV interconnection test, and temperature monitoring, with a detection delay of no more than 0.5ns; when a local fault is detected, the layer number, bank number, row number, column number, and fault type of the fault area are marked, and the TSV is a through silicon via.

[0043] It should be noted that (1) parity data generation: When user data is written to HBM, the parity operation module in the buffer die starts synchronously. For each 3D-RAID parity group, parity operation is performed on all data units in the group (XOR operation for RAID-5, XOR operation + even parity operation for RAID-6) to generate parity data. The parity operation adopts a parallel processing method and is performed synchronously with the data writing process. It does not increase the data writing delay and ensures the normal read and write performance of HBM.

[0044] (2) Distributed storage strategy: The generated verification data is stored in the verification storage area of ​​each layer of DRAM chip according to the preset rules. The specific rules are: the verification data of the same verification group is not stored in the layer and bank where the data unit of the group is located, but is evenly distributed to different banks of other layers; for example, the data unit of a certain verification group is distributed in Bank1 of layer 1 to layer L, and its verification data is stored in Bank2 to BankB of layer 1 to layer L. Each bank stores part of the verification data, realizing the fully distributed storage of verification data, avoiding the loss of verification data due to the failure of a single area, and improving the access efficiency of verification data.

[0045] (3) Verification data update: When user data is modified, the verification calculation module synchronously updates the verification data of the corresponding verification group to ensure the consistency between the verification data and the original data. The update process adopts an incremental update method, which only recalculates the verification value corresponding to the modified data, without recalculating the verification data of the entire verification group, thereby reducing the computational overhead and avoiding affecting the access bandwidth of HBM.

[0046] S400: Based on the updated verification data, the fault detection module monitors the status of storage units in each layer, bank, and row / column in real time. When a local fault is detected, the fault area address is marked and a fault signal is sent to the data reconstruction module. The data reconstruction module locates the corresponding three-dimensional parity check group in the three-dimensional verification network according to the fault area address, calls all intact data units and updated verification data in the check group, reconstructs the failed data of the fault area through parity inverse operation, and temporarily stores the reconstructed data in the cache unit of the buffer die. At the same time, the fault area is marked as failed, and all read and write requests for the fault area are forwarded through the cache unit.

[0047] Understandably, in this step, the data reconstruction module in S400 is based on a three-dimensional parity network. It locates the corresponding three-dimensional parity check group according to the fault area address, and calls the intact data units within the group and the aforementioned updated parity data to perform parity inverse operations. The data reconstruction module adopts a hardware-accelerated architecture design, integrating dedicated computing units and parallel computing architecture, with a reconstruction operation processing capability of 16 bytes per cycle, a reconstruction latency of no more than 2ns, and HBM access bandwidth fluctuation of no more than 2% during the reconstruction process. When a single local fault is detected, the corresponding RAID-5 parity check group is called to perform single parity inverse operation reconstruction; when two local faults are detected, the two parity units in the corresponding RAID-6 parity check group are called to perform double parity inverse operation reconstruction.

[0048] It should be noted that the reconstructed data is temporarily stored in the cache unit of the buffer die, and the faulty area is marked as invalid. Therefore, all read and write requests to this faulty area are forwarded through the cache unit, including: If the faulty area is repaired, the data reconstruction module will write the reconstructed data in the cache unit back to the repaired area, synchronously update the corresponding verification data, remove the fault mark and restore the normal use of the area. If the faulty area cannot be repaired, a redundancy switching mechanism is activated to migrate the storage tasks of the faulty area to other intact storage areas in the three-dimensional parity network. Within the three-dimensional space formed by vertically stacked multi-layer DRAM chips in HBM, a three-dimensional parity structure is constructed based on RAID-5 or RAID-6. The three-dimensional parity groups are divided using "layer-bank-row" as the basic unit. Each parity group covers four dimensions: layer, bank, row, and column, forming a three-dimensional parity network, including: During the fabrication of HBM stacks to build a three-dimensional verification network, process optimization and adaptation are performed. High-precision TSV etching technology and DRAM wafer bonding alignment technology are combined, and interlayer connectivity testing is added. Interlayer connectivity testing is performed after every two DRAM wafers are stacked to identify and avoid potential interlayer interconnection faults. The TSV is a through silicon via.

[0049] Specifically, in this embodiment, (1) fault detection: the fault detection module in the buffer die monitors the storage unit status of each layer, each bank, and each row and column of HBM in real time. It detects local faults (such as storage unit failure, poor TSV contact, bank failure, etc.) in real time through various methods such as data read and write verification, TSV interconnection test, and temperature monitoring. The detection frequency can be adjusted according to actual needs (by default, it is detected once every 10ms). The detection delay is ≤0.5ns to ensure that the fault can be detected quickly. When a fault is detected, the fault detection module immediately marks the address information of the fault area (layer number, bank number, row number, column number) and sends a fault signal to the data reconstruction module, while recording the fault type and fault range.

[0050] (2) Hardware-accelerated reconstruction: The data reconstruction module adopts a hardware-accelerated design, integrating a dedicated computing unit and a parallel computing architecture. Referring to the ECC acceleration engine design concept of NVIDIA H200 GPU, it achieves a reconstruction computing capability of 16 bytes per cycle, compressing the reconstruction latency to within 2ns, and ensuring that the reconstruction process does not affect the normal access bandwidth of HBM (bandwidth fluctuation ≤2%). The reconstruction process is as follows: ① When a single local fault is detected (such as the failure of a Bank in a certain layer), the data reconstruction module locates the corresponding 3D-RAID check group based on the address of the fault area, and calls all intact data units and distributed storage check data in the check group; ② By performing the inverse operation of parity, the failed data in the faulty area can be reconstructed; for example, in a RAID-5 structure, the failed data unit = the XOR operation result of all intact data units ⊕ the check data unit, thus achieving rapid recovery of failed data; ③ After reconstruction is completed, the reconstructed data is temporarily stored in the cache unit of the buffer die, and the faulty area is marked as "failed state". Subsequent read and write requests to this area are forwarded through the cache unit of the buffer die to ensure the continuity of data access. ④ If a dual partial fault is detected (supported only by RAID-6 architecture), two parity units are invoked, and the failed data of the two fault regions is reconstructed through the inverse operation of dual parity, thus achieving dual fault tolerance.

[0051] (3) Fault recovery and redundancy switching: When the faulty area is repaired (such as replacing the failed wafer or repairing the TSV interconnect), the data reconstruction module writes the reconstructed data into the repaired area, updates the verification data, removes the fault mark, and restores the normal use of the area; if the faulty area cannot be repaired, the redundancy switching mechanism is started to migrate the storage tasks of the faulty area to other intact areas to ensure the continuous and stable operation of HBM and further reduce the module scrap rate.

[0052] It is understood that this invention does not require changes to the existing HBM stacking structure, TSV interconnection method, and data read / write protocol. It only requires the addition of three hardware modules in the buffer die: verification operation, fault detection, and data reconstruction. It can be directly integrated into the existing HBM production line and is compatible with multiple generations of products such as HBM2, HBM3, and HBM3E. It does not require large-scale equipment modification and has good compatibility and industrialization feasibility.

[0053] Meanwhile, by optimizing the distributed storage layout of the verification data, access conflicts are reduced; a hardware-accelerated parallel computing architecture is adopted to ensure that the generation and reconstruction of verification data do not occupy the normal access bandwidth of HBM. Actual tests show that during the fault reconstruction process, the access bandwidth of HBM remains above 98% of the nominal bandwidth, with a bandwidth difference of ≤2% compared to the fault-free state; at the same time, the fault detection algorithm is optimized to reduce detection overhead and ensure that the read and write latency of HBM is not affected.

[0054] Furthermore, by combining high-precision TSV etching technology (aperture deviation less than 0.1 micrometers) with DRAM wafer bonding alignment technology (alignment deviation less than 0.2 micrometers), the initial defect rate is reduced; and an "interlayer connectivity test" is added during the stacking process, which is performed after every two DRAM wafers are stacked, to detect interlayer interconnection faults in advance, further improving the reliability of HBM.

[0055] Example 2:

[0056] like Figure 2 As shown, this embodiment provides a 3D-RAID cross-layer error correction HBM fault avoidance system. See [link to documentation]. Figure 2 The system includes: Partitioning Module 701: Used for parameter configuration and region partitioning of the HBM vertical stacking structure, determining the number of DRAM chip layers L, the number of banks B in each DRAM chip layer, the number of rows R in each bank, and the number of columns C in each row of the HBM vertical stacking, and constructing a four-dimensional storage address system of "layer-bank-row-column"; dividing the storage area of ​​each DRAM chip layer into a data storage area and a parity storage area, with the parity storage area evenly distributed to different banks in each layer using a distributed partitioning method; integrating a fault detection module, a parity calculation module, and a data reconstruction module in the buffer die; Verification construction module 702: Used to construct a three-dimensional parity structure based on RAID-5 or RAID-6 in the three-dimensional space composed of multi-layer DRAM chips vertically stacked in HBM. The three-dimensional parity groups are divided with "layer-bank-row" as the basic unit. Each parity group covers four dimensions: layer, bank, row, and column, forming a three-dimensional parity network. The calculation and update module 703 is used to perform parity operations in parallel for each three-dimensional parity check group when user data is written to HBM, and synchronously generate parity data; it adopts a distributed storage strategy to store the parity storage area of ​​each layer of DRAM chip, so that the parity data of the same parity group is not stored in the layer and bank where the data unit of the group is located; when user data is modified, it adopts an incremental update method to recalculate only the parity value corresponding to the modified data to obtain the updated parity data; Data Reconstruction Module 704: Based on the updated verification data, the fault detection module monitors the storage unit status of each layer, each bank, and each row and column in real time. When a local fault is detected, the fault area address is marked and a fault signal is sent to the data reconstruction module. According to the fault area address, the data reconstruction module locates the corresponding three-dimensional parity check group in the three-dimensional verification network, calls all intact data units and updated verification data in the check group, reconstructs the failed data of the fault area through parity inverse operation, and temporarily stores the reconstructed data in the cache unit of the buffer die. At the same time, the fault area is marked as failed, and all read and write requests for the fault area are forwarded through the cache unit.

[0057] Specifically, it also includes a redundancy switching module 705, which is signal-connected to the data reconstruction module 704. Once the faulty area is repaired, the data reconstruction module writes the reconstructed data from the cache unit back to the repaired area and updates the corresponding verification data, thus removing the fault marker. When a faulty area cannot be repaired, the redundancy switching module migrates the storage tasks of the faulty area to other intact storage areas in the three-dimensional verification network.

[0058] Specifically, it also includes a process optimization and adaptation module 706: the process optimization and adaptation module is used to combine high-precision TSV etching technology with DRAM wafer bonding alignment technology, and to perform inter-layer connectivity testing after every 2 layers are completed in the wafer stacking process corresponding to the construction of the three-dimensional verification network, thereby checking inter-layer interconnection faults; the buffer die adopts a process compatible with the existing HBM, and the system as a whole is adapted to HBM2, HBM3 and subsequent generations of vertical stacked DRAM architecture, wherein the TSV is a through silicon via.

[0059] It should be noted that the specific methods by which each module performs operations in the system described in the above embodiments have been described in detail in the embodiments related to the method, and will not be elaborated here.

[0060] Example 3:

[0061] Corresponding to the above method embodiments, this embodiment also provides a 3D-RAID cross-layer error correction HBM fault avoidance device. The 3D-RAID cross-layer error correction HBM fault avoidance device described below and the 3D-RAID cross-layer error correction HBM fault avoidance method described above can be referred to in correspondence.

[0062] Figure 3 This is a block diagram illustrating a 3D-RAID cross-layer error correction HBM fault avoidance device 800 according to an exemplary embodiment. Figure 3 As shown, the 3D-RAID cross-layer error correction HBM fault avoidance device 800 includes a processor 801 and a memory 802. The 3D-RAID cross-layer error correction HBM fault avoidance device 800 also includes one or more of a multimedia component 803, an I / O interface 804, and a communication component 805.

[0063] The processor 801 controls the overall operation of the 3D-RAID cross-layer error correction HBM fault avoidance device 800 to complete all or part of the steps in the aforementioned 3D-RAID cross-layer error correction HBM fault avoidance method. The memory 802 stores various types of data to support the operation of the 3D-RAID cross-layer error correction HBM fault avoidance device 800. This data may include, for example, instructions for any application or method operating on the 3D-RAID cross-layer error correction HBM fault avoidance device 800, as well as application-related data such as contact data, sent and received messages, images, audio, video, etc. The memory 802 can be implemented using any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The multimedia component 803 may include a screen and an audio component. The screen may be, for example, a touchscreen, and the audio component is used to output and / or input audio signals. For example, the audio component may include a microphone for receiving external audio signals. The received audio signals may be further stored in the memory 802 or transmitted via the communication component 805. The audio component also includes at least one speaker for outputting audio signals. I / O interface 804 provides an interface between processor 801 and other interface modules, such as keyboards, mice, or buttons. These buttons can be virtual or physical. Communication component 805 is used for wired or wireless communication between the 3D-RAID cross-layer error correction HBM fault avoidance device 800 and other devices. Wireless communication includes, for example, Wi-Fi, Bluetooth, Near Field Communication (NFC), 2G, 3G, or 4G, or a combination thereof. Therefore, the corresponding communication component 805 may include a Wi-Fi module, a Bluetooth module, or an NFC module.

[0064] In an exemplary embodiment, the 3D-RAID cross-layer error correction HBM fault avoidance device 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the 3D-RAID cross-layer error correction HBM fault avoidance method described above.

[0065] In another exemplary embodiment, a computer-readable storage medium including program instructions is also provided. When executed by a processor, these program instructions implement the steps of the 3D-RAID cross-layer error correction HBM fault avoidance method described above. For example, the computer-readable storage medium may be the memory 802 including the program instructions described above. These program instructions may be executed by the processor 801 of the 3D-RAID cross-layer error correction HBM fault avoidance device 800 to complete the 3D-RAID cross-layer error correction HBM fault avoidance method described above.

[0066] Example 4:

[0067] Corresponding to the above method embodiments, this embodiment also provides a readable storage medium. The readable storage medium described below can be referred to in conjunction with the 3D-RAID cross-layer error correction HBM fault avoidance method described above.

[0068] A computer program is stored on a readable storage medium, and when the computer program is executed by a processor, it implements the steps of the 3D-RAID cross-layer error correction HBM fault avoidance method of the above method embodiment.

[0069] Specifically, the readable storage medium can be a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, or any other readable storage medium capable of storing program code.

[0070] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A 3D-RAID cross-tier error correction HBM fault avoidance method, characterized in that, include: The parameters of the HBM vertical stacking structure are configured and the area is divided to determine the number of DRAM chip layers L, the number of banks B in each DRAM chip layer, the number of rows R in each bank, and the number of columns C in each row, thus constructing a four-dimensional storage address system of "layer-bank-row-column". The storage area of ​​each DRAM chip layer is divided into a data storage area and a parity storage area. The parity storage area is evenly distributed to different banks in each layer using a distributed partitioning method. A fault detection module, a parity calculation module, and a data reconstruction module are integrated into the buffer die. Within the three-dimensional space formed by vertically stacked multilayer DRAM chips in HBM, a three-dimensional parity check structure is constructed based on RAID-5 or RAID-6. The three-dimensional parity check groups are divided with "layer-bank-row" as the basic unit. Each parity check group covers four dimensions: layer, bank, row, and column, forming a three-dimensional parity check network. When user data is written to HBM, the parity calculation module performs parity calculations in parallel for each three-dimensional parity check group, and generates parity data synchronously. A distributed storage strategy is adopted to store the parity data in the parity storage area of ​​each layer of DRAM chip, so that the parity data of the same parity group is not stored in the layer and bank where the data unit of the group is located. When user data is modified, an incremental update method is used to recalculate only the parity value corresponding to the modified data to obtain the updated parity data. Based on the updated verification data, the fault detection module monitors the status of storage units in each layer, bank, and row and column in real time. When a local fault is detected, the fault area address is marked and a fault signal is sent to the data reconstruction module. The data reconstruction module locates the corresponding three-dimensional parity check group in the three-dimensional verification network according to the fault area address, calls all intact data units and updated verification data in the check group, reconstructs the failed data of the fault area through parity inverse operation, and temporarily stores the reconstructed data in the cache unit of the buffer die. At the same time, the fault area is marked as failed, and all read and write requests for the fault area are forwarded through the cache unit.

2. The 3D-RAID cross-tier error correction HBM fault avoidance method of claim 1, wherein, In the three-dimensional parity network: the RAID-5 structure is suitable for single local fault tolerance scenarios. Each parity group contains L data units and 1 parity unit. The parity unit is the result of the XOR operation of all data units in the group and is stored in a parity storage area of ​​different layer and different bank than the data units in the group using a distributed storage method; the RAID-6 structure is suitable for dual local fault tolerance scenarios. Each parity group contains L data units and 2 parity units. The two parity units are generated by XOR operation and even parity operation respectively and are stored in parity storage areas of different layer and different bank respectively.

3. The 3D-RAID cross-layer error correction HBM fault avoidance method according to claim 1, characterized in that, In the three-dimensional verification network, the verification storage area of ​​each Bank occupies 5% to 10% of the total storage capacity of the Bank; the distributed storage strategy is as follows: the verification data of the same verification group avoids the layer and Bank where the data unit of the group is located, and is evenly distributed to the verification storage areas of different Banks in other layers for distributed storage.

4. The 3D-RAID cross-layer error correction HBM fault avoidance method according to claim 1, characterized in that, Based on the updated verification data, the fault detection module monitors the status of storage units in each layer, each bank, and each row and column in real time through at least one of the following methods: data read / write verification, TSV interconnection test, and temperature monitoring, with a detection delay of no more than 0.5ns. When a local fault is detected, the layer number, bank number, row number, column number, and fault type of the fault area are marked. The TSV is a through-silicon via.

5. The 3D-RAID cross-layer error correction HBM fault avoidance method according to claim 1, characterized in that, The data reconstruction module is based on a three-dimensional parity network. It locates the corresponding three-dimensional parity check group based on the fault area address, and calls the intact data units within the group, along with the previously updated parity data, to perform the inverse parity operation. The data reconstruction module adopts a hardware-accelerated architecture design, integrating dedicated computing units and a parallel computing architecture. It has a reconstruction processing capability of 16 bytes per cycle, a reconstruction latency of no more than 2ns, and HBM access bandwidth fluctuations of no more than 2% during the reconstruction process. When a single local fault is detected, the corresponding RAID-5 parity check group is called to perform a single parity inverse operation reconstruction. When two local faults are detected, two parity units in the corresponding RAID-6 parity check group are called to perform a double parity inverse operation reconstruction.

6. The 3D-RAID cross-layer error correction HBM fault avoidance method according to claim 1, characterized in that, The reconstructed data is temporarily stored in the cache unit of the buffer die, and the faulty area is marked as invalid. Therefore, all read and write requests to this faulty area are forwarded through the cache unit, including: If the faulty area is repaired, the data reconstruction module will write the reconstructed data in the cache unit back to the repaired area, synchronously update the corresponding verification data, remove the fault mark and restore the normal use of the area. If the faulty area cannot be repaired, a redundancy switching mechanism is activated to migrate the storage tasks of the faulty area to other intact storage areas in the three-dimensional verification network.

7. The 3D-RAID cross-layer error correction HBM fault avoidance method according to claim 1, characterized in that, Within the three-dimensional space formed by vertically stacked multilayer DRAM chips in HBM, a triple parity check structure is constructed based on RAID-5 or RAID-6. The triple parity check groups are divided using "layer-bank-row" as the basic unit. Each parity group covers four dimensions: layer, bank, row, and column, forming a three-dimensional parity network, including: During the fabrication of HBM stacks to build a three-dimensional verification network, process optimization and adaptation are performed. High-precision TSV etching technology and DRAM wafer bonding alignment technology are combined, and interlayer connectivity testing is added. Interlayer connectivity testing is performed after every two DRAM wafers are stacked to identify and avoid potential interlayer interconnection faults. The TSV is a through silicon via.

8. A 3D-RAID cross-layer error correction HBM fault avoidance system, based on the 3D-RAID cross-layer error correction HBM fault avoidance method according to claim 1, characterized in that, include: The partitioning module is used to configure parameters and partition regions for the HBM vertical stacking structure, determining the number of DRAM chip layers L, the number of banks B in each DRAM chip layer, the number of rows R in each bank, and the number of columns C in each row, thus constructing a four-dimensional storage address system of "layer-bank-row-column". It divides the storage area of ​​each DRAM chip layer into a data storage area and a parity storage area, with the parity storage area evenly distributed across different banks in each layer using a distributed partitioning method. A fault detection module, a parity calculation module, and a data reconstruction module are integrated into the buffer die. Verification building module: Used to build a three-dimensional parity structure based on RAID-5 or RAID-6 in the three-dimensional space composed of multi-layer DRAM chips vertically stacked in HBM. The three-dimensional parity groups are divided with "layer-bank-row" as the basic unit. Each parity group covers four dimensions: layer, bank, row, and column, forming a three-dimensional parity network. The calculation and update module is used to perform parity operations in parallel for each three-dimensional parity check group when user data is written to HBM, and synchronously generate parity data. A distributed storage strategy is adopted to store the parity data in the parity storage area of ​​each layer of DRAM chip, so that the parity data of the same parity group is not stored in the layer and bank where the data unit of the group is located. When user data is modified, an incremental update method is used to recalculate only the parity value corresponding to the modified data to obtain the updated parity data. Data Reconstruction Module: Based on the updated verification data, the fault detection module monitors the storage unit status of each layer, bank, and row / column in real time. When a local fault is detected, the fault area address is marked and a fault signal is sent to the data reconstruction module. The data reconstruction module locates the corresponding three-dimensional parity check group in the three-dimensional verification network according to the fault area address, calls all intact data units and updated verification data in the check group, and reconstructs the failed data of the fault area through parity inverse operation. The reconstructed data is temporarily stored in the cache unit of the buffer die, and the fault area is marked as failed. Thus, all read and write requests for the fault area are forwarded through the cache unit.

9. The 3D-RAID cross-layer error correction HBM fault avoidance system according to claim 8, characterized in that, It also includes a redundancy switching module, which is signal-connected to the data reconstruction module. Once the faulty area is repaired, the data reconstruction module writes the reconstructed data from the cache unit back to the repaired area and updates the corresponding verification data, thus removing the fault marker. When a faulty area cannot be repaired, the redundancy switching module migrates the storage tasks of the faulty area to other intact storage areas in the three-dimensional verification network.

10. The 3D-RAID cross-layer error correction HBM fault avoidance system according to claim 8 or 9, characterized in that, It also includes a process optimization and adaptation module: The process optimization and adaptation module is used to combine high-precision TSV etching technology with DRAM wafer bonding and alignment technology. During the wafer stacking process corresponding to the construction of the three-dimensional verification network, inter-layer connectivity test is performed after every 2 layers of stacking is completed, thereby checking inter-layer interconnection faults. The buffer die uses a process compatible with existing HBM, and the system as a whole is adapted to HBM2, HBM3 and subsequent generations of vertically stacked DRAM architectures; the TSV is a through silicon via.

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