Test method, device and equipment of storage chip and storage medium

Abstract

This invention provides a testing method, apparatus, device, and storage medium for memory chips. It acquires a set of failure addresses generated by multi-level test vector testing of the memory chip under test; constructs a failure texture map data structure based on the spatial distribution and failure mode markings of the failure physical addresses; extracts failure density description information and dominant failure mode markings within the local neighborhood of each failure physical address; packages failure physical addresses with similar dominant failure mode markings and spatially continuous distribution into repair candidate packages based on defect propagation law constraints; acquires the segmented layout information of redundant resources; matches the repair candidate packages with redundant resource segments to generate a repair resource segment allocation table; and generates segmented repair control instructions accordingly. Overlapping read / write operations are applied at the segment boundaries for stress verification; after successful verification, the segmented repair control instructions are solidified and written into a non-volatile repair control information storage area. This invention can improve the utilization rate and reliability of memory chip repair resources.

Description

Technical Field

[0001] This invention relates to the fields of chip testing and electrical data processing, and in particular to a testing method, apparatus, device, and storage medium for memory chips. Background Technology

[0002] Built-in self-healing in memory chips involves replacing and repairing faulty memory cells discovered during testing using redundant row or column resources after chip manufacturing. Currently, this typically involves obtaining the faulty addresses generated during memory cell testing, constructing a repair analysis matrix to characterize the conflict relationships between faulty addresses (whether they can be jointly repaired by the same redundant resources), and using a heuristic algorithm to solve the repair analysis matrix to obtain a repair scheme for each faulty address allocated to redundant row or column resources. Finally, repair control instructions are generated and the repair scheme is written into the chip's non-volatile memory area. However, this approach treats each faulty address as an isolated repair object, failing to connect the distribution texture characteristics of faulty addresses in the memory array space with the intrinsic relationship between their failure causes. This leads to fragmentation of redundant resources during the repair allocation process, limiting their utilization, and the repaired chip still has potential reliability issues under complex operating conditions. Summary of the Invention

[0003] This invention provides a testing method, apparatus, device, and storage medium for memory chips.

[0004] In a first aspect, embodiments of the present invention provide a testing method for a memory chip, comprising: The set of failure addresses generated after the memory chip under test is tested by a multi-level set of test vectors containing different defect sensitization conditions is obtained. Each physical failure address in the set of failure addresses is accompanied by a failure mode marker. Based on the spatial distribution of the failed physical addresses in the failed address set within the storage array and their respective failure mode labels, a failure texture map data structure is constructed. The failure texture map data structure contains tile nodes indexed by the failed physical address. Each tile node covers descriptive information of the failure density within a preset address neighborhood centered on the failed physical address and statistical information of the dominant failure mode label within that neighborhood. Repair groups are packaged based on the defect expansion law constraint on the failure texture map data structure to generate a repair candidate package that merges multiple failure physical addresses that meet the same defect type label and whose spatial location is continuously distributed along the defect expansion direction. Obtain the segmented redundancy layout information of the internal redundant resources of the tested memory chip after being divided by the segmented decoding circuit. The segmented redundancy layout information includes the row address range driven by each redundant row resource physical segment and the column address range driven by each redundant column resource physical segment. Based on the segmented redundancy layout information, match the repair candidate packets with the redundant resource segments and output the repair resource segment allocation table. A set of segmented repair control instructions is generated based on the repair resource segment allocation table. Each instruction in the set of segmented repair control instructions records the number of the replacement resource that is enabled in the redundant resource segment, the range of the address range to be replaced, and the effective polarity of the segment enable signal. The contents of the repair resource segment allocation table are called to guide the temporary repair logic circuit built into the memory chip under test to apply overlapping read and write operations at the segment boundary. The stress verification test is performed on the address interval adjacent to the segment boundary to obtain the segment boundary stress test result set. When the segment boundary stress test result set indicates that no new failure address has been generated in the boundary overlapping area, the segment repair control instruction set is solidified and written into the non-volatile repair control information storage area of ​​the memory chip under test.

[0005] Secondly, embodiments of the present invention provide a testing apparatus for a memory chip, comprising: The data acquisition module is used to acquire the set of failure addresses generated after the memory chip under test is tested by a multi-level test vector set containing different defect sensitization conditions. Each failure physical address in the set of failure addresses is accompanied by a failure mode marker. The structure construction module is used to construct a failure texture map data structure based on the spatial distribution of the failed physical addresses in the failure address set within the storage array and their respective failure mode labels. The failure texture map data structure contains tile nodes indexed by the failed physical address. Each tile node covers descriptive information of the failure density within a preset address neighborhood centered on the failed physical address and statistical information of the dominant failure mode label within that neighborhood. The data packaging module is used to package the failure texture map data structure into repair groups based on the constraint of defect expansion law, and generate a repair candidate package by merging multiple failure physical addresses that meet the same defect type label and whose spatial location is continuously distributed along the defect expansion direction. The resource matching module is used to obtain the segmented redundancy layout information of the redundant resources inside the tested memory chip after being divided by the segmented decoding circuit. The segmented redundancy layout information includes the row address range driven by each redundant row resource physical segment and the column address range driven by each redundant column resource physical segment. Based on the segmented redundancy layout information, the repair candidate package is matched with the redundant resource segments, and the repair resource segment allocation table is output. The instruction generation module is used to generate a set of segmented repair control instructions based on the repair resource segment allocation table. Each instruction in the segmented repair control instruction set records the number of the replacement resource that is enabled in the redundant resource segment, the range of the address range to be replaced, and the effective polarity of the segment enable signal. The verification test module is used to call the contents of the repair resource segment allocation table to guide the temporary repair logic circuit built into the memory chip under test to apply overlapping read and write operations at the segment boundary, perform stress verification tests on the adjacent address intervals of the segment boundary, and obtain the segment boundary stress test result set. When the segment boundary stress test result set indicates that no new failure addresses have been generated in the boundary overlapping area, the segment repair control instruction set is solidified and written into the non-volatile repair control information storage area of ​​the memory chip under test.

[0006] Thirdly, embodiments of the present invention provide a testing device, including a memory and a processor. The memory stores a computer program that can run on the processor, and the processor executes the program to implement the steps in the above method.

[0007] Fourthly, embodiments of the present invention provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps in the above method.

[0008] This invention obtains a set of failure addresses carrying failure mode markers, directly associating the spatial location of the physical failure address with the defect sensitization condition category. By constructing a failure texture map data structure, it uses failure density description information within local neighborhoods and dominant failure mode markers to jointly characterize the texture features of the failure distribution, transforming discrete failure points into spatial texture expressions with defect type tendencies. Based on this, repair groups are packaged according to defect expansion rules, grouping failure addresses that conform to the same defect type and are continuously distributed along the defect expansion direction into repair candidate packages. This allows redundant resources to be allocated in units of continuous defect segments, overcoming resource fragmentation caused by isolated address repair. Repair candidate packages and redundant resource segments are precisely matched in address intervals based on segmented redundancy layout information, avoiding decoding conflicts and routing detours caused by cross-segment replacement. Overlapping read / write pressure verification without waiting cycles is applied at the segment boundaries of the temporary repair logic circuit. Repair instructions are only solidified and written to the non-volatile memory area when no new failure addresses are generated in the boundary overlap area, thereby ensuring the repair reliability of weak links in segment handover and improving the accuracy and long-term operational stability of memory chip repair. Attached Figure Description

[0009] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present invention and, together with the specification, serve to explain the technical solutions of the present invention.

[0010] Figure 1This is a schematic diagram illustrating the principle of a testing method for a memory chip provided in an embodiment of the present invention.

[0011] Figure 2 This is a schematic diagram illustrating the implementation process of a testing method for a memory chip provided in an embodiment of the present invention.

[0012] Figure 3 This is a schematic diagram of the composition structure of a chip testing device provided in an embodiment of the present invention.

[0013] Figure 4 This is a schematic diagram of the hardware entity of a testing device provided in an embodiment of the present invention. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on the present invention. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of the invention.

[0016] This invention provides a testing method for memory chips, which can be executed by the processor of a testing device. The testing device can refer to a data processing device such as a server, laptop, or desktop computer.

[0017] Please refer to Figure 1 In the embodiment of the present invention, firstly, a set of failure addresses carrying failure mode markers is obtained, generated by multi-level test vector detection; then, a failure texture map data structure is constructed, and the failure density and dominant failure mode markers in the local neighborhood are extracted with each failure physical address as the center; based on the failure texture information and the constraint of defect expansion law, failure addresses with the same defect type and spatially continuous distribution are packaged into repair candidate packages; subsequently, the segmented layout information of redundant resources inside the chip is obtained, and the repair candidate packages are matched with the redundant resource segments to form a repair resource segment allocation table, and a set of segmented repair control instructions recording the replacement resource number, address range and enable signal is generated accordingly; finally, the overlapping read and write pressure is applied to the segment boundary using temporary repair logic for verification, and after confirming that there are no new failures, the instructions are solidified to the non-volatile memory area to complete the high-reliability permanent repair.

[0018] The following is combined Figure 2 The implementation process is illustrated in detail with a diagram, such as... Figure 2As shown, the method includes the following steps S100~S600: Step S100: Obtain the set of failure addresses generated after the memory chip under test is tested by a multi-level test vector set containing different defect sensitization conditions. Each failure physical address in the failure address set is accompanied by a failure mode marker. The failure mode marker is used to indicate the defect sensitization condition category corresponding to the test vector type that detected the failure physical address.

[0019] A multi-level test vector set is an ordered set of test vectors that differ from each other in timing parameters, access sequences, data flip patterns, and voltage bias conditions. Each set of test vectors specifically creates a particular type of defect sensitization condition within the memory array, forcing potential physical defects from a latent state to functional failures that can be captured by external test equipment. Defect sensitization conditions generally refer to the combination of electrical stresses and time window constraints applied to induce specific physical defects to expose observable faults. Specific manifestations include the delay of the word line activation pulse relative to the bit line precharge pulse, a deliberately shortened turnaround period between written and read data, consecutive reverse flip sequences on adjacent memory cells, amplitude offset of the word line boost voltage, and disturbance amplitude of the substrate bias voltage. The failure physical address is the precise location coordinate of the memory cell in the physical topology of the memory array, determined by the automated test equipment after executing the test vectors and comparing the output response. This coordinate is uniquely determined by three dimensions: memory cell number, row address, and column address. It does not correspond to a logical address but directly corresponds to the three-dimensional physical arrangement of the memory cells on the silicon wafer. Failure mode markers are attribute codes recorded along with each failed physical address. These codes have a one-to-one mapping relationship with a certain level of test vector in the multi-level test vector set, thus semantically binding the failed physical address with the defect sensitization condition category detected at that address. Different defect sensitization condition categories point to different defect root cause types, such as bit line short circuit, word line open circuit, storage capacitor leakage, and adjacent cell coupling interference.

[0020] When acquiring the set of failure addresses generated after the memory chip under test has undergone multi-level test vector set testing, the automated test equipment places the memory chip under test in the electrical connection environment between the test head and the test interface board. The main control module of the test equipment loads the multi-level test vector set from the test program memory into the vector generator in a preset order. The first-level test vector is configured to sensitize the inter-word line bridging defect. Its core parameters include compressing the interval between word line activation and word line pre-charging to below the critical lower limit of the design specification, while writing an all-one pattern to all even-numbered column addresses and an all-zero pattern to all odd-numbered column addresses on a background of all zeros. This causes the memory cells controlled by adjacent word lines to experience different voltage swings in a short period of time, maximizing the parasitic capacitive coupling effect between word lines. The vector generator drives the address and data combination to the address and data buses of the memory chip under test in burst mode. At the end of each read cycle, the comparator array of the test equipment latches the read data bit by bit from the chip's output port and performs an XOR comparison with a pre-calculated expected data vector based on the write pattern by the test program. Any bit in the XOR result that is logic high indicates that the corresponding memory cell has exhibited a functional failure in this test. For each bit failure that occurs during the execution of the first-level test vector, the failure address acquisition circuit of the test equipment synchronously captures the current memory bank number, row address, and column address from the address generator, and reads the defect sensitization condition category code to which the currently executed test vector type belongs from the vector configuration register. This category code is appended as a failure mode marker to the end of the data structure of the captured failure physical address to obtain a complete failure record entry.

[0021] After the first-level test vector is executed and the resulting failure record entries are cached in the acquisition memory, the test equipment automatically switches to the second-level test vector. This second-level test vector aims to sensitize storage capacitor leakage defects. Its defect sensitization condition is set by pre-writing a checkerboard data pattern in all memory cells, followed by pausing the refresh operation for a hold time far exceeding the refresh cycle allowed by the device datasheet. After the hold time expires, continuous readings are performed from low to high addresses according to the same address sequence as the writing order. Any memory cell where the read data does not match the written checkerboard pattern due to capacitor charge leakage is identified as a failed physical address and is marked with a failure mode flag indicating the sensitization condition category of the storage capacitor leakage defect. The third-level test vector applies a complementary flipped data sequence at half the system clock frequency to adjacent bit line pairs. The latching action of the sense amplifier is initiated before the bit line pre-charge balancing circuit has fully recovered. Utilizing the charge-sharing effect of the inter-bit line parasitic capacitance, the weak cell data is overwritten in reverse, thereby detecting inter-bit line coupling defects. The corresponding failed physical address is marked with a failure mode flag indicating the sensitization condition category of the inter-bit line coupling defect. Similarly, each subsequent test vector constructs a series of non-overlapping defect sensitization conditions by changing parameters such as the row address transition sequence, the setup time of the column address decoder pre-decoding signal, the delay of the sensitivity amplifier enable signal, and the duration of the write recovery operation.

[0022] After all levels of the multi-level test vector set have been executed, a complete set of failure addresses has been accumulated in the memory of the automated test equipment. Each record in the set contains a physical failure address consisting of a memory bank number, row address, and column address, as well as a failure mode flag closely associated with the detection condition. This set of failure addresses is uploaded as a whole data block through the test interface bus to the engineering analysis workstation used for subsequent failure texture analysis and repair resource allocation.

[0023] Step S200: Based on the spatial distribution of the failed physical addresses in the failed address set within the storage array and their respective failure mode markers, construct a failure texture map data structure. The failure texture map data structure contains tile nodes indexed by the failed physical address. Each tile node covers descriptive information of the failure density within a preset address neighborhood centered on the failed physical address and statistical information of the dominant failure mode markers within that neighborhood.

[0024] The failure texture graph data structure is a non-Euclidean graph data structure built on the three-dimensional address coordinate system of the storage array. Its topological vertices are not abstract semantic nodes, but rather anchor points directly located at the physical addresses of failures within the three-dimensional address grid. By encoding the failure distribution density and dominant failure mode categories within the local spatial neighborhood of the anchor points, it structures the spatial clustering characteristics of discrete failure points, the local tendency of defect types, and the continuity information of the failure texture into a high-order graph representation that can be traversed, searched, and clustered. Patch nodes are the basic topological units in the failure texture graph data structure; their unique index key directly takes the three-dimensional coordinates of a physical address of a failure, without using additional hash mapping or numbering assignment. Each tile node carries a data payload containing at least two components: First, a description of failure density, representing the ratio of the number of grid cells marked as failed within a preset address neighborhood centered on the tile node's index address to the total number of grid cells within that neighborhood, reflecting the density of local failure clusters. Second, statistical information on dominant failure mode markings, calculated by frequency analysis of all grid cells carrying failure mode markings within the same preset address neighborhood, reflecting the dominant defect sensitization condition characteristics of that local area. The preset address neighborhood is a rectangular sampling window controlled by a half-window width parameter. The window's extension range in the row and column directions is determined by a first preset number and a second preset number, respectively, correspondingly determining the number of row address steps extending upwards and downwards along the row axis centered on the current failure physical address, and the number of column address steps extending left and right along the column axis.

[0025] In an exemplary embodiment, step S200 may specifically include the following steps S210 to S260: Step S210: Perform address space mapping projection on the set of failed addresses, divide the failed physical addresses into the three-dimensional address grid of the memory array according to their memory bank location, row address and column address, mark the grid cell position occupied by each failed physical address and its associated failure mode label in the three-dimensional address grid, and obtain a marked failure grid map.

[0026] Address space mapping projection is based on the topological organization of the physical memory array—a memory chip contains multiple memory banks, each a separate two-dimensional subarray. Within the subarray, word lines define the row address dimension, bit lines define the column address dimension, and the memory bank number constitutes the third dimension. The three-dimensional address grid is a mathematical reconstruction of this physical topology. Its data structure can be implemented using a three-dimensional array. The first-dimensional index traverses the memory bank number, the second-dimensional index traverses the row address, and the third-dimensional index traverses the column address. Each element of the array is a grid cell, initialized to empty. The mapping projection operation essentially parses the discrete field group of each record in the failure address set into integer coordinates in a three-dimensional coordinate system, and marks the failure state and additional failure mode on the corresponding grid cell in the three-dimensional array. During the traversal of the failure address set, for each record read, the analysis program in the engineering analysis workstation extracts its memory bank number component as the first-dimensional index value of the three-dimensional array, its row address component as the second-dimensional index value, and its column address component as the third-dimensional index value, accurately locating the unique grid cell in the three-dimensional address grid. If the grid cell was not previously marked as having a failure status, its status value is rewritten from the default empty value to a valid failure value, and the binary code of the failure mode marker in the record is written into the marker field of the grid cell. If the grid cell was previously marked as having a failure, and the failure mode marker recorded this time is different from the existing marker, the previous priority rule determines whether to overwrite or retain it. Usually, the failure mode marker that was detected first is retained to reflect the location priority of the earliest sensitization condition for that address. After processing all records in the set of failure addresses, each physical location in the 3D address grid where a test failure has occurred obtains a non-empty failure status indication and a corresponding failure mode marker, resulting in a marked failure grid diagram.

[0027] Step S220: For each marked grid cell in the marked failure grid diagram, extract the local neighborhood window formed by the grid cell as the center, extending a first preset number of grid cells along the row direction and a second preset number of grid cells along the column direction, to obtain the texture sampling window of the grid cell.

[0028] The first preset quantity defines the half-width of the texture sampling window in the row direction. This quantity is equal to both the number of row address steps sampled upwards from the central grid cell and the number of row address steps sampled downwards. Therefore, the row span of the window is the sum of the first preset quantity of rows above the central row, the central row itself, and the first preset quantity of rows below the central row. Similarly, the second preset quantity defines the half-width of the window in the column direction. The column span of the window is the sum of the second preset quantity of columns from the left, the central column itself, and the second preset quantity of columns from the right. The extraction principle centered on this grid cell means that for each grid cell in the marked failure grid diagram that has been assigned a valid failure state, the analysis program uses the coordinates of that grid cell as the reference origin to determine the rectangular boundary of the texture sampling window. If the row start coordinate obtained by subtracting the first preset quantity from the row coordinates of the current central grid cell is less than the minimum row address index of the 3D address grid, the actual row start coordinate of the window is truncated to zero. If the row end coordinate obtained by adding the first preset quantity to the row coordinates of the central grid cell exceeds the maximum row address index of the 3D address grid, the actual row end coordinate of the window is truncated to that maximum index value. The column coordinates are also subject to fully symmetrical boundary constraints to ensure that the texture sampling window always falls within the legal address space of the storage array and does not access out-of-bounds addresses.

[0029] After performing the boundary calculations on each failed grid cell in the marked failure mesh map, the analysis program reads the state information and failure mode marker information of each grid cell within the rectangular area enclosed by the row start coordinates, row end coordinates, column start coordinates, and column end coordinates from the marked failure mesh map. This information, along with the window size and the offset of the window center relative to the original failed grid cell, is packaged and attached to the currently processed failed grid cell, thus completing the instantiation of the texture sampling window for that failed grid cell. For failed grid cells located near the physical boundary of the storage array, their texture sampling window will asymmetrically cover only the actual existing address range; the window area is smaller than a two-dimensional fully internal window, but the total number of grid cells contained within is still accurately recorded.

[0030] Step S230: Calculate the ratio of the number of mesh cells marked as failure state in the texture sampling window to the total number of mesh cells in the window, use this ratio as the failure density description information of the texture sampling window, and count the failure mode marker that appears most frequently in the window as the dominant failure mode marker.

[0031] The number of grid cells in a failed state is determined by iterating through all grid cells within the texture sampling window constructed in step S220, querying the state value of each grid cell one by one, and performing an incrementing count operation on grid cells whose state value equals the valid failure value. The count value stored in the accumulator after the traversal is the number of grid cells marked as failed. The total number of grid cells within the window is the total number of grid cells actually contained in the rectangular area of ​​the texture sampling window. When the window boundary is not truncated, this total number is equal to the product of the row span and the column span. When the window is truncated, it is the product of the actual number of sampled rows and the actual number of sampled columns after truncation. The ratio obtained by dividing the former by the latter is directly used as the failure density description information of the texture sampling window. This ratio is an unsigned decimal between 0 and 1. A value close to 0 indicates that the failure distribution in the area where the window is located is extremely sparse, while a value close to 1 indicates that a large number of failure points are highly concentrated in the area where the window is located, exhibiting a high-density failure cluster texture.

[0032] The process of identifying the most frequent failure mode marker within the statistics window is based on a frequency statistics mapping table where failure mode marker category is the key and frequency of occurrence is the value. During the traversal of all mesh cells within the texture sampling window, for each mesh cell with a valid failure value, the analysis program reads its associated failure mode marker and increments the corresponding counter value in the frequency statistics mapping table by 1. After one traversal, the frequency statistics mapping table records the total number of occurrences of each failure mode marker within the window. The analysis program then employs a comparison-by-comparison method to obtain the maximum value: First, the failure mode marker of the first entry in the frequency statistics map is set as the candidate dominant marker, and its frequency count value is set as the current maximum frequency value. Next, the failure mode markers and their frequency values ​​for subsequent entries in the frequency statistics map are retrieved sequentially. For each retrieved entry, its frequency value is compared with the current maximum frequency value. If the newly retrieved frequency value is strictly greater than the current maximum frequency value, the candidate dominant marker is replaced with the failure mode marker of that entry, and the current maximum frequency value is updated to match the entry's frequency value. If the newly retrieved frequency value is equal to the current maximum frequency value, the original candidate dominant marker remains unchanged, or in another variant, the encoded values ​​of the two markers are compared, and the smaller encoded value is used as the new candidate dominant marker to provide a deterministic tie-breaking rule. After all entries have been traversed, the final retained candidate dominant marker is identified as the dominant failure mode marker, which reflects the statistically dominant defect sensitization condition category within the local window.

[0033] In an exemplary embodiment, step S230 may specifically include the following steps S231 to S236: Step S231: Read the row coordinate range and column coordinate range of the grid cells covered by the texture sampling window, and generate a window grid coordinate traversal sequence. The window grid coordinate traversal sequence contains an ordered combination of the row coordinates and column coordinates of all grid cells in the window.

[0034] The process of reading the row and column coordinate ranges involves directly extracting the row start coordinates, row end coordinates, column start coordinates, and column end coordinates—defined during the construction phase—from the metadata of the texture sampling window. The analysis program generates a two-dimensional nested loop output sequence based on these four boundary values: the outer loop variable sequentially takes each integer row coordinate value from the row start coordinate to the row end coordinate; for each iteration of the outer loop, the inner loop variable sequentially takes each integer column coordinate value from the column start coordinate to the column end coordinate. Each time, the inner and outer loops combine to form an ordered pair of row and column coordinates, which is appended to the end of the window grid coordinate traversal sequence in this order. This ordered combination completely covers all grid cells selected by the texture sampling window, and the traversal sequence is arranged in row-major order: first, all column positions in the first row of the window are traversed, then all column positions in the second row are traversed, and so on, until the last row of the window. The generation of the window grid coordinate traversal sequence ensures that the access to grid cells within the window in subsequent statistical steps is deterministic, ordered, and without duplication or omission.

[0035] Step S232: Extract the grid cell coordinates one by one according to the window grid coordinate traversal sequence, query whether there is a failure status mark at the coordinate position of the marked failure grid diagram, and record the query results.

[0036] The analysis program maintains a read pointer to the window grid coordinate traversal sequence. Starting from the first row and column coordinate pair at the beginning of the sequence, it uses the row coordinate as the second-dimensional index, the column coordinate as the third-dimensional index, and the memory cell number to which the currently failed grid cell belongs as the first-dimensional index to access the corresponding grid cell in the three-dimensional address grid. If the status field of the grid cell is not empty, i.e., a failure status marker exists, the query result is considered true; otherwise, the query result is false. The query results are sequentially stored in a Boolean intermediate record table of the same length as the window grid coordinate traversal sequence. The position indexes of this intermediate record table correspond strictly one-to-one with the position indexes of the window grid coordinate traversal sequence, ensuring that subsequent readings of query results can unambiguously associate true or false values ​​back to the corresponding grid cell coordinates.

[0037] Step S233: Maintain an accumulator for the number of occurrences of failed grid cells and a recorder for the frequency of occurrence of each failure mode tag category. When the query result indicates that the current grid cell has a failure status tag, the count value of the accumulator is incremented. At the same time, the failure mode tag attached to the grid cell is read, and the count value of the recorder of the corresponding category is incremented.

[0038] The accumulator is implemented as an unsigned integer variable, initialized to 0. The frequency recorder for each failure mode marker category can employ an associative data structure, which maps each possible failure mode marker category to an independent integer counter. During implementation, this data structure can be a key-value storage structure, where the key is the binary code of the failure mode marker and the value is the current cumulative occurrence count; or it can be a fixed-length integer array pre-allocated based on the total number of failure mode markers, using the marker code directly as the array index, eliminating the key-value lookup step. The analysis program increments the accumulator by 1 for each grid cell whose query result recorded in step S232 is true, using the failure mode marker code of that grid cell as an index to increment the corresponding counter in the associative data structure. Once the Boolean intermediate record table is fully processed, the total value in the accumulator represents the total number of failure grid cells within the window, and the frequency recorder for each failure mode marker category stores fine-grained distribution statistics of different defect sensitization condition categories within the window.

[0039] Step S234: After the window grid coordinate traversal sequence has been traversed, read the final count value of the accumulator, divide the final count value by the total number of grid cells in the texture sampling window, and store the result value in the failure density description information field.

[0040] The analysis program retrieves the final count value representing the number of mesh cells marked as failed within the window from the accumulator. Simultaneously, it reads the product of the row and column spans of the window from the texture sampling window's metadata as the total number of mesh cells. When performing division, it's crucial to ensure computational precision; a double-precision floating-point divider can be used to obtain a floating-point result between 0 and 1. This result is then directly written into the failure density description field of the current tile node, serving as a key quantitative basis for subsequent repair group packaging and defect spatial distribution analysis.

[0041] Step S235: Read the failure mode tag category corresponding to the maximum count value in the frequency recorder of each failure mode tag category, determine the failure mode tag category as the dominant failure mode tag, and store it in the dominant failure mode tag field.

[0042] The analysis program initializes a variable to temporarily store the current maximum frequency value and assigns the occurrence frequency value of the first failure mode marker category to this variable. Simultaneously, it assigns the code of the first failure mode marker category to another variable temporarily storing candidate dominant markers. Subsequently, the program iterates through all remaining failure mode marker categories, performing the following operations for each category: comparing its occurrence frequency value with the current maximum frequency value; if its occurrence frequency value is strictly greater than the current maximum frequency value, then the frequency value of that category is assigned to the current maximum frequency value variable, and the marker code of that category is assigned to the candidate dominant marker variable; otherwise, the original maximum frequency value and candidate dominant marker remain unchanged. Once the iteration through all categories is complete, the failure mode marker category stored in the candidate dominant marker variable is the category with the highest occurrence frequency within the window, officially determined as the dominant failure mode marker, and written to the corresponding field of the current tile node.

[0043] In an exemplary embodiment, step S235 may specifically include the following steps S2351 to S2356: Step S2351: Obtain all failure mode marker categories that have been statistically obtained from the texture sampling window, establish a category list, and extract the occurrence frequency values ​​in the same order based on the occurrence frequency recorder of each failure mode marker category to form a category-frequency correspondence array.

[0044] The analysis program iterates through the frequency recorders for each failure mode tag category, extracting all failure mode tag categories with non-zero occurrences. These categories are then sorted in ascending order of their category codes to form a category list, where each item in the list represents a failure mode tag code. Simultaneously, based on the order of items in the category list, the corresponding frequency values ​​are read from the frequency recorders and populated into a frequency array of the same length. The two arrays maintain a logical correspondence between categories and frequencies, resulting in a logical array that maps categories to frequencies.

[0045] Step S2352: Set the first category in the category-frequency correspondence array as the current candidate category, set its occurrence frequency value as the current maximum frequency value, and compare the occurrence frequency values ​​of subsequent categories with the current maximum frequency value in turn.

[0046] Step S2353: During the comparison process, if the occurrence frequency value of a certain subsequent category exceeds the current maximum frequency value, then the subsequent category is updated as the current candidate category, and the current maximum frequency value is refreshed with the occurrence frequency value; otherwise, the original candidate category and the maximum frequency value are retained.

[0047] Steps S2352 and S2353 are combined to implement a deterministic algorithm for finding the maximum value of a linear scan. This ensures that even if multiple categories appear with the same frequency, the first category in the category list is always selected as the dominant category, or a reproducible tie-breaking choice is made based on the size of the encoded value, thus avoiding non-deterministic statistical results.

[0048] Step S2354: After comparing all categories, the current candidate category that is finally retained is identified as the dominant failure mode label, and the failure mode code corresponding to the dominant failure mode label is written into the dominant failure mode label field.

[0049] Step S2355: Simultaneously extract the current maximum frequency value as the dominant frequency, divide the dominant frequency by the total number of failed mesh cells in the window to obtain the dominant concentration information, and simultaneously record the dominant concentration information into the texture attribute field.

[0050] The dominance concentration information characterizes the proportion of dominant failure mode markers in the group of failure mesh cells within the window. It is calculated by dividing the frequency of occurrence of the dominant failure mode marker by the final count value of the accumulator in step S234. This ratio also ranges from 0 to 1; a value closer to 1 indicates higher purity of the failure mode marker type within the window, and a more singular and concentrated failure mode; a value closer to 0 indicates that multiple failure mode markers appear mixed within the window, lacking a single dominant type. This dominance concentration information is recorded as a subfield of the tile node texture attribute field, providing a complete statistical characterization of the window texture along with the dominant failure mode markers.

[0051] Step S2356: Bind the texture attribute field, which consists of the dominant failure mode marker field and the dominant concentration information, to the index address of the current tile node, and update the attribute entry of the corresponding tile node in the failure texture map data structure.

[0052] The analysis program uses a triplet consisting of the memory cell number, row address, and column address of the currently failed mesh cell as the unique index address of the tile node. It then searches the failure texture map data structure to see if an entry with that index already exists. If it does, the texture attribute field of the entry is overwritten with the latest calculated dominant failure mode flag and dominant concentration information. If it does not yet exist, a new tile node record is created, and the index address and texture attribute fields are written to it. This binding operation ensures a strong and consistent association between each tile node and its corresponding physical address and local failure texture information within the data structure.

[0053] Step S236: Merge the failure density description information field and the dominant failure mode marker field into the texture attribute field of the texture sampling window and attach it to the currently processed tile node.

[0054] The analysis program encapsulates the failure density description information obtained in step S234 and the dominant failure mode marker obtained in step S235 into a structure, generating a texture attribute field data block with two fixed member fields. This texture attribute field is then directly written into the payload area of ​​the tile node indexed by the physical address of the currently processed failure mesh cell, completing the transformation from discrete failure mesh coordinates to graph structure vertices carrying local spatial statistical characteristics. After this mounting action is completed, the current tile node possesses failure texture information that can be directly used for subsequent defect propagation law constraint packaging processing.

[0055] Step S240: Create a tile node indexed by the physical address of the mesh cell, and store the failure density description information and dominant failure mode marker of the texture sampling window into the texture attribute field of the tile node to complete the construction of the tile node corresponding to the failure physical address.

[0056] During the creation of a tile node, the analysis program first uses a combination of the storage cell number, row address, and column address of the current failed mesh cell as the unique identifier for that tile node in the failure texture map data structure. This identifier serves a dual role as both the identity label of the graph vertex and the storage addressing key. Before adding a new node to the node container of the failure texture map data structure, an existence check is performed to avoid duplicate creation. If the check shows that the index address is not yet bound to any tile node, a new tile node instance is allocated in the node container, the index address is assigned to the node's index attribute, and the texture attribute field containing the failure density description information and the dominant failure mode marker obtained in step S236 is stored in the texture attribute area of ​​the node instance through data copying. If a tile node with the same index address already exists, only its texture attribute field is updated to keep the texture attribute as the result of the latest sampling calculation. Once the tile node is created, it signifies that an observation vertex with a local spatial statistical description has been established for the physical failure location in the vertex set of the failure texture map data structure.

[0057] Step S250: Repeat the operations of texture sampling window extraction, failure density description information statistics, dominant failure mode marking statistics, and tile node construction for each marked mesh cell in the marked failure mesh map to generate a set of tile nodes corresponding to all failure physical addresses.

[0058] The analysis program maintains a loop whose control logic traverses all grid cells in the marked failure mesh graph in memory order, row address incrementing order, and column address incrementing order. Whenever a grid cell is detected as having a valid failure state, it is immediately designated as the current processing center, sequentially invoking the texture sampling window extraction function in step S220, the failure density description information and dominant failure mode marking statistics function in step S230, and the tile node construction and mounting function in step S240. Since the texture sampling windows of different failure mesh cells may overlap, the calculation process is executed independently for each failure mesh cell, without window reuse or cache fusion, to ensure that each tile node carries neighborhood statistical features centered on its own index address, without distortion due to the processing order of adjacent failure physical addresses. After the entire marked failure mesh graph has been completely scanned, the node container of the failure texture graph data structure contains tile nodes corresponding one-to-one with each failure physical address in the failure address set, resulting in a complete tile node set.

[0059] Step S260: Perform boundary node marking operation on the tile nodes in the tile node set. If the texture sampling window of a certain tile node overlaps with the physical boundary of the storage array or the boundary of the storage volume, set a boundary adjacent identifier in the tile node, and merge all tile nodes and their associated relationships into a failed texture map data structure.

[0060] Physical boundaries refer to the insurmountable address edges formed by the minimum and maximum limits of the row address range and the minimum and maximum limits of the column address range of the entire memory chip. Memory bank boundaries are natural isolation surfaces between different memory banks; the row and column addresses of different memory banks are physically discontinuous. Boundary truncation was performed during the extraction of the texture sampling window in step S220. In this step S260, the analysis program checks whether the texture sampling window corresponding to each tile node experienced boundary truncation in the row or column direction during its generation process. The determination method is to compare the original requested half-width range of the texture sampling window during its construction phase with the final actual row and column spans: if the actual covered row span is smaller than the row span that should have been truncated, or the actual covered column span is smaller than the column span that should have been truncated, it indicates that the texture sampling window of the tile node overlaps with the physical boundary of the memory array. Furthermore, if the window's neighborhood in the memory bank dimension involves cross-memory access and is prohibited, this is also considered an overlap of memory bank boundaries. For a tile node that meets any of the above conditions, the analysis program sets a boundary adjacency identifier in the attribute region of its payload. This identifier occupies one Boolean width and marks it as a boundary adjacency node. This serves as a reminder to the subsequent repair group packaging algorithm to consider the truncation asymmetry of local spatial texture information caused by boundary effects when processing this node. After all tile nodes have completed boundary checks and label writing, the analysis program serializes and outputs all tile nodes together with their association relationships established in step S250 using index addresses as the primary key, forming the final failure texture map data structure, which is then delivered to step S300.

[0061] Step S300: Pack the failure texture map data structure into repair groups based on the constraint of defect expansion law, and generate a repair candidate package by merging multiple failure physical addresses that meet the same defect type label and whose spatial location is continuously distributed along the defect expansion direction. The repair candidate package is attached with defect type label and packaging boundary address.

[0062] The constraint of defect propagation patterns refers to the specific directional preferences and continuity characteristics of the growth and spread patterns of different types of physical defects in the memory array space. For example, leakage paths caused by lattice dislocations are usually distributed continuously along the word line extension direction, while bit line bridging caused by photoresist residue tends to extend continuously along the bit line direction. Short-circuit defects between adjacent word lines may repeat along the row address direction at fixed step intervals. The purpose of repair grouping is to make full use of this continuity pattern of spatial directional propagation. Multiple failed physical addresses belonging to the same defect type and arranged continuously in space along the main or secondary propagation direction at allowable address step intervals are aggregated into a whole repair candidate package. This allows for replacement in subsequent redundant resource allocation on a whole package basis, rather than consuming valuable redundant row or column resources on a single isolated failed unit basis, thereby significantly improving the utilization efficiency of repair resources. A repair candidate package is a logical group output by the packaging operation. It contains a set of spatially contiguous failure physical addresses that are consistent in their defect type labels. The package is bounded by packaging boundary addresses, which indicate the minimum row start address, maximum row end address, minimum column start address, and maximum column end address occupied by the failure physical addresses within the package. The defect type labels originate from the failure mode markers of the seed nodes during the packaging process and are used to provide the overall defect repair strategy type that the repair candidate package should follow in the redundant resource allocation decision.

[0063] In an exemplary embodiment, step S300 may specifically include the following steps S310 to S360: Step S310: Read the dominant failure mode marker of each tile node in the failure texture map data structure, group the tile nodes with the same dominant failure mode marker into the same node subgroup, and determine the primary and secondary expansion directions corresponding to each dominant failure mode marker according to the preset defect expansion direction mapping relationship.

[0064] The dominant failure mode (DFM) flag of a tile node is retrieved directly from the texture attribute field of each tile node, using the DFM flag encoding stored in the previous step. The analysis program creates a grouped dictionary data structure with the DFM flag encoding as the key and a list of tile node pointers as the value. It iterates through all tile nodes in the failure texture graph data structure, extracting the DFM flag encoding for each visited tile node. The corresponding tile node pointer list is then searched in the grouped dictionary using this encoding as the key. If the list is not yet initialized, an empty list is allocated, and the pointer of the current tile node is appended to this list. After the traversal is complete, each entry in the grouped dictionary corresponds to a node subgroup, and all tile nodes within this subgroup share the same DFM flag.

[0065] The preset defect propagation direction mapping relationship is a pre-fixed mapping table. Each record in this table associates a failure mode label category with a primary propagation direction and a secondary propagation direction. The primary propagation direction is the direction in which the defect category is most likely to extend continuously in space, taking only two categories: along the row direction or along the column direction. The secondary propagation direction is the orthogonal direction of the primary propagation direction. When the primary propagation direction is the row direction, the secondary propagation direction is the column direction, and vice versa. The mapping table is constructed based on prior knowledge from device physical failure analysis. Specifically, for the failure mode label corresponding to word line bridging defects, the mapping table sets its primary propagation direction to the column direction because in word line bridging failures, a defect on a word line will simultaneously affect the positions of multiple bit lines that the word line passes through, exhibiting continuity along the column direction, i.e., along the bit line direction. For the failure mode label corresponding to bit line short circuit defects, the mapping table sets its primary propagation direction to the row direction because a bit line short circuit will trigger a cascading failure between memory cells with the same column address but different row addresses, exhibiting continuity along the row address direction. After the analysis program reads the dominant failure mode flag of the current node subgroup, it looks up the main expansion direction and secondary expansion direction of the subgroup according to this table and passes them to subsequent steps S320 and S330 for use.

[0066] Step S320: Within each node subgroup, based on the storage location of the failed physical address of the tile node index, tile nodes belonging to the same storage are further divided into body-level node pools, and each body-level node pool independently performs subsequent packaging operations.

[0067] The partitioning process based on storage location uses the storage bank number field in the tile node index address for hash grouping. For each node subgroup formed in step S310, the analysis program creates a new two-level grouping structure, with the storage bank number as the key in its outer layer. It iterates through each tile node in the subgroup, reads the storage bank number from its index address, and adds the tile node to the corresponding storage bank number's level node pool. Thus, even if the physical addresses of failures from different storage banks are identical in the dominant failure mode labeling category, their subsequent packing operations are strictly limited to within their respective storage banks. This is because redundant row and column resources between storage banks are independent of each other; cross-storage bank packing does not aid in repair and violates resource usage constraints.

[0068] Step S330: For any body-level node pool, select the tile node that has not yet been merged into any repair candidate package and has the highest row address as the seed node. Search in the body-level node pool along the main expansion direction for tile nodes that have the same dominant failure mode marker and present a continuous address interval with the seed node in the row or column direction, and connect them in sequence to form a candidate chain.

[0069] In a given pool of volume-level nodes, the analysis program first sorts all its tile nodes in ascending order by row address as the primary sorting key and column address as the secondary sorting key, resulting in an ordered list. The program scans from the head of this ordered list, skipping all tile nodes already marked as merging into a certain repair candidate package, and selects the first unmerged tile node encountered as the seed node. Once the seed node is selected, the main expansion direction is determined in step S310: if the main expansion direction is row-oriented, then in the ordered list, among the tile nodes whose column address is fixed to the column address of the seed node, subsequent tile nodes with the same dominant failure mode marker are searched in ascending order of row address, and the matching tile nodes are concatenated after the seed node in ascending order of address; if the main expansion direction is column-oriented, then the row address is fixed, and the search and concatenation are performed in ascending order of column address. During the search process, the row and column addresses of the current chain tail node are compared with the corresponding addresses of the next candidate node. When the step interval formed by the address difference falls within the allowable range preset in step S340, the candidate node is added to the end of the candidate chain, and the candidate node is used as the new chain tail for the next round of search. If the address difference exceeds the allowable range, the extension along the current chain stops, and a candidate chain is generated.

[0070] Step S340: Verify whether the address interval between adjacent tile nodes in the candidate chain meets the preset step interval allowable range of the defect type corresponding to the seed node, retain the tile nodes that meet the allowable range in the candidate chain, and remove the tile nodes that exceed the allowable range to obtain continuous defect segments.

[0071] The allowable step interval is a set of constraint parameters closely related to the defect type, specifying the maximum legal address jump distance in both the row and column address directions for consecutive failures caused by the same defect type. For ideal continuum defects, the allowable step interval can be defined as a maximum address interval of one in both the row and column directions, meaning adjacent nodes must be strictly adjacent in both rows and columns. For dispersed failures caused by periodic structural defects, the allowable maximum address interval in the row direction may be relaxed to conform to the regular periodicity of the pattern defect. The analysis program performs address interval verification on each pair of adjacent nodes of the candidate chain generated in step S330.

[0072] In an exemplary embodiment, step S340 may specifically include the following steps S341 to S346: Step S341: Retrieve the defect step interval tolerance table corresponding to the dominant failure mode flag of the seed node. This defect step interval tolerance table defines the maximum allowable address interval in the row direction and the maximum allowable address interval in the column direction for each defect type.

[0073] The defect step interval tolerance table is stored in the configuration space of the analysis software as a direct-addressable memory or register array, using failure mode tag codes as index addresses. The analysis program uses the dominant failure mode tag code of the seed node to perform a lookup operation on this table, reading the maximum address interval parameter value in the row direction and the maximum address interval parameter value in the column direction corresponding to the defect type at once, and storing them in two local variables for repeated use in steps S342 to S345.

[0074] Step S342: Take out two adjacent tile nodes from the candidate chain in sequence, read the row address and column address of the previous node and the row address and column address of the subsequent node respectively, and calculate the difference between the row address and the column address.

[0075] The row address difference is calculated by subtracting the row address of the previous node from the row address of the next node and taking the absolute value of the difference. The column address difference is calculated in the same way, that is, by taking the absolute value of the difference between the column address of the next node and the column address of the previous node.

[0076] Step S343: When the row address difference exceeds the maximum allowed address interval in the row direction or the column address difference exceeds the maximum allowed address interval in the column direction, record the position of the next node in the candidate chain as the chain truncation position, and mark the next node as a breakpoint.

[0077] Step S344: Define all tile nodes before the discontinuity as a continuous defect segment along the concatenation order of the candidate chain, and retain the record of all tile nodes in the chain for the continuous defect segment. At the same time, move the discontinuity and all subsequent tile nodes into the unclassified node buffer.

[0078] The unclassified node buffer is a temporary container for a set of tile nodes that have not yet been assigned a segment due to being truncated in the candidate chain. These nodes will be reconsidered and packaged in subsequent seed node selection iterations.

[0079] Step S345: If no discontinuity is found after traversing all adjacent tile nodes in the candidate chain, the entire candidate chain is defined as a continuous defect segment.

[0080] Step S346: For the tile nodes identified as continuous defect segments, clear the corresponding node records from the unclassified node buffer, output the node list and start and end addresses of the continuous defect segment, and complete the acquisition of a continuous defect segment.

[0081] The start and end addresses of a segment are determined based on the row and column addresses of the first and last nodes within the continuous defect segment, thus obtaining the minimum and maximum values ​​of the row address and the minimum and maximum values ​​of the column address of the segment.

[0082] Step S350: Use the physical addresses of the tile nodes at both ends of the continuous defect segment as the packaging boundary address, generate a repair candidate package for the failure physical address corresponding to all tile nodes in the continuous defect segment, and attach the defect type label obtained by the failure mode label conversion dominated by the seed node, and store the repair candidate package into the repair candidate package set.

[0083] The packaging boundary address is a set of row and column boundary descriptions that define the smallest rectangular area covered by the repair candidate package in the storage array space. The defect type label is directly derived from the dominant failure mode marker of the seed node and adopts the same encoding system as the failure mode marker to ensure semantic consistency between the multi-level test vector detection stage and the repair packaging stage. The generated repair candidate package is added as an independent entry to the repair candidate package set, which will contain a complete partition of repair candidate packages covering the failure addresses of the entire tested memory chip by the end of step S300.

[0084] In an exemplary embodiment, step S350 may specifically include the following steps S351 to S356: Step S351: Extract the physical addresses of the first and last nodes in the list of continuous defect segment nodes, take the row address of the first node as the row start address, take the row address of the last node as the row end address, compare the column addresses of the first and last nodes, take the smaller column address as the column start address, and take the larger column address as the column end address.

[0085] Step S352: Generate row boundary descriptors in the packing boundary address based on row start address and row end address, and generate column boundary descriptors in the packing boundary address based on column start address and column end address, and combine them to form a complete packing boundary address.

[0086] The row boundary descriptor is a structure containing a start row address field and an end row address field, and the column boundary descriptor is a structure containing a start column address field and an end column address field. When combined, the two can unambiguously describe the rectangular occupancy area of ​​the repair candidate packet in the storage array.

[0087] Step S353: Aggregate the failed physical addresses of all tile nodes within the continuous defect segment into an address group, and traverse each address in the address group to store the physical location of each failed physical address and the defect type label associated with the continuous defect segment in the group record.

[0088] Address groups are implemented in the form of compact arrays or linked lists. Each record contains the complete memory bank number, row address, column address, and corresponding defect type label for the failed physical address, providing a fine-grained list of replacement addresses for subsequent redundant resource allocation.

[0089] Step S354: Check if there is redundant resource allocation selection information in the address group that simultaneously contains row repair availability and column repair availability. If so, mark the dual-resource repair option in the repair candidate package; otherwise, mark the single-resource repair option according to the direction of the continuous defect segment along the main expansion direction.

[0090] The information on available redundant resource allocation for row repair and column repair is a repair capability configuration determined during the memory chip design phase. This information is used by the analysis tool to determine whether the candidate repair package has the capability to select a row replacement scheme, a column replacement scheme, or both. If a continuous defect segment is repairable in both row and column directions, a dual-resource repair option is marked; if only the directional component along the main expansion direction has available redundant resources, a single-resource repair option is marked according to that direction.

[0091] Step S355: Generate the defect type label for the repair candidate package, and encapsulate the defect type label, packaging boundary address, address group and repair options into a repair candidate package record.

[0092] Step S356: After the packaging operation of all body-level node pools is completed, summarize all repair candidate package records to obtain the repair candidate package set.

[0093] Step S360: For the remaining tile nodes in the body-level node pool that have not yet been merged, repeat the process of seed node selection, candidate chain generation, continuous defect segment acquisition and repair candidate package generation until all tile nodes in the body-level node pool have been assigned to a certain repair candidate package.

[0094] Within each body-level node pool, the analysis program tracks the packaging status of each tile node by maintaining a global merged flag table. After each round of seed node selection and candidate chain generation is completed and a repair candidate package is output, the merged flag of all tile nodes covered by the repair candidate package is set to true. In the next packaging iteration, a new seed node is selected from those tile nodes whose merged flags are still false, and the subsequent operations are repeated until the merged flags of all tile nodes in the body-level node pool are set to true, at which point the packaging process terminates for that body-level node pool.

[0095] Step S400: Obtain the segmented redundancy layout information of the internal redundant resources of the tested memory chip after being divided by the segmented decoding circuit. The segmented redundancy layout information includes the row address range driven by each redundant row resource physical segment and the column address range driven by each redundant column resource physical segment. Match the repair candidate packet with the redundant resource segments according to the segmented redundancy layout information and output the repair resource segment allocation table.

[0096] Segmented decoding circuitry is a group of logic circuits integrated into the address path within the memory chip. It is used to split a complete row or column address into multiple segments, each driving an independent set of redundant resources. This ensures that a redundant row resource does not globally replace any row address, but is limited to a specific row address physical segment; similarly, a redundant column resource only provides replacement functionality within a specific column address segment. Segmented redundancy layout information is a complete description of this resource segmentation pattern, explicitly listing the row start and end address ranges driven by each redundant row resource physical segment, and the column start and end address ranges driven by each redundant column resource physical segment. The repair resource segment allocation table is the final output allocation scheme record table. Each record records the binding relationship between a repair candidate package and a selected redundant row or column resource segment, the specific number of resource entries allocated within that segment, and the enabled intra-segment resource number information.

[0097] In an exemplary embodiment, step S400 may specifically include the following steps S410 to S460: Step S410: Read the segmented decoding input signal line definition of all redundant row resources in the bit width from the configuration register or hard-line preset of the memory chip under test, parse the number of row segments and the address bit ranges participating in decoding in each row segment, and obtain the row segment address range list.

[0098] Configuration registers are a set of non-volatile memory cells within a memory chip, addressable and readable via a test access port. They store redundant resource allocation information written during the chip's factory configuration phase. Hard-line presets refer to fixed logic states pulled high or low internally via selective metal layer connections, directly determining the redundant resource segmentation pattern without relying on register writes. Domain definitions describe which bits in the row address bus width are used as decoding selection bits for redundant row segments and which are used as selection bits within the segment. The analysis program sends a sequence of configuration read instructions to the chip through the test access port, reads a configuration word of several words from the target address of the configuration register, and then performs bit segmentation on the configuration word according to the bit field distribution diagram published in the memory chip design manual. For example, it extracts several high-order bits from the configuration word to obtain the number of bits for the row segment decoding, which directly determines the total number of row segments. Then, based on the wiring relationship of the segment decoding bits in the row address bus, it is known that each segment corresponds to a specific combination of row address high-order segments, thereby parsing out the start address and end address of each row segment. Finally, these start addresses and end addresses are organized into a row segment address range list in the order of segment numbers.

[0099] Step S420: Read the segmented decoding input signal lines of all redundant column resources in the bit width and parse the number of column segments and the address bit ranges participating in decoding in each column segment to obtain the column segment address range list.

[0100] The logic and steps of reading and parsing S410 are exactly the same in processing row direction resources, except that the operation object is changed to the segmented decoding configuration word of redundant column resources and its corresponding column address bus bit field definition, which ultimately forms a column segmented address range list.

[0101] Step S430: For each repair candidate packet in the repair candidate packet set, extract the row boundary descriptor and column boundary descriptor of its packaging boundary address. Compare the row boundary descriptor with the row segment address range list one by one, and select the row segments whose row boundary descriptors fall completely within their address range as candidate row segments. Compare the column boundary descriptors with the column segment address range list one by one, and select the column segments whose column boundary descriptors fall completely within their address range as candidate column segments.

[0102] In an exemplary embodiment, step S430 involves comparing each row boundary descriptor with the row segment address range list to select row segments whose row boundary descriptors fall entirely within their address ranges as candidate row segments. This may specifically include the following steps S431 to S436: Step S431: Extract the row start address and row end address from the row boundary descriptor of the repair candidate packet to form a row address interval segment.

[0103] Step S432: Sequentially obtain a row segment entry from the row segment address range list. The row segment entry records the row segment start address and the row segment end address.

[0104] Step S433: Compare the starting address of the row address range with the starting address of the row segment, and at the same time compare the ending address of the row address range with the ending address of the row segment.

[0105] The comparison operation is implemented using a digital comparator, which outputs the Boolean truth value of the comparison result of the row start address and the Boolean truth value of the comparison result of the row end address. Both Boolean truth values ​​must be true for the condition to be met.

[0106] Step S434: If the row start address is not less than the row segment start address and the row end address is not greater than the row segment end address, then the row segment is determined to be a candidate row segment, and the segment identifier of the row segment is added to the candidate row segment list.

[0107] Step S435: If the row start address is less than the row segment start address or the row end address is greater than the row segment end address, then the row segment is determined not to meet the complete inclusion condition and the row segment is skipped.

[0108] Step S436: Traverse all row segment entries in the row segment address range list, perform a one-to-one comparison between the row boundary descriptor and all row segments, and output a candidate row segment list for subsequent selection of redundant row resource segments.

[0109] Step S440: Combining the dual-resource repair option or single-resource repair option markings of the repair candidate package, if row repair is marked as allowed, calculate the number of row addresses to be replaced based on the packaging boundary address of the repair candidate package as the row repair requirement quantity, select a redundant row resource segment from the candidate row segments with an internal free redundant row resource number not less than the row repair requirement quantity, and record its segment identifier and the number of row resources to be allocated in the allocation entry; if column repair is marked as allowed, calculate the number of column addresses to be replaced based on the packaging boundary address of the repair candidate package as the column repair requirement quantity, select a redundant column resource segment from the candidate column segments with an internal free redundant column resource number not less than the column repair requirement quantity, and record its segment identifier and the number of column resources to be allocated in the allocation entry.

[0110] The row repair requirement is calculated by subtracting the row start address from the row end address in the row boundary descriptor and adding 1, representing the number of row addresses required to replace the candidate repair package. The number of internal free redundant row resources in each candidate row segment is obtained by querying a dynamically maintained segment resource occupancy status table. This table is initialized with the total number of redundant resources per segment at the start of the allocation process, and the allocated amount is gradually deducted as the allocation operation progresses. If row repair is marked as allowed but none of the candidate row segments meets the requirement of having internal free resources equal to or greater than the row repair requirement, a splitting strategy is triggered. The candidate repair package is then truncated along the row boundary direction into multiple sub-packages with smaller row requirements, and the segmentation matching operation is re-performed on the sub-packages. The allocation logic used when column repair is marked as allowed is completely symmetrical to the row direction.

[0111] In an exemplary embodiment, step S440 may specifically include the following steps S441 to S446: Step S441: Read the segment identifier of each candidate row segment in the candidate row segment list, query the segment resource occupancy status table, and obtain the number of redundant row resources currently occupied by each candidate row segment.

[0112] The segmented resource occupancy status table uses the segment identifier as the primary key. Each record maintains the number of redundant row resource entries allocated within that segment and the physical location number of each allocated resource. The analysis program uses the segment identifier to perform a key lookup in this table to retrieve the current occupancy value.

[0113] Step S442: Subtract the number of currently occupied redundant row resources from the total capacity of segmented redundant row resources to obtain the number of internal free resources for each candidate row segment.

[0114] The total capacity of segmented redundant line resources is the number of hard lines fixed in the design of each segment. The analysis program has recorded this in the segment information list during the parsing phase of step S410 or S420, and it can be retrieved directly.

[0115] Step S443: Obtain the number of row repair requirements calculated based on the packaging boundary address of the repair candidate package, and compare it with the number of internal free resources of each candidate row segment. Select the candidate row segments whose number of internal free resources is not less than the number of row repair requirements as available row segments.

[0116] Step S444: For the selected available row segments, calculate the difference between the number of idle resources within each segment and the number of row repair requirements as the remaining resource margin, and extract the continuity of the physical location number of the idle resources within each available row segment as continuity description information.

[0117] The continuity of the physical location number of the idle resource describes the length of the continuous segment of the physical group number of the redundant row resources that have not been occupied in the segment in the number field. The longer the continuous segment, the more compact the idle resources in the segment are, which is beneficial to maintaining the continuity of address decoding and signal integrity after replacement.

[0118] Step S445: Based on the remaining resource balance and continuity description information, select the available row segment with the smallest remaining resource balance and the highest continuity description information as the selected redundant row resource segment from the available row segments, and write its segment identifier and the set of physical location numbers of the free resources within the segment corresponding to the number of row repair requirements into the allocation preparation entry.

[0119] The priority selection logic is to first minimize the remaining resource margin, so that resource allocation closely matches the demand and avoids large segments of resources being fragmented and occupied by small demand packages; when the remaining resource margin is the same, prioritize segments with higher continuity of idle resources to reserve better continuous idle resource reserves for subsequent large package allocation.

[0120] Step S446: When none of the candidate row segments meet the condition that the number of internal free resources is not less than the number of row repair requirements, generate an abnormal indication of insufficient segment resources, and split the repair candidate package into multiple sub-packages according to the row boundary and re-execute segment matching.

[0121] The splitting strategy starts from the beginning address of the row of the candidate repair packet, and each time a continuous address segment within the row boundary is extracted. The length of the segment is taken as the maximum number of rows with no more than the number of free resources inside any candidate segment, thus generating the first sub-packet. The remaining row address portion continues to be extracted using the same strategy to extract subsequent sub-packets until the entire row address range of the candidate repair packet is covered by sub-packets. The split sub-packets are then re-sent into the candidate segment matching process.

[0122] Step S450: Write the segment identifier of the selected redundant resource segment, the starting number of the enabled resources within the segment, the packaging boundary address of the repair candidate package, and the defect type label into an allocation record. All allocation records corresponding to the repair candidate packages form a repair resource segment allocation table.

[0123] The starting number of the enabled resources within a segment comes from the initial value of the set of physical location numbers of the free resources written in the allocation preparation entry in step S445. The packaging boundary address and defect type label are directly copied from the repair candidate package record. After each repair candidate package is allocated, the allocation record is appended to the end of the dataset of the repair resource segment allocation table.

[0124] Step S460: In the repair resource segment allocation table, for multiple repair candidate packages that occupy the same redundant resource segment, adjust the allocation order of their intra-segment resource numbers according to the priority of the defect type label, and update the adjusted allocation order to the repair resource segment allocation table.

[0125] The priority of defect type tags is determined by a pre-defined priority decision list. This list sorts defect type tags according to the severity of the defect's impact on the chip's long-term reliability. For example, tags for storage capacitor leakage defects are given higher priority, tags for word line bridging defects are given the next highest priority, and tags for weak cell flipping defects are given a normal priority. When multiple allocation records share the same redundant resource segment, the analysis program rearranges the allocation order based on this priority list. This ensures that the allocation record corresponding to the higher-priority defect type tag receives a resource entry that is more centrally located or closer to the decoder output within that segment, reducing the impact of electrical parameter inconsistencies caused by differences within redundant resources on the repair effect of high-severity defects. The rearranged allocation order is written back to the repair resource segment allocation table, overwriting the original allocation order field.

[0126] Step S500: Generate a set of segmented repair control instructions based on the repair resource segment allocation table. Each instruction in the set of segmented repair control instructions records the number of the replacement resource that is enabled in the redundant resource segment, the range of the address range to be replaced, and the effective polarity of the segmentation enable signal.

[0127] The segmented repair control instruction set transforms the allocation decisions in the repair resource segmentation allocation table into a sequence of control words writable into the memory chip's fuse array or antifuse programming circuit. The replacement resource number is directly taken from the starting number and consecutive allocation quantity of the enabled resources within each allocation record in the repair resource segmentation allocation table, converted into the corresponding redundancy element selection code, and input into the chip's internal segmented redundancy decoder. The address range to be replaced is generated by a set of address matching signals after pre-decoding the row start address, row end address, column start address, and column end address of the packet boundary address. This set of signals triggers the redundancy resource replacement action when the row or column address falls within this range during the chip's normal operating mode. The effective polarity of the segmentation enable signal is specified as either high or low, according to the chip design reference manual, to ensure that the redundant path is correctly opened during repair activation. The analysis program performs instruction encoding conversion on each allocation record in the repair resource segmentation allocation table, arranging the above three components into fixed-length binary control words according to a simplified instruction format, and compiling them into the segmented repair control instruction set.

[0128] Step S600: Call the contents of the repair resource segment allocation table to guide the temporary repair logic circuit built into the memory chip under test to apply overlapping read and write operations at the segment boundary, perform stress verification test on the adjacent address interval of the segment boundary, and obtain the segment boundary stress test result set. When the segment boundary stress test result set indicates that no new failure address has been generated in the boundary overlapping area, the segment repair control instruction set is solidified and written into the non-volatile repair control information storage area of ​​the memory chip under test.

[0129] The temporary repair logic circuit is a set of digital logic circuits integrated inside the memory chip under test, consisting of configurable registers, address remapping multiplexers, and redundant resource replacement decoders. This circuit is in a reset state before the non-volatile repair control information storage area is programmed, and does not perform any address replacement behavior externally. When the automated test equipment loads a set of configuration signals corresponding to the contents of the repair resource segment allocation table into this circuit through the test access port, the configuration register latches inside the temporary repair logic circuit are sequentially set, and the selection terminal logic state of the address remapping multiplexer changes accordingly. This temporarily establishes a segment boundary remapping path from the external address bus to the physical memory array within the chip, so that address requests originally pointing to the segment boundary neighboring memory cells are actually routed to the replacement units within the redundant resource segments. This temporary configuration state is power-loss volatile, therefore it can be repeatedly modified and reloaded during stress verification testing without causing any irreversible impact on the chip's permanent configuration.

[0130] Segment boundaries refer to the demarcating neighborhoods in the memory array address space between different physical segments of redundant row or column resources. Because the segmented decoding circuit allocates different address bits to different redundant resource segments for decoding, the signal flipping behavior on the address bus during decoding of adjacent segments will abruptly change at the segment boundaries. On one side of the segment boundary, a high-weight address bit of the row or column address remains in one logical state, while on the other side, the same high-weight address bit changes to the opposite logical state. This address bit level flipping simultaneously triggers abrupt changes in the load conditions of multiple fan-out lines within the segmented decoding circuit, the sequence of enable signals for adjacent word line drivers, and minor disturbances in the bias settling time of the sensitive amplifier. If there are weak memory cells or parasitic defects introduced during the manufacturing process in the segment boundary area, normal operating mode or routine testing may not expose them. However, when high-speed access occurs alternately on both sides of the segment boundary, the repeated decoding switching stress, transient current spikes on the power distribution network, and the cumulative effect of voltage imbalance between the two address spaces in the bit line precharge circuit will constitute an accelerating stress condition on the boundary neighborhood, which can induce latent defects and transform them into failure behaviors that can be captured by external testing equipment.

[0131] Overlapping read / write operations are a test access sequence specifically designed to apply the aforementioned segment boundary neighborhood pressure. Its core lies in repeatedly overlapping the access addresses on both sides of the segment boundary, ensuring that adjacent read / write cycles are in completely opposite address travel directions, with no wait cycles inserted between cycles. This operation generates the highest density of logic flip events on the address bus, causing the fan-out nodes of the segment decoding circuit to undergo a complete transition from one decoding strobe state to another every clock cycle. This maximizes the stretching of transient load current on the address signal path at the segment boundary, while simultaneously applying continuous and uninterrupted state-switching pressure to the bit line precharge circuit and the sensitive amplifier enable logic. The overlapping address range band is the address window defined for implementing this test; it is formed by splicing the end address range of the currently verified redundant resource segment and the beginning address range of the adjacent next redundant resource segment, ensuring that the address swing focus of the stress test is precisely aligned with the segment boundary.

[0132] The non-volatile repair control information storage area refers to the array of non-volatile programmable memory cells inside the tested memory chip used to permanently store repair configuration information. Its physical implementation can be one of the following: fuse array, antifuse array, charge-trapping programmable read-only memory, or ferroelectric random access memory cell array. This storage area is not programmed at the time of chip manufacturing; all its memory cells are in their initial state. Once programmed via a sequence of programming voltage pulses, the logical state of the memory cells is permanently rewritten. The redundant resource replacement logic inside the chip will then perform the final and unchangeable repair behavior based on the content programmed into this storage area. Therefore, before permanently programming this storage area, a stress verification test must first be performed in the overlapping address range using a temporary repair logic circuit to ensure that the planned repair scheme does not introduce new failure addresses at the segment boundaries. Only when the verification results of all overlapping address ranges indicate that no new failure addresses have been generated in the overlapping boundary areas can the programming process for the non-volatile repair control information storage area be safely initiated, thereby permanently writing the content of the segment repair control instruction set.

[0133] In an exemplary embodiment, step S600 may specifically include the following steps S610 to S660: Step S610: Read the allocation records one by one from the repair resource segment allocation table. Based on the segment identifier and packaging boundary address in each allocation record, locate the end address range of the address range covered by the redundant resource segment, and at the same time locate the beginning address range of the next adjacent redundant resource segment. Combine the end address range and the beginning address range into an overlapping address range band.

[0134] In step S400, the repair resource segment allocation table has completed the matching and allocation between all repair candidate packages and redundant resource segments. Each allocation record in this table clearly records the segment identifier of the selected redundant resource segment, the start number of the enabled resources within the segment, the packaging boundary address of the repair candidate package, and the defect type label. The segment identifier is a unique hardware number for each redundant resource segment within the chip. This number can be used to retrieve the complete row or column address range corresponding to the segment from the row or column segment address range list generated in steps S410 and S420, i.e., the segment start and end addresses. The row boundary descriptor in the packaging boundary address provides the row start and end addresses, and the column boundary descriptor provides the column start and end addresses.

[0135] The terminal address range is a continuous range of addresses near the termination boundary of the verified redundant resource segment. The span of this range is determined by the overlap depth parameter. The analysis program first locates the termination address of the segment in the row segment address range list or column segment address range list based on the segment identifier. Then, it backtracks from the termination address in the address decreasing direction, with the number of backtracking steps equal to the overlap depth, thus forming the terminal address range. For example, if the termination address of a redundant row resource segment is a certain row address value and the overlap depth is three, then the terminal address range includes three row addresses: 2 steps down from the termination address, 1 step down from the termination address, and the termination address itself. The starting address range is the address range formed by the next redundant resource segment adjacent to this segment, advancing the same number of overlap depth steps in the address increasing direction from its starting address. The next adjacent segment is determined by searching for an entry in the row segment address range list or column segment address range list whose segment start address is exactly equal to the current segment end address plus 1. If the current segment end address has reached the maximum row address or the maximum column address of the entire storage array, then there is no next adjacent segment. The segment boundary verification corresponding to this allocation record is aimed at the end boundary of the chip, and only tests the switching behavior of address access between the end address range and the address outside the boundary.

[0136] The overlapping address range is formed by sequentially concatenating the end address range and the beginning address range, with no address gaps between the two ranges. For row-direction segment boundary verification, the overlapping address range appears as a continuous address window. The address of the first segment within the window comes from the end of the currently verified segment, and the address of the second segment comes from the beginning of the adjacent segment. The addresses within the window maintain a strict increasing relationship in row address order. The construction logic of the overlapping address range for column-direction segment boundary verification is exactly the same, only the dimension is replaced with column address instead of row address.

[0137] Step S620: Write the contents of the corresponding allocation record in the repair resource segment allocation table to the temporary repair logic circuit through the test access port of the memory chip under test, so that the temporary repair logic circuit can take over the address decoding path of the overlapping address range and obtain the segment boundary remapping path.

[0138] The test access port on the memory chip under test consists of a set of external pins conforming to the Joint Test Action Group standard interface protocol, including a test clock pin, a test mode selection pin, a test data input pin, a test data output pin, and an optional test reset pin. The test channel on the automated test equipment establishes an electrical connection with these pins through a test interface board and runs a test access port controller state machine corresponding to the memory chip design rules. During the execution of step S620, the test equipment first sends a sequence of instructions to the chip via the test mode selection pin to enter the test access port controller shift state, causing the chip's internal test access port logic to enter the data register shift mode. Subsequently, the test equipment completes the contents of the currently unverified allocation record in the repair resource segment allocation table, including the segment identifier field, the start number field of the enabled resources within the segment, the start and end address fields of the packet boundary address, and the defect type label field, and arranges them into a continuous bit stream configuration packet according to the bit order of the temporary repair logic circuit configuration register. This configuration packet is then serially shifted into the configuration register chain of the temporary repair logic circuit via the test data input pin under the drive of the test clock. When the last bit of the configuration packet is shifted to the end bit of the configuration register chain, the test device issues an update command through the test mode selection pin, and latches the data shifted in from the configuration register chain into the function register group of the temporary repair logic circuit in parallel at a valid edge of the test clock.

[0139] After the function register group is latched, the selection control terminal of the address remapping multiplexer inside the temporary repair logic circuit is immediately set to the logic level corresponding to the content in the configuration packet. These multiplexers are located between the row address pre-decoder and column address pre-decoder inside the memory chip and the physical word line driver and bit line selector of the memory array. In normal operation mode, the multiplexer directly connects the output of the pre-decoder to the physical addressing path of the memory array; however, after the temporary repair logic circuit is configured and taken over, the multiplexer cuts off the decoding result of part of the address from the original address path according to the configuration data, and instead selects the corresponding redundant word line or redundant bit line from the output of the redundant resource segment decoder, thereby establishing a segment boundary remapping path. This remapping path allows all access requests within the overlapping address range that originally pointed to the original memory cell to be redirected to the allocated replacement memory cell within the redundant resource segment under the action of the temporary repair logic circuit, thereby accurately simulating the actual addressing behavior of the chip after the final burn-in repair configuration during the stress verification test phase.

[0140] Step S630: Perform a continuous read / write operation sequence in alternating directions on the overlapping address range. The continuous read / write operation sequence in alternating directions includes an address increment read / write cycle from the end address range to the beginning address range and an address decrement read / write cycle in the opposite direction, and no waiting cycle is inserted between adjacent read / write cycles.

[0141] The alternating direction continuous read / write operation sequence is the core operation process for applying segment boundary overlap stress testing to the overlapping address range. The address-incrementing read / write cycle starts from the starting address of the last address range, advances address by address in the ascending direction, crosses the segment boundary to enter the first address range, and finally reaches the ending address of the first address range. The address-decreasing read / write cycle is the opposite, starting from the ending address of the first address range, retreating address by address in the descending direction, crossing the segment boundary to return to the starting address of the last address range. The two read / write cycles are executed alternately, and in the next clock cycle after the write recovery operation at the last address of the previous read / write cycle is completed and the read operation data is latched, the address flow immediately reverses and starts the first address access of the next read / write cycle, without inserting any wait cycles or even refresh cycles. This generates a continuous address flip and decoding switching storm above and below the segment boundary line of the overlapping address range. This operating method imposes the most stringent design limits on the address bit fan-out buffers in the segmented decoding circuit, the setup and hold time margins of the segmented strobe signals, the alternating charging and discharging of the word line drivers, and the state transition speed of the bit line precharge balancing circuit between adjacent address intervals.

[0142] In an exemplary embodiment, step S630 may specifically include the following steps S631 to S636: Step S631: Set the starting address of the overlapping address range as the starting address of the alternating direction read / write scan, and set the ending address of the overlapping address range as the ending address, thereby generating an address incrementing scan queue and an address decrementing scan queue.

[0143] The starting address is the address with the smallest address value in the overlapping address range, which corresponds to the very beginning of the last address range in the address increment read / write cycle. The ending address is the address with the largest address value in the overlapping address range, which corresponds to the very end of the first address range in the address increment read / write cycle. The address increment scan queue is an ordered list of addresses. Starting from the starting address, each increment is incremented by one and stored sequentially in the next position of the list until the ending address is stored at the end of the list. The address decrement scan queue is also an ordered list of addresses, but it is generated starting from the ending address and decremented by one, storing each decrement by one in the next position of the list until the starting address is stored at the end of the list. Because the addresses within the overlapping address range are consecutively addressed, the address increment scan queue and the address decrement scan queue contain the exact same set of addresses, only arranged in reverse order.

[0144] During the execution of step S631, the address generator of the automated testing equipment pre-generates the two scan queues mentioned above. The address generator includes an address counter with a preset initial value and a set of address sequence memories. When generating the address increment scan queue, the initial value of the address counter is loaded as the starting address, and incrementing is performed under the drive of the address clock. Each counter output value is sequentially written into the increment queue area of ​​the address sequence memory. When generating the address decrement scan queue, the initial value of the address counter is loaded as the ending address, and decrementing is performed under the drive of the address clock. Each counter output value is sequentially written into the decrement queue area of ​​the address sequence memory.

[0145] Step S632: Enable continuous burst read / write mode. The burst clock generator generates a burst pulse train without interval. Under the control of the burst pulse train, the addresses in the address increment scan queue are sequentially read, written and then read again in a pipelined operation. In this pipelined operation, the old data is read out first at the same address, then the flip test pattern is written, and then the written flip test pattern is immediately read out for self-comparison.

[0146] Continuous burst read / write mode is a high-speed memory access mode. In this mode, a burst clock generator produces a continuous sequence of clock pulses with no idle bus cycles between adjacent rising edges. The period of this sequence is strictly equal to the maximum read / write cycle time specified in the datasheet of the memory chip under test. During the activation of continuous burst read / write mode, the setup time, hold time, and precharge time of the row and column address strobe signals inside the memory chip are all compressed to the lower limit of the specification, and the address bus and data bus are in a continuous state of transition.

[0147] The read-write-read pipelined operation is a three-stage atomic operation sequence performed on each address. The first stage is the read stage. Within a complete read cycle in a burst of pulses, a read command is issued to the target address. After the inherent column address gating read delay of the memory chip, the old data currently held in the memory cell at that address is latched into the first read data register of the test device via the data bus. The second stage is the write stage. In the write cycle immediately following the read stage, the test device inverts the bits of the old data latched in the first read data register to generate a flip test pattern. This pattern, along with the same target address on the address bus, is driven to the data bus and address bus of the memory chip, and a write command is issued to write the flip test pattern into the memory cell at that address. Since the flip test pattern is the result of inverting each logical value of the old data, writing the flip test pattern means that each bit cell of the memory cell needs to undergo a complete charge-discharge state flip to maximize the electrical stress of the write operation on the memory cell and the bit line pre-charge circuit. The third stage is the read-out stage. In another read cycle immediately following the write stage, a read command is sent to the same target address again to read the flip test pattern that was just written from the storage cell and latch it into the second read data register of the test device.

[0148] The self-compare operation is executed immediately after the second read data register finishes receiving the read data. The comparison logic circuit inside the test equipment inverts the old data in the first read data register bit by bit to obtain the desired flip test pattern. This desired flip test pattern is then compared in parallel with the read copy in the second read data register using a bitwise XOR logic comparator. The bitwise XOR logic comparator consists of a number of independent XOR gates equal to the width of the data bus. The two inputs of each XOR gate are connected to the corresponding bits of the desired flip test pattern and the corresponding bits of the read copy, respectively. The logic characteristics of the XOR gates determine that the output is low when the two input signals have the same logic state, and high when their logic states are different.

[0149] In an exemplary embodiment, step S632 may specifically include the following steps S6321 to S6326: Step S6321: During the current burst pulse period, a read command is sent to the current scan address in the overlapping address range. After the read delay period, the old data pre-stored in the storage unit of the scan address is latched into the first read data register.

[0150] The current burst pulse cycle is a clock cycle uniquely identified by the pulse count index of the burst clock generator. At the beginning of this cycle, the test equipment, based on the address value pointed to by the current address pointer in the address increment scan queue, drives the row address and column address onto the address bus of the memory chip under test in a time-division or simultaneous manner, while simultaneously applying the read command code to the chip's read / write control signal lines. The address decoder inside the memory chip decodes the applied row address and column address, selects the corresponding word line and bit line pair in the target memory bank, enables the sensitive amplifier to detect the charge state held in the memory cell and converts it into a full-swing logic level, which is then transmitted to the data output buffer via the column select circuit. The read delay cycle is the inherent delay time of the chip from the issuance of the read command to the stable validity of the data on the data output buffer. The comparator sampling window of the test equipment is aligned with the data validity moment at the end of the read delay cycle, latching the old data presented on the data output buffer into the first read data register.

[0151] Step S6322: In the next burst pulse cycle, a write command is sent to the current scan address. At the same time, the bitwise inversion result of the old data in the first read data register is written as a flip test pattern into the storage unit of the scan address. In the next burst pulse cycle after the write operation is completed, a read command is sent to the scan address again.

[0152] The bit-by-bit inversion of the old data in the first read data register is implemented by a set of bit-by-bit inverters embedded in the test equipment's data generator. The number of inverters in this set is consistent with the data bus width. The input of each inverter is connected to the output of the corresponding bit in the first read data register, and the output of the inverter forms the corresponding bit of the flip test pattern. During the write command issuance, the address bus maintains drive on the current scan address, and the data bus is driven by the flip test pattern. The write driver inside the memory chip writes the flip test pattern into the target memory cell. After the write operation is completed, the address bus and data bus are reconfigured at the beginning of the next burst pulse cycle to issue the next read command, and the address bus maintains drive on the same scan address.

[0153] Step S6323: After the read delay period of the read command again, the data read back from the scan address is latched into the second read data register. The read back data is the read copy of the flip test pattern that was just written.

[0154] Step S6324: Invert the old data in the first read data register bit by bit to obtain the desired flip test pattern, and send the desired flip test pattern and the read copy in the second read data register into the bit-by-bit XOR logic comparator.

[0155] The bit-inverting operation can be performed by the same set of bit inverters used to generate the flip test pattern in step S6322, or by a separate set of bit inverters with identical structures. Instead of directly latching the old data in the first read data register by bit-inverting it again to generate the desired flip test pattern, this method avoids the propagation of logic errors that may occur during the write and read-out process from the flip test pattern generation circuit itself to the self-comparison stage. This ensures that the calculation path of the desired value and the generation path of the written value are independent of each other, thus guaranteeing that any comparison mismatch indicates a failure on the memory cell read / write path rather than a fault in the test logic itself.

[0156] Step S6325: The bitwise XOR logic comparator outputs the comparison result of each bit. If the comparison result of all bits is zero, a match indication for the current scan address is generated and the match indication along with the address tag is recorded in the match indication recording area. Otherwise, a failure indication is generated and the position information of the failure bit is recorded.

[0157] The output of each XOR gate in the bitwise XOR logic comparator is individually connected to a single acquisition channel of the test equipment's result acquisition module. The acquisition module performs a bitwise OR reduction operation on the logic levels of all XOR gate outputs. If the final reduction result is a logic low level, it indicates that the XOR output of all bits is low, meaning that the expected value and the read value of each bit are consistent, generating a match indication; if the reduction result is a logic high level, it indicates that at least one XOR output is high, generating a failure indication. Simultaneously with generating the failure indication, the acquisition module records the logic level state of the corresponding output of each XOR gate bit by bit to obtain the failure bit location information. The record clearly indicates which data bits experienced comparison failure. This information will be transmitted to the synchronous acquisition path in step S640 for the generation of boundary failure markers.

[0158] The address tag is the complete physical address of the current scan address, including the memory bank number, row address, and column address. It is directly obtained from the output of the address generator and written to the match indication record area along with the match indication or failure indication. The match indication record area is a dedicated storage space in the test device's memory, used to store the test result record entries for each scan address in sequence.

[0159] Step S6326: After completing the pipelined operation of reading, writing and reading again after the current scan address is read and self-compare, update the address pointer to the next scan address in the address increment scan queue, and repeat the above process until all addresses in the address increment scan queue have been processed.

[0160] The address pointer is updated by the address generator control logic inside the test device according to the sequential advancement rules of the address increment scan queue. After detecting that the self-compare completion indication signal of the current scan address is valid, the address generator points the address pointer to the next address in the address increment scan queue before the next burst pulse cycle arrives. If the current scan address is already the last address in the address increment scan queue, i.e., the termination address, the address generator will enter the address flow switching process described in step S633.

[0161] Step S633: After the pipelined operation is completed at the last address in the address incrementing scan queue, without inserting any waiting cycle, immediately switch the address flow to the address decrementing scan queue, and perform the same read-write-read pipelined operation on the addresses in the address decrementing scan queue in sequence.

[0162] The strict meaning of "no waiting cycle insertion" is as follows: After the end signal of the self-compare operation of the last address in the address increment scan queue is latched by the test device's control state machine, at the start of the next burst clock cycle, the output address of the address generator switches to the first address in the address decrement scan queue, i.e., the termination address, and the test device immediately issues the first read command to that address. During the transition from the address increment scan queue to the address decrement scan queue, the pulse train output by the burst clock generator does not experience any pauses, idle cycles, or waiting states; the oscillation frequency and phase continuity of the burst clock remain constant throughout. This uninterrupted address direction switching at the segment boundary has the effect that the scan direction in the address space instantly reverses from advancing towards the boundary to retreating away from the boundary. The flip direction of the high-weight address bits on the address bus, along with the selection path of the segment decoding signal, undergoes completely opposite changes within two consecutive clock cycles, thereby generating continuous read / write stresses in opposite directions on adjacent physical memory cells on both sides of the segment boundary.

[0163] When performing a read-write-read pipelined operation on addresses in the address-decreasing scan queue, the operation sequence for each address is still to first read out the old data, then write the flip test pattern, and then immediately read out and compare it with itself. The operation process is completely consistent with the pipelined operation in the address-increasing direction, only the address order is reversed.

[0164] Step S634: After the reverse address decrement read / write cycle is completed, without inserting a wait cycle, the address flow is switched back to the address increment scan queue, thus forming a complete overlapping read / write cycle.

[0165] A complete overlapping read / write cycle consists of one address increment read / write cycle followed by one address decrement read / write cycle, with no idle bus cycles between the two cycles. The address flow is seamlessly connected between the two switches. Each address increment read / write cycle traverses all addresses within the overlapping address range once, and the same address is accessed in opposite directions in the two cycles. Therefore, each memory cell is accessed once in each of the two completely opposite address switching contexts within a complete overlapping read / write cycle, resulting in a symmetrical bidirectional stress application to the segment boundary neighborhood.

[0166] Step S635: Repeatedly execute the overlapping read / write cycle, and perform a full address range data integrity check on the overlapping address range after each read / write cycle, until the preset number of cycles is reached, or the data integrity check fails.

[0167] The repeated execution of overlapping read / write cycles is controlled by a loop counter within the test equipment. The loop counter initially has a value of 0, and increments by 1 after each complete overlapping read / write cycle (including one address incrementing read / write cycle and one address decrementing read / write cycle). Immediately after each overlapping read / write cycle, a data integrity check is performed covering the entire overlapping address range. This check uses a full address read comparison method. The test equipment sequentially issues a simple read command to each address within the overlapping address range, comparing the read data bit-by-bit with the flip test pattern last written to that address in the last overlapping read / write cycle. If the readback data from all addresses is completely consistent with the flip test pattern written last time, the data integrity check passes. The loop counter is incremented by 1 and compared with the preset loop count threshold. If the threshold is not reached, the next overlapping read / write cycle continues. If the readback data from any address differs from the flip test pattern written last time by even one bit, the data integrity check fails. The test device immediately stops the execution of the overlapping read / write cycle and records the failed address and its bit failure information as part of the stress verification data packet.

[0168] The preset loop count threshold is set according to the reliability verification outline of the memory chip. This value is stored in the test program configuration file of the test equipment and loaded into the loop comparator of the test equipment before the start of step S635. The loop comparator continuously monitors the relationship between the current value of the loop counter and the preset loop count threshold. Once the current value of the loop counter equals the preset loop count threshold, the test equipment terminates the overlapping read / write loop and proceeds to step S636.

[0169] Step S636: After stopping, output the matching indication record generated by each round of data integrity verification, and attach the corresponding read / write cycle order mark and the address range information of the overlapping address range band, which together form the stress verification data packet of the overlapping address range band.

[0170] The read / write cycle sequence marker is an integer sequence number incrementing from 1 to the current cycle sequence at the end, used to uniquely identify the overlapping read / write cycle number corresponding to each round of data integrity verification. The address range information in the overlapping address range includes the start and end addresses of the range, used to indicate the spatial range covered by the stress verification data packet to the backend analysis program. The match indication record is a complete set of match indications or failure indications generated for each address in each round of data integrity verification. The stress verification data packet structurally packages the above three components and, after verification stops, is output by the test equipment to the storage system of the engineering analysis workstation through the test control interface.

[0171] Step S640: During the execution of the continuous read and write operation sequence in alternating directions, the data read back from each read operation is synchronously collected and matched bit by bit with the flip test pattern previously written to the corresponding address to generate an indication record of each matching result. Any bit failure to match will generate a boundary failure mark.

[0172] The synchronous acquisition mechanism is fully synchronized with the operating clocks of the address bus and data bus. The acquisition triggering logic inside the test equipment samples all data bits on the data output buffer during each read data latch cycle without any data masking or bit width clipping. Each sampled data bit value is simultaneously sent to the comparison logic unit of the corresponding channel and XORed with the corresponding bit of the toggle test pattern written in the most recent write operation at that address. If the comparison output of a bit is logic high, a bit match failure event is recorded, and a globally valid boundary failure flag signal is set in the boundary failure flag generation logic based on this event. The boundary failure flag is a single-bit aggregated indicator that is evaluated once during the test cycle of each address. The boundary failure flag is set to valid as long as at least one bit at that address fails to match. The valid state of the boundary failure flag, along with the address where the failure occurred and its failure bit information, is written into the entry of the acquisition result recorder, completing the generation of an indication record.

[0173] Step S650: Records containing boundary failure markers or all successfully matched records are included as verification result entries for the overlapping address interval band and incorporated into the segmented boundary stress test result set.

[0174] The segment boundary stress test result set is a structured data table consisting of multiple verification result entries. Each verification result entry uses the address range information of the overlapping address interval as one of the primary keys. The entry content includes the boundary failure marker status of that interval, the matching indication sequence of all tested addresses, and, if failures exist, a list of failed addresses and a list of failure bit positions for each failed address. When the boundary failure marker status indicates no failure, each record in the matching indication sequence is considered a successful match. The engineering analysis workstation converts the stress verification data packets generated for each repair resource segment allocation table record in steps S610 to S636 into verification result entries one by one, and inserts them sequentially into the segment boundary stress test result set, completing the summary of stress verification data for all segment boundaries.

[0175] Step S660: When the verification result entries of the overlapping address intervals corresponding to all allocation records indicate successful matching, confirm that no new failure addresses have been generated in the boundary overlapping area, apply a programming pulse sequence to the non-volatile repair control information storage area, and burn the non-volatile repair control information storage area address by address with the content of the segmented repair control instruction set.

[0176] The criterion for confirming that no new failure addresses have been generated in the boundary overlap area is that the boundary failure marker status in each verification result entry of the segmented boundary stress test result set indicates no failure. The judgment logic in the engineering analysis workstation traverses all verification result entries in the segmented boundary stress test result set, extracts the boundary failure marker field one by one, and performs a logical AND reduction. Only when all boundary failure markers indicate a successful match is the reduction result true. At this point, it is determined that no new failure addresses have been generated in the boundary overlap area, and the process can proceed to the curing and burning stage.

[0177] Following the confirmation steps, the engineering analysis workstation issues a programming authorization command to the automated test equipment and distributes the contents of the segmented repair control command set as the data source for programming. The programming module of the automated test equipment responds to the authorization command, executing the generation and application of the programming pulse sequence. The programming pulse sequence includes an address setup phase, a data application phase, a high-voltage programming pulse application phase, and a programming verification phase. In the address setup phase, the test equipment drives the target programming address of the non-volatile repair control information storage area onto the chip's programming address bus. In the data application phase, the instruction control word data corresponding to the address in the segmented repair control command set is driven onto the chip's programming data bus. In the high-voltage programming pulse application phase, the programming module applies a programming pulse greater than the normal operating voltage to the chip's high-voltage programming power supply pin. The amplitude and duration of this pulse are strictly within the programming window specified in the memory chip datasheet.

[0178] During the high-level platform of the programming pulse, a high-voltage electric field acts on the memory cell at the target address of the non-volatile repair control information storage area, changing the threshold voltage or resistance state of the memory cell, thereby programming it from its initial state to the logical state corresponding to the applied data. After the falling edge of the programming pulse ends, address establishment and data application are maintained for a stable period of time, followed by the programming verification stage. In the programming verification stage, the test equipment initiates a low-voltage read operation on the target address that has just been programmed, comparing the read data bit by bit with the instruction control word data that was just written to confirm successful programming. If the comparison matches, the address pointer is incremented to the address corresponding to the next instruction in the segmented repair control instruction set, and the above process of address establishment, data application, high-voltage programming pulse application, and programming verification is repeated until all instructions in the segmented repair control instruction set have been burned and verified successfully. If a mismatch occurs at a certain address during the programming verification stage, a complete programming pulse is reapplied to the original target address according to the retry strategy specified in the datasheet. If verification still fails after reaching the maximum number of retries, the chip is marked as a hardening failure and the process is terminated.

[0179] Once the entire set of segmented repair control instructions has been successfully programmed and verified, the contents stored in the non-volatile repair control information storage area represent the final permanent repair configuration of the tested memory chip. This configuration is automatically loaded from the storage area by the chip's internal repair control state machine when the chip is powered on and working normally, and drives the redundant resource segmented decoding circuit to perform permanent address replacement.

[0180] Based on the foregoing embodiments, this invention provides a chip testing device. The units and modules included in the device can be implemented by a processor in a computer device; of course, they can also be implemented by specific logic circuits. In the implementation process, the processor can be a central processing unit (CPU), a microprocessor unit (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA), etc.

[0181] Figure 3 This is a schematic diagram of the composition structure of a chip testing device provided in an embodiment of the present invention, as shown below. Figure 3 As shown, the chip testing apparatus 200 includes: The data acquisition module 210 is used to acquire the set of failure addresses generated after the memory chip under test is tested by a multi-level test vector set containing different defect sensitization conditions. Each failure physical address in the set of failure addresses is accompanied by a failure mode marker. The structure construction module 220 is used to construct a failure texture map data structure based on the spatial distribution of the failed physical addresses in the failure address set within the storage array and their respective failure mode labels. The failure texture map data structure contains tile nodes indexed by the failed physical address. Each tile node covers descriptive information of the failure density within a preset address neighborhood centered on the failed physical address and statistical information of the dominant failure mode label within that neighborhood. The data packaging module 230 is used to package the failure texture map data structure into repair groups based on the constraint of defect expansion law, and generate a repair candidate package by merging multiple failure physical addresses that meet the same defect type label and whose spatial location is continuously distributed along the defect expansion direction. The resource matching module 240 is used to obtain the segmented redundancy layout information of the internal redundant resources of the tested memory chip after being divided by the segmented decoding circuit. The segmented redundancy layout information includes the row address range driven by each redundant row resource physical segment and the column address range driven by each redundant column resource physical segment. Based on the segmented redundancy layout information, the repair candidate package is matched with the redundant resource segments, and the repair resource segment allocation table is output. The instruction generation module 250 is used to generate a set of segmented repair control instructions based on the repair resource segment allocation table. Each instruction in the set of segmented repair control instructions records the number of the replacement resource that is enabled in the redundant resource segment, the range of the address range to be replaced, and the effective polarity of the segmentation enable signal. The verification test module 260 is used to call the contents of the repair resource segment allocation table to guide the temporary repair logic circuit built into the memory chip under test to apply overlapping read and write operations at the segment boundary, perform stress verification tests on the adjacent address intervals of the segment boundary, and obtain the segment boundary stress test result set. When the segment boundary stress test result set indicates that no new failure address has been generated in the boundary overlapping area, the segment repair control instruction set is solidified and written into the non-volatile repair control information storage area of ​​the memory chip under test.

[0182] The descriptions of the apparatus embodiments above are similar to those of the method embodiments above, and have similar beneficial effects. In some embodiments, the functions or modules included in the apparatus provided by the present invention can be used to perform the methods described in the method embodiments above. For technical details not disclosed in the apparatus embodiments of the present invention, please refer to the descriptions of the method embodiments of the present invention for understanding.

[0183] It should be noted that, in the embodiments of the present invention, if the above-described testing method for the memory chip is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of the present invention, or the part that contributes to related technologies, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), magnetic disks, or optical disks. Thus, the embodiments of the present invention are not limited to any specific hardware, software, or firmware, or any combination of hardware, software, and firmware.

[0184] Figure 4 This is a schematic diagram of the hardware entity of a testing device provided in an embodiment of the present invention, such as... Figure 4 As shown, the hardware entity of the test device 1000 includes a processor 1001 and a memory 1002, wherein the memory 1002 stores a computer program that can run on the processor 1001, and the processor 1001 executes the program to implement the steps in the method of any of the above embodiments.

[0185] The memory 1002 stores computer programs that can run on the processor. The memory 1002 is configured to store instructions and applications that can be executed by the processor 1001. It can also cache data to be processed or already processed (e.g., image data, audio data, voice communication data, and video communication data) of the processor 1001 and various modules in the test device 1000. It can be implemented by flash memory or random access memory (RAM).

[0186] When the processor 1001 executes the program, it implements the steps of the testing method for the memory chip described above. The processor 1001 typically controls the overall operation of the test equipment 1000.

[0187] This invention provides a computer storage medium that stores one or more programs, which can be executed by one or more processors to implement the steps of the testing method for the memory chip as described in any of the above embodiments.

[0188] It should be noted that the descriptions of the above storage medium and device embodiments are similar to those of the above method embodiments, and have similar beneficial effects. For technical details not disclosed in the storage medium and device embodiments of the present invention, please refer to the descriptions of the method embodiments of the present invention for understanding. The processor described above can be at least one of an Application Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), a Digital Signal Processing Device (DSPD), a Programmable Logic Device (PLD), a Field Programmable Gate Array (FPGA), a Central Processing Unit (CPU), a controller, a microcontroller, and a microprocessor. It is understood that the electronic device implementing the above processor function can also be other types, and the embodiments of the present invention do not specifically limit it.

[0189] The aforementioned computer storage media / memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM), etc.; or it can be various terminals that include one or any combination of the above-mentioned memories, such as mobile phones, computers, tablet devices, personal digital assistants, etc.

[0190] The above description is merely an embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A test method of a memory chip, characterized by, The method includes: Obtain the set of failure addresses generated after the memory chip under test is tested by a multi-level test vector set containing different defect sensitization conditions. Each failure physical address in the set of failure addresses is accompanied by a failure mode marker. Based on the spatial distribution of the failed physical addresses in the set of failed addresses within the storage array and their respective failure mode markers, a failure texture map data structure is constructed. The failure texture map data structure includes tile nodes indexed by the failed physical address. Each tile node covers descriptive information of the failure density within a preset address neighborhood centered on the failed physical address and statistical information of the dominant failure mode markers within that neighborhood. The failure texture map data structure is packaged into repair groups based on the constraint of defect expansion law to generate a repair candidate package formed by merging multiple failure physical addresses that meet the same defect type label and whose spatial location is continuously distributed along the defect expansion direction. Obtain the segmented redundancy layout information of the internal redundant resources of the tested memory chip after being divided by the segmented decoding circuit. The segmented redundancy layout information includes the row address range driven by each redundant row resource physical segment and the column address range driven by each redundant column resource physical segment. Match the repair candidate packet with the redundant resource segments according to the segmented redundancy layout information and output the repair resource segment allocation table. A set of segmented repair control instructions is generated based on the repair resource segment allocation table. Each instruction in the set of segmented repair control instructions records the number of the replacement resource that is enabled in the redundant resource segment, the range of the address range to be replaced, and the effective polarity of the segment enable signal. The contents of the repair resource segment allocation table are invoked to guide the temporary repair logic circuit built into the memory chip under test to apply overlapping read and write operations at the segment boundary. Stress verification tests are performed on the adjacent address intervals of the segment boundary to obtain a segment boundary stress test result set. When the segment boundary stress test result set indicates that no new failure addresses have been generated in the boundary overlapping area, the segment repair control instruction set is solidified and written into the non-volatile repair control information storage area of ​​the memory chip under test.

2. The method of claim 1, wherein, Based on the spatial distribution of failed physical addresses within the storage array and their respective associated failure mode markers in the failed address set, a failure texture map data structure is constructed. This failure texture map data structure includes tile nodes indexed by the failed physical addresses. Each tile node encompasses descriptive information about the failure density within a preset address neighborhood centered on that failed physical address and statistical information about the dominant failure mode markers within that neighborhood, including: An address space mapping projection is performed on the set of failed addresses, and the failed physical addresses are divided into a three-dimensional address grid of the memory array according to their memory location, row address and column address. The grid cell position occupied by each failed physical address and its associated failure mode label are marked in the three-dimensional address grid to obtain a marked failure grid map. For each marked grid cell in the marked failure grid diagram, a local neighborhood window is extracted, which is centered on the grid cell and extends along the row direction by a first preset number of grid cells and along the column direction by a second preset number of grid cells, to form the texture sampling window of the grid cell. The ratio of the number of mesh cells marked as failed within the texture sampling window to the total number of mesh cells within the window is used as the failure density description information of the texture sampling window. The failure mode marker that appears most frequently within the window is also used as the dominant failure mode marker. Create a tile node indexed by the physical address of the grid cell, and store the failure density description information and dominant failure mode marker of the texture sampling window into the texture attribute field of the tile node to complete the construction of the tile node corresponding to the failure physical address. For each marked mesh cell in the marked failure mesh graph, the operations of extracting texture sampling window, statistically analyzing failure density description information, statistically analyzing dominant failure mode marking, and constructing tile nodes are repeated to generate a set of tile nodes corresponding to all failure physical addresses. A boundary node marking operation is performed on the tile nodes in the set of tile nodes. If the texture sampling window of a certain tile node overlaps with the physical boundary of the storage array or the boundary of the storage volume, a boundary adjacent identifier is set in the tile node, and all tile nodes and their associated relationships are merged into the failed texture map data structure.

3. The method of claim 2, wherein, The ratio of the number of mesh cells marked as failed within the texture sampling window to the total number of mesh cells within the window is used as the failure density description information for the texture sampling window. Furthermore, the most frequently occurring failure mode marker within the window is identified as the dominant failure mode marker, including: Read the row coordinate range and column coordinate range of the grid cells covered by the texture sampling window, and generate a window grid coordinate traversal sequence. The window grid coordinate traversal sequence contains an ordered combination of the row coordinates and column coordinates of all grid cells in the window. Based on the window grid coordinate traversal sequence, the grid cell coordinates are retrieved one by one. The system queries whether the marked failure grid diagram has a failure status marker at the coordinate position and records the query results. An accumulator for the occurrence of failed grid cells and a frequency recorder for each failure mode tag category are maintained. When the query result indicates that the current grid cell has a failure status tag, the count value of the accumulator is incremented. At the same time, the failure mode tag attached to the grid cell is read, and the count value of the recorder of the corresponding category is incremented. After the window grid coordinate traversal sequence has been completed, the final count value of the accumulator is read, the final count value is divided by the total number of grid cells in the texture sampling window, and the result is stored in the failure density description information field. Read the failure mode tag category corresponding to the maximum count value in the frequency recorder of each failure mode tag category, determine the failure mode tag category as the dominant failure mode tag, and store it in the dominant failure mode tag field; The failure density description information field and the dominant failure mode marker field are merged into a texture attribute field of the texture sampling window and attached to the currently processed tile node.

4. The method of claim 3, wherein, The step of reading the failure mode marker category corresponding to the maximum count value in the frequency recorder of each failure mode marker category, determining that failure mode marker category as the dominant failure mode marker, and storing it in the dominant failure mode marker field includes: Obtain all failure mode marker categories that have been statistically obtained from the texture sampling window, establish a category list, and extract the occurrence frequency values ​​in the same order based on the occurrence frequency recorder of each failure mode marker category to form a category-frequency correspondence array; Set the first category in the category-frequency correspondence array as the current candidate category, set its occurrence frequency value as the current maximum frequency value, and then compare the occurrence frequency values ​​of subsequent categories with the current maximum frequency value. During the comparison process, if the occurrence frequency of a certain subsequent category exceeds the current maximum frequency value, then the subsequent category is updated as the current candidate category, and the current maximum frequency value is refreshed with the occurrence frequency value; otherwise, the original candidate category and maximum frequency value are retained. After comparing all categories, the current candidate category that is finally retained is identified as the dominant failure mode label, and the failure mode code corresponding to the dominant failure mode label is written into the dominant failure mode label field. Simultaneously, the current maximum frequency value is extracted as the dominant frequency, and the dominant frequency is divided by the total number of failed mesh cells in the window to obtain the dominant concentration information. The dominant concentration information is also recorded in the texture attribute field. The texture attribute field, which is composed of the dominant failure mode marker field and the dominant concentration information, is bound to the index address of the current tile node, and the attribute entry of the corresponding tile node in the failure texture map data structure is updated.

5. The method of claim 1, wherein, The process of packaging the failure texture map data structure into repair groups based on defect expansion rules generates a repair candidate package by merging multiple failure physical addresses that conform to the same defect type label and are continuously distributed in spatial location along the defect expansion direction. The repair candidate package is appended with a defect type label and a packaging boundary address, including: Read the dominant failure mode label of each tile node in the failure texture map data structure, group the tile nodes with the same dominant failure mode label into the same node subgroup, and determine the main expansion direction and secondary expansion direction corresponding to each dominant failure mode label according to the preset defect expansion direction mapping relationship. Within each node subgroup, based on the storage location of the invalid physical address of the tile node index, tile nodes belonging to the same storage are further divided into body-level node pools, and each body-level node pool independently performs subsequent packaging operations. For any body-level node pool, select the tile node that has not yet been merged into any repair candidate package and has the highest row address as the seed node. Search the body-level node pool along the main expansion direction for tile nodes that have the same dominant failure mode marker and present a continuous address interval with the seed node in the row or column direction, and connect them in sequence to form a candidate chain. Verify whether the address interval between adjacent tile nodes in the candidate chain conforms to the preset step interval allowable range of the defect type corresponding to the seed node. Retain the tile nodes that conform to the allowable range in the candidate chain and remove the tile nodes that exceed the allowable range to obtain continuous defect segments. The physical addresses of the tile nodes at both ends of the continuous defect segment are used as the packaging boundary addresses. A repair candidate package is generated for the failure physical addresses corresponding to all tile nodes in the continuous defect segment, and a defect type label obtained by the failure mode label conversion dominated by the seed node is attached. The repair candidate package is then stored in the repair candidate package set. For the remaining tile nodes in the volume-level node pool that have not yet been merged, repeat the process of seed node selection, candidate chain generation, continuous defect segment acquisition and repair candidate package generation until all tile nodes in the volume-level node pool have been assigned to a certain repair candidate package.

6. The method of claim 5, wherein, The step of verifying whether the address interval between adjacent tile nodes in the candidate chain conforms to the preset step interval allowable range of the defect type corresponding to the seed node, retaining tile nodes that conform to the allowable range in the candidate chain, and removing tile nodes that exceed the allowable range to obtain continuous defect segments, includes: Retrieve the defect step interval tolerance table corresponding to the dominant failure mode flag of the seed node. This defect step interval tolerance table defines the maximum allowable address interval in the row direction and the maximum allowable address interval in the column direction for each defect type. Take out two adjacent tile nodes from the candidate chain in sequence, read the row address and column address of the preceding node and the row address and column address of the following node respectively, and calculate the difference between the row address and the column address. When the row address difference exceeds the maximum allowed address interval in the row direction or the column address difference exceeds the maximum allowed address interval in the column direction, the position of the subsequent node in the candidate chain is recorded as the chain truncation position, and the subsequent node is marked as a breakpoint. All tile nodes before the discontinuity are defined as a continuous defect segment along the concatenation order of the candidate chain, and all tile nodes within this continuous defect segment are recorded in the chain. At the same time, the discontinuity and all subsequent tile nodes are moved into the unclassified node buffer. If no discontinuity is found after traversing all adjacent tile nodes in the candidate chain, the entire candidate chain is defined as a continuous defect segment. For each tile node identified as a continuous defect segment, the corresponding node record is cleared from the unclassified node buffer, and the node list and start and end addresses of the continuous defect segment are output, thus completing the acquisition of a continuous defect segment.

7. The method of claim 5, wherein, The step of using the physical addresses of the tile nodes located at both ends of the continuous defect segment as the packaging boundary address to generate a repair candidate packet for the failure physical addresses corresponding to all tile nodes in the continuous defect segment includes: Extract the physical addresses of the first and last nodes in the list of continuous defect segments. Use the row address of the first node as the row start address and the row address of the last node as the row end address. Compare the column addresses of the first and last nodes, and take the smaller column address as the column start address and the larger column address as the column end address. The row boundary descriptor in the packing boundary address is generated based on the row start address and the row end address, and the column boundary descriptor in the packing boundary address is generated based on the column start address and the column end address. The two descriptors are then combined to form the complete packing boundary address. The failed physical addresses of all tile nodes within the continuous defect segment are aggregated into an address group, and each address in the address group is traversed. The physical location of each failed physical address and the defect type label associated with the continuous defect segment are stored in the grouped record. Check whether the address group contains redundant resource allocation selection information that is available for both row repair and column repair. If so, mark the dual-resource repair option in the repair candidate package; otherwise, mark the single-resource repair option according to the direction of the continuous defect segment along the main expansion direction. Generate a defect type label for the repair candidate package, and encapsulate the defect type label, the packaging boundary address, the address group, and the repair options into a repair candidate package record; After the packaging operation of all body-level node pools is completed, all repair candidate package records are summarized to form the repair candidate package set.

8. The method of claim 1, wherein, The process involves acquiring the segmented redundancy layout information of the internal redundant resources of the tested memory chip after segmented decoding circuitry. This segmented redundancy layout information includes the row address range driven by each redundant row resource physical segment and the column address range driven by each redundant column resource physical segment. Based on this segmented redundancy layout information, the repair candidate packet is matched with the redundant resource segments, and a repair resource segment allocation table is output, including: Read the segmented decoding input signal lines of all redundant row resources in the bit width from the configuration register or hard-line preset of the memory chip under test, and parse the number of row segments and the address bit ranges participating in decoding in each row segment to form a row segment address range list. Read the segmented decoding input signal lines of all redundant column resources in the bit width and parse the number of column segments and the address bit ranges involved in decoding in each column segment to form a column segment address range list. For each repair candidate packet in the repair candidate packet set, extract the row boundary descriptor and column boundary descriptor of its packaging boundary address. Compare the row boundary descriptor with the row segment address range list one by one, and select the row segments whose row boundary descriptors fall completely within their address range as candidate row segments. Compare the column boundary descriptor with the column segment address range list one by one, and select the column segments whose column boundary descriptors fall completely within their address range as candidate column segments. Based on the dual-resource repair option or single-resource repair option markings of the repair candidate package, if row repair is marked as allowed, the number of row addresses to be replaced is calculated based on the packaging boundary address of the repair candidate package as the row repair requirement. A redundant row resource segment with an internal number of free redundant row resources not less than the row repair requirement is selected from the candidate row segments, and its segment identifier and the number of row resources to be allocated are recorded in the allocation entry. If column repair is marked as allowed, the number of column addresses to be replaced is calculated based on the packaging boundary address of the repair candidate package as the column repair requirement. A redundant column resource segment with an internal number of free redundant column resources not less than the column repair requirement is selected from the candidate column segments, and its segment identifier and the number of column resources to be allocated are recorded in the allocation entry. Write the segment identifier of the selected redundant resource segment, the starting number of the enabled resources within the segment, the packaging boundary address of the repair candidate package, and the defect type label into an allocation record. All allocation records corresponding to the repair candidate packages constitute the repair resource segment allocation table. In the repair resource segment allocation table, for multiple repair candidate packages that occupy the same redundant resource segment, the allocation order of their resource numbers within the segment is adjusted according to the priority of the defect type label, and the adjusted allocation order is updated in the repair resource segment allocation table.

9. The method of claim 8, wherein, The step of comparing each row boundary descriptor with the list of row segment address ranges and selecting row segments whose row boundary descriptors fall entirely within their address ranges as candidate row segments includes: Extract the row start address and row end address from the row boundary descriptor of the repair candidate packet to form a row address interval segment; A row segment entry is sequentially obtained from the row segment address range list. The row segment entry records the row segment start address and the row segment end address. The row start address of the row address interval is compared with the row segment start address, and the row end address of the row address interval is compared with the row segment end address. If the row start address is not less than the row segment start address and the row end address is not greater than the row segment end address, then the row segment is determined to be a candidate row segment, and the segment identifier of the row segment is added to the candidate row segment list. If the row start address is less than the row segment start address or the row end address is greater than the row segment end address, then the row segment is determined not to meet the complete inclusion condition and is skipped. Traverse all row segment entries in the row segment address range list, perform a one-to-one comparison between the row boundary descriptor and all row segments, and output the candidate row segment list for subsequent selection of redundant row resource segments.

10. A testing apparatus for a memory chip, characterized by comprising: include: The data acquisition module is used to acquire the set of failure addresses generated after the memory chip under test is tested by a multi-level test vector set containing different defect sensitization conditions. Each failure physical address in the set of failure addresses is accompanied by a failure mode marker. The structure construction module is used to construct a failure texture map data structure based on the spatial distribution of the failed physical addresses in the failure address set within the storage array and their respective failure mode markers. The failure texture map data structure includes tile nodes indexed by the failed physical address. Each tile node covers descriptive information of the failure density within a preset address neighborhood centered on the failed physical address and statistical information of the dominant failure mode markers within that neighborhood. The data packaging module is used to package the failure texture map data structure into repair groups based on the constraint of defect expansion law, and generate a repair candidate package by merging multiple failure physical addresses that meet the same defect type mark and whose spatial location is continuously distributed along the defect expansion direction. The resource matching module is used to obtain the segmented redundancy layout information of the redundant resources inside the tested memory chip after being divided by the segmented decoding circuit. The segmented redundancy layout information includes the row address range driven by each redundant row resource physical segment and the column address range driven by each redundant column resource physical segment. Based on the segmented redundancy layout information, the repair candidate package is matched with the redundant resource segments, and a repair resource segment allocation table is output. The instruction generation module is used to generate a set of segmented repair control instructions based on the repair resource segment allocation table. Each instruction in the set of segmented repair control instructions records the number of the replacement resource that is enabled in the redundant resource segment, the range of the address range to be replaced, and the effective polarity of the segment enable signal. The verification test module is used to call the contents of the repair resource segment allocation table to guide the temporary repair logic circuit built into the memory chip under test to apply overlapping read and write operations at the segment boundary, perform stress verification tests on the adjacent address intervals of the segment boundary, obtain the segment boundary stress test result set, and when the segment boundary stress test result set indicates that no new failure address has been generated in the boundary overlapping area, the segment repair control instruction set is solidified and written into the non-volatile repair control information storage area of ​​the memory chip under test.

11. A testing device, comprising a memory and a processor, wherein the memory stores a computer program executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method according to any one of claims 1 to 9.

12. A computer readable storage medium having stored thereon a computer program, characterized in that, When executed by a processor, the computer program implements the steps of the method according to any one of claims 1 to 9.

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