Memristor array parallel testing system integrating multi-channel source table and matrix switch

Abstract

The application discloses a kind of integrated multi-channel source table and matrix switch memristor array parallel test system, comprising: multi-channel source measurement unit (1), provide multiple source measurement channels to work independently in direct current or pulse mode, as excitation source applies voltage or current, or as measurement unit collects current or voltage response;Matrix switch module (2) is connected with each source measurement channel of the multi-channel source measurement unit (1) one by one, and its output port is connected to the full row line and column line of probe row respectively through multiplexing topology;Probe row (3) is arranged with spring probe socket corresponding to the row electrode and column electrode of the array to be measured, for test system connection;Test main control unit is connected with multi-channel source measurement unit (1) and matrix switch module (2) communication connection through LAN bus respectively.The application can fundamentally eliminate the contact resistance fluctuation and calibration inconsistency problem introduced by artificial alignment.

Description

Technical Field

[0001] This invention relates to the field of microelectronic device testing technology, and in particular to a parallel testing system for memristor arrays that integrates multi-channel source meters and matrix switches. Background Technology

[0002] In recent years, memristors have been widely regarded as core candidate devices for next-generation non-volatile memory and neuromorphic computing hardware due to their non-volatility, miniaturization, multi-value storage capabilities, and compatibility with CMOS processes. In memristor storage or computing systems integrated with cross-array structures, accurate and efficient electrical characteristic testing of each unit device in the array is fundamental for evaluating device performance, studying array operation schemes, and analyzing inter-device crosstalk and yield. However, testing memristor cross-arrays faces several unique challenges.

[0003] Currently, laboratory testing of memristor cross-arrays typically employs the following approach: A separate signal generator or semiconductor parameter analyzer is used as the excitation and measurement source, connected to an external mechanical probe array. The array under test is manually contacted and excited row by row or point by point. For example, for a 5×5 array, the operator must align the probe array with a row or column of electrode pads, connecting only one device or row corresponding to that row / column at a time for DC scanning or pulse excitation. After completion, the probe array is manually moved to the next position, repeating the operation until all devices have been traversed.

[0004] However, this existing testing method has obvious technical flaws: First, the testing efficiency is extremely low and introduces significant human error. The entire testing process relies on operators repeatedly aligning the probe array with the array microelectrodes manually, which is extremely time-consuming. Performing a complete molding, positioning / resetting, and IV scan test on a 5×5 array typically takes tens of minutes to several hours. Manual alignment is prone to introducing contact resistance fluctuations due to inconsistent calibration, resulting in significant deviations in the measured values ​​of key parameters such as molding voltage and operating voltage, making it difficult to reproduce test data from different rounds.

[0005] Secondly, effective multi-channel parallel excitation and crosstalk testing cannot be achieved. One of the key application scenarios of memristor crossbar arrays is to perform half-select voltage parallel operation on multiple cells or to study creeping path effects. However, traditional single-channel or limited-channel solutions with manual probe arrays are limited by the number of physical connections and cannot simultaneously apply independent and synchronous excitation signals to multiple word lines or bit lines. Furthermore, it is difficult to measure the dynamic interference and crosstalk current distribution between cells at the array level, which severely restricts the development and verification of array-level operation algorithms.

[0006] Third, the testing process carries the risk of device misoperation. During manual switching of the row / column under test, the removal and re-contact of the probes, as well as the physical movement of the test cables, can introduce uncontrollable transient leakage currents or electrostatic discharges. For state-sensitive nanoscale memristors, such unexpected voltage or current spikes can easily cause misconfiguration or reset of surrounding devices, and may even lead to drift or permanent damage to the intrinsic resistance state of the device, severely affecting the accuracy of test results and the evaluation of device yield.

[0007] Therefore, there is an urgent need for a new test system and method that can achieve automated, high-precision, multi-channel parallel excitation and measurement of memristor arrays, so as to fundamentally overcome the shortcomings of traditional manual testing in terms of efficiency, accuracy and functional coverage. Summary of the Invention

[0008] The purpose of this invention is to provide a parallel test system for memristor arrays that integrates multi-channel source meters and matrix switches, in order to solve the technical problems of low automation, resulting in low efficiency and insufficient test accuracy in existing memristor array test schemes; and the uncontrollable disturbances in the manual switching process, which can easily lead to device malfunctions.

[0009] This invention is achieved using the following technical solution: a parallel test system for memristor arrays integrating multi-channel source meters and matrix switches, comprising: The multi-channel source measurement unit provides multiple source measurement channels to operate independently in DC or pulse mode, either as an excitation source to apply voltage or current, or as a measurement unit to acquire current or voltage response. The matrix switch module is connected one-to-one with each source measurement channel of the multi-channel source measurement unit, and its output port is connected to all row lines and column lines of the probe array through a multiplexing topology. The probe array is equipped with spring probe sockets that correspond one-to-one with the row and column electrodes of the array under test, for connection to the test system. The test control unit is connected to the multi-channel source measurement unit and the matrix switch module via a LAN bus. The test control unit is configured to: shut down the output of the relevant source measurement channel before switching any row or column by matrix switch, and apply the preset excitation waveform from zero after the matrix switch connection is stable.

[0010] Furthermore, there are two multi-channel source measurement units, and each multi-channel source measurement unit is equipped with three source meter modules. Each source meter module has two source meter output channels, and the source meter modules are connected to the matrix switch module through the source meter output channels.

[0011] Furthermore, the matrix switch module includes six matrix switch boards, with every three matrix switch boards connected to a multi-channel source measurement unit. Under the control of the test main control unit, the matrix switch boards can quickly switch any one or more input channels to any row or column of electrodes in the array via software programming.

[0012] Furthermore, the array under test is a 5×5 memristor cross array.

[0013] Furthermore, the memristor array parallel test system adopts a steady-state switching strategy of disconnection, grounding, switching, connection, and excitation to eliminate the transient voltage spikes and electrostatic discharge risks introduced by manual line switching, ensuring that unselected devices are always in a safe static bias environment.

[0014] Furthermore, the memristor array parallel test system is used for automated addressing and traversal testing, which includes the following steps: Initial configuration; Stochastic configuration; Motivation and measurement; Iterate through the loop.

[0015] Furthermore, the initial configuration includes: connecting the row electrodes and column electrodes of the array under test to the corresponding row pins and column pins of the probe array (3), respectively; loading the layout file of the array under test into the test main control unit; and establishing a mapping table between the coordinates of each device and its corresponding row / column channel.

[0016] Furthermore, the gating configuration includes: when an electrical operation is required on the target device with coordinates (i, j) in the array, the test master control unit controls the matrix switch module (2) to connect the first source measurement channel to the i-th row and the second source measurement channel to the j-th column; other unselected rows and columns in the array are switched to ground, floating or preset bias ports according to test requirements to suppress creeping path interference.

[0017] Furthermore, the excitation and measurement include: independently connecting the two ends of the array under test to two different source measurement channels, one channel as the excitation terminal to apply a scanning voltage or pulse sequence, and the other channel as the acquisition terminal to measure the current flowing through the device, thereby obtaining the DC IV characteristics or pulse response characteristics of the array under test.

[0018] Furthermore, the traversal loop includes: the test control unit automatically traversing all coordinate points in the array, repeating the above steps until all predetermined test items of the entire array are completed.

[0019] The beneficial effects of this invention are as follows: This invention establishes a fully topologically programmable connection between each independent channel of a multi-channel source meter and all row and column electrodes of the array using a matrix switch. Combined with the automatic traversal algorithm of the test control unit, it enables one-time wiring and fully automated testing of 5×5 or even larger memristor arrays. Operators only need to connect the array to the interface motherboard at the initial testing stage; subsequent device addressing and switching are completed by software in microseconds, completely eliminating the time-consuming manual movement of probe blocks in traditional solutions. In actual comparisons, for a complete DC IV scan and pulse shaping test of 25 devices, the total test time was reduced from tens of minutes using traditional methods to minutes, and the test throughput was increased by more than an order of magnitude.

[0020] This invention overcomes the inherent limitation of traditional single-channel testing schemes, which can only excite points one by one, by leveraging the complete independence of each channel in a multi-channel source table and the flexible routing capability of a matrix switch. The system can simultaneously apply independent and synchronous bias voltages or pulse sequences to multiple row and column lines in the array, realistically simulating the working environment of a memristor array in actual storage or computing operations. Combined with multi-channel synchronous acquisition, it can accurately measure the basic performance of the memristor array, providing an irreplaceable hardware experimental platform for verifying novel memristors. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the system of the present invention; In the figure, 1-multi-channel source measurement unit, 2-matrix switch module, 3-probe array, 4-source meter module. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0024] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0025] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0026] See Figure 1 A parallel test system for memristor arrays integrating multi-channel source meters and matrix switches is characterized by comprising: a multi-channel source measurement unit 1, providing multiple source measurement channels to operate independently in DC or pulse mode, serving as an excitation source to apply voltage or current, or as a measurement unit to acquire current or voltage responses; a matrix switch module 2, connected one-to-one with each source measurement channel of the multi-channel source measurement unit 1, its output port being connected to all row and column lines of a probe array via a multiplexing topology; a probe array 3, equipped with spring probe sockets corresponding one-to-one with the row and column electrodes of the array under test, for connection to the test system; and a test main control unit, communicating with the multi-channel source measurement unit 1 and the matrix switch module 2 via a LAN bus.

[0027] In this embodiment, there are two multi-channel source measurement units 1, and each multi-channel source measurement unit 1 is equipped with three source meter modules 4. Each source meter module 4 has two source meter output channels, and the source meter modules 4 are connected to the matrix switch module 2 through the source meter output channels. The matrix switch module 2 includes six matrix switch boards. Under the control of the test master control unit, the matrix switch boards can be programmed in software to quickly switch any one or more input channels to any row or column of electrodes in the array. The test master control unit is communicatively connected to the multi-channel source measurement unit 1 and the matrix switch boards, and is responsible for executing the preset test sequence, controlling the conduction configuration of the matrix switches, and synchronously collecting the measurement data of each channel. The probe array 3 has 10 probes, which can provide the electrode interface of the array under test: the row and column electrode leads of the 5×5 memristor array, which are usually arranged in the form of probe arrays on the array motherboard for connection by the test system.

[0028] In this embodiment, the multi-channel source measurement unit 1 can be a high-precision source meter host equipped with 10 independent source measurement channels. Each channel has DC output and pulse generation functions. Different source measurement channels are electrically isolated from each other and can synchronously execute different excitation and measurement tasks. This is the physical basis for the parallel testing of this invention.

[0029] In this embodiment, the matrix switch module 2 consists of six switch boards, from matrix board 1 to matrix board 6. Each board has excellent conductivity, ensuring leakage current capability at the pA level. Under the command of the test control unit, flexible interconnection between any source meter channel and any array row / column can be achieved.

[0030] In this embodiment, probe row 3 is a printed circuit board with spring probe sockets that correspond one-to-one with the row and column electrodes of the 5×5 array under test. There are five row electrode pads arranged in a row, labeled R1 to R5; and five column electrode pads arranged in a column, labeled C1 to C5. During testing, the 5×5 memristor array under test is fixed to the motherboard via wire bonding or crimping, ensuring that each word line and bit line of the array is reliably connected to the corresponding pad on the probe row. Each pad on the probe row is connected to a standard coaxial connector via printed traces for the output cable of the aforementioned matrix switch board. Therefore, only an initial physical clamping is required between the array under test and the test system; all subsequent test operations are performed in a fully electrified environment without any probe movement.

[0031] In this embodiment, the test control unit is a general-purpose computer that communicates with the multi-channel source meter host and the matrix switch controller via a LAN bus. The control unit runs self-developed test control software, which is loaded with array layout files, a mapping table of device coordinates to rows / columns, and user-preset test sequence scripts.

[0032] Using the parallel test system architecture for memristor arrays provided by this invention, all test tasks can be completed through software configuration simply by connecting the 5×5 memristor cross array to be tested to the array interface motherboard beforehand, without the need for any physical probe movement.

[0033] Furthermore, this memristor array parallel test system can perform automated addressing and traversal testing. Specifically, this automated addressing and traversal testing includes: Initial configuration: Connect the row and column electrodes of the 5×5 array to the corresponding row and column pins of the array interface motherboard, respectively. The test control unit loads the layout file of the array and establishes a mapping table between the coordinates of each device and its corresponding row / column channel.

[0034] Gating configuration: When an electrical operation is required on the target device at coordinates (i, j) in the array, the main control unit controls the matrix switch to connect the first source measurement channel to the i-th row and the second source measurement channel to the j-th column; other unselected rows and columns in the array are switched to ground, floating or preset bias ports according to the test requirements to suppress creeping path interference.

[0035] Excitation and Measurement: Two ends of the target device are independently connected to two different source measurement channels. One channel acts as the excitation terminal, applying a scanning voltage or pulse sequence, while the other channel acts as the acquisition terminal, measuring the current flowing through the device, thereby obtaining the DC IV characteristics or pulse response characteristics of the unit device.

[0036] Traversal loop: The test master unit automatically traverses all coordinate points in the array, repeating steps 2 and 3 until all the predetermined test items for all 25 devices in the array are completed.

[0037] Furthermore, to overcome the challenge of traditional solutions being unable to perform array-level parallel testing, this invention possesses multi-channel parallel operation capabilities: when studying array interference under half-select voltage, the main control unit is configured with a matrix switch to synchronously activate multiple source measurement channels. Specifically, five source meter channels apply excitation to a row of memristors, while another five source meter channels measure the state of this row of memristors. The array memristors can be tested by controlling the matrix switch. Since the matrix switch and each channel of the source meter are completely independent, this parallel excitation and synchronous measurement can be completed without changing any physical connections, thereby enabling precise quantification and analysis of the state of the memristors in the array under different excitations.

[0038] To address the core challenge of device malfunction caused by electrical disturbances introduced by manual switching, this invention employs a safe electrical switching method: the selection and disconnection of any device are entirely executed by a matrix switch, requiring no movement of physical probes or cables. Before performing row or column switching, the test control unit can first shut down the output of the relevant source measurement channels. After the switch connection stabilizes, a preset excitation waveform is applied from zero. This steady-state switching strategy of disconnect-ground-switch-connect-excitation fundamentally eliminates the transient voltage spikes and electrostatic discharge risks introduced by manual line switching, ensuring that unselected devices are always in a safe static bias environment.

[0039] The following example demonstrates the complete operation steps of this embodiment by performing a DC IV characteristic scan on all 25 memristor cells of a 5×5 array.

[0040] Step 1: Initial Connection and System Configuration The operator connects the prepared 5×5 memristor cross array to the system via a probe array, confirming good conductivity on row lines R1-R5 and column lines C1-C5. An array mapping table is loaded onto the test control unit, defining the row line Ri and column line Cj corresponding to the device at coordinate (i, j). For example, the target device located in row 2, column 3 corresponds to R2 and C3. Simultaneously, the user sets the parameters for each test item in the software interface, including the start voltage, end voltage, voltage step, current limit, and data sampling rate for the DC scan.

[0041] Step 2: Target device selection configuration Once the test sequence is initiated, the main control unit first traverses to the current coordinates of the device under test, for example, (2, 3). The main control unit configures the matrix switch via instructions; the specific control logic is as follows: Turn on matrix board 1 and matrix board 4, so that the Force / Sense terminal of source table module 1 is connected to array row line R2; Turn on matrix board 2 and matrix board 5, so that the Force / Sense terminal of source table module 2 is connected to array column line C3; Connect the remaining unselected row lines R1, R3, R4, R5 and unselected column lines C1, C2, C4, C5 to the system ground or leave them floating via matrix board 6. The specific bias strategy is selected by the software according to the test requirements: if it is necessary to suppress creeping paths, ground both the unselected rows and columns; if it is necessary to simulate half-selected bias conditions, connect the unselected rows and columns to the preset bias voltage.

[0042] At this point, the top electrode of the target device (2, 3) is connected to the excitation terminal of source meter module 1 via row line R2, and the bottom electrode is connected to the acquisition terminal of source meter module 2 via column line C3, forming a complete four-wire Kelvin measurement circuit. The entire configuration process of the matrix switch is completed in milliseconds by electronic relays.

[0043] Step 3: Safe Steady-State Switching and Excitation Measurement In this invention, to ensure that no transient disturbances occur during the test, all channels execute controlled operation timing before and after switching. Specifically, before executing the matrix switch configuration in step two, the main control unit first instructs both source meter module 1 and source meter module 2 to forcibly set their outputs to 0V and current-limiting mode. After all matrix switches have completed their operations and the relay contacts have closed stably, the main control unit then sends a DC scan command to source meter module 1.

[0044] Source module 1 performs a linear scan starting from the initial voltage according to preset parameters. Simultaneously, source module 2 maintains a 0V virtual ground and collects the current flowing through the device in real time. The current value corresponding to each voltage step is synchronously recorded by the built-in analog-to-digital converters of the two source modules and transmitted back to the main control unit for storage via the bus. When the scan voltage reaches the predetermined maximum value or the current reaches the current limiting threshold, the scan terminates, and the excitation of source module 1 automatically returns to zero. Thus, the single DC IV characteristic measurement of device (2, 3) is completed.

[0045] Step 4: Automatic Traversal of the Entire Array The main control unit automatically jumps to the next device coordinate based on the array mapping table, repeating steps two and three. The traversal order can be row-by-row scanning, column-by-column scanning, or any user-defined path. This process is entirely automated and controlled by software until all 25 devices have completed their scheduled test items. Throughout the entire testing cycle, the operator does not need to touch any hardware.

[0046] Based on the above embodiments, the present invention has at least the following technical effects: Since there is no movement or re-contact of any physical probes during the entire testing process, the contact conditions of each measurement loop remain constant, fundamentally eliminating the contact resistance fluctuations and calibration inconsistencies introduced by manual alignment. Simultaneously, each channel of the multi-channel source meter possesses independent high-precision measurement capabilities, allowing for precise and controllable excitation of each unit device and synchronous acquisition of the response current. This significantly reduces measurement deviations for key parameters such as molding voltage and high / low resistance distribution. Test data from different batches and time points exhibit excellent comparability and reproducibility, providing a reliable data foundation for statistical modeling of memristor devices and arrays.

[0047] This invention employs a fully electronic steady-state switching strategy, replacing physical probe movement with matrix switches. Before selecting or disconnecting any device, the test control unit can first shut down the relevant channel outputs, and then apply the excitation waveform after the switch connection is fully established. This controlled operation sequence completely eliminates transient voltage spikes, electrostatic discharge, and contact bounce caused by the physical movement of cables and probes during manual testing. In principle, it eliminates the fatal disturbance sources that lead to mis-setting, mis-resetting, or impedance drift of unselected devices, thereby maximizing the protection of the intrinsic characteristics of the device under test and ensuring that the test results accurately reflect the inherent reliability and yield level of the memristor array.

[0048] The modular architecture of the multi-channel source table-matrix switch-probe array proposed in this invention is independent of the physical design of arrays of a specific size. By increasing the number of ports of the matrix switch and the number of source table channels, it can be linearly expanded to support the testing needs of 8×8, 10×10 and larger arrays without fundamentally modifying the core test and control architecture and software logic. Furthermore, this testing system is also applicable to other array topologies, exhibiting good device adaptability and laboratory versatility, and can widely serve memristor research and development work in universities, research institutes, and semiconductor companies.

[0049] For the foregoing embodiments, in order to simplify the description, they are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, because according to this application, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to this application.

[0050] The above embodiments describe the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Modifications and variations made by those skilled in the art without departing from the spirit and scope of the invention should be within the protection scope of the appended claims.

Claims

1. A parallel test system for memristor arrays integrating multi-channel source meters and matrix switches, characterized in that, include: The multi-channel source measurement unit (1) provides multiple source measurement channels to work independently in DC or pulse mode, to apply voltage or current as an excitation source, or to acquire current or voltage response as a measurement unit; The matrix switch module (2) is connected one-to-one with each source measurement channel of the multi-channel source measurement unit (1), and its output port is connected to all row lines and column lines of the probe array through a multiplexing topology. The probe array (3) is equipped with spring probe sockets that correspond one-to-one with the row and column electrodes of the array under test, for connection to the test system; The test control unit is connected to the multi-channel source measurement unit (1) and the matrix switch module (2) via the LAN bus. The test control unit is configured to: turn off the output of the relevant source measurement channel before switching any row or column by matrix switch, and apply the preset excitation waveform from zero after the matrix switch connection is stable.

2. The memristor array parallel test system integrating multi-channel source meters and matrix switches as described in claim 1, characterized in that, There are two multi-channel source measurement units (1), and each multi-channel source measurement unit (1) is equipped with three source table modules (4). Each source table module (4) has two source table output channels. The source table module (4) is connected to the matrix switch module (2) through the source table output channels.

3. The integrated multi-channel source list and matrix switch memristor array parallel test system of claim 2, wherein, The matrix switch module (2) includes six matrix switch boards. Every three matrix switch boards are connected to a multi-channel source measurement unit (1). Under the control of the test main control unit, the matrix switch boards can quickly switch any one or more input channels to any row or column of electrodes in the array by means of software programming.

4. The integrated multi-channel source list and matrix switch memristor array parallel test system of claim 3, wherein, The array under test is a 5×5 memristor cross array.

5. The integrated multi-channel source list and matrix switch memristor array parallel test system of claim 4, wherein, The memristor array parallel test system adopts a steady-state switching strategy of disconnection, grounding, switching, connection, and excitation to eliminate the transient voltage spikes and electrostatic discharge risks introduced by manual line switching, and ensure that unselected devices are always in a safe static bias environment.

6. The system of any one of claims 1-5, wherein the system further comprises a plurality of source tables, each source table comprising a plurality of source channels, each source channel comprising a source driver and a source resistor. The memristor array parallel test system is used for automated addressing and traversal testing, which includes the following steps: Initial configuration; Stochastic configuration; Motivation and measurement; Iterate through the loop.

7. The integrated multi-channel source list and matrix switch memristor array parallel test system of claim 6, wherein, The initial configuration includes: connecting the row electrodes and column electrodes of the array under test to the corresponding row pins and column pins of the probe array (3), respectively; loading the layout file of the array under test into the test main control unit; and establishing a mapping table between the coordinates of each device and its corresponding row / column channel.

8. The integrated multi-channel source list and matrix switch memristor array parallel test system of claim 6, wherein, The gating configuration includes: when an electrical operation is required on the target device with coordinates (i, j) in the array, the test master control unit controls the matrix switch module (2) to connect the first source measurement channel to the i-th row and the second source measurement channel to the j-th column; other unselected rows and columns in the array are switched to ground, floating or preset bias ports according to the test requirements to suppress creeping path interference.

9. The integrated multi-channel source list and matrix switch memristor array parallel test system of claim 6, wherein, The excitation and measurement include: independently connecting the two ends of the array under test to two different source measurement channels, one channel as the excitation terminal to apply a scanning voltage or pulse sequence, and the other channel as the acquisition terminal to measure the current flowing through the device, thereby obtaining the DC IV characteristics or pulse response characteristics of the array under test.

10. The memristor array parallel test system integrating multi-channel source meters and matrix switches as described in claim 6, characterized in that, The traversal loop includes the master control unit automatically traversing all coordinate points in the array, repeating the above steps until all predetermined test items of the entire array are completed.

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