Multi-chip series laser package structure and preparation method thereof

Abstract

This invention relates to a multi-chip tandem laser packaging structure and its fabrication method, belonging to the technical field of semiconductors. The packaging structure comprises a chip, an upper substrate, and a lower substrate. Multiple lower substrate bumps and grooves are alternately arranged on the upper surface of the lower substrate, while the lower surface of the upper substrate has matching upper substrate grooves and bumps. A chip is placed between each set of matching bumps and grooves. The lower substrate bumps have through-hole isolation grooves; the upper substrate grooves also have through-hole isolation grooves. An insulating layer, a metal layer, and a solder layer are sequentially formed on the surfaces of the bumps and grooves of both the lower and upper substrates. On the lower substrate bumps, chip one has its P-side facing upwards, and in the lower substrate grooves, chip two has its N-side facing upwards. This invention eliminates the need for the 45° reflector required in existing technologies, achieving chip insulation and tandem connection through the substrate metal solder isolation grooves, thus eliminating the high-cost reflector component and significantly reducing device material costs.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and specifically to a multi-chip tandem laser packaging structure and its fabrication method. Background Technology

[0002] Semiconductor lasers have advantages such as small size, high efficiency, and long lifespan, and are widely used in industrial processing, medical aesthetics, optical communication, and consumer electronics. With the development of portable devices, laser displays, and integrated optoelectronic sensing systems, higher requirements are being placed on laser light sources: on the one hand, high optical power output is needed to meet application needs; on the other hand, packaging structures are required to be thinner and smaller to facilitate system integration.

[0003] Patent JP2004205701A describes a semiconductor laser packaging and fabrication method, as shown in the figure below: The laser and a reflector are mounted on a substrate. The reflector reflects the light emitted from the chip by 90°, causing it to emit light upwards. The positive electrode of the laser chip is led out through a perforated substrate, and the negative electrode is led out through gold wire bonding. When multiple chips are needed, multiple sets of identical structures are required to connect the lasers together.

[0004] However, the technical approach in the aforementioned patent requires the use of a 45° reflector, which has a high manufacturing cost. When aligning the laser with the reflector, high assembly precision is required. When packaging multiple chips, it is difficult to guarantee the consistency of the distance between the laser and the reflector. It is also difficult to guarantee the accuracy of the beams of multiple chips on a single axis, resulting in low yield, strong dependence on high-precision equipment, and high cost. Summary of the Invention

[0005] To address the problems of high mirror manufacturing cost, stringent assembly precision requirements between chips and mirrors, difficulty in controlling optical spacing and beam coaxiality consistency during multi-chip packaging, low packaging yield and high dependence on high-precision equipment, and high overall production cost in existing multi-chip semiconductor lasers, this invention provides a multi-chip tandem laser packaging structure and its fabrication method to solve the above problems.

[0006] The technical solution of this invention is as follows: In a first aspect, the present invention provides a multi-chip tandem laser packaging structure, comprising a chip, an upper substrate, and a lower substrate. The upper surface of the lower substrate is alternately provided with multiple lower substrate bumps and lower substrate recesses, and the lower surface of the upper substrate is provided with matching upper substrate recesses and upper substrate bumps. A chip is disposed between each set of matching bumps and recesses. The lower substrate bumps are provided with through-hole isolation grooves; the upper substrate recesses are provided with through-hole isolation grooves; an insulating layer, a metal layer, and a solder layer are sequentially disposed on the surfaces of the bumps and recesses of both the lower and upper substrates; on the lower substrate bumps, chip one with its P-side facing upwards, and in the lower substrate recesses, chip two with its N-side facing upwards.

[0007] Furthermore, the length of the lower substrate = chip width × 2 × number of chips; the width of the lower substrate = chip cavity length + 200μm; the height of the lower substrate is 2~3mm.

[0008] Furthermore, the depth of the grooves in the lower substrate and the upper substrate is the same as the thickness of the chip substrate, and the depth is 100~150μm. The width of the grooves in the lower substrate and the upper substrate is the width of the bosses in the upper substrate and the lower substrate + 0.2mm.

[0009] Furthermore, the upper and lower substrates are made of copper. The length of the upper substrate is equal to the length of the lower substrate plus 0.5 mm; the widths of the upper and lower substrates are the same; and the thicknesses of the upper and lower substrates are the same.

[0010] Furthermore, the insulating layer is SiO2, Si3N4 or Al2O3, with a thickness of 200nm~500nm.

[0011] Furthermore, the solder layer is AuSn or In; the total thickness of the metal layer and the solder layer is 4~6μm.

[0012] Furthermore, the width of the isolation groove is 0.05~0.1mm, which is used to separate the metal layer and the solder layer.

[0013] Furthermore, the chip is placed at the center of the boss and the groove.

[0014] Furthermore, the multi-chip tandem laser packaging structure also includes a housing, with the upper substrate and lower substrate connected to the housing; the housing thickness is 2~3mm, the housing length is greater than the upper substrate length + 10mm, and the housing width is greater than the upper substrate + lower substrate height + 10mm; a fence with a height of 1~1.5mm is provided on one side of the housing, and negative and positive terminals are respectively provided on the fence, with the negative and positive terminals insulated from the fence; two fixing holes are provided on the bottom plate of the housing.

[0015] Secondly, the present invention provides a method for preparing the above-mentioned multi-chip tandem laser packaging structure, as detailed below: (1) Prepare a lower substrate, grow an insulating layer on the upper surface of the lower substrate, and then grow a metal layer and a solder layer in sequence; (2) Counting from the left side of the lower substrate, a through-hole is cut on the left side of the second boss to separate the metal layer and the solder layer; (3) Prepare the upper substrate, the length of the upper substrate = the length of the lower substrate + 0.5 mm, grow an insulating layer on the lower surface of the upper substrate, and then grow a metal layer and a solder layer in sequence; (4) Starting from the left side of the upper substrate, a through-hole is cut into the right side of the first groove to separate the metal layer and the solder layer; (5) Place the semiconductor laser chip on the lower substrate, with the P-side of the protrusion chip facing up and the N-side of the groove chip facing up. The chip is placed in the middle of the protrusion or groove, and the light-emitting surface of the chip is aligned with the substrate surface. (6) Align the groove of the upper substrate with the protrusion of the lower substrate to ensure that the chip is aligned with the middle position of the groove and protrusion of the upper substrate; then use a sintering fixture to clamp the upper substrate and the lower substrate, and sinter the upper substrate, the lower substrate and the chip into a whole. (7) The upper and lower substrates of the sintered multi-chip tandem laser are sintered onto the tube shell with solder, wherein the bottom surfaces of the upper and lower substrates are sintered with the bottom plate of the tube shell, and the two sides of the upper substrate are aligned and sintered with the two tube pins respectively. After sintering, a multi-chip tandem laser packaging structure is obtained.

[0016] The beneficial effects of this invention are as follows: The multi-chip tandem laser packaging structure provided by this invention eliminates the need for the 45° reflector required in existing technologies. It achieves chip-to-chip insulated tandem packaging by relying on substrate metal solder isolation grooves, thus eliminating the high-cost reflector component and significantly reducing device material costs. By matching the substrate groove depth to the chip epitaxial substrate thickness, the light-emitting areas of all chips with different placement methods are aligned on the same horizontal line, eliminating the need for high-precision alignment and assembly equipment. In multi-chip packaging, optical spacing and beam coaxiality consistency are controllable, significantly improving packaging yield.

[0017] The multi-chip tandem laser packaging structure provided by this invention employs upper and lower dual substrates to dissipate heat from the P-side of the chips, resulting in superior heat dissipation performance and suitability for multi-chip integration applications. Solder interconnects are used between chips and between pins and the substrate, eliminating all gold wire bonding processes, simplifying the packaging process, improving electrode connection reliability, and reducing reliance on high-precision assembly equipment. The overall package thickness is significantly reduced, achieving ultra-thin miniaturized laser packaging and broadening the application scenarios for the device. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the chip substrate structure in Embodiment 1 of the present invention.

[0020] Figure 2 This is a schematic diagram of the chip substrate structure in Embodiment 1 of the present invention.

[0021] Figure 3 This is a schematic diagram of the chip placement direction in Embodiment 1 of the present invention.

[0022] Figure 4 This is a schematic diagram of the sintering of the upper and lower substrates in Embodiment 1 of the present invention.

[0023] Figure 5 This is a schematic diagram of the tube shell of Embodiment 1 of the present invention.

[0024] Figure 6 This is a schematic diagram of the sintering of the chip substrate and the casing in Embodiment 1 of the present invention.

[0025] Figure 7 This is a schematic diagram of the connection between the casing pins and the chip substrate in Embodiment 1 of the present invention.

[0026] Among them, 1-lower substrate, 2-lower substrate groove, 3-lower substrate boss, 4-insulating layer, 5-solder layer, 6-isolation groove, 7-upper substrate, 8-upper substrate groove, 9-upper substrate boss, 10-chip light-emitting surface, 11-chip one, 12-chip two, 13-shell bottom plate, 14-enclosure, 15-negative electrode pin, 16-positive electrode pin, 17-fixing hole, 18-positive electrode connection point, 19-negative electrode connection point. Detailed Implementation

[0027] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0028] Example 1 A multi-chip tandem laser packaging structure is disclosed. The selected laser chip dimensions are: width 0.5 mm, length 1500 μm, and thickness 110 μm (including an epitaxial substrate thickness of 106 μm). A 6-chip integrated package is required. The specific fabrication method is as follows: (1) Make a chip substrate made of copper. The length of the substrate is 0.5×2×6=6mm, the width of the substrate is 1500μm+200μm=1700μm, and the height of the substrate is 2mm. Make grooves on the upper surface of the substrate. The width of the groove is 1mm, the depth of the groove is 106μm, and the number of grooves is 3.

[0029] (2) An insulating layer SiO2 is grown on the upper surface of the lower substrate with a thickness of 300 nm; then a metal layer and an AuSn solder layer are grown, with a total thickness of 4 μm.

[0030] (3) Starting from the second boss on the left side of the lower substrate, cut an isolation groove with a width of 0.05mm on the upper surface of the boss to separate the metal layer and the solder layer.

[0031] (4) Make a chip substrate made of copper. The length of the substrate is 0.5×2×6+0.5=6.5mm, the width of the substrate is 1500μm+200μm=1700μm, and the thickness of the substrate is 2mm. Make grooves on the substrate. The width of the grooves is 1mm, the depth of the grooves is 106μm, and the number of grooves is 3.

[0032] (5) An insulating layer SiO2 is grown on the lower surface of the upper substrate with a thickness of 300 nm; then a metal layer and an AuSn solder layer are grown, with a total thickness of 4 μm. (6) Starting from the left side of the upper substrate, cut an isolation groove with a width of 0.05mm on the right side of the first groove to separate the metal layer and the solder layer; (7) Place the semiconductor laser chip on the lower substrate, with the P-side of the protruding chip facing up and the N-side of the recessed chip facing up. The chip is placed in the middle of the protrusion or recess, and the light-emitting surface of the chip is aligned with the substrate surface. (8) Align the groove of the upper substrate with the protrusion of the lower substrate to ensure that the chip is aligned with the middle position of the groove and protrusion of the upper substrate; then use a sintering fixture to clamp the upper substrate and the lower substrate, and sinter the upper substrate, the lower substrate and the chip into a whole. (9) Make a laser tube shell with a thickness of 3mm, a length of 17mm and a width of 14mm; set a fence on one side of the tube shell with a height of 1mm, and set two tube feet on the fence, which are the positive and negative poles of the laser respectively, and the tube feet are insulated from the fence; set two fixing holes on the bottom plate of the tube shell. (10) The upper and lower substrates of the sintered multi-chip tandem laser are sintered onto the tube shell with solder, wherein the bottom surfaces of the upper and lower substrates are sintered with the bottom plate of the tube shell, and the two sides of the upper substrate are aligned and sintered with the two tube pins respectively. After sintering, a multi-chip tandem laser packaging structure is obtained.

[0033] The fabricated multi-chip tandem laser packaging structure is as follows: A multi-chip tandem laser packaging structure comprises a chip, an upper substrate 7, and a lower substrate 1. The upper surface of the lower substrate 1 has three alternating lower substrate protrusions 3 and three lower substrate recesses 2. The lower surface of the upper substrate 7 has mating upper substrate recesses 8 and upper substrate protrusions 9. A chip is disposed between each set of mating protrusions and recesses. The lower substrate protrusions 3 have through-hole isolation grooves 6. The upper substrate recesses 8 also have through-hole isolation grooves 6. An insulating layer 4, a metal layer, and a solder layer are sequentially disposed on the surfaces of the protrusions and recesses of both the lower and upper substrates. Chip 11 on the lower substrate protrusion 3 has its P-side facing upwards, and chip 212 in the lower substrate recess 2 has its N-side facing upwards.

[0034] The lower substrate 1 has a length of 6 mm, a width of 1700 μm, and a height of 2 mm.

[0035] The lower substrate groove 2 and the upper substrate groove 8 have the same depth as the chip thickness, which is 106 μm. The width of the lower substrate groove 2 and the upper substrate groove 8 is 1 mm.

[0036] The upper substrate 7 and the lower substrate 1 are made of copper. The upper substrate 7 has a length of 6.5 mm, a width of 1700 μm, and a thickness of 2 mm.

[0037] The insulating layer 4 is SiO2 with a thickness of 300 nm.

[0038] The solder layer 5 is AuSn; the total thickness of the metal layer and solder layer 5 is 4μm.

[0039] The isolation groove 6 has a width of 0.05 mm and is used to separate the metal layer and the solder layer 5.

[0040] The chip is placed at the center of the boss and the groove.

[0041] Furthermore, the multi-chip cascaded laser packaging structure also includes a housing, with the upper substrate 7 and lower substrate 1 connected to the housing; the housing thickness is 2-3 mm, the housing length is greater than the upper substrate length + 10 mm, and the housing width is greater than the upper substrate 7 + lower substrate 1 height + 10 mm; a fence 14 with a height of 1-1.5 mm is provided on one side of the housing, and a negative electrode pin 15 and a positive electrode pin 16 are respectively provided on the fence 14, which are insulated from the fence 14; two fixing holes 17 are provided on the bottom plate of the housing. The negative electrode pin 15 is connected to the upper substrate through a negative electrode connection point 19, and the positive electrode pin 16 is connected to the upper substrate through a positive electrode connection point.

[0042] Although the present invention has been described in detail with reference to the accompanying drawings and preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made to the embodiments of the present invention by those skilled in the art without departing from the spirit and essence of the invention, and such modifications or substitutions should all be within the scope of the present invention. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should also be covered within the protection scope of the present invention.

Claims

1. A multi-chip series connection type laser package structure consisting of a chip, an upper substrate and a lower substrate, characterized in that, The upper surface of the lower substrate is alternately provided with multiple lower substrate bosses and lower substrate grooves, and the lower surface of the upper substrate is provided with matching upper substrate grooves and upper substrate bosses; a chip is provided between each set of matching bosses and grooves; the lower substrate bosses are provided with through isolation grooves; the upper substrate grooves are provided with through isolation grooves; the surfaces of the bosses and grooves of the lower and upper substrates are sequentially provided with an insulating layer, a metal layer and a solder layer; the chip on the lower substrate boss has its P-side facing upward, and the chip in the lower substrate groove has its N-side facing upward.

2. The multi-chip tandem laser packaging structure as described in claim 1, characterized in that, The length of the lower substrate = chip width × 2 × number of chips; the width of the lower substrate = chip cavity length + 200μm; the height of the lower substrate is 2~3mm.

3. The multi-chip tandem laser packaging structure as described in claim 1, characterized in that, The grooves on the lower substrate and the upper substrate have the same depth as the chip substrate, and the depth is 100~150μm; the width of the grooves on the lower substrate and the upper substrate is the width of the bosses on the upper substrate and the lower substrate + 0.2mm.

4. The multi-chip tandem laser packaging structure as described in claim 1, characterized in that, The upper and lower substrates are made of copper; the length of the upper substrate is equal to the length of the lower substrate plus 0.5 mm; the widths of the upper and lower substrates are the same; and the thicknesses of the upper and lower substrates are the same.

5. The multi-chip tandem laser packaging structure as described in claim 1, characterized in that, The insulating layer is SiO2, Si3N4 or Al2O3, with a thickness of 200nm~500nm.

6. The multi-chip tandem laser packaging structure as described in claim 1, characterized in that, The solder layer is AuSn or In; the total thickness of the metal layer and the solder layer is 4~6μm.

7. The multi-chip tandem laser packaging structure as described in claim 1, characterized in that, The isolation groove has a width of 0.05~0.1mm and is used to separate the metal layer and the solder layer.

8. The multi-chip tandem laser packaging structure as described in claim 1, characterized in that, The chip is placed at the center of the boss and the groove.

9. The multi-chip tandem laser packaging structure as described in claim 1, characterized in that, The multi-chip tandem laser packaging structure also includes a housing, with the upper substrate and lower substrate connected to the housing; the housing thickness is 2~3mm, the housing length is greater than the upper substrate length + 10mm, and the housing width is greater than the upper substrate + lower substrate height + 10mm; a fence with a height of 1~1.5mm is provided on one side of the housing, and negative and positive terminals are respectively provided on the fence, which are insulated from the fence; two fixing holes are provided on the bottom plate of the housing.

10. A method for preparing a multi-chip tandem laser packaging structure as described in any one of claims 1-9, characterized in that, Specifically as follows: (1) Prepare a lower substrate, grow an insulating layer on the upper surface of the lower substrate, and then grow a metal layer and a solder layer in sequence; (2) Counting from the left side of the lower substrate, a through-hole is cut on the left side of the second boss to separate the metal layer and the solder layer; (3) Prepare the upper substrate, the length of the upper substrate = the length of the lower substrate + 0.5 mm, grow an insulating layer on the lower surface of the upper substrate, and then grow a metal layer and a solder layer in sequence; (4) Starting from the left side of the upper substrate, a through-hole is cut into the right side of the first groove to separate the metal layer and the solder layer; (5) Place the semiconductor laser chip on the lower substrate, with the P-side of the protrusion chip facing up and the N-side of the groove chip facing up. The chip is placed in the middle of the protrusion or groove, and the light-emitting surface of the chip is aligned with the substrate surface. (6) Align the groove of the upper substrate with the protrusion of the lower substrate to ensure that the chip is aligned with the middle position of the groove and protrusion of the upper substrate; then use a sintering fixture to clamp the upper substrate and the lower substrate, and sinter the upper substrate, the lower substrate and the chip into a whole. (7) The upper and lower substrates of the sintered multi-chip tandem laser are sintered onto the tube shell with solder, wherein the bottom surfaces of the upper and lower substrates are sintered with the bottom plate of the tube shell, and the two sides of the upper substrate are aligned and sintered with the two tube pins respectively. After sintering, a multi-chip tandem laser packaging structure is obtained.

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