A heterogeneous integrated chip

Abstract

This invention provides a heterogeneous integrated chip, comprising: a silicon photonic chip including a silicon substrate, a photoelectronic functional structure disposed on the silicon substrate, and a chip end coupler for receiving optical signals; and a III-V chip integrated on the silicon substrate for emitting optical signals; wherein the III-V chip includes: a metal layer disposed on the silicon substrate; a first ohmic contact layer disposed on the silicon substrate and the metal layer; an optical waveguide structure protruding from the III-V chip, the optical waveguide structure being used to constrain the transverse mode output conditions during optical pumping; a combined layer structure disposed on the optical waveguide structure; a substrate layer disposed on the combined layer structure; and a second ohmic contact layer disposed on the substrate layer. The heterogeneous integrated chip provided by this invention is used to integrate a silicon photonic chip and a III-V chip, resulting in good heat dissipation of the integrated chip and achieving highly efficient non-field-aligned coupling.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of integrated optoelectronic chips, and particularly to a heterogeneous integrated chip. Background Technology

[0002] With the rapid development of semiconductor technology, the demand for high-performance, multifunctional integrated optoelectronic chips is increasing daily. Silicon materials dominate the integrated circuit field, possessing mature processes and low-cost advantages. However, silicon-based materials have certain limitations in optoelectronics, such as their relatively low luminous efficiency. In contrast, III-V semiconductor materials, such as gallium arsenide (GaAs) and indium phosphide (InP), exhibit excellent luminescent properties. Heterogeneous integration of III-V semiconductor light-emitting chips on silicon-based optoelectronic chips can fully leverage the advantages of both, showing broad application prospects in numerous fields such as optical communication, optical display, and optical sensing.

[0003] Current solutions for heterogeneous integration of III-V semiconductor light-emitting chips on silicon-based chips face several serious problems:

[0004] 1. Poor heat dissipation: III-V semiconductor chips generate high heat during operation, while the buried layer and cladding material of silicon-based optical chips are mostly silicon oxide, which has low thermal conductivity and poor heat dissipation. This results in high operating temperature of III-V semiconductor light-emitting chips, which can easily lead to thermal failure.

[0005] 2. High-efficiency passive alignment coupling is difficult to achieve, and coupling efficiency heavily relies on active alignment coupling. Active alignment coupling refers to the need to supply current to the ZN-5 semiconductor light-emitting chip during heterogeneous integration to keep it in an emitting state, and then dynamically monitor the coupling efficiency of the light signal emitted by the ZN-5 semiconductor light-emitting chip to the silicon photonics chip. This allows for real-time adjustment of the relative positions between the chips to ensure maximum coupling efficiency. Active alignment coupling requires current to be supplied to the ZN-5 semiconductor light-emitting chip to maintain its working state, which makes heterogeneous integration slow and difficult to scale. In contrast, passive alignment coupling does not require current to be supplied to the ZN-5 semiconductor light-emitting chip during heterogeneous integration, resulting in high packaging efficiency and strong scalability. However, because the coupling efficiency cannot be dynamically monitored in passive operation, it is difficult to guarantee high coupling efficiency. Summary of the Invention

[0006] This invention provides a method for integrating silicon photonics chips and III-V group chips, resulting in a chip with good heat dissipation and high-efficiency non-aligned coupling heterogeneous integrated chip.

[0007] To address the aforementioned technical problems, embodiments of the present invention provide a heterogeneous integrated chip, comprising:

[0008] A silicon photonic chip includes a silicon substrate, an optoelectronic functional structure disposed on the silicon substrate, and a chip end coupler for receiving optical signals.

[0009] A group III-V chip, integrated on the silicon substrate, is used to emit optical signals;

[0010] The III-V chip includes:

[0011] A metal layer, disposed on the silicon substrate, is composed of one or more metals;

[0012] The first ohmic contact layer is disposed on the silicon substrate and the metal layer;

[0013] An optical waveguide structure protrudes from the group III-V chip and is used to constrain the output conditions of the transverse mode during optical pumping.

[0014] A composite layer structure is disposed on the optical waveguide structure;

[0015] A substrate layer is disposed on the combined layer structure; and

[0016] A second ohmic contact layer is disposed on the substrate layer.

[0017] In one embodiment, the substrate is made of indium phosphide; or the substrate is made of gallium arsenide.

[0018] In one embodiment, both the first ohmic contact layer and the second ohmic contact layer are composed of one or more metal layers.

[0019] In one embodiment, the second ohmic contact layer is bonded to the metal layer via a metal bonding process.

[0020] In one embodiment, the metal layer is hollowed out, and a limiting groove is formed in the middle of the metal layer in conjunction with the silicon substrate for positional mismatch in a direction parallel to the layer. The second ohmic contact layer is limited to the metal layer based on the limiting groove.

[0021] In one embodiment, the optical waveguide structure protrudes towards the side facing the limiting groove. When the second ohmic contact layer is bonded to the optical waveguide layer and the metal layer, it is limited between the optical waveguide layer and the metal layer by the protrusion and the limiting groove, and is in close contact with the optical waveguide layer and the metal layer.

[0022] In one embodiment, the width of the protrusion on the optical waveguide layer is smaller than the width of the limiting groove, and the absolute value of the difference between the width of the protrusion and the width of the limiting groove is less than 5 micrometers.

[0023] In one embodiment, the optical signal coupling method between the silicon photonics chip and the III-V chip is end-face coupling. In the direction perpendicular to the silicon substrate, the absolute value of the difference between the center height of the optical waveguide layer and the center height of the receiving end face in the chip end-face coupler is no greater than 5 micrometers.

[0024] In a direction parallel to the silicon substrate, the positional difference between the center position of the limiting groove and the center position of the chip end face coupler is no greater than 5 micrometers.

[0025] In one embodiment, the combined layer structure includes a confinement layer disposed on the waveguide layer, an active layer disposed on the confinement layer, and a buffer layer disposed on the active layer.

[0026] In one embodiment, among the metal layer, the first ohmic contact layer, the optical waveguide structure, the confinement layer, the active layer, the buffer layer, the substrate layer, and the second ohmic contact layer, adjacent two layer structures can cooperate to form a concave-convex fit. One or more concave structures and / or convex structures are provided on the same layer structure. The concave structures on the same layer structure may be the same or different, and the convex structures on the same layer may be the same or different.

[0027] Based on the disclosure of the above embodiments, it can be understood that the beneficial effects of the embodiments of the present invention include the aforementioned III-V chip, namely, the III-V semiconductor light-emitting chip is constructed by epitaxial multilayer semiconductor materials using indium phosphide (InP) or gallium arsenide (GaAs) as a substrate. When the III-V semiconductor light-emitting chip is operating, the solution in this embodiment can improve the heat dissipation characteristics of the III-V light-emitting chip, reduce the operating temperature, and simultaneously support passive alignment coupling from large-scale III-V light-emitting chips to silicon-based optical chips.

[0028] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings.

[0029] The technical solution of this application will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0030] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0031] Figure 1This is a schematic diagram of the heterogeneous integrated chip in an embodiment of the present invention.

[0032] Figure 2 This is another structural schematic diagram of the heterogeneous integrated chip in an embodiment of the present invention.

[0033] Figure 3 This is a partial top view of the heterogeneous integrated chip in an embodiment of the present invention.

[0034] Figure 4 This is a schematic diagram of the structure of a heterogeneous integrated chip in another embodiment of the present invention.

[0035] Figure 5 This is another structural schematic diagram of a heterogeneous integrated chip in another embodiment of the present invention.

[0036] Figure 6 This is a structural diagram of a heterogeneous integrated chip according to another embodiment of the present invention.

[0037] Figure 7 This is a structural diagram of a heterogeneous integrated chip according to another embodiment of the present invention. Detailed Implementation

[0038] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but these are not intended to limit the scope of the invention.

[0039] It should be understood that various modifications can be made to the embodiments disclosed herein. Therefore, the following description should not be considered as limiting, but merely as an example of embodiments. Other modifications within the scope of this disclosure will be apparent to those skilled in the art.

[0040] The accompanying drawings, which are included in and form part of this specification, illustrate embodiments of the present disclosure and, together with the general description of the disclosure given above and the detailed description of the embodiments given below, serve to explain the principles of the disclosure.

[0041] These and other features of the invention will become apparent from the following description of preferred forms of embodiments given as non-limiting examples, with reference to the accompanying drawings.

[0042] It should also be understood that although the invention has been described with reference to some specific examples, those skilled in the art can certainly implement many other equivalent forms of the invention, which have the features described in the claims and are therefore all within the scope of protection defined herein.

[0043] The above and other aspects, features and advantages of this disclosure will become more apparent when taken in conjunction with the accompanying drawings and in view of the following detailed description.

[0044] Specific embodiments of the present disclosure are described thereafter with reference to the accompanying drawings; however, it should be understood that the disclosed embodiments are merely examples of the present disclosure and can be implemented in various ways. Well-known and / or repeated functions and structures are not described in detail to avoid unnecessary or redundant details that could obscure the present disclosure. Therefore, the specific structural and functional details disclosed herein are not intended to be limiting, but merely to serve as the basis and representative basis for the claims to teach those skilled in the art to use the present disclosure in a variety of substantially any suitable detailed structures.

[0045] This specification may use the phrases “in one embodiment,” “in another embodiment,” “in yet another embodiment,” or “in still another embodiment,” all of which may refer to one or more of the same or different embodiments according to this disclosure.

[0046] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0047] Current heterogeneous integration solutions for III-V semiconductor light-emitting chips on silicon-based chips often face technical challenges, such as poor heat dissipation and difficulty in achieving high-efficiency passive alignment coupling. Figure 1 , Figure 2 As shown, an embodiment of the present invention provides a heterogeneous integrated chip, comprising:

[0048] A silicon photonic chip includes a silicon substrate, an optoelectronic functional structure disposed on the silicon substrate, and a chip end coupler for receiving optical signals.

[0049] A group III-V chip, integrated on the silicon substrate, is used to emit optical signals;

[0050] The III-V chip includes:

[0051] A metal layer, disposed on the silicon substrate, is composed of one or more metals;

[0052] The first ohmic contact layer is disposed on the silicon substrate and the metal layer;

[0053] An optical waveguide structure protrudes from the group III-V chip and is used to constrain the output conditions of the transverse mode during optical pumping.

[0054] A composite layer structure is disposed on the optical waveguide structure;

[0055] A substrate layer is disposed on the combined layer structure; and

[0056] A second ohmic contact layer is disposed on the substrate layer.

[0057] Based on the above, it can be seen that the purpose of this embodiment is to provide a silicon-based heterogeneous integration scheme to generate heterogeneous integrated chips and realize high-quality heterogeneous integration of III-V semiconductor light-emitting chips on silicon-based optical chips.

[0058] In one embodiment, the substrate layer is made of indium phosphide; or the substrate layer is made of gallium arsenide. Both the first ohmic contact layer and the second ohmic contact layer are composed of one or more metal layers. The combined layer structure includes a confinement layer disposed on the waveguide layer, an active layer disposed on the confinement layer, and a buffer layer disposed on the active layer.

[0059] As can be seen from the above, the beneficial effects of this embodiment include the aforementioned group III-V chip, namely, the group III-V semiconductor light-emitting chip is constructed using indium phosphide (InP) or gallium arsenide (GaAs) as a substrate through epitaxial multilayer semiconductor materials. When the group III-V semiconductor light-emitting chip is operating, the solution in this embodiment can improve the heat dissipation characteristics of the group III-V light-emitting chip, reduce the operating temperature, and simultaneously support passive alignment coupling from large-scale group III-V light-emitting chips to silicon-based optical chips.

[0060] like Figure 1 , Figure 2 , Figure 4 and Figure 5 As shown, the second ohmic contact layer is bonded to the metal layer via a metal bonding process. Specifically, the metal layer is perforated, meaning it does not completely cover the silicon substrate but only partially covers it. The uncovered portion forms a groove with the silicon substrate. For example, in this embodiment, the center of the metal layer forms a positioning groove with the silicon substrate. This positioning groove is used for positional mismatch in a direction parallel to the layer, and the second ohmic contact layer is positioned on the metal layer based on the positioning groove.

[0061] Specifically, continue to combine Figure 1 , Figure 2 , Figure 4 and Figure 5 As shown, the optical waveguide structure protrudes towards the side facing the limiting groove. When the second ohmic contact layer is attached to the optical waveguide layer and the metal layer, it is limited between the optical waveguide layer and the metal layer by the concave-convex fit between the protrusion and the limiting groove, and is in close contact with the optical waveguide layer and the metal layer.

[0062] In practical applications, such as Figure 1 , Figure 2The diagram shows a cross-sectional view (xy plane) of a heterogeneous integration of a group III-V semiconductor light-emitting chip based on indium phosphide on a silicon-based optical chip. Its layer structure includes a first ohmic contact layer (composed of a single metal layer and multiple metal layers), a substrate layer (Indium phosphide, InP), a buffer layer (InGaAsP), an active layer (InGaAsP quantum well structure), a confinement layer (InP or InGaAsP), a waveguide layer (InGaAsP), an isolation layer (silicon nitride, silicon oxide, or silicon oxynitride), and a second ohmic contact layer (composed of a single gold layer and multiple metal layers). The area enclosed by the dashed line represents the raised optical waveguide structure with a width of w1. The waveguide structure serves to meet the single transverse mode output condition during optical pumping. The metal layers deposited on the silicon substrate and the second ohmic contact layer constituting the group III-V chip are bonded together using a metal bonding process.

[0063] like Figure 4 , Figure 5 The diagram shows a cross-sectional structure (xy plane) of a gallium arsenide (GaAs)-based group III-V semiconductor light-emitting chip heterogeneously integrated on a silicon-based optical chip. The core components of the GaAs-based group III-V semiconductor light-emitting chip include: a first ohmic contact layer (composed of a single metal layer or multiple metal layers), a substrate layer (GaAs), a buffer layer (LT-GaAs, LT-Al GaAs, or NT-Al GaAs), a confinement layer (GaAs, Al GaAs, or InGaAs), an active layer (GaAs quantum well structure or Al GaAs quantum well structure, or InGaAs quantum well structure / quantum dot structure), a confinement layer (Al GaAs, InGaP, or doped GaAs), a waveguide layer (Al GaAs, InGaAs, or GaAs), an isolation layer (silicon nitride / silicon oxide, or silicon oxynitride), and a second ohmic contact layer (composed of a single metal layer or multiple metal layers). The area enclosed by the dashed line represents the raised optical waveguide structure with a width of w3. The waveguide structure serves to constrain the transverse mode output conditions during optical pumping. The metal layer deposited on the silicon substrate and the second ohmic contact layer that constitutes the III-V chip are bonded together by a metal bonding process.

[0064] Furthermore, in this embodiment, the width of the protrusion on the optical waveguide layer is smaller than the width of the limiting groove, and the absolute value of the difference between the width of the protrusion and the width of the limiting groove is less than 5 micrometers.

[0065] The optical signal coupling method between the silicon photonics chip and the III-V chip is end-face coupling. In the direction perpendicular to the silicon substrate, the absolute value of the difference between the center height of the optical waveguide layer and the center height of the receiving end face in the chip end-face coupler is no greater than 5 micrometers.

[0066] In a direction parallel to the silicon substrate, the positional difference between the center position of the limiting groove and the center position of the receiving end face in the chip end face coupler is no greater than 5 micrometers.

[0067] For example, such as Figure 2 The diagram shows a side view (xz plane) of a heterogeneous integration of a group III-V semiconductor light-emitting chip based on indium phosphide on a silicon-based optical chip. The metal layer deposited on the silicon substrate and the second ohmic contact layer of the group III-V semiconductor light-emitting chip are bonded together by metal bonding. The optical signals of the two chips are coupled end-to-end; that is, when the left-side group III-V semiconductor light-emitting chip is operating, it emits a light signal horizontally to the right, which is received by the end-to-end coupler of the right-side silicon-based optical chip. In the vertical direction (x-direction) shown in the diagram, the height difference between the center height of the waveguide layer of the group III-V semiconductor light-emitting chip and the center height of the end-to-end coupler of the silicon-based optical chip is Δh1. To ensure high end-to-end coupling efficiency, the absolute value of Δh in this embodiment should be less than 5 μm, i.e., |Δh1| ≤ 5 μm.

[0068] like Figure 5 The diagram shows a side view (xz plane) of a gallium arsenide (GaAs) Z5 semiconductor light-emitting diode (LED) chip heterogeneously integrated on a silicon-based optical chip. The metal layer deposited on the silicon substrate and the second ohmic contact layer of the GaAs LED chip are bonded together by metal bonding. The optical signal coupling between the two chips is end-face coupling; that is, when the left-side GaAs LED chip is operating, it emits a light signal horizontally to the right, which is received by the end-face coupler of the right-side silicon-based optical chip. In the vertical direction (x-direction) shown in the diagram, the height difference between the center height of the waveguide layer of the GaAs LED chip and the center height of the receiving end face of the silicon-based optical chip is Δh2. To ensure high end-face coupling efficiency, the absolute value of Δh2 in this embodiment should be less than 5 μm, i.e., |Δh| ≤ 5 μm.

[0069] like Figure 3 The diagram shown is a top view (yz plane) of heterogeneous integration of a group III-V semiconductor light-emitting chip based on indium phosphide on a silicon-based photonic chip. It shows the structural features of the silicon substrate surface in the heterogeneous integration region. The area enclosed by the dashed line is the heterogeneous integration region. In the horizontal (y direction) direction, the width difference between the center of the limiting groove and the center of the silicon photonic chip end face coupler is Δw1. To ensure high end face coupling efficiency, the absolute value of Δw1 in this embodiment should be less than 5μm, that is, |Δw|≤5μm.

[0070] Similarly, when a gallium arsenide-based group III-V semiconductor light-emitting chip is heterogeneously integrated on a silicon-based optical chip, the structural features of the silicon substrate surface in the heterogeneous integration area shown by the dashed line include the width difference Δw2 between the center of the limiting groove and the center of the silicon optical chip end face coupler in the horizontal (y direction) direction shown in the figure. To ensure high end face coupling efficiency, the absolute value of Δw2 in this embodiment should be less than 5μm, that is, |Δw|≤5μm.

[0071] The fabrication process for heterogeneous integrated chips includes:

[0072] On a silicon-based wafer, active and passive optoelectronic device structures are fabricated. Then, in the region on the silicon-based optical chip where a III-V semiconductor light-emitting chip needs to be integrated, the cladding silicon oxide and buried silicon oxide of the heterogeneous integration region are etched or etched away through etching or etching processes to expose the silicon substrate. Then, a metal layer is deposited and patterned on the silicon substrate of the heterogeneous integration region to create a limiting groove structure. Finally, the III-V semiconductor light-emitting chip is bonded and fixed to the heterogeneous integration region through a metal bonding process.

[0073] like Figure 5 , Figure 6 As shown, in the metal layer, the first ohmic contact layer, the optical waveguide structure, the confinement layer, the active layer, the buffer layer, the substrate layer, and the second ohmic contact layer, adjacent layers can cooperate to form a concave-convex fit. One or more concave structures and / or convex structures are provided on the same layer. The concave structures on the same layer may be the same or different, and the convex structures on the same layer may be the same or different. That is, adjacent layers can be respectively fitted with protrusions and grooves. The size, depth, and height of the protrusions and grooves corresponding to different positions are variable. Multiple protrusions or multiple grooves can be provided in the same layer, or protrusions and grooves can be provided simultaneously. The size and structure of the protrusions can be the same or different; similarly, the size and structure of the grooves can be the same or different.

[0074] The above embodiments are merely exemplary embodiments of the present invention and are not intended to limit the present invention. The scope of protection of the present invention is defined by the claims. Those skilled in the art can make various modifications or equivalent substitutions to the present invention within its spirit and scope of protection, and such modifications or equivalent substitutions should also be considered to fall within the scope of protection of the present invention.

Claims

1. A heterogeneous integrated chip, characterized in that, include: A silicon photonics chip includes a silicon substrate, an optoelectronic functional structure disposed on the silicon substrate, and an end-face coupler structure for receiving optical signals. The III-V group chip, integrated on the silicon substrate, is used to emit optical signals; The III-V chip includes: A metal layer, disposed on the silicon substrate, is composed of one or more metals; The first ohmic contact layer is disposed on the silicon substrate and the metal layer; An optical waveguide structure protrudes from the group III-V chip and is used to constrain the output conditions of the transverse mode during optical pumping. A composite layer structure is disposed on the optical waveguide structure; The substrate bottom layer is disposed on the combined layer structure; and A second ohmic contact layer is disposed on the substrate layer.

2. The heterogeneous integrated chip of claim 1, wherein, The substrate is made of indium phosphide; or the substrate is made of gallium arsenide.

3. The heterogeneous integrated chip of claim 1, wherein, Both the first ohmic contact layer and the second ohmic contact layer are composed of one or more metal layers.

4. The heterogeneous integrated chip of claim 1, wherein, The second ohmic contact layer is bonded to the metal layer by a metal bonding process.

5. The heterogeneous integrated chip of claim 4, wherein, The metal layer is hollowed out, and a limiting groove is formed in the middle of the metal layer in conjunction with the silicon substrate to allow for positional mismatch in a direction parallel to the layer. The second ohmic contact layer is limited to the metal layer based on the limiting groove.

6. The heterogeneous integrated chip of claim 5, wherein, The optical waveguide structure protrudes towards the side facing the limiting groove. When the second ohmic contact layer is bonded to the optical waveguide layer and the metal layer, it is limited between the optical waveguide layer and the metal layer by the protrusion and the limiting groove, and is in close contact with the optical waveguide layer and the metal layer.

7. The heterogeneous integrated chip according to claim 6, characterized in that, The width of the protrusion on the optical waveguide layer is smaller than the width of the limiting groove, and the absolute value of the difference between the width of the protrusion and the width of the limiting groove is less than 5 micrometers.

8. The heterogeneous integrated chip of claim 1, wherein, The optical signal coupling method between the silicon photonics chip and the III-V group chip is end-face coupling. In the direction perpendicular to the silicon substrate, the absolute value of the difference between the center height of the optical waveguide layer and the center height of the receiving end face in the chip end-face coupler is no greater than 5 micrometers. In a direction parallel to the silicon substrate, the positional difference between the center position of the limiting groove and the center position of the receiving end face in the chip end face coupler is no greater than 5 micrometers.

9. The heterogeneous integrated chip of claim 1, wherein, The combined layer structure includes a confinement layer disposed on the waveguide layer, an active layer disposed on the confinement layer, and a buffer layer disposed on the active layer.

10. The heterogeneous integrated chip according to claim 9, characterized in that, In the metal layer, the first ohmic contact layer, the optical waveguide structure, the confinement layer, the active layer, the buffer layer, the substrate layer, and the second ohmic contact layer, adjacent two layer structures can cooperate to form a concave-convex fit. One or more concave structures and / or convex structures are provided on the same layer structure. The concave structures on the same layer structure may be the same or different, and the convex structures on the same layer may be the same or different.

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