Optimized structure for reliability enhancement of heterogeneously integrated laser bonding interface and preparation process thereof

Abstract

This application relates to an optimized structure and its fabrication process for enhancing the reliability of the bonding interface in heterogeneous integrated lasers. The laser includes a III-V group gain chip and a silicon-based photonic integrated circuit substrate connected to it via a bonding layer. The bonding layer is a benzocyclobutene bonding layer with a thickness of 2.5–5.5 μm. The III-V group gain chip has stress-reducing corner features at at least two diagonal points in contact with the bonding layer. These corner features are either 45° flat truncated angles or rounded chamfers, with flat truncated angles having a length of 15–25 μm and rounded chamfers having a radius of 12–18 μm. The stress-reducing corner features are located outside the active waveguide region and ≥40 μm from the center of the active waveguide. The optimized structure of this application can reduce thermal cycling stress concentration at the bonding interface and improve reliability.

Description

Technical Field

[0001] This application relates to the field of semiconductor laser technology, and in particular to an optimized structure for enhancing the reliability of bonding interfaces in heterogeneous integrated lasers and its fabrication process. Background Technology

[0002] With the development of silicon photonics technology, heterogeneous integration of III-V gain chips with silicon-based photonic integrated circuit substrates to realize on-chip laser sources has become an important technical route. In traditional heterogeneous integration structures, benzocyclobutene (BCB) polymer is typically used as the bonding layer between the III-V gain chip and the silicon substrate. However, due to the significant difference in the coefficient of thermal expansion between BCB and silicon and III-V materials, large thermal stresses are generated at the bonding interface during device operation and environmental temperature cycling, especially concentrated in the corner areas of the chip. This leads to the initiation and propagation of interface cracks, ultimately causing laser performance degradation or failure. Currently, there is a lack of scientific optimization basis for the selection of BCB bonding layer thickness in engineering practice, and the chip corners usually retain a standard rectangular shape, which cannot effectively release stress concentration, making it difficult for heterogeneous integrated lasers to meet the stringent requirements of automotive-grade and other applications in terms of thermal cycling reliability. Summary of the Invention

[0003] Therefore, it is necessary to provide an optimized structure and its fabrication process for enhancing the reliability of bonding interfaces in heterogeneous integrated lasers, which can reduce the thermal cycling stress concentration at the bonding interface and thus improve the bonding interface reliability.

[0004] In a first aspect, this application provides an optimized structure for enhancing the reliability of the bonding interface of a heterogeneous integrated laser. The laser includes a III-V group gain chip and a silicon-based photonic integrated circuit substrate connected thereto via a bonding layer. The bonding layer includes a benzocyclobutene bonding layer with a thickness of 2.5–5.5 μm. The III-V group gain chip has stress-reducing corner features at at least two diagonal points in contact with the bonding layer. The corner features are either 45° flat truncated angles or rounded chamfers, wherein the truncated angle of the 45° flat truncated angle has a length of 15–25 μm, and the radius of the rounded chamfer is 12–18 μm. The stress-reducing corner features are located outside the active waveguide region and at a distance greater than or equal to 40 μm from the center of the active waveguide.

[0005] In one embodiment, the bonding layer includes: a titanium adhesion layer formed on the upper surface of the silicon dioxide cladding layer of the silicon-based photonic integrated circuit substrate, and a benzocyclobutene layer formed above the titanium adhesion layer; the thickness of the titanium adhesion layer is 3-7 nm.

[0006] In one embodiment, the silicon-based photonic integrated circuit substrate includes a silicon nitride waveguide layer with a thickness of 250–350 nm and located below the bonding layer. The crack propagation path between the bonding layer and the silicon dioxide upper cladding of the silicon-based photonic integrated circuit substrate is along the interface between the bonding layer and the silicon dioxide upper cladding.

[0007] Secondly, this application also provides a fabrication process for a heterogeneous integrated laser bonding interface based on any of the optimized structures described above, comprising the following steps: A silicon-based photonic integrated circuit substrate is provided, the surface of which is a silicon dioxide cladding layer with a surface roughness of less than or equal to 0.5 nm; The corners of the III-V group gain chip are pre-processed by using laser scribing or mechanical grinding to form 45° flat chamfers or rounded chamfers at the four corners of the III-V group gain chip, wherein the length of the flat chamfer is 15 to 25 μm and the radius of the rounded chamfer is 12 to 18 μm. The bonding region of the silicon-based photonic integrated circuit substrate is subjected to ultraviolet ozone activation treatment; A benzocyclobutene precursor solution was coated onto the bonding region using a spin coating process. The thickness of the bonded layer after curing was controlled to be 2.5–5.5 μm by adjusting the spin coating speed. Under nitrogen protection, the temperature is increased to 250°C at a heating rate of 5–15°C / min for thermosetting, held at that temperature for 30–90 minutes, and then naturally cooled to room temperature to form the bonding layer. The III-V group gain chip, which has undergone the corner pretreatment, is flip-chip bonded onto the bonding layer, bonding pressure is applied and post-curing is performed to complete the bonding.

[0008] In one embodiment, after the UV ozone activation treatment of the bonding region of the silicon-based photonic integrated circuit substrate and before the BCB precursor solution is coated by spin coating, the method further includes: depositing a titanium adhesion layer with a thickness of 3-7 nm on the surface of the silicon dioxide cladding layer by electron beam evaporation or magnetron sputtering, wherein the titanium adhesion layer is located between the bonding layer and the silicon dioxide cladding layer.

[0009] In one embodiment, the process of applying BCB precursor solution to the bonding region using spin coating includes controlling the thickness of the bonding layer to 3.0–4.0 μm using a non-monotonic stress-thickness relationship curve obtained through finite element simulation, with the thickness tolerance controlled within ±0.2 μm.

[0010] Thirdly, this application also provides an application of the optimized structure described in any of the above claims in in-situ monitoring of stress at the bonding interface of heterogeneous integrated lasers, comprising the following steps: The computer device includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the above-described XXX method.

[0011] Photoluminescence measurements were performed on the output surface of the III-V group gain chip in the optimized structure using a 532nm excitation laser, and the TE polarization intensity was collected. and TM polarization intensity Calculate the degree of polarization ; Record the reference polarization degree in the initial state of the device. The initial residual biaxial stress was calculated using a pre-established linear calibration curve between the degree of polarization and the residual biaxial stress. ; Throughout the device's entire lifespan, the photoluminescence measurement is repeated periodically to obtain the current polarization degree. And calculate the stress evolution index according to the following formula. ; A three-level failure warning is determined based on the value of the stress evolution index ΔS. A Level 1 warning is issued when the first threshold is exceeded. A level-two warning is issued when the threshold is exceeded. A level 3 warning is issued when the threshold is exceeded; wherein the first threshold is less than the second threshold, and the second threshold is less than the third threshold.

[0012] In one embodiment, the method further includes: adjusting the stress evolution index. Linear regression analysis was performed on the threshold current change rate measured simultaneously to construct an empirical relationship between the stress evolution index ΔS and the threshold current change rate. This relationship was used to indirectly estimate the interface stress evolution state through electrical parameters when photoluminescence measurement was not available. The expression for the threshold current change rate is as follows: , The initial threshold current, This represents the change in the threshold current.

[0013] Fourthly, this application also provides an application of the optimized structure described in any of the above claims in the prediction of the bonding interface lifetime of heterogeneous integrated lasers, comprising the following steps: Failure data of a heterogeneous integrated laser with the optimized structure is obtained using a multi-stress accelerated aging matrix, which includes at least three thermal cycling conditions with different temperature swing amplitudes and at least two high-temperature operating lifetime conditions with junction temperatures. The Coffin-Manson model for thermal cycling life and the Arrhenius model for high-temperature operating life were established respectively. A Paris law crack propagation model is parameterized based on the range of stress intensity factor at the crack tip at the interface between the bonded layer and the silica cladding layer calculated by three-dimensional finite element thermo-mechanical simulation. The parameters of the Paris law crack propagation model were experimentally verified by measuring the cross-sectional crack length using focused ion beam or scanning electron microscopy. By combining the Coffin-Manson model, the Arrhenius model, and the Paris law crack propagation model, a B10 lifetime prediction map is generated with temperature swing and mean temperature as parameters.

[0014] In one embodiment, the stacked structure of the three-dimensional finite element thermal and mechanical simulation, from bottom to top, consists of: a silicon substrate, a silicon dioxide lower cladding layer, a silicon nitride waveguide layer, a silicon dioxide upper cladding layer, a bonding layer, and an indium phosphide gain chip. The stress reference temperature for the three-dimensional finite element thermal and mechanical simulation is set to the curing temperature of the bonding layer, which is 250°C. The mesh for the three-dimensional finite element thermo-mechanical simulation is divided at the interface between the bonding layer and the silicon dioxide cladding and at the interface between the bonding layer and the indium phosphide gain chip, with element sizes less than or equal to 0.1 μm. The mesh convergence error of the three-dimensional finite element thermal and mechanical simulation is less than or equal to 3%.

[0015] The aforementioned optimized structure and fabrication process for enhancing the reliability of bonding interfaces in heterogeneous integrated lasers, which reduces stress concentration during thermal cycling, achieves a reduction in interface peak stress by limiting the BCB bonding layer thickness to 2.5–5.5 μm. This avoids the unfavorable non-monotonic range where excessively thin layers result in excessive stress, or excessively thick layers increase crack propagation driving forces. Simultaneously, by setting 45° flat chamfers or rounded corners at the corners of the III-V gain chip and placing these corner features outside the active waveguide region and at least 40 μm from the waveguide center, stress concentration accumulated at the chip corners during thermal cycling is effectively dispersed, preventing damage to the active region from stress peaks without affecting the laser's optical performance. These structural features synergistically enhance the fatigue resistance of the bonding interface under thermal cycling conditions, thereby extending the reliable service life of the heterogeneous integrated laser. Attached Figure Description

[0016] Figure 1 This is a cross-sectional schematic diagram of an optimized structure for enhancing the reliability of bonding interfaces in heterogeneous integrated lasers, as shown in one embodiment. Figure 2 This is a schematic diagram illustrating the effect of BCB bonding layer thickness on the peak von Mises stress at the interface in one embodiment (cross-validation by FEM simulation and PL-DOP experiment); Figure 3 This is a comparative schematic diagram of the von Mises stress cloud diagrams of the BCB layer for three chip corner geometry schemes in one embodiment. Figure 4 This is a schematic diagram of the BCB / Ti / SiO2 composite bonding interface structure in one embodiment (comparison between standard process and Ti adhesion layer scheme). Figure 5 This is a schematic diagram of an in-situ stress monitoring method for bonding interfaces based on PL-DOP in one embodiment (monitoring principle, process, InP calibration curve, and three-level early warning threshold). Figure 6 This is a schematic diagram of the results of a multi-stress accelerated aging matrix test (thermal cycling ΔIth degradation curve and HTOLArrhenius lifetime extrapolation plot) in one embodiment; Figure 7 This is a Weibull probability plot (MLE fitting) under three thermal cycling conditions in one embodiment. Figure 8 A Coffin-Manson / Arrhenius combined B10 lifetime prediction plot in one embodiment Figure 9 This is a schematic diagram comparing the Paris law crack propagation model (FEM ΔK parameterization) with FIB / SEM experimental measurements in one embodiment; Figure 10 This is a schematic diagram summarizing the effects of a comprehensive reliability improvement scheme in one embodiment (FEM peak interface stress and Weibull B10 lifetime and three-step optimization roadmap). Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. First, to facilitate understanding of the technical solutions provided by the embodiments of this application, the background technology involved in the embodiments of this application will be described below.

[0018] In the field of silicon photonics, heterogeneous integration of III-V compound semiconductors with silicon-based photonic integrated circuits is a key technological path for realizing on-chip high-efficiency laser sources. Among these, heterogeneous integration schemes using benzocyclobutene (BCB) as the bonding layer have been widely studied due to their process compatibility and excellent optical performance. However, there is a significant difference in the coefficient of thermal expansion (CTE) between BCB and silicon and III-V materials: BCB's CTE is approximately 52 × 10⁻⁶. -6 K -1 Silicon is approximately 2.6 × 10⁻⁶. -6 K -1III-V materials (such as InP) have a density of approximately 4.6 × 10⁻⁶. -6 K -1 When actual devices undergo temperature cycling (e.g., from -40°C to +85°C), this CTE mismatch leads to enormous thermal stress at the bonding interface, particularly concentrated in the corner regions of III-V gain chips. Experiments and finite element analysis show that at the corners of standard rectangular chips, the peak paradigm equivalent stress (von Mises stress) can reach as high as 312 MPa, far exceeding the fatigue strength of the BCB / SiO2 interface. Under long-term thermal cycling, interfacial cracks initiate at stress concentration points and propagate along the interface, ultimately leading to increased laser threshold current, decreased output power, and even catastrophic failure.

[0019] In existing technologies, engineering practices often rely solely on experience to select the thickness of the BCB bonding layer, lacking an optimization window based on thermodynamic simulation and experimental verification. Furthermore, III-V gain chips typically retain the rectangular corner shape after dicing, without addressing stress concentration through geometric stress reduction design. These shortcomings result in heterogeneous integrated lasers failing to meet the stringent requirements of demanding applications such as automotive-grade systems in terms of thermal cycling reliability.

[0020] Therefore, in order to effectively reduce interfacial thermal stress and delay crack propagation through synergistic optimization of bonding layer thickness and chip corner structure, this application provides an optimized structure, fabrication process and application for enhancing the reliability of bonding interfaces in heterogeneous integrated lasers.

[0021] Firstly, in one embodiment, a heterogeneous integrated laser based on a III-V compound semiconductor (such as indium phosphide InP) and silicon nitride (Si3N4) photonic integrated circuit platform is described as an example. However, those skilled in the art should understand that the technical solutions of this application are also applicable to other III-V material systems and other silicon-based photonic platforms. As mentioned above, during thermal cycling, heterogeneous integrated lasers experience significant thermal stress at the bonding interface due to thermal expansion coefficient mismatch, particularly concentrated in the corner regions of III-V gain chips. How to reduce the peak interface stress through reasonable thickness design and corner geometry optimization is crucial for improving device reliability. Therefore, as... Figure 1As shown, an optimized structure for enhancing the reliability of the bonding interface of a heterogeneous integrated laser is provided. The laser includes a III-V group gain chip and a silicon-based photonic integrated circuit substrate connected thereto via a bonding layer. The bonding layer includes a benzocyclobutene bonding layer with a thickness of 2.5–5.5 μm. The III-V group gain chip has stress-reducing corner features at at least two diagonal points in contact with the bonding layer. The corner features are either 45° flat truncated angles or rounded chamfers, wherein the truncated angle length of the 45° flat truncated angle is 15–25 μm, and the radius of the rounded chamfer is 12–18 μm. The stress-reducing corner features are located outside the active waveguide region and at a distance greater than or equal to 40 μm from the center of the active waveguide.

[0022] Specifically, the silicon-based photonic integrated circuit substrate is used to carry optical waveguides and electronic circuits. In this embodiment, the silicon-based photonic integrated circuit substrate is fabricated using an 8-inch silicon wafer and, from bottom to top, includes a silicon substrate, a silicon dioxide lower cladding layer, a silicon nitride waveguide layer, and a silicon dioxide upper cladding layer. The substrate surface is the silicon dioxide upper cladding layer, and its surface roughness is less than or equal to 0.5 nm after chemical mechanical polishing to meet bonding requirements.

[0023] For III-V group gain chips, this embodiment uses an indium phosphide (InP)-based multi-quantum well gain chip with a cavity length of 500 μm and a width of 200 μm. This chip is used to provide optical gain. The center of the chip's active waveguide is located at the geometric center along the chip's length and centered along its width.

[0024] The bonding layer includes a benzocyclobutene (BCB) bonding layer. BCB is a photosensitive polymer with low dielectric constant, high planarization, and good thermal stability. In this application, the thickness of the BCB bonding layer is limited to 2.5–5.5 μm. This thickness range was determined through cross-validation using thermodynamic finite element simulation and photoluminescence polarization degree experiments, such as… Figure 2 As shown, when the thickness is less than 2.5 μm, the peak von Mises stress at the interface increases sharply with decreasing thickness (exceeding 350 MPa); when the thickness is greater than 5.5 μm, although the stress decreases, the interfacial crack propagation driving force (characterized by strain energy release rate) calculated based on the Paris law crack propagation model increases with increasing thickness, resulting in a non-monotonic decrease in interfacial lifetime. Figure 2 The green shaded area represents the 2.5–5.5 μm optimization window. The error between the finite element simulation prediction and the PL-DOP experimental measurement is less than 15 MPa, verifying the effectiveness of this window. In this embodiment, the thickness of the BCB bonding layer can be specifically selected as 3.0 μm, 3.5 μm, or 4.0 μm to achieve the best balance between stress and crack propagation resistance.

[0025] Stress-reducing corner features are provided at at least two opposite corners where the III-V gain chip contacts the bonding layer. In this embodiment, all four corners are provided with such features. The corner features can be 45° flat chamfers or rounded chamfers. A 45° flat chamfer refers to cutting an isosceles right triangle at the right-angle vertex of the chip, with a chamfer length c (i.e., the length of the right-angle side) of 15–25 μm. A rounded chamfer refers to machining the right-angle vertex of the chip into a rounded arc with a radius r of 12–18 μm. The above size ranges are obtained based on finite element simulation optimization: when the chamfer length or radius is too small (e.g., less than 12 μm), the stress-reducing effect is not obvious; when it is too large (e.g., greater than 25 μm), it may affect the mechanical strength of the chip edge or interfere with the gold wire bonding area. Figure 3 The von Mises stress cloud diagrams of the BCB layer are compared for three chip corner geometry schemes (standard rectangular corner, 20 μm flat chamfer, and 15 μm rounded chamfer). The flat chamfer scheme reduces the peak interface stress by approximately 18%, while the rounded chamfer scheme reduces it by approximately 16%. In this embodiment, when a flat chamfer is used, the chamfer length c is preferably 20 μm; when a rounded chamfer is used, the radius r is preferably 15 μm.

[0026] The stress-relief corner features are located outside the active waveguide region and at least 40 μm from the center of the active waveguide. The center of the active waveguide refers to the central axis of the waveguide structure used to generate and transmit light in the III-V gain chip. The corner features being at least 40 μm from the center of the active waveguide ensures that the stress-relief area does not affect the optical field distribution and laser output characteristics. In practical designs, this distance can be ensured through photolithographic alignment marks or mechanical positioning. In this embodiment, the chip length is 500 μm, the center of the active waveguide is approximately 250 μm from the chip edge, and the corner features are located at the four corners of the chip, with a distance greater than 200 μm from the center of the active waveguide, meeting the requirement of at least 40 μm.

[0027] During thermal cycling, the difference in thermal expansion coefficients between the BCB bonding layer and the silicon substrate and III-V chip leads to thermal stress at the interface. Controlling the BCB bonding layer thickness within an optimized window of 2.5–5.5 μm avoids the unfavorable ranges of drastically increased stress when the thickness is too thin and increased crack propagation driving force when the thickness is too thick, thus keeping the peak interfacial stress at a low level. Simultaneously, setting 45° flat chamfers or rounded corners at the chip corners transforms the originally sharp right angles into gentle slopes or curves, effectively dispersing the stress concentrated at the corners. Figure 3 As shown in the stress cloud diagram, the corner features are located outside the active waveguide region and at a sufficiently large distance, ensuring that the stress reduction effect does not impair optical performance. These technical features work synergistically to slow down the initiation and propagation rate of interface cracks under thermal cycling, thereby improving the thermal cycling reliability of the heterogeneous integrated laser. Figure 10The bar chart on the left shows a comparison of the peak stress at the interface before and after optimization: the peak stress of the standard structure is about 312 MPa, while it is reduced to about 256 to 262 MPa after adopting the structure of this application.

[0028] Based on the basic structure, the interfacial adhesion strength between the BCB and the silicon dioxide cladding in the bonding layer directly affects the crack propagation path and delamination resistance. If the interfacial adhesion is insufficient, cracks are prone to propagate along the interface, leading to bonding failure. Therefore, in one embodiment, the bonding layer includes: a titanium adhesion layer formed on the upper surface of the silicon dioxide cladding of the silicon-based photonic integrated circuit substrate, and a benzocyclobutene layer formed above the titanium adhesion layer; the thickness of the titanium adhesion layer is 3–7 nm.

[0029] Specifically, the silicon dioxide cladding layer: This layer is the top layer of the silicon-based photonic integrated circuit substrate, serving as the substrate for BCB bonding. The coefficient of thermal expansion of silicon dioxide is approximately 2.6 × 10⁻⁶. -6 K -1 It differs significantly from BCB.

[0030] Titanium exhibits good biocompatibility and metal-oxide adhesion. The titanium adhesion layer is formed via physical vapor deposition methods such as electron beam evaporation or magnetron sputtering, with a thickness of 3–7 nm. The selection of this thickness range is based on the following: a thickness below 3 nm may prevent the titanium layer from forming a continuous film, resulting in insufficient adhesion enhancement; a thickness above 7 nm may increase the stress within the titanium layer itself and potentially affect the transmission characteristics of the optical waveguide (titanium absorbs visible and near-infrared light). In practical applications, a titanium adhesion layer thickness of 5 nm is suitable, as this thickness ensures an approximately 35% increase in adhesion between BCB and silicon dioxide without introducing significant additional stress or optical loss.

[0031] Benzocyclobutene layer: formed above the titanium adhesive layer, i.e., the titanium adhesive layer serves as an intermediate layer, connecting silicon dioxide and BCB.

[0032] Figure 4 A comparison is shown between the standard BCB / silica interface and the BCB / titanium / silica composite interface in this application: under standard process conditions, cracks propagate along the BCB / silica interface ( Figure 4 (Left), and after the introduction of the titanium adhesion layer, crack propagation was hindered ( Figure 4 (Right), because the titanium layer forms stronger chemical bonds with the materials on both sides.

[0033] A titanium adhesion layer is introduced between BCB and silica. Titanium atoms form chemical bonds with oxygen atoms on the silica surface, while the titanium layer and the benzene ring structure of BCB generate strong van der Waals forces and interfacial interlocking effects, thereby improving the interfacial adhesion energy. When thermal stress is applied to the bonded interface, the enhanced adhesion energy hinders the direct propagation of cracks along the BCB / silica interface, forcing the cracks to deviate along other paths or requiring higher energy to continue propagating, thus delaying interfacial delamination and failure. In this embodiment, this composite interface structure increases the interfacial adhesion energy by approximately 35%, effectively enhancing the fatigue resistance of the bonded interface.

[0034] In heterogeneous integrated lasers, silicon-based photonic integrated circuit substrates typically include silicon nitride waveguide layers. Due to the high Young's modulus of silicon nitride (approximately 250 GPa), its presence alters the stress distribution and crack propagation path at the bonding interface. Without considering this unique layer structure, existing reliability models may produce prediction biases. Therefore, in one embodiment, the silicon-based photonic integrated circuit substrate includes a silicon nitride waveguide layer with a thickness of 250–350 nm located below the bonding layer. The crack propagation path between the bonding layer and the silicon dioxide upper cladding of the silicon-based photonic integrated circuit substrate follows the interface between the bonding layer and the silicon dioxide upper cladding.

[0035] Specifically, silicon nitride (Si3N4) is a low-loss optical waveguide material with a refractive index between that of silicon and silicon dioxide. In this embodiment, the silicon nitride waveguide layer is prepared by low-pressure chemical vapor deposition (LPCVD) with a thickness of 250–350 nm, preferably 300 nm. This layer is located below the bonding layer. Specifically, the stacking order from top to bottom is: bonding layer, upper silicon dioxide cladding layer, silicon nitride waveguide layer, lower silicon dioxide cladding layer, and silicon substrate, as follows. Figure 1 As shown.

[0036] Due to the high Young's modulus (approximately 250 GPa) and relatively hard mechanical properties of silicon nitride, when cracks form at the bonding interface, the cracks tend to propagate along the interface between BCB and silicon dioxide (i.e., the BCB / silicon dioxide interface) rather than penetrating the high-modulus silicon nitride layer into deeper substrate regions. This is because the silicon nitride layer provides high fracture toughness, forcing the crack to extend along the weaker interface. This application explicitly defines the crack propagation path along the interface between the bonding layer and the silicon dioxide cladding, providing accurate interface location parameters for subsequent lifetime prediction models (such as the Paris law crack propagation model). Figure 9 This approach was validated by crack length data measured in cross sections using focused ion beam / scanning electron microscopy (FIB / SEM), with the experimental measurements showing an error of less than 8.5% compared to the predictions from the Paris law model.

[0037] In heterogeneous integrated structures containing silicon nitride waveguide layers, cracks are primarily confined to the BCB / silicon dioxide interface rather than propagating into the substrate. This understanding provides the correct geometric boundary conditions for Paris law-based crack propagation analysis, preventing the incorrect application of crack modes from InP / silicon-on-insulator (SOI) structures to the platform of this application. Based on this explicit crack path, subsequent finite element simulations and lifetime predictions can more accurately describe the stress intensity factor at the crack tip, thereby improving the accuracy of reliability assessments.

[0038] Secondly, to achieve the aforementioned optimized structure, a fabrication process is needed that can precisely control the bonding layer thickness while simultaneously forming stress-reducing features at the chip corners. Existing processes lack a systematic control method for thickness and corner shape, resulting in large variations in device reliability. Therefore, in one embodiment, a fabrication process for a heterogeneous integrated laser bonding interface based on the aforementioned optimized structure includes the following steps: Step S1: Provide a silicon-based photonic integrated circuit substrate with a silicon dioxide cladding layer on its surface and a surface roughness of less than or equal to 0.5 nm; Step S2: Perform corner preprocessing on the III-V group gain chip by using laser scribing or mechanical grinding to form 45° flat chamfers or rounded chamfers at the four corners of the III-V group gain chip, wherein the length of the flat chamfer is 15-25μm and the radius of the rounded chamfer is 12-18μm; Step S3: Perform ultraviolet ozone activation treatment on the bonding region of the silicon-based photonic integrated circuit substrate; Step S4: A benzocyclobutene precursor solution is coated onto the bonding area using a spin coating process. The thickness of the bonded layer after curing is controlled to be 2.5–5.5 μm by adjusting the spin coating speed. Step S5: Under nitrogen protection, heat to 250°C at a heating rate of 5-15°C / min for thermosetting, hold at that temperature for 30-90 minutes, and allow to cool naturally to room temperature to form the bonding layer; Step S6: The III-V group gain chip that has undergone the corner pretreatment is flip-chip bonded onto the bonding layer, bonding pressure is applied and post-curing is performed to complete the bonding.

[0039] Specifically, in step S1, the silicon-based photonic integrated circuit substrate is fabricated using standard CMOS technology, with a silicon dioxide top cladding layer. Chemical mechanical polishing (CMP) is used to ensure the surface roughness of the silicon dioxide top cladding layer is ≤0.5 nm, guaranteeing good bonding quality with the BCB. The surface roughness can be verified by atomic force microscopy (AFM).

[0040] In step S2, laser scribing refers to using a picosecond or femtosecond laser to cut the chip corners at a 45° angle to form a flat chamfer; or cutting along an arc trajectory to form a rounded chamfer. Mechanical grinding refers to using a precision cutting wheel or grinding wheel to shape the chip corners. The flat chamfer length (i.e., the length of the right-angled edge removed) is controlled to be 15–25 μm, and the rounded chamfer radius is controlled to be 12–18 μm. After cutting or grinding, the characteristic dimensions of the chip corners can be confirmed by inspection using an optical microscope or a scanning electron microscope. Figure 3 The stress cloud diagram corresponding to the geometry of the processed corner is shown.

[0041] In step S3, the substrate is placed in an ultraviolet ozone cleaner, and the bonding area is irradiated with ultraviolet light at wavelengths of 184.9 nm and 253.7 nm, while oxygen or air is simultaneously introduced. The ultraviolet light decomposes oxygen to produce ozone and atomic oxygen. These active oxygen species react with and remove organic contaminants on the silica surface, while simultaneously introducing polar groups such as hydroxyl (-OH) groups onto the silica surface, increasing the surface energy and facilitating the wetting and adhesion of BCB. The treatment time is typically 60–120 seconds. In this embodiment, a 60-second activation treatment is used.

[0042] In step S4, the benzocyclobutene (BCB) precursor solution can be a commercially available Cyclotene 3022-35 type BCB resin solution (35% solid content). The solution is dropped onto the center of the substrate bonding area, and then the substrate is rotated at a set speed to spread the solution evenly using centrifugal force. There is an empirical relationship between the spin-coating speed and the thickness of the cured BCB layer: the higher the speed, the thinner the layer. In this embodiment, the speed-thickness curve was calibrated through pre-experimentation, and the speed was adjusted to ensure that the cured thickness falls within the range of 2.5–5.5 μm. For example, a speed of approximately 4000 rpm can achieve a thickness of approximately 3.5 μm. After coating, a soft-bake (e.g., baking at 90°C for 1 minute) is performed on a hot plate to remove some of the solvent.

[0043] In step S5, the substrate coated with the BCB precursor solution is placed in a high-temperature oven or programmable furnace under nitrogen protection. It is heated to 250°C at a heating rate of 5–15°C / min (e.g., 10°C / min) and held at this temperature for 30–90 min (e.g., 60 min). This holding process causes the BCB to undergo a thermal crosslinking reaction, forming a three-dimensional network structure, which then solidifies. After natural cooling to room temperature, a solid BCB bonding layer is obtained.

[0044] In step S6, the pre-treated III-V group gain chip is inverted so that its active surface faces the BCB bonding layer. The chip is precisely aligned and attached to the bonding layer using a flip-chip bonding machine. A certain bonding pressure (e.g., 0.5–1.0 MPa) is applied, and post-curing is performed at 150–200°C for 10–30 minutes to enhance the bond between the chip and the BCB. After bonding is complete, electrical connection can be achieved through wire bonding or other methods.

[0045] The above process first creates stress-reducing features at the chip corners through mechanical or laser processing, achieving the corner geometry optimization of the aforementioned optimized structure. Second, by precisely adjusting the spin coating speed, the BCB bonding layer thickness is controlled within an optimized window of 2.5–5.5 μm. Ultraviolet ozone activation treatment increases the substrate surface energy, ensuring good BCB spreading and adhesion. Stepped-temperature thermosetting under nitrogen protection prevents BCB oxidation and bubble formation, ensuring the density and uniformity of the bonding layer. Finally, flip-chip bonding and post-curing complete the high-strength bonding between the chip and the substrate. This fabrication process, combined with the optimized structure, ensures reduced interfacial stress and improved reliability from the manufacturing stage.

[0046] To further enhance the adhesion strength between BCB and silicon dioxide, a metal adhesion layer can be introduced before bonding. However, the timing and thickness of this adhesion layer need to be precisely controlled to avoid affecting the subsequent BCB coating and curing effects. Therefore, in one embodiment, after the UV ozone activation treatment of the bonding region of the silicon-based photonic integrated circuit substrate and before the spin-coating process for the BCB precursor solution, a titanium adhesion layer with a thickness of 3–7 nm is deposited on the surface of the silicon dioxide cladding layer by electron beam evaporation or magnetron sputtering, the titanium adhesion layer being located between the bonding layer and the silicon dioxide cladding layer.

[0047] Specifically, this step occurs after UV ozone activation treatment and before spin coating of the BCB precursor solution. The UV ozone activation treatment introduces hydroxyl groups into the silica surface; immediate deposition of the titanium adhesion layer at this point allows the titanium atoms to fully react with the surface functional groups, forming strong chemical bonds.

[0048] For deposition methods, electron beam evaporation or magnetron sputtering techniques are employed. Electron beam evaporation: in high vacuum (<10⁻⁶ ℃) -4 Under an argon atmosphere, an electron beam bombards a titanium target, causing titanium atoms to evaporate and deposit onto the substrate surface. Alternatively, magnetron sputtering involves bombarding a titanium target with ions generated by glow discharge in an argon atmosphere, sputtering titanium atoms onto the substrate surface. Both methods can yield titanium films with uniform thickness and high purity. In this embodiment, magnetron sputtering is preferred due to its better controllability of the deposition rate.

[0049] The thickness of the titanium adhesion layer is precisely controlled by deposition time, sputtering power, or electron beam current. A quartz crystal micro-sky can be used for on-site monitoring of the film thickness. When the thickness is less than 3 nm, the titanium film is discontinuous and a complete adhesion layer cannot be formed; when it is greater than 7 nm, excessive titanium may cause light absorption and residual stress problems. In this embodiment, a thickness of 5 nm is used.

[0050] The titanium adhesive layer is formed directly on the upper surface of the silica overcoat, followed by a BCB precursor solution being coated on top. After curing, the BCB bonding layer lies above the titanium adhesive layer. Therefore, the titanium adhesive layer is sandwiched between the BCB bonding layer and the silica overcoat, as shown below. Figure 4 As shown in the figure on the right.

[0051] A titanium adhesion layer is deposited on the surface of silica activated by ultraviolet ozone. Titanium atoms chemically react with oxygen on the silica surface to form Ti-O-Si bonds, which exhibit a bonding strength far exceeding that of physical adsorption. Simultaneously, the titanium layer possesses high surface energy and good compatibility with BCB, enabling the subsequent spin-coated BCB to spread uniformly and adhere firmly. The resulting BCB / titanium / silica composite interface exhibits approximately 35% higher adhesion energy compared to the interface without a titanium layer, effectively resisting the propagation of interfacial delamination cracks during thermal cycling, thereby further enhancing the reliability of the bonded interface.

[0052] In the spin-coating BCB process, it is difficult to accurately obtain the optimal thickness value for stress by simply adjusting the rotation speed based on experience. There is a non-monotonic relationship between thickness and stress, requiring simulation to pre-determine the optimal thickness range and achieve precise control during the process. Therefore, in one embodiment, the spin-coating process for applying the BCB precursor solution to the bonding region includes: controlling the thickness of the bonding layer to 3.0–4.0 μm using a non-monotonic stress-thickness relationship curve obtained through finite element simulation, with a thickness tolerance controlled within ±0.2 μm.

[0053] Specifically, to obtain the non-monotonic relationship curve between stress and thickness, a three-dimensional thermo-mechanical model of the bonding interface of the heterogeneous integrated laser was established using finite element analysis software (such as ANSYS or ABAQUS). The model layer stack structure from bottom to top is: silicon substrate, silicon dioxide lower cladding (3 μm), silicon nitride waveguide layer (300 nm), silicon dioxide upper cladding (2 μm), BCB bonding layer (thickness variable, ranging from 1 to 8 μm), and InP gain chip. The applied temperature load was from the BCB curing temperature (250℃) to room temperature (25℃), with a temperature difference ΔT = 225℃. At various BCB thicknesses, the peak von Mises stress of the bonding interface (especially the corner region of the chip) and the strain energy release rate at the interface crack tip were calculated. The simulation results are as follows: Figure 2As shown: with increasing BCB thickness, the peak stress initially decreases rapidly (in the 1-2.5 μm range), then remains low and gradual within the 2.5-5.5 μm range, and ceases to decrease significantly beyond 5.5 μm. Meanwhile, based on the Paris law crack propagation model (… ,in μm / cycle Calculations of the interface lifetime revealed that the thermal cycling lifetime of B10 reaches its maximum value within the thickness range of 3.0–4.0 μm. This optimal thickness range was determined to be 3.0–4.0 μm through simulation.

[0054] During the spin coating process, based on the non-monotonic relationship curve obtained from the simulation, a target thickness (e.g., 3.5 μm) corresponding to the optimal lifetime is selected. The required spin speed (e.g., 4000 rpm) to achieve 3.5 μm is determined through a pre-calibrated relationship between spin coating speed and cured thickness. A high-precision spin coater with a speed control accuracy better than ±10 rpm is used during coating to ensure the cured thickness is within the range of 3.0–4.0 μm. Furthermore, process parameters are determined through multiple experiments to control the thickness tolerance within ±0.2 μm. For example, when the target thickness is 3.5 μm, an actual thickness between 3.3 and 3.7 μm is considered acceptable.

[0055] For thickness testing, an ellipsometry or surface profilometer can be used to measure the thickness of the cured BCB layer. Unqualified samples can be screened or process parameters can be adjusted.

[0056] Based on the above, finite element simulation revealed the non-monotonic relationship between BCB thickness and interfacial stress and crack propagation driving force, providing a theoretical basis for thickness optimization. Controlling the thickness within a narrow window of 3.0–4.0 μm avoids the high-stress zone at smaller thicknesses and the high crack propagation driving force zone at larger thicknesses, enabling the bonding interface to achieve optimal resistance to thermal cycling fatigue. A tolerance of ±0.2 μm ensures thickness consistency in mass production, thereby guaranteeing that the reliability of each device meets design expectations. Through the combination of process and simulation, a complete technical closed loop from structural optimization to process controllability has been achieved. Figure 10 The bar chart on the right shows the comparison of B10 lifespan before and after optimization: the B10 lifespan of the standard structure is about 390 thermal cycles, while the B10 lifespan is increased to more than 900 cycles after adopting the structure and process of this application.

[0057] In the embodiments of this application, an in-situ monitoring method for bonding interface stress based on photoluminescence polarization degree (PL-DOP) and a multi-stress accelerated aging test and combined lifetime prediction model are also provided as verification and monitoring means for the above-mentioned optimized structure. However, these contents are not the core structural features protected by this application. A brief explanation is as follows: Thirdly, during the fabrication and use of heterogeneous integrated lasers, the residual stress at the bonding interface evolves with thermal cycling. However, traditional stress detection methods (such as micro-Raman spectroscopy and X-ray diffraction) require device destruction or offline measurement, making in-situ monitoring impossible. Therefore, in one embodiment, an application of the optimized structure described above in in-situ monitoring of stress at the bonding interface of heterogeneous integrated lasers is provided, comprising the following steps: Photoluminescence measurements were performed on the output surface of the III-V group gain chip in the optimized structure using a 532nm excitation laser, and the TE polarization intensity was collected. and TM polarization intensity Calculate the degree of polarization ; Record the reference polarization degree in the initial state of the device. The initial residual biaxial stress was calculated using a pre-established linear calibration curve between the degree of polarization and the residual biaxial stress. ; Throughout the device's entire lifespan, the photoluminescence measurement is repeated periodically to obtain the current polarization degree. And calculate the stress evolution index according to the following formula. ; A three-level failure warning is determined based on the value of the stress evolution index ΔS. A Level 1 warning is issued when the first threshold is exceeded. A level-two warning is issued when the threshold is exceeded. A level 3 warning is issued when the threshold is exceeded; wherein the first threshold is less than the second threshold, and the second threshold is less than the third threshold.

[0058] Specifically, for photoluminescence measurement and polarization degree calculation, a 532 nm continuous-wave laser is used as the excitation source, and the laser is focused onto the output facet of a III-V group gain chip (such as an InP-based multi-quantum-well structure). After the excitation light is absorbed by the chip material, a photoluminescence (PL) signal is generated. A polarization beam splitter is placed in the output optical path to decompose the PL signal into a TE polarization component (electric field direction parallel to the chip surface) and a TM polarization component (electric field direction perpendicular to the chip surface). The intensity of each component is collected by two photodetectors and denoted as . and The degree of polarization (DOP) is calculated according to the formula... The calculation reflects the relative difference between the TE and TM polarization components, with DOP values ​​ranging from 0 (completely unpolarized) to 1 (completely TE polarized). In this field, residual biaxial stress distorts the band structure, causing changes in the polarization transition probabilities of TE and TM, thus resulting in a linear relationship between DOP and stress.

[0059] For the reference recording and calibration curve, the first photoluminescence measurement is performed in the initial state of the device (usually after BCB curing and before gold wire bonding, at room temperature of 25°C), and the reference polarization degree is recorded. The pre-established linear calibration curve between polarization degree and residual biaxial stress was obtained by synchronous X-ray diffraction or micro-Raman spectroscopy calibration of standard InP samples with different stresses, in the form of... Where k is a proportionality coefficient (in this embodiment, k≈19.2MPa / %DOP, but in actual applications it can be recalibrated according to the specific material system). This curve converts DOP0 into initial residual biaxial stress. This serves as a reference zero point for subsequent stress evolution.

[0060] For periodic monitoring and stress evolution index, the above photoluminescence measurement is repeated at set time intervals (e.g., every 100 thermal cycles or every 500 hours) throughout the entire life cycle of the device (including pre-shipment aging tests and periodic maintenance during user operation) to obtain the polarization degree at the current moment. The stress evolution index ΔS is defined as the percentage change in current DOP relative to the baseline DOP0: A positive ΔS indicates an increase in stress (usually due to compressive stress accumulation caused by interface degradation), while a negative ΔS indicates stress release. This application focuses on the case where ΔS increases.

[0061] For the three-level failure warning determination, the first, second, and third thresholds increase sequentially, corresponding to minor anomalies, moderate risk, and near-failure levels, respectively. In this embodiment, based on a large amount of accelerated aging test data, the first threshold is set to 15%, the second threshold to 28%, and the third threshold to 45% (e.g., ...). Figure 5 (As shown in the right figure). The specific judgment rules are as follows: When ΔS>15%, a Level 1 warning is issued, indicating that the interface stress has significantly deviated from the initial state, and it is recommended to increase the monitoring frequency. When ΔS>28%, a Level 2 warning is issued, indicating that the interface has significantly deteriorated and suggesting that repair or replacement be prepared. When ΔS > 45%, a Level 3 warning is issued, indicating that the interface is about to experience a catastrophic failure and should be stopped immediately.

[0062] The aforementioned three-level warning thresholds can be jointly calibrated using an interface stress-life model (such as the Coffin-Manson model) and the Paris law crack propagation model to ensure the accuracy and timeliness of the warnings. In practical applications, users can adjust the threshold values ​​according to specific reliability requirements, but the hierarchical relationship of the three-level warnings (first threshold < second threshold < third threshold) remains unchanged.

[0063] Based on the above, utilizing the sensitivity of photoluminescence polarization of III-V group materials to residual stress, when the bonding interface develops cracks or delamination due to thermal cycling, the residual stress distribution within the chip changes, leading to a change in the DOP value. By periodically measuring DOP and calculating ΔS, the evolution of interface stress can be tracked in real time without damaging the device. The linear calibration curve quantifies DOP into a stress value, providing a quantitative basis for engineering judgment. A three-level early warning mechanism enables maintenance personnel to take different response measures according to the risk level, avoiding losses caused by sudden failures. This method, used in conjunction with the aforementioned optimized structure, can screen out individuals with abnormal stress before the device leaves the factory and also provide health status monitoring during use, improving the maintainability and system reliability of heterogeneous integrated lasers.

[0064] Photoluminescence measurement requires dedicated laser excitation and polarization detection equipment (PL equipment), which may be difficult to implement in certain field applications (such as after packaging or system integration). Threshold current, however, is a fundamental electrical parameter of a laser and is easy to measure. If a correlation can be established between the stress evolution index and the rate of change of the threshold current, the interface stress state can be indirectly evaluated through electrical parameters even without photoluminescence measurement capabilities. Therefore, in one embodiment, the method further includes: measuring the stress evolution index... Linear regression analysis was performed on the threshold current change rate measured simultaneously to construct an empirical relationship between the stress evolution index ΔS and the threshold current change rate. This relationship was used to indirectly estimate the interface stress evolution state through electrical parameters when photoluminescence measurement was not available. The expression for the threshold current change rate is as follows: , The initial threshold current, This represents the change in the threshold current.

[0065] Specifically, synchronous measurement refers to simultaneously performing photoluminescence measurement to obtain ΔS and electrical measurement to obtain threshold current on the same device. The threshold current is defined as the injection current when the laser begins lasing, and is typically determined by measuring the optical output power-current (LI) curve. Initial threshold current. Measured before device aging (at the same time as DOP0). Record the current threshold current at each periodic monitoring. Calculate the threshold current change rate .

[0066] Linear regression analysis refers to collecting ΔS and corresponding values ​​for multiple devices (e.g., 20 devices) at different aging stages. The data points are plotted as a scatter plot. A straight line is fitted using the least squares method to obtain an empirical formula: , where a and b are fitting coefficients. In practical applications, since there is an approximately linear relationship between ΔS and the rate of change of the threshold current (because both are affected by the increase in nonradiative recombination caused by interface stress), the correlation coefficient is usually greater than 0.85. In this embodiment, based on experimental data, a≈1.2 and b≈0.5% were obtained through fitting.

[0067] Indirect estimation refers to measuring only the current threshold current of the device when photoluminescence measurement conditions are unavailable. ,according to Calculate Then, by substituting the empirical formula, the current stress evolution index can be estimated. Then, you can The method compares the data with the three-level warning threshold to determine whether a warning is needed. The accuracy of this method depends on the correlation coefficient of the regression model and the data range, and it can be recalibrated periodically to maintain accuracy.

[0068] Based on the above, the rise in threshold current is a comprehensive manifestation of laser degradation, among which carrier leakage caused by bonding interface stress and nonradiative recombination are important factors. A synchronous measurement was used to establish ΔS and... The empirical relationship essentially maps electrical parameters to optical stress monitoring results. This allows for the estimation of interfacial stress states using simple threshold current tests even in situations lacking PL equipment (such as at the user's site or during system operation), thus expanding the applicability of the monitoring method. Furthermore, this method can serve as a supplement to or verification of PL monitoring, improving the robustness of reliability assessments.

[0069] Fourthly, to quantitatively assess the long-term reliability of the bonding interface of heterogeneous integrated lasers, an accurate lifetime prediction model is needed. Existing methods typically only employ single thermal cycling conditions or single high-temperature operating lifetime conditions and lack coupled analysis of crack propagation dynamics. Therefore, in one embodiment, an application of the optimized structure described above in lifetime prediction of the bonding interface of heterogeneous integrated lasers is provided, including the following steps: Failure data of a heterogeneous integrated laser with the optimized structure is obtained using a multi-stress accelerated aging matrix, which includes at least three thermal cycling conditions with different temperature swing amplitudes and at least two high-temperature operating lifetime conditions with junction temperatures. The Coffin-Manson model for thermal cycling life and the Arrhenius model for high-temperature operating life were established respectively. A Paris law crack propagation model is parameterized based on the range of stress intensity factor at the crack tip at the interface between the bonded layer and the silica cladding layer calculated by three-dimensional finite element thermo-mechanical simulation. The parameters of the Paris law crack propagation model were experimentally verified by measuring the cross-sectional crack length using focused ion beam or scanning electron microscopy. By combining the Coffin-Manson model, the Arrhenius model, and the Paris law crack propagation model, a B10 lifetime prediction map is generated with temperature swing and mean temperature as parameters.

[0070] Specifically, accelerated aging tests are employed to obtain failure data within a reasonable timeframe. The multi-stress accelerated aging matrix includes: Thermal cycling (TC) conditions: at least three different temperature swings ΔT. For example: TC-A: -40℃ to +85℃ (ΔT=125℃); TC-B: -40℃ to +125℃ (ΔT=165℃); TC-C: -40℃ to +165℃ (ΔT=205℃). The high and low temperature holding times are the same for each cycle (e.g., 15 min each), and the heating / cooling rates are controllable (e.g., 10℃ / min). High Temperature Operating Life (HTOL) conditions: at least two junction temperatures For example: HTOL-1: ℃; HTOL-2: ℃; HTOL-3: ℃. The device operates under constant current injection, and the optical power and threshold current are measured periodically.

[0071] At least eight devices were tested under each condition, and the failure time (number of thermal cycles or hours) was recorded. The failure criterion was typically defined as a relative change in threshold current exceeding 20% ​​or a decrease in optical output power exceeding 30%. Figure 6 The left figure shows the degradation curves of the threshold current change rate with the number of cycles under different TC conditions; Figure 6 The right figure is an extrapolation plot of Arrhenius under HTOL conditions.

[0072] For thermal cycling failure, the Coffin-Manson model is used to describe the fatigue damage caused by plastic strain, specifically:

[0073] in, B10 lifetime (number of thermal cycles when cumulative failure rate is 10%), ΔT is the temperature fluctuation. The average temperature is expressed in Kelvin. To activate energy, Where is the Boltzmann constant, and m is the Coffin-Manson exponent. is a material constant. In this embodiment, according to... Figure 7 Fitting the Weibull probability plots of the three thermal cycles yields m=2.0. eV. This model reveals that the larger the temperature swing and the higher the average temperature, the shorter the thermal cycle life.

[0074] For failures under high-temperature operating conditions (such as dark line defect growth and contact degradation), the Arrhenius model is adopted, specifically:

[0075] in, Mean time to failure, Junction temperature (unit: Kelvin). The activation energy is typically different from the activation energy in thermal cycling, but a similar value of 0.72 eV was obtained in this application. It is a constant. By extrapolating the HTOL data to the 25℃ operating condition, the MTTF is found to be >100,000 h, which meets the telecommunications-grade reliability requirements.

[0076] To describe the subcritical propagation of interfacial cracks during thermal cycling, a Paris law crack propagation model (finite element parameterization) is adopted, specifically:

[0077] in, Crack propagation length per thermal cycle (μm / cycle). The range of stress intensity factor at the crack tip (MPa·√m). and is a material constant. Three-dimensional finite element thermo-mechanical simulation was used to establish a layered stacked structure model, and the initial crack length was preset at the BCB / silica interface. (e.g., 5 μm), a steady-state temperature field is applied from the curing temperature of 250℃ to -40℃ (considering the cold end of the thermal cycle), and ΔK at the crack tip is calculated. The crack length a is varied to obtain the ΔK(a) function. Then, the Paris law is numerically integrated to predict the crack's path from... Extended to critical crack length The number of thermal cycles N required (e.g., 35 μm). Figure 9 The left figure shows the curve of crack propagation length versus number of cycles, where the FIB / SEM experimental measurement points match the model prediction curve well.

[0078] During experimental verification, a focused ion beam (FIB) was used to cut a cross section at the interface of the device that had been aged to different cycles, and then a scanning electron microscope (SEM) was used to observe and measure the actual crack length. Figure 9 The right figure shows the prediction error statistics for each data point. The maximum error is less than 8.5%, verifying the accuracy of the Paris law model parameters. μm / cycle ).

[0079] The three models are coupled: thermal cycling conditions determine ΔT and T_mean, and the upper limit of lifetime without initial defects can be estimated using the Coffin-Manson model; however, microcracks always exist in actual devices, and the Paris law model provides the lifetime under crack propagation dominance; the smaller of the two is taken as the final B10 lifetime. Simultaneously, the HTOL condition considers activation degradation under high-temperature operation. The combined model generates a lifetime based on the temperature swing ΔT and the average temperature. A B10 lifetime prediction chart with horizontal and vertical axes (e.g.) Figure 8 (As shown). The contour lines in the figure represent different ΔT and The number of B10 thermal cycles under a combination, for example, ΔT corresponding to 1000 cycles for a vehicle identification target. Range. Using this diagram, engineers can quickly predict device reliability under specific environmental conditions without having to repeat the entire set of experiments.

[0080] By employing a multi-stress accelerated aging matrix, sufficient failure data can be obtained in a shorter time, avoiding lengthy field tests. The Coffin-Manson model describes fatigue damage caused by thermal stress, the Arrhenius model describes high-temperature accelerated chemical degradation, and the Paris law model characterizes crack propagation dynamics from a fracture mechanics perspective. The combination of these three models overcomes the limitations of a single model, particularly by specifically parameterizing the unique crack path (along the BCB / silicon dioxide interface) of the silicon nitride platform. Focused ion beam / scanning electron microscopy experiments ensured the accuracy of the model parameters. The resulting B10 lifetime prediction map provides an intuitive and quantitative reliability basis for engineering design, enhancing the scientific rigor and practicality of heterogeneous integrated laser reliability assessment.

[0081] The layer stacking structure, boundary conditions, mesh generation accuracy, and convergence requirements of three-dimensional finite element thermo-mechanical simulation directly affect the accuracy of ΔK calculation, and thus the reliability of lifetime prediction. Therefore, in one embodiment, the layer stacking structure of the three-dimensional finite element thermo-mechanical simulation, from bottom to top, consists of: a silicon substrate, a silicon dioxide lower cladding layer, a silicon nitride waveguide layer, a silicon dioxide upper cladding layer, a bonding layer, and an indium phosphide gain chip. The stress reference temperature for the three-dimensional finite element thermal and mechanical simulation is set to the curing temperature of the bonding layer, which is 250°C. The mesh for the three-dimensional finite element thermo-mechanical simulation is divided at the interface between the bonding layer and the silicon dioxide cladding and at the interface between the bonding layer and the indium phosphide gain chip, with element sizes less than or equal to 0.1 μm. The mesh convergence error of the three-dimensional finite element thermal and mechanical simulation is less than or equal to 3%.

[0082] Specifically, the simulation model of the stacked structure is a two-dimensional or three-dimensional cross-section, and the stacking strictly follows the actual manufacturing process sequence. The thickness and material properties of each layer are as follows: Silicon substrate: approximately 500 μm thick (can be simplified to rigid body constraint), Young's modulus E = 130 GPa, Poisson's ratio ν = 0.28, coefficient of thermal expansion CTE = 2.6 × 10⁻⁶ -6 K -1 ; Silica undercoat: thickness 3 μm, E=70 GPa, ν=0.17, CTE=0.55×10 -6 K -1 ; Silicon nitride waveguide layer: thickness 300 nm (typical value in the range of 250–350 nm), E = 250 GPa, ν = 0.27, CTE = 3.2 × 10⁻⁶ -6 K -1 ; Silica top cladding: 2 μm thickness, material parameters are the same as the top cladding; Bonding layer (BCB): thickness 2.5–5.5 μm (typical 3.5 μm), E = 2.5 GPa (after curing), ν = 0.34, CTE = 52 × 10⁻⁶ -6 K -1 ; Indium phosphide gain chip: 200 μm thickness, E=80 GPa, ν=0.35, CTE=4.6×10 -6 K -1 .

[0083] The thermosetting temperature of BCB is 250℃, at which temperature it exists in a liquid or gel state with zero internal stress. When the temperature drops to room temperature (25℃) or lower (-40℃), thermal stress is generated due to the different CTEs of each layer. Therefore, the stress reference temperature is set to 250℃ in the simulation, meaning the model has no initial stress at this temperature. The applied temperature load is... , For operating temperature (e.g., 25℃ or -40℃).

[0084] To accurately capture the stress gradient and singularity at the interface, mesh refinement is necessary near the interfaces between the bonding layer and the silicon dioxide cladding, and between the bonding layer and the indium phosphide gain chip. Element sizes should be no larger than 0.1 μm (i.e., 100 nm). At the crack tip, singular elements or adaptive mesh refinement can be used. For regions far from the interface, coarser meshes (e.g., 1–5 μm) can be used to conserve computational resources.

[0085] To ensure the simulation results are independent of mesh density, mesh convergence analysis is required: the mesh size at the interface is progressively refined (e.g., 0.5 μm, 0.2 μm, 0.1 μm, 0.05 μm), and the peak von Mises stress or ΔK value at the same location is calculated. When the mesh size is refined from 0.1 μm to 0.05 μm, if the rate of change of stress or ΔK is less than 3%, the mesh convergence error is considered ≤3%, and a mesh size of 0.1 μm is acceptable. In this embodiment, it has been verified that a 0.1 μm mesh meets the convergence requirements. Figure 9 The comparison between the experimental and simulation results is shown in the figure.

[0086] Based on the above, the clearly defined 3D finite element simulation specifications ensure that the mechanical behavior of the interface is accurately modeled. The correct layer stacking order reflects the physical composition of the actual device, and the isotropic linear elastic material parameters are based on literature and experimental measurements. Setting the stress reference temperature to the BCB curing temperature of 250℃ is consistent with the stress generation mechanism of BCB. The high-resolution mesh (≤0.1 μm) can resolve stress concentrations near the interface and singular fields at the crack tip, while mesh convergence checks guarantee the reliability of the numerical solution. The standardization of all these parameters allows different researchers to reproduce the simulation results under the same conditions, thus providing a reliable ΔK input for the Paris law crack propagation model and ultimately enhancing the engineering value of the B10 lifetime prediction map.

[0087] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps.

[0088] Finally, for ease of understanding, the following table provides information on... Figure 2-10 The English terms in the text are explained:

[0089]

[0090]

[0091] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0092] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. An optimized structure for enhancing the reliability of the bonding interface of a heterogeneous integrated laser, the laser comprising a III-V group gain chip and a silicon-based photonic integrated circuit substrate connected thereto via a bonding layer, characterized in that: The bonding layer includes a benzocyclobutene bonding layer with a thickness of 2.5–5.5 μm. The III-V gain chip has stress-reducing corner features at at least two diagonal points in contact with the bonding layer. The corner features are either 45° flat truncated angles or rounded chamfers, wherein the truncated angle length of the 45° flat truncated angle is 15–25 μm, and the radius of the rounded chamfer is 12–18 μm. The stress-reducing corner features are located outside the active waveguide region and at a distance greater than or equal to 40 μm from the center of the active waveguide.

2. The optimized structure according to claim 1, characterized in that, The bonding layer includes: a titanium adhesion layer formed on the upper surface of the silicon dioxide cladding layer of the silicon-based photonic integrated circuit substrate, and a benzocyclobutene layer formed above the titanium adhesion layer; the thickness of the titanium adhesion layer is 3-7 nm.

3. The optimized structure according to claim 1, characterized in that, The silicon-based photonic integrated circuit substrate includes a silicon nitride waveguide layer with a thickness of 250–350 nm and located below the bonding layer. The crack propagation path between the bonding layer and the silicon dioxide upper cladding of the silicon-based photonic integrated circuit substrate is along the interface between the bonding layer and the silicon dioxide upper cladding.

4. A fabrication process for a heterogeneous integrated laser bonding interface based on the optimized structure described in any one of claims 1 to 3, characterized in that, Includes the following steps: A silicon-based photonic integrated circuit substrate is provided, the surface of which is a silicon dioxide cladding layer with a surface roughness of less than or equal to 0.5 nm; The corners of the III-V group gain chip are pre-processed by using laser scribing or mechanical grinding to form 45° flat chamfers or rounded chamfers at the four corners of the III-V group gain chip, wherein the length of the flat chamfer is 15 to 25 μm and the radius of the rounded chamfer is 12 to 18 μm. The bonding region of the silicon-based photonic integrated circuit substrate is subjected to ultraviolet ozone activation treatment; A benzocyclobutene precursor solution was coated onto the bonding area using a spin coating process. The thickness of the bonded layer after curing was controlled to be 2.5–5.5 μm by adjusting the spin coating speed. Under nitrogen protection, the temperature is increased to 250°C at a heating rate of 5–15°C / min for thermosetting, held at that temperature for 30–90 minutes, and then naturally cooled to room temperature to form the bonding layer. The III-V group gain chip, which has undergone the corner pretreatment, is flip-chip bonded onto the bonding layer, bonding pressure is applied and post-curing is performed to complete the bonding.

5. The preparation process according to claim 4, characterized in that, After performing UV ozone activation treatment on the bonding region of the silicon-based photonic integrated circuit substrate and before applying the BCB precursor solution using a spin coating process, the method further includes: depositing a titanium adhesion layer with a thickness of 3-7 nm on the surface of the silicon dioxide cladding layer by electron beam evaporation or magnetron sputtering, wherein the titanium adhesion layer is located between the bonding layer and the silicon dioxide cladding layer.

6. The preparation process according to claim 4, characterized in that, The process of applying BCB precursor solution to the bonding region using spin coating includes controlling the thickness of the bonding layer to 3.0–4.0 μm using a non-monotonic stress-thickness relationship curve obtained through finite element simulation, with the thickness tolerance controlled within ±0.2 μm.

7. An application of the optimized structure as described in any one of claims 1-3 in in-situ monitoring of stress at the bonding interface of heterogeneous integrated lasers, characterized in that, Includes the following steps: Photoluminescence measurements were performed on the output surface of the III-V group gain chip in the optimized structure using a 532nm excitation laser, and the TE polarization intensity was collected. and TM polarization intensity Calculate the degree of polarization ; Record the reference polarization degree in the initial state of the device. The initial residual biaxial stress was calculated using a pre-established linear calibration curve between the degree of polarization and the residual biaxial stress. ; Throughout the device's entire lifespan, the photoluminescence measurement is repeated periodically to obtain the current polarization degree. And calculate the stress evolution index according to the following formula. ; A three-level failure warning is determined based on the value of the stress evolution index ΔS. A Level 1 warning is issued when the threshold is exceeded. A level-two warning is issued when the threshold is exceeded. A level 3 warning is issued when the threshold is exceeded; wherein the first threshold is less than the second threshold, and the second threshold is less than the third threshold.

8. The application according to claim 7, characterized in that, Also includes: The stress evolution index Linear regression analysis was performed on the threshold current change rate measured simultaneously to construct an empirical relationship between the stress evolution index ΔS and the threshold current change rate. This relationship was used to indirectly estimate the interface stress evolution state through electrical parameters when photoluminescence measurement was not available. The expression for the threshold current change rate is as follows: , The initial threshold current, This represents the change in the threshold current.

9. An application of the optimized structure as described in any one of claims 1-3 in lifetime prediction of bonding interfaces in heterogeneous integrated lasers, characterized in that, Includes the following steps: Failure data of a heterogeneous integrated laser with the optimized structure is obtained using a multi-stress accelerated aging matrix, which includes at least three thermal cycling conditions with different temperature swing amplitudes and at least two high-temperature operating lifetime conditions with junction temperatures. The Coffin-Manson model for thermal cycling life and the Arrhenius model for high-temperature operating life were established respectively. A Paris law crack propagation model is parameterized based on the range of stress intensity factor at the crack tip at the interface between the bonded layer and the silica cladding layer calculated by three-dimensional finite element thermo-mechanical simulation. The parameters of the Paris law crack propagation model were experimentally verified by measuring the cross-sectional crack length using focused ion beam or scanning electron microscopy. By combining the Coffin-Manson model, the Arrhenius model, and the Paris law crack propagation model, a B10 lifetime prediction map is generated with temperature swing and mean temperature as parameters.

10. The application according to claim 9, characterized in that, The layer stacked structure of the three-dimensional finite element thermal and mechanical simulation, from bottom to top, is as follows: silicon substrate, silicon dioxide lower cladding, silicon nitride waveguide layer, silicon dioxide upper cladding, bonding layer, and indium phosphide gain chip; The stress reference temperature for the three-dimensional finite element thermal and mechanical simulation is set to the curing temperature of the bonding layer, which is 250°C. The mesh for the three-dimensional finite element thermo-mechanical simulation is divided at the interface between the bonding layer and the silicon dioxide cladding and at the interface between the bonding layer and the indium phosphide gain chip, with element sizes less than or equal to 0.1 μm. The mesh convergence error of the three-dimensional finite element thermal and mechanical simulation is less than or equal to 3%.

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