Short time overload boundary enabled power converter gate drive protection method and system

Abstract

This application provides a power converter gate drive protection method and system with short-time overload boundary enabled. The method steps are as follows: When planning short-time overload operation requirements, the upper-level controller generates short-time overload boundary constraint information, including constraint objects, effective windows, target current or current trajectory, and energy budget or thermal budget; the gate driver receives and verifies the information, generating the expected conduction state of the power switching device; local electrical quantities are collected, and the physical consistency residual between the local electrical quantities and the expected conduction state is calculated; the budget criterion is updated based on the local electrical quantities, target current or current trajectory, and energy budget or thermal budget boundary; the state of the gate driver is adjusted based on the short-time overload boundary constraint information, physical consistency residual, and budget criterion. This application establishes an auditable closed-loop judgment relationship between system-level planned overload, local device physical state, and hardware fault protection.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor gate drive protection technology, and in particular to a power converter gate drive protection method and system with short-time overload boundary enable. Background Technology

[0002] Power semiconductor devices such as SiC MOSFETs, GaN HEMTs, and IGBTs are widely used in inverters, converters, motor drives, energy storage converters, and new energy equipment. In order to reduce switching losses and increase power density, the switching speed of power devices is constantly increasing, which brings about problems such as overshoot, ringing, electromagnetic interference, crosstalk, and reduced short-circuit protection time margin.

[0003] Existing active gate drive technologies typically balance switching losses, dv / dt, di / dt, overshoot, and electromagnetic interference by altering gate resistance, gate current, gate voltage, or multi-level switching traces. Current short-circuit protection technologies generally employ desaturation detection, on-state voltage drop detection, source inductor voltage detection, Rogowski coil detection, or multi-stage soft turn-off to reduce the risk of device failure during short circuits or overcurrents.

[0004] From the perspective of existing technical approaches, schemes that issue drive parameters from the master controller usually focus on optimizing switching losses or electromagnetic interference under different operating conditions, but may not determine whether a high current belongs to a planned short-term overload; local threshold protection schemes have a fast response, but are prone to identifying both controlled short-term overloads and uncontrolled short circuits as overcurrents; desaturation detection or blanking optimization schemes focus on fault detection speed, but usually do not handle the distinction between planned overloads and fault semantics; simple active gate parameter optimization schemes can improve switching trajectories, but if time, energy and hard protection priority constraints are lacking, they may still weaken the fault protection boundary.

[0005] However, for short-term large overload conditions in systems such as inverters, the short-term overload can be a transient operation exceeding the rated operating current and intentionally enabled by the upper-level controller. This overload is not necessarily caused by a short circuit in the power device or a loss of control in the main circuit. If the gate driver only relies on the local current or on-state voltage drop threshold for protection, it may misjudge controllable overloads scheduled by the upper-level controller as faults; if the protection threshold is simply increased, the protection capability against uncontrollable faults such as short circuits may be weakened.

[0006] Therefore, there is an urgent need for a method that can utilize the known system operating condition boundaries of the upper-level controller while retaining the local fast hard protection capability of the gate driver, so that short-term overloads can pass within a controlled time and energy range, while uncontrollable faults such as short circuits, desaturation, gate anomalies, and communication anomalies can still be handled quickly.

[0007] In existing technologies, master controllers can issue drive parameters based on operating conditions, optimize active gate drive parameters, provide local overcurrent or desaturation threshold protection, implement SOA or thermal budget protection, and use intelligent drive communication to improve some of the problems. However, these approaches typically focus on drive parameter optimization, fault detection speed, or device stress limitations, and have not yet formed a closed-loop discrimination mechanism that mutually constrains short-term overload semantics, local conduction physical consistency, time or energy budget, and hard protection coverage. Summary of the Invention

[0008] The purpose of this invention is to provide a power converter gate drive protection method and system with short-time overload boundary enabled. It addresses the technical problem of how, when a power converter experiences a planned short-time large overload triggered by an upstream controller, the gate driver can distinguish between tolerable planned overloads and uncontrollable short-circuit or desaturation faults without relaxing or disabling hardware fault protection, and how to limit the planned overload within verifiable device thermal safety boundaries and local physical consistency boundaries.

[0009] First, this application provides a power converter gate drive protection method with short-time overload boundary enabled. The power converter includes an upper-level controller, a gate driver, and power switching devices. The specific steps are as follows:

[0010] S1: The upper-level controller determines the planned short-time overload operation requirements of the power converter and generates short-time overload boundary constraint information, including constraint objects, effective windows, target current or current trajectory, and energy budget or thermal budget.

[0011] S2: The gate driver receives and verifies the short-time overload boundary constraint information, and forms the expected on-state of the power switching device based on the on-state voltage drop, target current or current trajectory, temperature or gate state.

[0012] S3: The gate driver acquires local electrical quantities and calculates the physical consistency residual between the local electrical quantities and the expected on-state.

[0013] S4: Update the budget criteria based on local electrical quantities, target current or current trajectory, and energy budget or thermal budget boundaries;

[0014] S5: Adjust the state of the gate driver based on the short-time overload boundary constraint information, physical consistency residual, and budget criterion.

[0015] Optionally, the planned short-term overload operation requirement mentioned in step S1 is generated by motor starting, grid-connected transient, energy storage PCS impact power, load step, or parallel system current sharing requirement.

[0016] The short-time overload boundary constraint information also includes at least one of the following: phase identifier, bridge arm identifier, power module identifier, serial number, timestamp, check code, heartbeat count, allowable bus voltage range, allowable temperature range, budget derating factor, and allowable drive parameter set.

[0017] Optionally, the specific steps in step S2 are as follows:

[0018] S2.1: After receiving short-time overload boundary constraint information, the gate driver determines whether the enabled object matches, whether the sequence number is continuous, whether the timestamp is within a valid range, whether the heartbeat is normal, and whether the verification is passed; when any validity condition is not met, the gate driver enters the fault latch state.

[0019] S2.2: Determine the expected conduction state vector of the power switching device based on the target current or current trajectory, bus voltage, temperature, gate voltage, and device model parameters.

[0020] Optionally, the local electrical quantities mentioned in step S3 include at least two of the following: on-state voltage drop or saturation voltage drop, device current, gate voltage, junction temperature or case temperature, bus voltage, complementary switch status, and desaturation detection status.

[0021] The physical consistency residual is the weighted residual between the observation vector composed of the local electrical quantities and the expected vector composed of the expected conduction state.

[0022] Optionally, the cumulative energy budget or heat budget in step S4 is updated as follows:

[0023]

[0024] in, This represents the cumulative energy budget or heat budget occupancy after the update in the kth sampling period. For recovery or attenuation coefficient; The sampling period; The value of the budget increment function. It is determined based on at least one of the following: conduction loss, residual power, I²t, junction temperature margin, safe operating area occupancy, or transient thermal resistance model;

[0025] The upper limit of the budget criterion is determined by short-term overload boundary constraint information, device calibration data, or the derating strategy of the upper-level controller, and the short-term overload boundary constraint information is not used to clear, cover, or increase the accumulated budget occupancy of the gate driver.

[0026] Optionally, the specific method in step S5 is as follows:

[0027] When the short-time overload boundary constraint information is valid, the physical consistency residual meets the preset threshold, the budget criterion does not exceed the limit, and the hardware fault protection signal is invalid, the gate driver enters the controlled overload state and selects the overload gate drive parameter group.

[0028] When any one of the following conditions is met: the hardware fault protection signal is valid, the physical consistency residual does not meet the preset threshold, the budget criterion exceeds the limit, or the short-term overload boundary constraint information is invalid, the gate driver is prohibited from entering or exiting the controlled overload state; wherein, the hardware fault protection link that generates the hardware fault protection signal is independent of the short-term overload boundary constraint information and has priority over the selection of the overload gate drive parameter group, and the short-term overload boundary constraint information is not used to change the fault detection threshold, hardware blanking time, or fault latching logic of the hardware fault protection link.

[0029] Optionally, the hardware fault protection signal in step S5 includes at least one of the following: desaturation detection signal, overcurrent comparison signal, short circuit detection signal, gate undervoltage signal, and gate overvoltage signal; the hardware fault protection signal directly covers the overload gate drive parameter group selection without going through the validity judgment path of the short-time overload boundary constraint information.

[0030] The overload gate drive parameter set includes at least one parameter among the following: turn-on gate resistance, turn-off gate resistance, gate current, gate positive voltage, gate negative voltage, Miller clamping time, soft turn-off slope, diagnostic sampling window, and diagnostic reporting cycle. The gate driver selects the overload gate drive parameter set from the preset allowed drive parameter set only when the controlled overload state is established, and transitions to the normal drive parameter set according to the recovery parameter set after the controlled overload state ends.

[0031] Secondly, this application provides a power converter gate drive protection system with short-time overload boundary enabled, which is used to implement the above-mentioned power converter gate drive protection method with short-time overload boundary enabled, including an upper-level controller, an isolation communication unit, a gate driver, a power switch unit, a detection unit, and a hard protection link.

[0032] The upper-level controller is used to generate short-time overload boundary constraint information. The isolation communication unit is used to transmit the short-time overload boundary constraint information. The gate driver is used to verify the short-time overload boundary constraint information, acquire the local electrical quantities of the power switching device, calculate the physical consistency residual, update the budget criterion, and select the gate drive parameter group. The power switching unit is a SiC MOSFET, IGBT, GaN HEMT, or a power module composed of devices. The detection unit is used to provide local electrical quantities to the gate driver. The hardware fault protection link is used to generate a hardware fault protection signal in the event of short circuit, desaturation, gate undervoltage, or gate overvoltage.

[0033] Optionally, the output of the hardware fault protection link is connected to the cover selector or drive disable terminal of the gate driver, so that the fault shutdown parameter group takes precedence over the overload gate drive parameter group.

[0034] Optionally, the gate driver includes an enable resolution module, a physical consistency determination module, a parameter group selection module, and a fault latch module;

[0035] The enable parsing module is used to parse the enable window, enable object and budget; the consistency discrimination module is used to calculate the residual based on the locally sampled electrical quantity; the parameter group selection module is used to select the target gate drive parameter group when the controlled overload is established; and the fault latching module is used to overwrite the overload gate drive parameter group selection signal and make the gate output stage execute the fault shutdown parameter group when the hardware fault protection signal is valid.

[0036] Because of the adoption of the above technical solution, the present invention has the following advantages:

[0037] 1. This application defines the planned boundary on the upper-level controller side as a necessary condition for entering the controlled overload, rather than a direct release condition; at the same time, it uses physical consistency residuals, time or energy budgets, and hard protection signals as independent verification conditions on the driver side. Thus, an auditable closed-loop judgment relationship is formed between system-level planned overload, local device physical state, and hardware fault protection.

[0038] 2. The short-time overload boundary constraint information in this application is used to limit the object, window, target current, and budget boundary of the planned overload. The local physical consistency residual is used to verify whether the high current still conforms to the normal conduction state of the power switching device. The budget criterion is used to constrain the energy or thermal stress during the controlled overload. The hardware fault protection link directly overrides the parameter group selection in the event of short circuit, desaturation, or gate abnormality. The above features together resolve the contradiction between planned overload false protection and the inflexibility of short-circuit hard protection.

[0039] 3. This application transforms the boundary constraint information of planned short-term overload into the driver's local expected conduction state and budget boundary, and then uses the physical consistency residual to determine whether to accept the planned boundary, while ensuring that the hardware fault protection link maintains a structural coverage relationship that cannot be rewritten by the boundary constraint information. This combined relationship changes the decision logic between planned overload and fault protection, rather than simply connecting multiple detection or control modules in parallel.

[0040] 4. The hardware fault protection link of this application is independent of the short-term overload boundary constraint information. Even if the boundary constraint is still within the effective window, desaturation, overcurrent comparison or gate abnormality signal can still force fault shutdown, thereby avoiding the need to relax the hard protection threshold to gain overload capacity.

[0041] 5. The controlled overload state of this application must also meet the physical consistency residual criterion, which can distinguish the high current operation planned and scheduled by the upper controller from uncontrollable faults such as desaturation and short circuit, and reduce false protection of short-term overload.

[0042] 6. The effective window, energy budget, and thermal budget of this application together define the controlled boundary, which can prevent planned short-term overload from evolving into device thermal runaway or exceeding the safe operating area.

[0043] 7. The failure shutdown state machine of this application reverts to normal or conservative drive when there is communication abnormality, boundary constraint frame abnormality, residual abnormality or budget exhaustion, which improves the security when the master control and drive coordination link fails.

[0044] 8. The gate drive parameter set of this application is constrained by switching losses, overshoot, crosstalk and thermal margin during controlled overload, which can improve the short-time overload operation quality without sacrificing the priority of short-circuit hard protection.

[0045] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0046] The accompanying drawings of this invention are described below.

[0047] Figure 1 This is a flowchart of the power converter gate drive protection method of the present invention.

[0048] Figure 2 This is a schematic diagram of the power converter gate drive protection system of the present invention.

[0049] Figure 3 This is a schematic diagram of the state machine of the present invention.

[0050] Figure 4 This is a schematic diagram of the controlled overload and short-circuit fault waveforms of the present invention.

[0051] Figure 5 This is a schematic diagram of the residual discrimination of the present invention.

[0052] Figure 6 This is a schematic diagram illustrating the selection of gate drive parameter groups according to the present invention.

[0053] Figure 7 This is a schematic diagram of the short-time overload boundary constraint information communication timing of the present invention.

[0054] Figure 8 This is a schematic diagram of the hardware protection overlay logic of the present invention.

[0055] Figure 9 This is a schematic diagram of the simulation waveform for the separability criterion of the present invention.

[0056] In the diagram: 110 - Upper-level controller; 120 - Isolation communication unit; 130 - Gate driver; 131 - Enable resolution module; 132 - Physical consistency discrimination module; 133 - Parameter group selection module; 134 - Fault latching module; 140 - Power switching unit; 150 - Detection unit; 160 - Hard protection link. Detailed Implementation

[0057] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0058] Example 1:

[0059] like Figure 2 The power converter gate drive protection system with short-time overload boundary enabled shown includes an upper-level controller 110, an isolation communication unit 120, a gate driver 130, a power switch unit 140, a detection unit 150, and a hard protection link 160.

[0060] 1. The upper-level controller 110 is used to generate short-term overload boundary constraint information;

[0061] In this embodiment, the upper-level controller 110 is either the inverter master controller or the power converter master controller. The upper-level controller 110 can obtain system-level current commands, bus voltage, temperature estimates, power commands, or external control requirements, and determine whether there is a short-term overload operation requirement, generating short-term overload boundary constraint information. The upper-level controller 110 does not directly shut down the hard protection link 160, but only sends short-term overload boundary constraint information indicating a planned short-term overload to the gate driver 130.

[0062] 2. The isolation communication unit 120 is used to transmit the short-time overload boundary constraint information;

[0063] In this embodiment, the isolation communication unit 120 employs a digital isolator, optical fiber, LVDS, SPI isolation link, CAN isolation link, or other anti-interference communication link. The short-term overload boundary constraint information transmitted by the isolation communication unit 120 includes one or more of the following: sequence number, timestamp, checksum, and heartbeat information, enabling the gate driver 130 to identify duplicate messages, delayed messages, and erroneous messages.

[0064] 3. The gate driver 130 is used to verify the short-time overload boundary constraint information, acquire the local electrical quantities of the power switching device, calculate the physical consistency residual, update the budget criterion, and select the gate drive parameter group;

[0065] In this embodiment, the gate driver 130 includes an enable resolution module 131, a physical consistency discrimination module 132, a parameter group selection module 133, and a fault latch module 134.

[0066] The enable resolution module 131 is used to resolve the enable window, enable object (bridge arm, phase unit, power module or device number) and budget; the consistency discrimination module 132 is used to calculate the residual based on the locally sampled electrical quantities (the residual model can be a lookup table model, a linear temperature compensation model, a piecewise model or a recursive identification model); the parameter group selection module 133 is used to select the target gate drive parameter group when a controlled overload is established (the short-time overload boundary constraint information is valid, the physical consistency residual meets the preset threshold, the budget criterion is not exceeded, and the hard protection input is invalid). The fault latch module 134 is used to overwrite the overload gate drive parameter group selection signal and make the gate output stage execute the fault shutdown parameter group when the hardware fault protection signal is valid; the gate driver 130 performs enable resolution, consistency discrimination, parameter group selection and fault latching locally.

[0067] The gate driver 130 further includes a communication interface, a detection interface, processing logic, a gate output stage, and a budget management module. The processing logic is configured to receive short-time overload boundary constraint information from the upper-level controller 110 through the communication interface, obtain locally sampled electrical quantities through the detection interface, call the physical consistency discrimination module 132 to calculate the physical consistency residual between the locally sampled electrical quantities and the expected conduction state, and call the budget management module to update the budget criterion.

[0068] In this embodiment, by Figure 3As shown, the gate driver 130 has a normal state, a boundary verification state, a controlled overload state, a recovery or derating state, and a fault latching state. The gate driver 130 sends back at least one of the physical consistency residual, budget occupancy rate, controlled overload duration, actual drive parameter set, and fault trigger source to the upper-level controller 110. The upper-level controller 110 adjusts the current limiting, modulation ratio, power allocation, or next short-term overload boundary constraint information based on the sent-back information. Furthermore, the gate driver 130 updates the device model parameters used to form the expected conduction state only in the non-overload, low residual, and hardware fault protection signal invalid state.

[0069] 4. The power switching unit 140 is a SiC MOSFET, IGBT, GaN HEMT, or a power module composed of the above devices.

[0070] 5. The detection unit 150 is used to provide the local electrical quantity to the gate driver 130;

[0071] In this embodiment, the detection unit 150 is used to detect the on-state voltage drop V of the power switching unit 140. DS，on Gate voltage V GS Drain or collector current I D The detection unit 150 is integrated with the gate driver 130, and the junction temperature or case temperature is estimated as well as the desaturation signal. In one embodiment of this application, the detection unit 150 is integrated with the gate driver 130; in another embodiment of this application, the detection unit 150 is implemented by an external sampling circuit, an isolation amplifier, a comparator, or a current sensor.

[0072] 6. The hardware fault protection link 160 is used to generate a hardware fault protection signal in the event of short circuit, desaturation, gate undervoltage, or gate overvoltage; wherein, the output of the hardware fault protection link 160 is connected to the overlay selector or drive disable terminal of the gate driver 130 so that the fault shutdown parameter group takes precedence over the overload gate drive parameter group.

[0073] In this embodiment, as Figure 8 As shown, the desaturation comparator, Blanking unit, logic gate, and fault latch form an independent hard protection link; this link outputs a coverage enable to the coverage selector, prioritizing the fault shutdown parameter group over the controlled overload parameter group. For different hard protection links 160, the hardware fault protection signal can be generated by the desaturation comparator, source inductor voltage detection, shunt resistor overcurrent comparison, Rogowski coil comparison, gate undervoltage lockout, gate overvoltage lockout, or a combination thereof.

[0074] Example 2:

[0075] like Figure 1The method for gate drive protection of a power converter with short-time overload boundary enabled, as shown, includes the following steps:

[0076] S1: The upper-level controller determines the planned short-time overload operation requirements of the power converter and generates short-time overload boundary constraint information, including constraint objects, effective windows, target current or current trajectory, and energy budget or thermal budget.

[0077] As one embodiment of this application, the short-time overload boundary constraint information further includes at least one of the following: phase identifier, bridge arm identifier, power module identifier, serial number, timestamp, check code, heartbeat count, allowable bus voltage range, allowable temperature range, budget derating factor, and allowable drive parameter set; the short-time overload boundary constraint information can be represented as:

[0078]

[0079] in, This provides the short-time overload boundary constraint information corresponding to the kth sampling period; For constraint objects; The effective window start point; For effective duration; The target current or target current trajectory within the effective window; This represents the upper limit of the energy budget or thermal budget. To allow the set of drive parameter groups; For serial number or heartbeat count; This is the verification code.

[0080] In this embodiment, the planned short-term overload operation requirement is generated by motor starting, grid-connected transients, energy storage PCS impact power, load step, or parallel system current sharing requirements.

[0081] In this embodiment, the short-term overload boundary constraint information is not equivalent to a normal turn-on signal. It defines the object, time window, target current or current trajectory, budget boundary, and operating range that allow overload. The short-term overload boundary constraint information only constitutes a necessary condition for entering the controlled overload state, and does not constitute a release command to shield hardware fault protection. In the communication implementation, the short-term overload boundary constraint information can be encapsulated into a boundary constraint frame; the boundary constraint frame is the message bearer form of the short-term overload boundary constraint information on an isolated communication link.

[0082] S2: The gate driver receives and verifies the short-time overload boundary constraint information, and forms the expected conduction state of the power switching device based on the target current or current trajectory; the specific steps are as follows:

[0083] S2.1: When the gate driver receives short-time overload boundary constraint information, it determines whether the enabled object (bridge arm, phase unit, power module or device number) matches, whether the serial number is continuous, whether the timestamp is within the valid range, whether the heartbeat is normal, and whether the verification is passed; when any validity condition is not met, the gate driver enters the fault latch state.

[0084] In this embodiment, as Figure 7 As shown, the upper-level controller, isolation communication unit, and gate driver can exchange short-term overload boundary constraint information using sequence number, timestamp, checksum, and heartbeat. When the short-term overload boundary constraint information, acknowledgment information, or heartbeat times out, the gate driver performs communication failure processing and exits the controlled overload state. The boundary validity can be determined by the following formula:

[0085]

[0086] in, This is the result of determining the validity of short-term overload boundary constraint information; , , , , and These respectively represent constraint object matching, consecutive sequence numbers, successful verification, normal heartbeat, within the valid window, and operating condition within the allowable range.

[0087] S2.2: The expected on-state of the power switch device is formed based on the on-state voltage drop, target current or current trajectory, temperature or gate state; specifically, the gate driver constructs the expected on-state vector of the power switch device in each sampling period k according to the boundary constraint frame and the device model. for:

[0088]

[0089] in: Let be the expected conduction state vector for the k-th sampling period; The value of the target current or target current trajectory in the kth sampling period; This refers to the bus voltage. This is an estimated value for junction temperature or shell temperature; This is the gate voltage; These are the parameters for the device model.

[0090] S3: The gate driver acquires local electrical quantities and calculates the physical consistency residual between the local electrical quantities and the expected conduction state; the specific steps are as follows:

[0091] S3.1: The gate driver acquires local electrical quantities, including the on-state voltage drop V. DS，on or saturation pressure drop VCE，sat Device current I D Gate voltage V GS At least two of the following: junction temperature or case temperature, bus voltage, complementary switch status, and desaturation detection status; the observation vector is constructed by locally sampled electrical quantities to form the sampling period k. The observation vector It is formed by at least two types of locally sampled electrical quantities;

[0092] S3.2: Calculate the expected conduction state vector With observation vector The weighted residuals between them are used to obtain the physically consistent residuals. The calculation is as follows:

[0093]

[0094] in, This is the local observation vector; This is the weighted residual vector; This is either a weight matrix or a normalized matrix; For physical consistency residuals; subscript This represents the i-th component in the weighted residual vector.

[0095] In this embodiment, to ensure that planned short-term overload and short-circuit or desaturation faults have separable criteria, the residual threshold can satisfy the following relationship:

[0096]

[0097] In the formula, Represents the condition set The upper bound of the residuals for the short-term overload sample under the next plan; Represents the condition set Lower bound of residuals for short-circuit or desaturation fault samples; This is a preset discrimination margin. When this margin condition cannot be met, the gate driver will not enter the controlled overload state or will switch to the recovery or derating state.

[0098] S4: Update the budget criteria based on local electrical quantities, target current or current trajectory, and energy budget or thermal budget boundaries; the specific method is as follows:

[0099] The budget criterion is accumulated or updated locally by the gate driver, and the accumulated energy budget or thermal budget is updated as follows:

[0100]

[0101] in, This represents the cumulative energy budget or heat budget occupancy after the update in the kth sampling period. For recovery or attenuation coefficient; The sampling period; The value of the budget increment function. It can be determined based on at least one of the following: conduction loss, residual power, I²t, junction temperature margin, safe operating area occupancy, or transient thermal resistance model.

[0102] The upper limit of the budget criterion is determined by the short-term overload boundary constraint information, device calibration data, or the derating strategy of the upper-level controller, and the short-term overload boundary constraint information is not used to clear, cover, or increase the accumulated budget occupancy of the gate driver.

[0103] As one embodiment of this application, the budget increment function The thermal budget can be determined based on a transient thermal resistance model, for example, by estimating the junction temperature increment based on the equivalent loss and the device's transient thermal resistance function for each sampling interval. This implementation is only used to illustrate one method of calculating the thermal budget; other methods can also be used, and this application does not limit the budget criteria.

[0104] In this embodiment, the energy budget E OL,k This represents the accumulated thermal stress occupancy of the device during a controlled overload. Different devices and packages may use different energy or thermal budget upper limits, which can be determined by the safe operating area, short-time overload profiles, junction temperature estimation, case temperature measurement, or master controller derating strategy. Short-time overload boundary constraint information is used to limit E. OL,k The allowed range, rather than replacing the local budget accumulation result of the gate driver; when the budget upper limit corresponding to the boundary constraint information is lower than the current accumulated budget occupancy, the gate driver should enter the recovery, derating or fault latch state.

[0105] S5: Adjust the state of the gate driver based on the short-time overload boundary constraint information, physical consistency residual, and budget criterion. The specific method is as follows:

[0106] When the short-time overload boundary constraint information is valid, the physical consistency residual meets the preset threshold, the budget criterion does not exceed the limit, and the hardware fault protection signal is invalid, the gate driver enters the controlled overload state and selects the overload gate drive parameter group.

[0107] When any one of the following conditions is met: the hardware fault protection signal is valid, the physical consistency residual does not meet the preset threshold, the budget criterion exceeds the limit, or the short-term overload boundary constraint information is invalid, the gate driver is prohibited from entering or exiting the controlled overload state; wherein, the hardware fault protection link that generates the hardware fault protection signal is independent of the short-term overload boundary constraint information and has priority over the selection of the overload gate drive parameter group, and the short-term overload boundary constraint information is not used to change the fault detection threshold, hardware blanking time, or fault latching logic of the hardware fault protection link.

[0108] In this embodiment, the controlled overload state is determined by the following formula:

[0109]

[0110] in, The result is the controlled overload condition determination. This is the physical consistency residual threshold under the current operating conditions; This indicates that the power switching device is within the safe operating area; Synthesized signals for hardware fault protection.

[0111] The hardware fault protection synthesized signal can be represented as:

[0112]

[0113] in, This is a desaturation detection signal; This is an overcurrent comparison signal; This is a short-circuit detection signal; This is a gate undervoltage signal; This is the gate overvoltage signal.

[0114] The final output parameter set is selected according to the hard protection coverage relationship:

[0115]

[0116] in, This is the actual gate drive output in the k-th cycle; Output for hardware failure or safety shutdown; Controlled overload output; This is the output for normal operation.

[0117] In this embodiment, the hardware fault protection signal includes at least one of the following: desaturation detection signal, overcurrent comparison signal, short circuit detection signal, gate undervoltage signal, and gate overvoltage signal; the hardware fault protection link includes at least one of the following: comparator, latch, logic gate, drive disable terminal, soft shutdown control terminal, or fault shutdown selection terminal; and the hardware fault protection signal directly covers the overload gate drive parameter group selection without going through the validity judgment path of the short-time overload boundary constraint information, so that the short-time overload boundary constraint information is only a necessary condition for the controlled overload judgment chain rather than a fault protection release condition.

[0118] In this embodiment, the overload gate drive parameter set includes at least one parameter among turn-on gate resistance, turn-off gate resistance, gate current, gate positive voltage, gate negative voltage, Miller clamping time, soft turn-off slope, diagnostic sampling window, and diagnostic reporting cycle; the fault turn-off parameter set includes at least one of multi-stage soft turn-off, reducing the rate of change of turn-off current, reducing the rate of change of turn-off voltage, clamping bus overshoot, fault latching, and fault source feedback; the gate driver selects the overload gate drive parameter set from the preset allowed drive parameter set only when the controlled overload state is established, and transitions to the normal drive parameter set according to the recovery parameter set after the controlled overload state ends.

[0119] In this embodiment, as Figure 5 As shown, the controlled overload point falls within the allowable band of the conduction model; when a short circuit or desaturation fault occurs, the power switching device is no longer in the normal low-dropout conduction state, and the conduction voltage drop or equivalent desaturation detection voltage rises and deviates from the allowable band. Therefore, the short circuit or desaturation point should be located above the allowable band and close to or exceed the desaturation threshold V. DESAT Instead of being located in a low-pressure-drop region. For example... Figure 6 As shown, the gate driver selects the target parameter group based on the candidate drive parameter group library and constraint input; when the hardware fault protection signal is valid, the fault shutdown parameter group is forcibly overridden by the controlled overload parameter group.

[0120] Simulation and Verification:

[0121] The feasibility of this application is further illustrated by a set of engineering parameters and first-order discrete simulation. The first-order discrete simulation takes as input short-term overload boundary constraint information generated by the master control side and conduction voltage drop, current, temperature, and desaturation signals acquired by the drive side, and outputs normalized residuals, budget occupancy, hard protection signals, and parameter set selection results. This setup is used to demonstrate the separability of planned short-term overloads and uncontrollable short-circuit faults in terms of conduction model consistency and hard protection triggering paths.

[0122] This simulation also outputs verifiable data fields, including the effective state of boundary constraints, device current, simulated on-state voltage drop, estimated on-state voltage drop, normalized residual, budget utilization, desaturation hard protection signal, controlled overload state, and selected gate drive parameter group. Parameter settings are shown in Table 1, short-time overload boundary constraint information fields are shown in Table 2, gate drive parameter groups are shown in Table 3, and the discrimination results are shown in Table 4.

[0123] Table 1 Parameter Setting Table

[0124]

[0125] Table 2 Short-time overload boundary constraint information fields

[0126]

[0127] Table 3 Gate Drive Parameter Group

[0128]

[0129] Table 4. Judgment Results

[0130]

[0131] The simulation above uses a first-order engineering model: rated current 20 A, controlled overload current 60 A, enable window 20 ms; the short-circuit event is set as the gate conduction voltage drop deviating from the conduction model and triggering the residual or desaturation criterion. The simulation results are used to illustrate the separability of the criterion and do not represent the ultimate capability of a specific device, nor do they indicate that any device can tolerate a 3x overload. Figure 9 As shown, the planned three-times short-term overload maintains low residuals and enters a controlled overload state within the enable window; even if the short-circuit condition is still within the enable window, it will switch to the fault shutdown parameter group due to residual exceeding the limit and triggering hard protection. For actual products, the desaturation or overcurrent comparator can adopt a microsecond-level protection response based on the device's short-circuit withstand time.

[0132] As shown in Table 4, under planned short-term overload conditions, although the current increases to three times the rated current, the on-state voltage drop remains consistent with the model, so the residual is below the threshold. Under short-circuit or desaturation fault conditions, the on-state voltage drop deviates rapidly from the on-state model. Even if the short-term overload boundary constraint information is still within the effective window, the hard protection link can still cover the controlled overload parameter group and force the system to enter fault shutdown.

[0133] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A method for short-time overload boundary enabled protection of a power converter gate driver, the power converter comprising a superior controller, a gate driver and a power switching device, characterized in that, The specific steps are as follows: S1: The upper-level controller determines the planned short-time overload operation requirements of the power converter and generates short-time overload boundary constraint information, including constraint objects, effective windows, target current or current trajectory, and energy budget or thermal budget. S2: The gate driver receives and verifies the short-time overload boundary constraint information, and forms the expected on-state of the power switching device based on the on-state voltage drop, target current or current trajectory, temperature or gate state. S3: The gate driver acquires local electrical quantities and calculates the physical consistency residual between the local electrical quantities and the expected on-state. S4: Update the budget criteria based on local electrical quantities, target current or current trajectory, and energy budget or thermal budget boundaries; S5: Adjust the state of the gate driver based on the short-time overload boundary constraint information, physical consistency residual, and budget criterion.

2. The short duration overload boundary enabled power converter gate drive protection method of claim 1, wherein, The planned short-term overload operation requirement mentioned in step S1 is generated by motor starting, grid-connected transient, energy storage PCS impact power, load step, or parallel system current sharing requirement. The short-time overload boundary constraint information also includes at least one of the following: phase identifier, bridge arm identifier, power module identifier, serial number, timestamp, check code, heartbeat count, allowable bus voltage range, allowable temperature range, budget derating factor, and allowable drive parameter set.

3. The short duration overload boundary enabled power converter gate drive protection method of claim 2, wherein, The specific steps in step S2 are as follows: S2.1: After receiving short-time overload boundary constraint information, the gate driver determines whether the enabled object matches, whether the sequence number is continuous, whether the timestamp is within a valid range, whether the heartbeat is normal, and whether the verification is passed; when any validity condition is not met, the gate driver enters the fault latch state. S2.2: Determine the expected conduction state vector of the power switching device based on the target current or current trajectory, bus voltage, temperature, gate voltage, and device model parameters.

4. The short duration overload boundary enabled power converter gate drive protection method of claim 1, wherein, The local electrical quantities mentioned in step S3 include at least two of the following: on-state voltage drop or saturation voltage drop, device current, gate voltage, junction temperature or case temperature, bus voltage, complementary switch status, and desaturation detection status. The physical consistency residual is the weighted residual between the observation vector composed of the local electrical quantities and the expected vector composed of the expected conduction state.

5. The short duration overload boundary enabled power converter gate drive protection method of claim 1, wherein, In step S4, the cumulative energy budget or heat budget is updated as follows: in, This represents the cumulative energy budget or heat budget occupancy after the update in the kth sampling period. For recovery or attenuation coefficient; The sampling period; The value of the budget increment function. It is determined based on at least one of the following: conduction loss, residual power, I²t, junction temperature margin, safe operating area occupancy, or transient thermal resistance model; The upper limit of the budget criterion is determined by short-term overload boundary constraint information, device calibration data, or the derating strategy of the upper-level controller, and the short-term overload boundary constraint information is not used to clear, cover, or increase the accumulated budget occupancy of the gate driver.

6. The power converter gate drive protection method with short-time overload boundary enable according to claim 1, characterized in that, The specific method in step S5 is as follows: When the short-time overload boundary constraint information is valid, the physical consistency residual meets the preset threshold, the budget criterion does not exceed the limit, and the hardware fault protection signal is invalid, the gate driver enters the controlled overload state and selects the overload gate drive parameter group. When any one of the following conditions is met: the hardware fault protection signal is valid, the physical consistency residual does not meet the preset threshold, the budget criterion exceeds the limit, or the short-term overload boundary constraint information is invalid, the gate driver is prohibited from entering or exiting the controlled overload state; wherein, the hardware fault protection link that generates the hardware fault protection signal is independent of the short-term overload boundary constraint information and has priority over the selection of the overload gate drive parameter group, and the short-term overload boundary constraint information is not used to change the fault detection threshold, hardware blanking time, or fault latching logic of the hardware fault protection link.

7. The short duration overload boundary enabled power converter gate drive protection method of claim 6, wherein, The hardware fault protection signal in step S5 includes at least one of the following: desaturation detection signal, overcurrent comparison signal, short circuit detection signal, gate undervoltage signal, and gate overvoltage signal; the hardware fault protection signal directly covers the overload gate drive parameter group selection without going through the validity judgment path of the short-time overload boundary constraint information. The overload gate drive parameter set includes at least one parameter among the following: turn-on gate resistance, turn-off gate resistance, gate current, gate positive voltage, gate negative voltage, Miller clamping time, soft turn-off slope, diagnostic sampling window, and diagnostic reporting cycle. The gate driver selects the overload gate drive parameter set from the preset allowed drive parameter set only when the controlled overload state is established, and transitions to the normal drive parameter set according to the recovery parameter set after the controlled overload state ends.

8. A short time overload boundary enabled power converter gate drive protection system, characterized by, The power converter gate drive protection method for implementing short-time overload boundary enable as described in any one of claims 1-7 includes an upper-level controller, an isolation communication unit, a gate driver, a power switch unit, a detection unit, and a hard protection link. The upper-level controller is used to generate short-time overload boundary constraint information. The isolation communication unit is used to transmit the short-time overload boundary constraint information. The gate driver is used to verify the short-time overload boundary constraint information, acquire the local electrical quantities of the power switching device, calculate the physical consistency residual, update the budget criterion, and select the gate drive parameter group. The power switching unit is a SiC MOSFET, IGBT, GaN HEMT, or a power module composed of devices. The detection unit is used to provide local electrical quantities to the gate driver. The hardware fault protection link is used to generate a hardware fault protection signal in the event of short circuit, desaturation, gate undervoltage, or gate overvoltage.

9. The short duration overload boundary enabled power converter gate drive protection system of claim 8, wherein, The output of the hardware fault protection link is connected to the cover selector or drive disable terminal of the gate driver so that the fault shutdown parameter group takes precedence over the overload gate drive parameter group.

10. The short duration overload boundary enabled power converter gate drive protection system of claim 8, wherein, The gate driver includes an enable resolution module, a physical consistency determination module, a parameter group selection module, and a fault latch module. The enable parsing module is used to parse the enable window, enable object and budget; the consistency discrimination module is used to calculate the residual based on the locally sampled electrical quantity; the parameter group selection module is used to select the target gate drive parameter group when the controlled overload is established; and the fault latching module is used to overwrite the overload gate drive parameter group selection signal and make the gate output stage execute the fault shutdown parameter group when the hardware fault protection signal is valid.

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