Method of protecting ups device, controller, ups device and storage medium

Abstract

The embodiment of the application discloses a protection method of a UPS device. The protection method comprises the following steps: in response to the UPS device entering a battery operation mode, sending a first pulse width modulation signal to a first tilted pair tube and a second pulse width modulation signal to a second tilted pair tube; obtaining a target current flowing through a bridge inverter circuit; if the target current is greater than or equal to a preset current threshold, determining a clamping time point of a target tilted pair tube; the clamping time point is an end time point of a high level received by the target tilted pair tube; the target tilted pair tube is a tilted pair tube to which a high level is applied in the bridge inverter circuit; controlling the bridge inverter circuit to stop working at the clamping time point; and controlling the bridge inverter circuit to resume working after a preset time delay. The embodiment of the application controls the bridge inverter circuit to stop working at the clamping time point, can avoid the first tilted pair tube and the second tilted pair tube from bearing excessive current stress or voltage stress, further avoid damaging the first tilted pair tube and the second tilted pair tube, and improve the service life of the bridge inverter circuit.

Description

Technical Field

[0001] This application relates to the field of UPS equipment technology, and in particular to a protection method, controller, UPS equipment and storage medium for UPS equipment. Background Technology

[0002] UPS (Uninterruptible Power Supply) equipment can switch back to battery operation mode and continue to supply power to the load via batteries when mains power is lost. When a UPS experiences transformer saturation or a short circuit causing a large current, the technology typically immediately and forcibly shuts down the main circuit's switching transistors, cutting off the current loop. However, this forced shutdown of the switching transistors results in a relatively large voltage drop, and can easily damage them. Summary of the Invention

[0003] One objective of this application is to provide a protection method, controller, UPS device, and storage medium for UPS equipment, in order to solve the technical problem that switching transistors are easily damaged in related technologies.

[0004] In a first aspect, embodiments of this application provide a protection method for a UPS device. The UPS device includes a bridge inverter circuit, a controller, and a battery. The bridge inverter circuit is configured to invert the DC power output from the battery into AC power. The bridge inverter circuit includes a first inverter tube, a second inverter tube, a third inverter tube, and a fourth inverter tube. The first and third inverter tubes are connected in series and then electrically connected between a preset first parallel node and a preset second parallel node. The second and fourth inverter tubes are connected in series and then electrically connected between the first parallel node and the second parallel node. The controller is electrically connected to the first, second, third, and fourth inverter tubes respectively. The protection method includes: responding to the UPS device entering battery operation mode, sending a first pulse width modulation signal to the first inverter tube and sending a first pulse width modulation signal to the fourth inverter tube. The second slant-pair transistor sends a second pulse width modulation signal. The waveform of the first pulse width modulation signal is complementary to the waveform of the second pulse width modulation signal. The first inverter transistor and the fourth inverter transistor form one slant-pair transistor, and the second inverter transistor and the third inverter transistor form another slant-pair transistor. The first slant-pair transistor is one of the two slant-pair transistors, and the second slant-pair transistor is the other slant-pair transistor besides the first slant-pair transistor. The target current flowing through the bridge inverter circuit is obtained. If the target current is greater than or equal to a preset current threshold, the blocking time point of the target slant-pair transistor is determined. The blocking time point is the end time point of the high level received by the target slant-pair transistor. The target slant-pair transistor is the slant-pair transistor in the bridge inverter circuit that is subjected to a high level. At the blocking time point, the bridge inverter circuit is controlled to stop working and then resume working after a preset delay.

[0005] The embodiments of this application control the bridge inverter circuit to stop working at the time of wave blocking, which can avoid the first and second slant transistors from being subjected to excessive current stress or voltage stress, thereby avoiding damage to the first and second slant transistors and improving the service life of the bridge inverter circuit.

[0006] Optionally, the UPS equipment includes a first switching switch, a power factor correction circuit, a main inverter circuit, a second switching switch, and a DC-DC conversion circuit. One end of the first switching switch is electrically connected to the mains power grid, and the other end of the first switching switch is electrically connected to the power factor correction circuit. The main inverter circuit is electrically connected to the power factor correction circuit, and one end of the second switching switch is electrically connected to the power factor correction circuit. The controller is electrically connected to the first switching switch, the power factor correction circuit, the main inverter circuit, and the second switching switch, respectively.

[0007] The DC-DC conversion circuit includes a bridge inverter circuit, a resonant circuit, and a bridge rectifier circuit. The resonant circuit is electrically connected between the first parallel node and the second parallel node. One end of the bridge rectifier circuit is electrically connected to the resonant circuit, and the other end of the bridge rectifier circuit is electrically connected to the other end of the second switching switch. The controller is electrically connected to the bridge rectifier circuit.

[0008] Optionally, the UPS device includes a first timer and a second timer. The first timer is configured to generate a pulse width modulation (PWM) signal in a counting mode based on a preset first counting period value. The inverter transistors of the bridge inverter circuit are driven by the PWM signal, which includes high and low levels. The second timer is configured with a first counting threshold, a second counting threshold, and a second counting period value. The second counting threshold is greater than the first counting threshold, and the second counting period value is greater than the first counting period value. The second timer operates synchronously with the first timer. When a high level is applied to the first slant transistor, the count value of the second timer is less than the first counting threshold, or the count value of the second timer is greater than the second counting threshold and less than the second counting period value. When a high level is applied to the second slant transistor, the count value of the second timer is greater than the first counting threshold and less than the second counting threshold.

[0009] The embodiments of this application utilize the count value of the second timer to reliably and accurately determine the target oblique transistor, so that a shutdown operation can be performed on the target oblique transistor subsequently.

[0010] Optionally, if the target current begins to be greater than or equal to a preset current threshold, determining the blocking time point of the target slant tube includes: if the target current begins to be greater than or equal to the preset current threshold, determining the target time point, where the target time point is the time point when the target current begins to be greater than or equal to the preset current threshold, determining the slant tube that is applied a high level at the target time point as the target slant tube, and determining the end time point of the falling edge of the response to the high level as the blocking time point.

[0011] Optionally, determining the slant pair that is applied a high level at the target time point as the target slant pair includes: determining the target count value of the second timer at the target time point; determining the first slant pair as the target slant pair in response to the target count value being less than a first count threshold, or determining the second slant pair as the target slant pair in response to the target count value being greater than a second count threshold and less than a second count period value; and determining the second slant pair as the target slant pair in response to the target count value being greater than the first count threshold and less than the second count threshold.

[0012] In this embodiment, a counting monitoring range is set for "the first slant pair is applied a high level" and another counting monitoring range is set for "the second slant pair is applied a high level". By combining the count value of the second timer and the two counting monitoring ranges, the target slant pair can be reliably and accurately determined.

[0013] Optionally, determining the end time of the falling edge of the target high level as the sealing time point includes: determining the target count value of the second timer at the target time point, responding to the first slant transistor as the target slant transistor, calculating the first counting time from the target count value to the first counting threshold of the second timer, the falling edge of the target high level ending at the time point corresponding to the first counting threshold, and adding the target time point to the first counting time to obtain the sealing time point.

[0014] When the first slant-pair transistor is the target slant-pair transistor, even if the target time point falls in the middle of the high level and not at the end of the high level, the embodiments of this application can still use the count value of the second timer to monitor the first counting time from the target count value to the first counting threshold, and then use the first counting time and the target time point to reliably calculate the blocking time point, ensuring that the blocking time point of turning off the first slant-pair transistor is at the time point when the current is close to or equal to 0.

[0015] Optionally, determining the end time of the falling edge of the target high level as the sealing time point includes: determining the target count value of the second timer at the target time point, the second swashplate being the target switching transistor, calculating the second counting time from the target count value to the second counting threshold, the falling edge of the target high level ending at the time point corresponding to the second counting threshold, and adding the target time point to the second counting time to obtain the sealing time point.

[0016] When the second slant pair is the target slant pair, even if the target time point falls in the middle of the high level and not at the end of the high level, the embodiments of this application can still use the count value of the second timer to monitor the second counting time from the target count value to the second counting threshold, and then use the second counting time and the target time point to reliably calculate the blocking time point, ensuring that the blocking time point of turning off the second slant pair is at the time point when the current is close to or equal to 0.

[0017] Optionally, the control of the bridge inverter circuit to resume operation after a preset delay includes: adding the blocking time point to the preset time point to obtain the recovery time point; applying a low level for a first duration to the target slant transistor at the recovery time point, where the first duration is the period of the pulse width modulation signal minus the high level time; determining the start slant transistor, where the start slant transistor is the slant transistor in the bridge inverter circuit excluding the target slant transistor; and applying a high level for a second duration to the start slant transistor at the recovery time point, where the second duration is the period of the pulse width modulation signal minus the low level time.

[0018] In the recovery phase, this embodiment applies a low level for a first duration to the target slant transistor and a high level for a second duration to the start-up slant transistor, thereby avoiding the occurrence of unilateral excitation and preventing the large current caused by transformer saturation during the recovery phase from damaging the switching transistors of the bridge rectifier circuit and the inverter transistors of the bridge inverter circuit.

[0019] Optionally, determining the starting oblique pair includes: in response to the first oblique pair being the target oblique pair, determining the second oblique pair being the starting oblique pair, or in response to the second oblique pair being the target oblique pair, determining the first oblique pair being the starting oblique pair.

[0020] In a second aspect, embodiments of this application provide a controller, including a memory and a processor. The memory is connected to the processor, and the processor is used to execute one or more computer programs stored in the memory. When the processor executes one or more computer programs, it causes the controller to implement the protection method of the UPS device described above.

[0021] In a third aspect, embodiments of this application provide a UPS device, including a first switching switch, a power factor correction circuit, a main inverter circuit, a second switching switch, a DC-DC conversion circuit, a bridge inverter circuit, a battery, and the aforementioned controller. One end of the first switching switch is electrically connected to the mains power grid, and the other end of the first switching switch is electrically connected to the power factor correction circuit. The main inverter circuit is electrically connected to the power factor correction circuit, and one end of the second switching switch is electrically connected to the power factor correction circuit. The controller is electrically connected to the first switching switch, the power factor correction circuit, the main inverter circuit, and the second switching switch, respectively.

[0022] The DC-DC conversion circuit includes a bridge inverter circuit, a resonant circuit, and a bridge rectifier circuit. The bridge inverter circuit includes a first inverter tube, a second inverter tube, a third inverter tube, and a fourth inverter tube. The first and third inverter tubes are connected in series and then electrically connected between a preset first parallel node and a preset second parallel node. The second and fourth inverter tubes are connected in series and then electrically connected between the first and second parallel nodes. The controller is electrically connected to the first, second, third, and fourth inverter tubes respectively. The resonant circuit is electrically connected between the first and second parallel nodes. One end of the bridge rectifier circuit is electrically connected to the resonant circuit, and the other end of the bridge rectifier circuit is electrically connected to the other end of the second switching switch. The controller is also electrically connected to the bridge rectifier circuit.

[0023] In a fourth aspect, embodiments of this application provide a computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor, cause the processor to perform the aforementioned protection method for the UPS device. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the circuit structure of a UPS device provided in an embodiment of this application;

[0026] Figure 2 This is a schematic diagram of the specific circuit structure of a UPS device provided in an embodiment of this application;

[0027] Figure 3a A circuit structure diagram of a UPS device provided in another embodiment of this application;

[0028] Figure 3b The timing diagram shows all the switching transistors in the bridge inverter circuit under maximum current shutdown for related technologies.

[0029] Figure 4 A circuit structure diagram of a UPS device is provided for another embodiment of this application;

[0030] Figure 5 A timing diagram for generating pulse width modulation signals for the first and second slant transistors based on a first timer, provided for embodiments of this application;

[0031] Figure 6A first timing diagram for generating pulse width modulation signals for the first and second slant transistors based on a first timer and a second timer, provided for embodiments of this application;

[0032] Figure 7 A flowchart illustrating a protection method for a UPS device provided in an embodiment of this application;

[0033] Figure 8 A schematic diagram of a pulse width modulation signal provided in an embodiment of this application;

[0034] Figure 9 A second timing diagram provided for embodiments of this application, based on a first timer and a second timer, for generating pulse width modulation signals for a first slant-pair transistor and a second slant-pair transistor;

[0035] Figure 10 This is a schematic diagram of the structure of a protection device for a UPS device provided in an embodiment of this application;

[0036] Figure 11 This is a schematic diagram of the structure of a controller provided in an embodiment of this application. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0038] It should be noted that, unless there is a conflict, the various features in the embodiments of this application can be combined with each other, all of which are within the protection scope of this application. Furthermore, although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than the module division in the device or the order in the flowchart. Moreover, the terms "first," "second," and "third" used in this application do not limit the data or execution order, but only distinguish identical or similar items with essentially the same function and effect.

[0039] UPS equipment can switch to battery operation mode in the event of a loss of mains power, providing power to the load through the battery. When the UPS is required to output 1kW-3kW in battery operation mode, the voltage range of existing batteries is 24V-96V. The system bus voltage of UPS equipment is typically 360V or 380V. It is usually difficult to increase the battery output voltage to 360V or 380V using a single-stage boost circuit. Therefore, UPS equipment provided by related technologies requires a two-stage boost circuit to increase the battery output voltage to 360V or 380V.

[0040] The related technology provides a two-stage boost circuit including an LLC boost circuit and a boost circuit. This technology uses a closed-loop control method to control the LLC boost circuit and the boost circuit separately; however, the software control logic of the closed-loop control method for the above-mentioned two-stage boost circuit is relatively complex.

[0041] Furthermore, in an LLC boost converter circuit, K = Lm / Lr, where Lr is the resonant inductance and Lm is the magnetizing inductance. A larger K value results in a flatter gain characteristic curve for the LLC boost converter, making it impossible to adjust the gain through frequency modulation. To achieve frequency conversion voltage regulation in the LLC boost converter, K needs to be as small as possible, i.e., Lm should be as small as possible and Lr as large as possible. If Lm is small, the losses in the LLC boost converter circuit tend to increase, leading to an imbalance in both magnetizing current and current stress. To ensure Lr meets high-frequency requirements, a ferrite core needs to be used, which increases cost. Additionally, a larger Lr value increases the size of the resonant inductor.

[0042] Considering the aforementioned adverse factors, the relevant technologies selected open-loop control for the LLC boost circuit and closed-loop control for the boost circuit. The K value was set relatively large, and a fixed frequency and maximum gain were used to control the conduction angle of each switch in the LLC boost circuit to adjust the battery output voltage.

[0043] While these technologies reduce costs, losses, and the size of resonant inductors, they still present some challenges. When the transformer in the LLC boost circuit saturates, a short circuit occurs at the output, or the bus voltage of the UPS drops rapidly, the current in the LLC boost circuit becomes very high, easily triggering the hardware overcurrent protection function. To prevent the current from exceeding the current withstand values ​​of the individual switches in the LLC boost circuit, these technologies require immediate shutdown of the switches. However, the drain-source voltage of the switches is relatively high during shutdown, which can easily damage the switches.

[0044] The following embodiment of this application provides a UPS device. Please refer to [link / reference]. Figure 1The UPS device 100 includes a first switching switch 11, a power factor correction circuit 12, a main inverter circuit 13, a second switching switch 14, a DC-DC conversion circuit 15, a battery 16, and a controller 17.

[0045] One end of the first switching switch 11 is electrically connected to the mains power grid, and the other end is electrically connected to the power factor correction circuit 12. The first switching switch 11 is also electrically connected to the controller 17, and is controlled by the controller 17 to control the input of the mains power supply. When the UPS device 100 is in battery operation mode, if the mains power grid suddenly supplies power, before switching to mains operation mode, the controller 17 performs a phase-locked loop operation and controls the first switching switch 11 to be in the open state. At this time, the mains power supply cannot yet be applied to the UPS device. After the controller 17 completes the phase-locked loop operation, the controller 17 controls the first switching switch to be in the closed state, at which point the mains power supply can be applied to the UPS device.

[0046] The power factor correction circuit 12 is used to boost the voltage of the mains power supply. It is understood that the circuit structure of the power factor correction circuit 12 is relatively complex. For an example, please refer to [link to example circuit]. Figure 2 The power factor correction circuit 12 consists of a first inductor L1, a second inductor L2, a first switch Q1, a second switch Q2, and a first capacitor C1.

[0047] The main inverter circuit 13 is electrically connected to the power factor correction circuit 12, and is used to invert the power output from the power factor correction circuit 12. It is understood that the circuit structure of the main inverter circuit 13 is relatively complex. For an example, please refer to... Figure 2 The main inverter circuit 13 includes a third switch Q3, a fourth switch Q4, a fifth switch Q5, and a sixth switch Q6.

[0048] When the mains power supply is positive, the controller 17 controls the switching states of the second switch Q2, the fourth switch Q4, and the fifth switch Q5 respectively in boost mode to boost the voltage of the mains power supply. When the mains power supply is negative, the controller 17 controls the switching states of the first switch Q1, the third switch Q3, and the sixth switch Q6 respectively in boost mode to boost the voltage of the mains power supply.

[0049] One end of the second switching switch 14 is electrically connected to the power factor correction circuit 12, and the other end is electrically connected to the DC-DC conversion circuit 15. The second switching switch 14 is also electrically connected to the controller 17 and is used to control the current output of the battery under the control of the controller 17.

[0050] The DC-DC converter circuit 15 is electrically connected to the battery 16 and also to the controller 17. Under the control of the controller 17, the DC-DC converter circuit 15 boosts the voltage of the battery 16 and then applies it to the power factor correction circuit 12 through the second switching switch 14.

[0051] Please see Figure 3a The DC-DC conversion circuit 15 includes a bridge inverter circuit 151, a resonant circuit 152, and a bridge rectifier circuit 153. The bridge inverter circuit 151 inverts the DC power output from the battery 16 into AC power. The resonant circuit 152 resonates the power output from the bridge inverter circuit 151, outputting a sine wave power supply. The bridge rectifier circuit 153 rectifies the sine wave power supply, outputting DC power.

[0052] Please combine Figure 2 The bridge inverter circuit 151 includes a first inverter transistor Q7, a second inverter transistor Q8, a third inverter transistor Q9, and a fourth inverter transistor Q10. The first inverter transistor Q7 and the third inverter transistor Q9 are connected in series and then electrically connected between a preset first parallel node and a preset second parallel node. The second inverter transistor Q8 and the fourth inverter transistor Q10 are connected in series and then electrically connected between the first parallel node and the second parallel node. The controller 17 is electrically connected to the first inverter transistor Q7, the second inverter transistor Q8, the third inverter transistor Q9, and the fourth inverter transistor Q10. The first inverter transistor Q7 and the fourth inverter transistor Q10 form one skew pair, and the second inverter transistor Q8 and the third inverter transistor Q9 form another skew pair. The first skew pair is one of the two skew pairs, and the second skew pair is the other skew pair excluding the first skew pair.

[0053] The controller 17 controls the switching states of the first inverter tube Q7, the second inverter tube Q8, the third inverter tube Q9 and the fourth inverter tube Q10 respectively according to the inverter mode, so as to convert the DC power supply of the battery 16 into AC pulses.

[0054] Please combine Figure 2 The resonant circuit 152 is electrically connected between the first parallel node and the second parallel node. The resonant circuit 152 includes a resonant coil S1, a second capacitor C2, a resonant inductor L3, and a magnetizing inductor (not shown). The resonant coil S1, the second capacitor C2, the resonant inductor L3, and the magnetizing inductor work together to resonate the AC pulse and output a sinusoidal power supply.

[0055] Please combine Figure 2One end of the bridge rectifier circuit 153 is electrically connected to the resonant circuit 152, and the other end of the bridge rectifier circuit 153 is electrically connected to the other end of the second switching switch 14. The bridge rectifier circuit 153 includes a first rectifier tube Q11, a second rectifier tube Q12, a third rectifier tube Q13, and a fourth rectifier tube Q14. The controller 17 controls the switching states of the first rectifier tube Q11, the second rectifier tube Q12, the third rectifier tube Q13, and the fourth rectifier tube Q14 according to the rectification mode, so as to rectify the sine wave power supply into DC power supply.

[0056] Please see Figure 3b In related technologies, the time point when a large current appears is tk. At time point tk, all the switches of the bridge inverter circuit 151 are turned off. However, the current of the sinusoidal power supply output by the resonant circuit 152 is the maximum current at time point tk. At this time, the switches of the resonant circuit 152 and the bridge rectifier circuit 153 are subjected to a large drain-source voltage Vds, which can easily lead to damage to the switches.

[0057] In this embodiment, all the switches of the bridge inverter circuit 151 are turned off when the current output of the resonant circuit 152 is 0. This avoids the switches of the resonant circuit 152 and the bridge rectifier circuit 153 from being subjected to a large drain-source voltage Vds, thus making it less likely to damage the switches.

[0058] In this embodiment, the first inverter diode Q7 and the fourth inverter diode Q10 are defined as a first skew pair, and the second inverter diode Q8 and the third inverter diode Q9 are defined as a second skew pair. The first skew pair and the second skew pair operate in a complementary manner.

[0059] In some embodiments, please refer to Figure 4 The UPS device 100 also includes a first timer 18, a second timer 19, and a third timer 110. It is understood that in some embodiments, the first timer 18, the second timer 19, and the third timer 110 can be integrated on the controller 17, while in some embodiments, the first timer 18, the second timer 19, and the third timer 110 are separate timing modules.

[0060] The first timer 18 is used to generate a pulse width modulation (PWM) signal in a counting mode based on a preset first counting period value. The first timer 18 is configured with at least a first signal output channel and a second signal output channel. Please refer to... Figure 2 The first signal output channel is connected to the first oblique tube, and the second signal output channel is connected to the second oblique tube.

[0061] Please see Figure 5 The first timer 18 starts counting from zero.

[0062] ① When the count value of the first timer 18 is less than or equal to the first counting threshold "0.5ARR", the first timer 18 outputs a high level through the first signal output channel and a low level through the second signal output channel. The first counting threshold is less than the first counting cycle value.

[0063] ②. When the count value of the first timer 18 is greater than the first count threshold "0.5ARR" but less than the first count period value "1ARR", the first timer 18 outputs a low level through the first signal output channel and a high level through the second signal output channel.

[0064] When the count value of the first timer 18 is equal to the first count cycle value "1ARR", the first timer performs a decrement operation based on the current count value.

[0065] ③. When the count value of the first timer 18 is greater than the first count threshold "0.5ARR" but less than the first count period value "1ARR", the first timer 18 outputs a low level through the first signal output channel and a high level through the second signal output channel.

[0066] ④. When the count value of the first timer 18 is less than the first count threshold "0.5ARR" but greater than 0, the first timer 18 outputs a high level through the first signal output channel and a low level through the second signal output channel.

[0067] Through processes ① to ④, within one pulse width signal cycle, the first signal output channel outputs a first pulse width modulation signal, and the second signal output channel outputs a second pulse width modulation signal, wherein the first pulse width modulation signal and the second pulse width modulation signal are complementary.

[0068] The switching transistors of the bridge inverter circuit 151 are driven by a pulse width modulation signal, which includes a high level and a low level. When a high level is applied to the slant transistor, the slant transistor enters the conducting state. When a low level is applied to the slant transistor, the slant transistor enters the turning state.

[0069] The second timer 19 operates synchronously with the first timer 18; that is, when the first timer 18 starts counting, the second timer 19 also starts counting. When the count value of the first timer 18 reaches zero, the count value of the second timer also reaches zero.

[0070] The second timer 19 is configured with a first counting threshold, a second counting threshold, and a second counting cycle value. The second counting threshold is greater than the first counting threshold, and the second counting cycle value is greater than the first counting cycle value.

[0071] When the count value of the second timer 19 reaches the second counting cycle value, the count value of the second timer 19 is reset to zero, that is, the count value of the second timer 19 is set to 0.

[0072] As mentioned above, since the second timer 19 operates synchronously with the first timer 18, and the second counting cycle value is greater than the first counting cycle value, the synchronization process between the second timer 19 and the first timer 18 is as follows:

[0073] Please see Figure 6 The first timer 18 and the second timer 19 start counting synchronously from zero.

[0074] ⑤. When the count value of the first timer 18 is less than or equal to the first counting threshold "0.5ARR", the count value of the second timer 19 will also be less than or equal to the first counting threshold "0.5ARR". The first timer 18 outputs a high level through the first signal output channel and a low level through the second signal output channel.

[0075] ⑥. When the count value of the first timer 18 is greater than the first count threshold "0.5ARR" but less than the first count period value "1ARR", the count value of the second timer 19 will also be greater than the first count threshold "0.5ARR" but less than the first count period value "1ARR". The first timer 18 outputs a low level through the first signal output channel and outputs a high level through the second signal output channel.

[0076] When the count value of the first timer 18 is equal to the first counting cycle value "1ARR", the first timer decrements by one based on the current count value. However, since the second counting cycle value "2ARR" is greater than the first counting cycle value "1ARR", the second timer 19 continues to increment by one based on the first counting cycle value "1ARR".

[0077] ⑦. When the count value of the first timer 18 is greater than the first count threshold "0.5ARR" but less than the first count period value "1ARR", the count value of the second timer 19 continues to increase from the first count period value "1ARR" to the second count threshold "1.5ARR". At this time, the first timer 18 outputs a low level through the first signal output channel and outputs a high level through the second signal output channel.

[0078] ⑧. When the count value of the first timer 18 is less than the first counting threshold "0.5ARR" but greater than 0, the count value of the second timer 19 continues to increase from the second counting threshold "1.5ARR" to the second counting cycle value "2ARR". At this time, the first timer 18 outputs a high level through the first signal output channel and outputs a low level through the second signal output channel.

[0079] After the count value of the second timer 19 reaches the second count cycle value "2ARR", it starts to return to zero, that is, the count value of the second timer 19 is set to 0.

[0080] From processes ⑤ to ⑧, it can be seen that when a high level is applied to the first slant-pair transistor, the count value of the second timer is less than the first counting threshold, or the count value of the second timer is greater than the second counting threshold and less than the second counting period value. When a high level is applied to the second slant-pair transistor, the count value of the second timer is greater than the first counting threshold and less than the second counting threshold.

[0081] In some embodiments, the first counting threshold is n1 times the value of the first counting cycle, where n1 is greater than 0 but less than 1. For example, n1 is 0.5.

[0082] In some embodiments, the second counting threshold is n² times the value of the first counting cycle, where n² is greater than 1. For example, n² is 1.5.

[0083] In some embodiments, the second counting period value is n3 times the first counting period value, where n3 is greater than n2. For example, n3 is 2.

[0084] It is understandable that when n1 = 0.5, n2 = 1.5, and n3 = 2, the turn-on time and turn-off time of the first and second slant pairs of transistors in the bridge inverter circuit 151 are the same, and the current stress time they are subjected to is the same. This can balance the current stress and help improve the service life of the switching transistors.

[0085] The third timer 110 is used to delay for a preset duration after the first and second slant transistors are turned off. When the controller 17 detects excessive current in the UPS equipment, the controller 17 controls the first timer 18 to stop outputting pulse width modulation signals to the first and second slant transistors, and both the first and second slant transistors enter the off state. After both the first and second slant transistors are in the off state, the controller 17 controls the third timer 110 to start counting. When the count value of the third timer 110 equals the preset duration, the controller 17 controls the first timer 18 to turn on the corresponding slant transistor according to the preset recovery strategy.

[0086] The following embodiments of this application provide a protection method for a UPS device, which is the UPS device described in the above embodiments. Please refer to... Figure 7 The protection method includes steps S71 to S75.

[0087] In the embodiment of this application, step S71 is executed, in response to the UPS device entering battery operation mode, a first pulse width modulation signal is sent to the first oblique pair and a second pulse width modulation signal is sent to the second oblique pair.

[0088] The operating mode refers to the mode in which the UPS device provides power to the load. Operating modes include battery operating mode and AC power operating mode. Battery operating mode is when the UPS device controls the battery to provide power to the load, while AC power operating mode is when the UPS device processes AC power and then provides it to the load. This application embodiment parses the mode marking information to determine the target operating mode of the UPS device. If the mode marking information indicates that the UPS device is operating in battery operating mode, then the target operating mode is battery operating mode. If the mode marking information indicates that the UPS device is operating in AC power operating mode, then the target operating mode is AC power operating mode.

[0089] The waveforms of the first pulse width modulation (PWM) signal and the second pulse width modulation (PWM) signal are complementary. At any given time, one of the PWM signals is at a high level, and the other is at a low level. For example, the first PWM signal is at a high level at time t0, and the second PWM signal is at a low level at time t0.

[0090] The period of the first pulse width modulation signal is the same as the period of the second pulse width modulation signal. Furthermore, when the duty cycle of the first pulse width modulation signal is M and the period is T, the duty cycle of the first pulse width modulation signal is TM. For example, the duty cycle of the first pulse width modulation signal is 60%, and the duty cycle of the second pulse width modulation signal is 40%.

[0091] When the UPS equipment enters battery operation mode, the controller controls the first timer to send the first pulse width modulation signal to the first diagonal transistor and the second pulse width modulation signal to the second diagonal transistor according to the preset inverter mode. For details, please refer to processes ① to ④, which will not be elaborated here.

[0092] In this embodiment of the application, step S72 is performed to obtain the target current flowing through the bridge inverter circuit.

[0093] This application embodiment includes a current sampling circuit that can detect the current flowing through the bridge inverter circuit to obtain the target current. The current sampling circuit includes a sampling resistor or a Hall sensor, etc.

[0094] In the implementation step S73 of this application embodiment, if the target current begins to be greater than or equal to a preset current threshold, the sealing time point of the target oblique tube is determined.

[0095] The target slant pair is the slant pair in the bridge inverter circuit that is applied a high level. Specifically: when the first slant pair is applied a high level, the second slant pair is applied a low level, and the target current begins to exceed or equal a preset current threshold, then the first slant pair is the target slant pair. When the first slant pair is applied a low level, the second slant pair is applied a high level, and the target current begins to exceed or equal a preset current threshold, then the second slant pair is the target slant pair.

[0096] The blocking time point is the end time of the high level received by the target oblique tube. Please refer to [link / reference]. Figure 8 The first slant tube is given a high level 81. The falling edge 82 of the high level 81 ends at time point tp. Therefore, time point tp is the end time of the high level, that is, time point tp is the sealing time point.

[0097] The blocking time point is used to instruct the controller to turn off the target skew transistor using the first timer. The preset current threshold is customized by the designer based on engineering experience and will not be elaborated here.

[0098] In this embodiment of the application, step S74 is executed to control the bridge inverter circuit to stop working at the time of wave blocking.

[0099] At the time of wave blocking, the controller controls the first timer to stop sending the first pulse width modulation signal to the first slant pair transistor, and at the same time stops sending the second pulse width modulation signal to the second slant pair transistor.

[0100] The output current of the bridge inverter circuit at the time of the wave blocking is equal to or close to 0, and the drain-source voltage Vds of the first and second slant transistors is equal to or close to 0. Therefore, the embodiment of this application controls the bridge inverter circuit to stop working at the time of the wave blocking, which can avoid the first and second slant transistors from being subjected to excessive current stress or voltage stress, thereby avoiding damage to the first and second slant transistors and improving the service life of the bridge inverter circuit.

[0101] In this embodiment of the application, step S75 is executed, controlling the bridge inverter circuit to resume operation after a preset delay.

[0102] When an overcurrent occurs in the UPS device while it is in battery operation mode, this embodiment controls the bridge inverter circuit to delay for a preset time to wait for the overcurrent to disappear. After the overcurrent disappears, the UPS device requires the battery to be in a ready-to-use state. This embodiment then controls the bridge inverter circuit to resume operation so that the battery can effectively provide power to the load uninterruptedly.

[0103] It is understood that the embodiments of this application can determine the blocking time point of the target oblique tube in a variety of ways. In some embodiments, if the target current begins to be greater than or equal to a preset current threshold, determining the blocking time point of the target oblique tube includes steps S741 to S743.

[0104] Step S741: If the target current starts to be greater than or equal to the preset current threshold, determine the target time point.

[0105] The target time point is the time point when the target current begins to be greater than or equal to the preset current threshold. When the controller detects that the target current begins to be greater than or equal to the preset current threshold, the controller records the time point corresponding to the current count value of the first timer and uses the time point corresponding to the current count value as the target time point.

[0106] Please combine Figure 6 The target current begins to be greater than or equal to the preset current threshold at time point tk. Therefore, in this embodiment of the application, time point tk is taken as the target time point.

[0107] Step S742: Determine the target slant transistor that is applied a high level at the target time point.

[0108] In some embodiments, the controller determines the signal output channel of the first timer outputting a high level at a target time point. When the signal output channel outputting a high level is the first signal output channel, a high level is applied to the first slant-pair transistor, which is the target slant-pair transistor. When the signal output channel outputting a high level is the second signal output channel, a high level is applied to the second slant-pair transistor, which is the target slant-pair transistor.

[0109] In other embodiments, determining the target slant transistor that is applied a high level at a target time point includes the following steps: determining the target count value of a second timer at the target time point, and determining the target slant transistor based on the target count value, a first count threshold, and a second count threshold. Embodiments of this application utilize the count value of the second timer to reliably and accurately determine the target slant transistor, so that a subsequent shutdown operation can be performed on the target slant transistor.

[0110] Determining the target count value of the second timer at the target time point includes the following steps: responding to the target current starting to be greater than or equal to a preset current threshold, and recording the count value of the second timer at the target time point as the target count value.

[0111] Determining the target slant transistor based on the target count value, a first count threshold, and a second count threshold includes the following steps: If the target count value is less than the first count threshold, or if the target count value is greater than the second count threshold and less than the second count period value, the first slant transistor is determined to be the target slant transistor; if the target count value is greater than the first count threshold and less than the second count threshold, the second slant transistor is determined to be the target slant transistor. In this embodiment, a counting monitoring range is set for "the first slant transistor being applied a high level," and another counting monitoring range is set for "the second slant transistor being applied a high level." By combining the count value of the second timer and the two counting monitoring ranges, the target slant transistor can be reliably and accurately determined.

[0112] Please combine Figure 6, when Nw < 0.5ARR, or 1.5ARR < Nw < 2ARR, the first timer outputs a high level through the first signal output channel and a low level through the second signal output channel, that is: the first diagonal pair of transistors receives a high level, and the second diagonal pair of transistors receives a low level. Therefore, the first diagonal pair of transistors is the target diagonal pair of transistors. Nw is the target count value.

[0113] When 0.5ARR < Nw < 1.5ARR, the first timer outputs a low level through the first signal output channel and a high level through the second signal output channel, that is: the first diagonal pair of transistors receives a low level, and the second diagonal pair of transistors receives a high level. Therefore, the second diagonal pair of transistors is the target diagonal pair of transistors.

[0114] Step S743: In response to the end of the falling edge of the high level, determine the end time point of the falling edge as the wave-cutting time point.

[0115] As described above, when the falling edge of the high level ends, the output current of the bridge inverter circuit is equal to or close to 0, and the drain-source voltage Vds of the first diagonal pair of transistors and the second diagonal pair of transistors is equal to or close to 0. Therefore, the embodiment of the present application determines the end time point of the falling edge as the wave-cutting time point. Please combine Figure 6 , the falling edge of the high level ends at the time point tp, and the embodiment of the present application uses the time point tp as the wave-cutting time point.

[0116] In some embodiments, in response to the end of the falling edge of the target high level, determining the end time point of the falling edge as the wave-cutting time point includes the following steps: determining the target count value of the second timer at the target time point, in response to the first diagonal pair of transistors being the target diagonal pair of transistors, calculating the first counting time for the count value of the second timer to reach the first counting threshold from the target count value, the falling edge of the target high level ends at the time point corresponding to the first counting threshold, and adding the target time point and the first counting time to obtain the wave-cutting time point.

[0117] When the first diagonal pair of transistors is the target diagonal pair of transistors, even if the target time point falls in the middle of the high level instead of the end time point of the high level, the embodiment of the present application can still use the count value of the second timer to monitor the first counting time for the count value of the second timer to reach the first counting threshold from the target count value, and then reliably calculate the wave-cutting time point using the first counting time and the target time point, ensuring that the wave-cutting time point for turning off the first diagonal pair of transistors is at the time point when the current is close to or equal to 0.

[0118] Please combine Figure 6When the first slant-pair transistor is the target slant-pair transistor, the high-level end time of the first slant-pair transistor occurs at the time point when the count value of the second timer is the first count threshold. Therefore, whenever the count value of the second timer is the first count threshold, if the first slant-pair transistor is the target slant-pair transistor, the high-level end of the first slant-pair transistor has just ended. When the target count value is not equal to the first count threshold, and the first slant-pair transistor is the target slant-pair transistor, it indicates that the time point when the target current begins to be greater than or equal to the preset current threshold is not the end time point of the high-level. In order to turn off the first slant-pair transistor when the output current of the bridge inverter circuit is equal to or close to 0, and the drain-source voltage Vds of the first and second slant-pair transistors is equal to or close to 0, this embodiment of the application needs to wait for the count value of the second timer to go from the target count value to the first count threshold.

[0119] Since the clock period of the second timer, the first counting threshold, and the target counting value are all known, the embodiments of this application can calculate the first counting time from the target counting value to the first counting threshold of the second timer, and add the target time point to the first counting time to obtain the wave blocking time point.

[0120] In other embodiments, determining the end time of the falling edge of the target high level as the sealing time point includes the following steps: determining the target count value of the second timer at the target time point, the second swashplate is the target switch, calculating the second counting time from the target count value to the second counting threshold, the falling edge of the target high level ends at the time point corresponding to the second counting threshold, and adding the target time point to the second counting time to obtain the sealing time point.

[0121] When the second slant pair is the target slant pair, even if the target time point falls in the middle of the high level and not at the end of the high level, the embodiments of this application can still use the count value of the second timer to monitor the second counting time from the target count value to the second counting threshold, and then use the second counting time and the target time point to reliably calculate the blocking time point, ensuring that the blocking time point of turning off the second slant pair is at the time point when the current is close to or equal to 0.

[0122] Please see Figure 9When the second slant-pair transistor is the target slant-pair transistor, the high-level signal of the second slant-pair transistor ends when the count value of the second timer reaches the second counting threshold. Therefore, whenever the count value of the second timer reaches the second counting threshold, if the second slant-pair transistor is the target slant-pair transistor, the high-level signal of the second slant-pair transistor has just ended. When the target count value is not equal to the second counting threshold, and the second slant-pair transistor is the target slant-pair transistor, it indicates that the time point when the target current begins to be greater than or equal to the preset current threshold is not the end time point of the high-level signal. In order to turn off the second slant-pair transistor when the output current of the bridge inverter circuit is equal to or close to 0, and the drain-source voltage Vds of the first and second slant-pair transistors is equal to or close to 0, this embodiment of the application needs to wait for the count value of the second timer to rise from the target count value to the second counting threshold.

[0123] Since the clock period of the second timer, the second counting threshold, and the target counting value are all known, the embodiments of this application can calculate the second counting time from the target counting value to the second counting threshold, and add the target time point to the second counting time to obtain the wave blocking time point.

[0124] When the sealing time point of the first or second oblique pair of transistors is obtained, this embodiment controls both the first and second oblique pairs of transistors to stop working for a preset time at the sealing time point. As mentioned above, the UPS equipment requires the battery to be in a standby state at all times. After the preset time, this embodiment controls the bridge inverter circuit to resume operation.

[0125] A DC-DC converter circuit includes a transformer. Under ideal operating conditions, an AC voltage is applied to the primary winding, and the magnetic flux in the core changes sinusoidally. Energy is transferred between the primary and secondary windings according to the law of electromagnetic induction. Taking a forward DC-DC converter circuit as an example, when the switching transistor is turned on, current flows through the primary winding, and the magnetic flux in the core begins to increase; when the switching transistor is turned off, the magnetic flux is reset to its initial state through the reset winding or other means.

[0126] Since a high level has been applied to the target slant tube when the target current exceeds the preset current threshold, the transformer is already energized. If a high level is still applied to the target slant tube during the recovery phase, one-sided energization is likely to occur. This means that the magnetic core continuously accumulates magnetic flux in only one direction, leading to transformer saturation.

[0127] When a transformer saturates, its inductance decreases. According to the formula for inductor current change, with the voltage across the inductor remaining constant, the decrease in inductance will cause the current to rise faster. This sharp increase in primary current will be reflected in the secondary side (i.e., the bridge rectifier circuit) through the transformer's turns ratio, leading to a significant increase in low-voltage current as well. This can easily damage the switching transistors of the bridge rectifier circuit and the inverter transistors of the bridge inverter circuit.

[0128] To avoid the aforementioned problems after the bridge inverter circuit resumes operation, in some embodiments, controlling the bridge inverter circuit to resume operation after a preset delay includes steps S751 to S754.

[0129] Step S751: Add the sealing time point to the preset duration to obtain the recovery time point.

[0130] The recovery time point is the time point at which the control bridge inverter circuit resumes operation. The preset duration is customized by the designer based on engineering experience. In some embodiments, the preset duration is m times the pulse width modulation period, where m is any value between [3, 10] and m is a positive integer.

[0131] Step S752: At the recovery time point, apply a low level for a first duration to the target oblique transistor. The first duration is the period of the pulse width modulation signal minus the high level time.

[0132] During the blocking phase, this embodiment applies a high level to the target oblique transistor. During the recovery phase, to avoid one-sided excitation, this embodiment applies a low level for a first duration to the target oblique transistor at the recovery time point, thus avoiding the one-sided excitation phenomenon that is easily caused by continuing to apply a high level to the target oblique transistor during the recovery phase.

[0133] Step S753: Determine the starting oblique tube.

[0134] The starting slant pair is the slant pair in the bridge inverter circuit excluding the target slant pair. If the first slant pair is the target slant pair, then in this embodiment, the second slant pair is determined to be the starting slant pair. If the second slant pair is the target slant pair, then in this embodiment, the first slant pair is determined to be the starting slant pair.

[0135] Step S754: At the recovery time point, apply a high level of a second duration to the start-up slant transistor. The second duration is the period of the pulse width modulation signal minus the time of the low level.

[0136] During the recovery phase, in order to avoid the phenomenon of one-sided excitation, the embodiments of this application apply a high level of a second duration to the start-up slant transistor at the recovery time point. In this way, the magnetic flux can be completely reset to the initial state by the start-up slant transistor, thus avoiding the phenomenon of one-sided excitation.

[0137] During the recovery phase, this embodiment updates the first counting threshold of the second timer to the first counting period value, updates the second counting threshold of the second timer to the second counting period value, and controls the second timer to work synchronously with the first timer.

[0138] For example, please combine Figure 6 The first slant pair (i.e., the first inverter Q7 and the fourth inverter Q10) is the target slant pair, and the second slant pair (i.e., the second inverter Q8 and the third inverter Q9) is the start-up slant pair. In this embodiment, time point tp is determined as the blocking time point, and at time point tp, the first inverter Q7 to the fourth inverter Q10 are turned off.

[0139] After a 5µs delay, this embodiment of the application determines time point tq as the recovery time point. At time point tq, a low level is applied to the first slant pair transistor and a high level is applied to the second slant pair transistor, so that the high level of the first slant pair transistor combined with the high level of time point tp and the low level of time point tq form a pulse width modulation signal, and at the same time, the low level of the second slant pair transistor combined with the low level of time point tp and the high level of time point tq form a pulse width modulation signal.

[0140] For another example, please combine Figure 9 The first slant pair (i.e., the first inverter Q7 and the fourth inverter Q10) is the start-up slant pair, and the second slant pair (i.e., the second inverter Q8 and the third inverter Q9) is the target slant pair. In this embodiment, the time point tr is determined as the wave blocking time point, and the first inverter Q7 to the fourth inverter Q10 are turned off at the time point tr.

[0141] After a 5µs delay, this embodiment of the application determines time point ts as the recovery time point. At time point ts, a high level is applied to the first slant pair transistor and a low level is applied to the second slant pair transistor, so that the low level of the first slant pair transistor combined with the low level of time point tr and the high level of time point ts form a pulse width modulation signal, and at the same time, the high level of the second slant pair transistor combined with the high level of time point tr and the low level of time point ts form a pulse width modulation signal.

[0142] In general, the embodiments of this application, during the recovery phase, apply a low level for a first duration to the target slant transistor and a high level for a second duration to the start-up slant transistor, thereby avoiding the occurrence of unilateral excitation, and thus avoiding the large current damage to the switching transistors of the bridge rectifier circuit and the inverter transistors of the bridge inverter circuit caused by transformer saturation during the recovery phase.

[0143] It should be noted that in the above embodiments, there is no necessarily a certain order between the steps. Those skilled in the art can understand from the description of the embodiments of this application that the above steps may have different execution orders in different embodiments, that is, they may be executed in parallel or in turn, etc.

[0144] As another aspect of the embodiments of this application, this application provides a protection device for a UPS device. The protection device for the UPS device can be a software module, which includes several instructions stored in a memory. A processor can access the memory, call the instructions, and execute them to complete the UPS device protection method described in the various embodiments above.

[0145] In some implementations, the protection device of a UPS can also be constructed from hardware components. For example, the protection device of a UPS can be constructed from one or more chips, which can work in coordination to complete the protection method of the UPS described in the various implementations above. As another example, the protection device of a UPS can also be constructed from various logic devices, such as general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), microcontrollers, ARM (Acorn RISC Machine) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination of these components.

[0146] Please see Figure 10 The protection device 101 of the UPS equipment includes an inverter control module 102, a current detection module 103, a wave blocking determination module 104, a working control module 105, and a working recovery module 106.

[0147] The inverter control module 102 is used to respond to the UPS equipment entering battery operation mode by sending a first pulse width modulation signal to the first slant-pair transistor and a second pulse width modulation signal to the second slant-pair transistor. The waveforms of the first and second pulse width modulation signals are complementary. The current detection module 103 is used to acquire the target current flowing through the bridge inverter circuit. The blocking determination module 104 is used to determine the blocking time point of the target slant-pair transistor if the target current starts to be greater than or equal to a preset current threshold. The blocking time point is the end time point of the high level received by the target slant-pair transistor. The target slant-pair transistor is the slant-pair transistor in the bridge inverter circuit that is subjected to a high level. The operation control module 105 is used to control the bridge inverter circuit to stop working at the blocking time point. The operation recovery module 106 is used to control the bridge inverter circuit to resume operation after a preset delay.

[0148] The UPS equipment includes a first timer and a second timer. The first timer is configured to generate a pulse width modulation signal in a counting mode based on a preset first counting cycle value. The inverter tubes of the bridge inverter circuit are driven by the pulse width modulation signal, which includes high level and low level.

[0149] The second timer is configured with a first counting threshold, a second counting threshold, and a second counting period value. The second counting threshold is greater than the first counting threshold, and the second counting period value is greater than the first counting period value. The second timer works synchronously with the first timer.

[0150] When the first slant transistor is applied a high level, the count value of the second timer is less than the first counting threshold, or the count value of the second timer is greater than the second counting threshold and less than the second counting period value.

[0151] When the second slant transistor is applied a high level, the count value of the second timer is greater than the first counting threshold and less than the second counting threshold.

[0152] In some embodiments, the blocking determination module 104 is specifically used to: if the target current starts to be greater than or equal to a preset current threshold, determine a target time point, the target time point being the time point when the target current starts to be greater than or equal to the preset current threshold, determine the slant transistor that is applied a high level at the target time point as the target slant transistor, and determine the end time point of the falling edge of the response to the high level as the blocking time point.

[0153] In some embodiments, the blocking determination module 104 is specifically used to: determine the target count value of the second timer at the target time point, respond to the target count value being less than the first count threshold, or, respond to the target count value being greater than the second count threshold and less than the second count period value, determine the first oblique tube as the target oblique tube, and respond to the target count value being greater than the first count threshold and less than the second count threshold, determine the second oblique tube as the target oblique tube.

[0154] In some embodiments, the blocking determination module 104 is specifically used to: determine the target count value of the second timer at the target time point, respond to the first slant tube as the target slant tube, calculate the first counting time from the target count value to the first counting threshold, the falling edge of the target high level ends at the time point corresponding to the first counting threshold, and add the target time point to the first counting time to obtain the blocking time point.

[0155] In some embodiments, the blocking determination module 104 is specifically used to: determine the target count value of the second timer at the target time point, respond to the second slant transistor as the target switching transistor, calculate the second counting time from the target count value to the second counting threshold, the falling edge of the target high level ends at the time point corresponding to the second counting threshold, and add the target time point and the second counting time to obtain the blocking time point.

[0156] In some embodiments, the working recovery module 106 is specifically used to: add the blocking time point to a preset duration to obtain a recovery time point; apply a low level for a first duration to the target slant pair at the recovery time point, the first duration being the period of the pulse width modulation signal minus the high level time; determine the start slant pair, the start slant pair being the slant pair in the bridge inverter circuit excluding the target slant pair; and apply a high level for a second duration to the start slant pair at the recovery time point, the second duration being the period of the pulse width modulation signal minus the low level time.

[0157] In some embodiments, the work recovery module 106 is specifically configured to: determine the second oblique tube as the starting oblique tube in response to the first oblique tube being the target oblique tube, or determine the first oblique tube as the starting oblique tube in response to the second oblique tube being the target oblique tube.

[0158] It should be noted that the protection device for the UPS equipment described above can execute the protection method for the UPS equipment provided in the embodiments of this application, and has the corresponding functional modules and beneficial effects for executing the method. Technical details not described in detail in the embodiments of the protection device for the UPS equipment can be found in the protection method for the UPS equipment provided in the embodiments of this application.

[0159] See Figure 11 , Figure 11 This is a schematic diagram of a controller provided in an embodiment of this application. The controller 110 includes one or more processors 111 and a memory 112. The memory 112 is connected to one or more processors 111, for example, via a bus.

[0160] Processor 111 is configured to support the controller in performing the corresponding functions in the methods described in the above method embodiments. Processor 111 may be a central processing unit (CPU), a network processor (NP), a hardware chip, or any combination thereof. The aforementioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The aforementioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0161] Memory 112 is used to store program code, etc. Memory 112 may include volatile memory (VM), such as random access memory (RAM); memory may also include non-volatile memory (NVM), such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid-state drive (SSD); memory may also include combinations of the above types of memory.

[0162] The memory 112 can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the UPS device protection method in the embodiments of this application. The processor executes the various functional applications and data processing of the UPS device protection method and the UPS device protection device by running the non-volatile software programs, instructions, and modules stored in the memory, that is, it realizes the functions of the various modules or units of the UPS device protection method and the UPS device protection device provided in the above method embodiments.

[0163] The memory 112 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and applications required for at least one function. The data storage area may store data created based on the use of the protection devices of the UPS equipment. In some embodiments, the memory may optionally include memory remotely configured relative to the processor, which can be connected to the protection devices of the UPS equipment via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0164] The one or more modules are stored in the memory. When executed by the one or more processors, they perform the protection method of the UPS device in any of the above method embodiments. For example, they perform the method steps described in the above method embodiments to realize the functions of the modules described in the above device embodiments.

[0165] This application also provides a computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a controller, cause the computer to perform the method described in the foregoing embodiments.

[0166] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0167] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Therefore, any equivalent variations made in accordance with the claims of this application shall still fall within the scope of this application.

Claims

1. A method of protecting an UPS device, characterized by, The UPS equipment includes a bridge inverter circuit, a controller, and a battery. The bridge inverter circuit is configured to invert the DC power output from the battery into AC power. The bridge inverter circuit includes a first inverter tube, a second inverter tube, a third inverter tube, and a fourth inverter tube. The first inverter tube and the third inverter tube are connected in series and then electrically connected between a preset first parallel node and a preset second parallel node. The second inverter tube and the fourth inverter tube are connected in series and then electrically connected between the first parallel node and the second parallel node. The controller is electrically connected to the first inverter tube, the second inverter tube, the third inverter tube, and the fourth inverter tube respectively. The protection method includes: In response to the UPS device entering battery operation mode, a first pulse width modulation signal is sent to the first slant pair and a second pulse width modulation signal is sent to the second slant pair. The waveform of the first pulse width modulation signal is complementary to the waveform of the second pulse width modulation signal. The first inverter and the fourth inverter form one slant pair, and the second inverter and the third inverter form another slant pair. The first slant pair is one of the two slant pairs, and the second slant pair is the other slant pair excluding the first slant pair. Obtain the target current flowing through the bridge inverter circuit; If the target current starts to be greater than or equal to a preset current threshold, the blocking time point of the target slant tube is determined. The blocking time point is the end time point of the high level received by the target slant tube. The target slant tube is the slant tube in the bridge inverter circuit that is subjected to a high level. The bridge inverter circuit is stopped working at the specified wave blocking time point. The bridge inverter circuit resumes operation after a preset delay.

2. The protection method according to claim 1, characterized in that, The UPS equipment includes a first switching switch, a power factor correction circuit, a main inverter circuit, a second switching switch, and a DC-DC conversion circuit. One end of the first switching switch is electrically connected to the mains power grid, and the other end of the first switching switch is electrically connected to the power factor correction circuit. The main inverter circuit is electrically connected to the power factor correction circuit, and one end of the second switching switch is electrically connected to the power factor correction circuit. The controller is electrically connected to the first switching switch, the power factor correction circuit, the main inverter circuit, and the second switching switch, respectively. The DC-DC conversion circuit includes the bridge inverter circuit, the resonant circuit, and the bridge rectifier circuit. The resonant circuit is electrically connected between the first parallel node and the second parallel node. One end of the bridge rectifier circuit is electrically connected to the resonant circuit, and the other end of the bridge rectifier circuit is electrically connected to the other end of the second switching switch. The controller is electrically connected to the bridge rectifier circuit.

3. The protection method according to claim 1, characterized in that, The UPS device includes a first timer and a second timer. The first timer is configured to generate a pulse width modulation signal in a counting mode based on a preset first counting cycle value. The inverter tubes of the bridge inverter circuit are driven by the pulse width modulation signal, which includes high level and low level. The second timer is configured with a first counting threshold, a second counting threshold, and a second counting period value. The second counting threshold is greater than the first counting threshold, and the second counting period value is greater than the first counting period value. The second timer works synchronously with the first timer. When the first slant transistor is applied a high level, the count value of the second timer is less than the first counting threshold, or the count value of the second timer is greater than the second counting threshold and less than the second counting period value; When the second slant transistor is applied a high level, the count value of the second timer is greater than the first counting threshold and less than the second counting threshold.

4. The protection method according to claim 3, characterized in that, If the target current begins to be greater than or equal to a preset current threshold, determining the sealing time point of the target oblique tube includes: If the target current begins to be greater than or equal to a preset current threshold, a target time point is determined, wherein the target time point is the time point when the target current begins to be greater than or equal to the preset current threshold; The slant pair that is subjected to a high level at the target time point is identified as the target slant pair. The falling edge of the high level signal has ended, and the end time of the falling edge is determined as the blocking time point.

5. The protection method according to claim 4, characterized in that, The determination that the slant-pair transistor to which a high level is applied at the target time point is the target slant-pair transistor includes: Determine the target count value of the second timer at the target time point; In response to the target count value being less than the first count threshold, or in response to the target count value being greater than the second count threshold and less than the second count period value, the first oblique tube is determined to be the target oblique tube; When the target count value is greater than the first count threshold and less than the second count threshold, the second oblique tube is determined to be the target oblique tube.

6. The protection method of claim 4, wherein, The determination of the end time of the falling edge of the target high level as the sealing time point includes: Determine the target count value of the second timer at the target time point; In response to the first slant-pair transistor being the target slant-pair transistor, the count value of the second timer is calculated from the target count value to the first count threshold, and the falling edge of the target high level ends at the time point corresponding to the first count threshold; The target time point is added to the first counting time to obtain the wave sealing time point.

7. The protection method of claim 4, wherein, The determination of the end time of the falling edge of the target high level as the sealing time point includes: Determine the target count value of the second timer at the target time point; In response to the second slant transistor being the target switch transistor, the second counting time from the target count value to the second counting threshold is calculated, and the falling edge of the target high level ends at the time point corresponding to the second counting threshold. The target time point is added to the second counting time to obtain the wave sealing time point.

8. The protection method according to any one of claims 1 to 7, characterized in that, The step of controlling the bridge inverter circuit to resume operation after a preset delay includes: The recovery time point is obtained by adding the sealing time point to the preset duration. At the recovery time point, a low level of a first duration is applied to the target oblique tube, the first duration being the period of the pulse width modulation signal minus the high level time; The starting slant pair is determined, which is the slant pair in the bridge inverter circuit excluding the target slant pair; At the recovery time point, a high level of a second duration is applied to the start-up slant tube, the second duration being the period of the pulse width modulation signal minus the low level time.

9. The protection method according to claim 8, characterized in that, The determination of the starting oblique tube includes: In response to the first oblique tube being the target oblique tube, the second oblique tube is determined to be the starting oblique tube; or... In response to the second oblique tube being the target oblique tube, the first oblique tube is determined to be the starting oblique tube.

10. A controller characterized by comprising: The device includes a memory and a processor, the memory being connected to the processor, the processor being configured to execute one or more computer programs stored in the memory, the processor causing the controller to implement the protection method for the UPS device as described in any one of claims 1-9 when executing the one or more computer programs.

11. A UPS apparatus, characterized by The system includes a first switching switch, a power factor correction circuit, a main inverter circuit, a second switching switch, a DC-DC converter circuit, a bridge inverter circuit, a battery, and a controller as described in claim 10. One end of the first switching switch is electrically connected to the mains power grid, and the other end of the first switching switch is electrically connected to the power factor correction circuit. The main inverter circuit is electrically connected to the power factor correction circuit, and one end of the second switching switch is electrically connected to the power factor correction circuit. The controller is electrically connected to the first switching switch, the power factor correction circuit, the main inverter circuit, and the second switching switch, respectively. The DC-DC conversion circuit includes a bridge inverter circuit, a resonant circuit, and a bridge rectifier circuit. The bridge inverter circuit includes a first inverter tube, a second inverter tube, a third inverter tube, and a fourth inverter tube. The first inverter tube and the third inverter tube are connected in series and then electrically connected between a preset first parallel node and a preset second parallel node. The second inverter tube and the fourth inverter tube are connected in series and then electrically connected between the first parallel node and the second parallel node. The controller is electrically connected to the first inverter tube, the second inverter tube, the third inverter tube, and the fourth inverter tube respectively. The resonant circuit is electrically connected between the first parallel node and the second parallel node. One end of the bridge rectifier circuit is electrically connected to the resonant circuit, and the other end of the bridge rectifier circuit is electrically connected to the other end of the second switching switch. The controller is also electrically connected to the bridge rectifier circuit.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, cause the processor to perform the protection method for the UPS device as described in any one of claims 1-9.

Images