Constant effective value output circuit and power control device

Abstract

This invention relates to a constant RMS output circuit and a power control device. In the constant RMS output circuit, the first terminals of a first capacitor and a second capacitor are connected to a power supply voltage, while their second terminals are connected to a first current source and a second current source, respectively. A first switch is connected across the first capacitor, and a second switch is connected across the second capacitor. By controlling the first and second switches at different time intervals, the voltage at the second terminals of the first and second capacitors can be adjusted. When the power supply voltage changes within a certain range, the duty cycle of the PWM wave will adjust accordingly, so that the effective value output voltage is basically unaffected by the power supply voltage, and the effective value output voltage can remain constant. The constant RMS output circuit uses an analog circuit to achieve constant RMS output, resulting in a simple circuit structure that avoids the logical complexity problems of digital circuits and has low cost. The power control device includes the aforementioned constant RMS output circuit.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and in particular to a constant RMS output circuit and a power control device. Background Technology

[0002] To meet different power supply requirements, existing voltage or current output devices need to be equipped with corresponding output circuits. These output circuits typically use different PWM control methods to achieve corresponding output quantities, such as constant average voltage, constant effective voltage (i.e., root mean square (RMS) voltage), and constant power. Among these, the commonly used circuit designs for constant effective voltage output suffer from the drawback of complex logic. Summary of the Invention

[0003] In order to achieve a constant effective value voltage output and avoid the logical complexity problems of digital circuits, the present invention provides a constant effective value output circuit, and also provides a power control device including the constant effective value output circuit.

[0004] On one hand, the present invention provides a constant RMS output circuit, the constant RMS output circuit comprising:

[0005] The duty cycle output module uses a PWM wave to control the duty cycle of the power supply voltage output, thereby generating an effective value output voltage.

[0006] A first capacitor, wherein a first terminal of the first capacitor is connected to the power supply voltage, a second terminal of the first capacitor is connected to a first current source, and both terminals of the first capacitor are connected to a first switch, the first switch responding to a first control signal by disconnecting both terminals of the first capacitor during a first time period (ta) and turning on both terminals of the first capacitor during a second time period (tb), thereby adjusting the voltage at the second terminal of the first capacitor; and

[0007] A second capacitor has a first terminal connected to the power supply voltage and two terminals connected to a second switch. The second switch responds to a second control signal by turning on the two terminals of the second capacitor during a first time period and turning off the two terminals of the second capacitor during a second time period to adjust the voltage at the second terminal of the second capacitor.

[0008] The duty cycle of the PWM wave is the second time period divided by the sum of the first time period and the second time period.

[0009] Optionally, the constant RMS output circuit includes:

[0010] During the first time period, the second terminal of the first capacitor is discharged, thereby changing the voltage of the second terminal from the power supply voltage to a preset voltage, and the voltage of the second terminal of the second capacitor is equal to the power supply voltage.

[0011] During the second time period, the voltage at the second terminal of the first capacitor is equal to the power supply voltage, and the second terminal of the second capacitor is discharged, causing the voltage at the second terminal to drop by a reference voltage.

[0012] Optionally, the constant RMS output circuit further includes:

[0013] The comparison module is configured to compare the voltage at a first voltage adjustment point between the first capacitor and the first current source with the preset voltage to form a first comparison result signal, and to compare the voltage at a second voltage adjustment point between the second capacitor and the second current source with the difference between the power supply voltage and the reference voltage to form a second comparison result signal; and

[0014] The latch module is used to generate the first control signal and the second control signal based on the level changes of the first comparison result signal and the second comparison result signal, wherein when the first comparison result signal or the second comparison result signal generates a level transition pulse, the level states of the first control signal and the second control signal change, and the change directions of the first control signal and the second control signal are opposite.

[0015] Optionally, the comparison module includes:

[0016] A first comparator, wherein the non-inverting input of the first comparator is connected to the first voltage adjustment point and the inverting input is connected to the preset voltage, and outputs the first comparison result signal; and

[0017] The second comparator has its non-inverting input connected to the second voltage adjustment point and its inverting input connected to the difference between the power supply voltage and the reference voltage, and outputs the second comparison result signal.

[0018] Optionally, the latch module includes an RS latch, a JK flip-flop, a D flip-flop, or a T flip-flop.

[0019] Optionally, the constant RMS output circuit further includes a reference voltage module, which includes a reference resistor and a reference current source. The two ends of the reference resistor are respectively connected to the power supply voltage and one end of the reference current source, and the other end of the reference current source is grounded. The voltage at the connection node of the reference resistor and the reference current source is the difference between the power supply voltage and the reference voltage.

[0020] Optionally, the preset voltage is less than or equal to the design value of the power supply voltage.

[0021] Optionally, the second control signal is connected to the duty cycle output module to obtain the duty cycle according to the second control signal.

[0022] Optionally, the capacitance of the first capacitor is smaller than the capacitance of the second capacitor.

[0023] On the other hand, the present invention provides a power control device, which includes the above-described constant RMS output circuit.

[0024] In the constant RMS output circuit and power control device provided by this invention, the first terminals of the first capacitor and the second capacitor are connected to the power supply voltage, while their second terminals are respectively connected to the first current source and the second current source. A first switch is connected across the first capacitor, and a second switch is connected across the second capacitor. By controlling the first and second switches at different time periods, the voltage at the second terminals of the first and second capacitors can be adjusted. When the power supply voltage changes within a certain range, the duty cycle will adjust accordingly, ensuring that the RMS output voltage obtained from the duty cycle output is essentially unaffected by the power supply voltage, thus maintaining a constant RMS output voltage. The constant RMS output circuit uses an analog circuit to achieve constant RMS output, resulting in a simple circuit structure that avoids the logical complexity issues present in digital circuits and has low cost. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of a constant RMS output circuit according to an embodiment of the present invention.

[0026] Figure 2 yes Figure 1 The diagram shows the waveform characteristics of multiple signals under the operating conditions of the constant RMS output circuit. Detailed Implementation

[0027] The constant RMS output circuit and power control device of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0028] This invention relates to a constant RMS output circuit and a power control device including the constant RMS output circuit. The constant RMS output circuit uses analog circuitry, which has a simple circuit structure and can avoid the logical complexity problems of digital circuits while achieving a constant RMS output.

[0029] Figure 1 A constant RMS output circuit according to an embodiment of the present invention is shown. Figure 2 This diagram illustrates the waveform characteristics of multiple signals corresponding to this constant RMS output circuit. (Refer to...) Figure 1 and Figure 2According to an embodiment of the present invention, the constant effective value output circuit includes a duty cycle output module 10, a first capacitor C_a, and a second capacitor C_b.

[0030] In the constant RMS output circuit, the duty cycle output module 10 uses a PWM wave to control the duty cycle of the power supply voltage VBAT (i.e., the supply voltage) to form an RMS output voltage. As an example, the duty cycle output module 10 includes a power switch disposed between the power supply voltage VBAT and the voltage output terminal, such as a MOS transistor. The control terminal of the power switch is connected to a PWM wave signal, and conducts according to the level of the PWM wave (e.g., ...). Figure 1 The PowerMOS is either ON or OFF, as shown, thereby generating a corresponding effective output voltage at the voltage output terminal. The effective output voltage can be expressed by the following equation (1):

[0031]

[0032] In equation (1), V orms Indicates the effective value of the output voltage, V p The pulse amplitude represents the output voltage, and D represents the duty cycle of the PWM wave. In this embodiment, V... p It is related to the input voltage, for example, equal to the power supply voltage VBAT.

[0033] like Figure 1 As shown, the first terminal of the first capacitor C_a is connected to the power supply voltage VBAT, and the first terminal of the second capacitor C_b is also connected to the power supply voltage VBAT; and, by setting an appropriate circuit structure, it is possible to ensure that: during the first time period ta (refer to...) of the PWM wave operating cycle... Figure 2 During the first time period ta, the second terminal of the first capacitor C_a, opposite to the first terminal, is discharged, causing the voltage at the second terminal (Vsaw_a) to drop from the power supply voltage VBAT to a preset voltage Voset. During the second time period tb of the operating cycle, the voltage at the second terminal of the first capacitor C_a is equal to the power supply voltage VBAT. During the second time period tb, the voltage at the second terminal of the second capacitor C_b, opposite to the first terminal (Vsaw_b), is equal to the power supply voltage VBAT. During the second time period tb, the second terminal of the second capacitor C_b is discharged, causing the voltage at the second terminal to drop by a reference voltage Vref.

[0034] The sum of the first time interval ta and the second time interval ta is the working period of the PWM wave. The duty cycle D of the PWM wave is the second time interval tb divided by the sum of the first time interval ta and the second time interval ta.

[0035] According to the capacitor charging and discharging formula In the first time interval ta, the first capacitor C_a (capacitance is C) aWhen the voltage at the second terminal of the signal changes from the power supply voltage VBAT to the preset voltage Voset, the following equation (2) holds:

[0036]

[0037] Where t represents time and V represents voltage.

[0038] Therefore, equation (3) holds:

[0039]

[0040] Additionally, in the second time period tb, the second capacitor C_b (with capacitance C) b When the voltage at the second terminal of the reference voltage Vref drops, the following equation (4) holds:

[0041]

[0042] Where t represents time and V represents voltage.

[0043] Therefore, equation (5) holds:

[0044]

[0045] In equation (5), Iref represents the reference current and Rref represents the reference resistance, for example, corresponding to respectively Figure 1 The exemplary circuit shown includes a reference current Iref and a reference resistance Rref.

[0046] Based on equations (3) and (5) and the definition of duty cycle D above, we can obtain the following equation (6):

[0047]

[0048] According to equation (6), in C a C b When Iref, Rref, and Voset are known, the duty cycle D decreases as the power supply voltage VBAT increases and increases as the power supply voltage VBAT decreases, meaning the duty cycle D and the power supply voltage VBAT have an inverse relationship. Combining this with equation (1), it can be seen that when the power supply voltage VBAT varies within a certain range, the duty cycle D has a compensating effect, making the effective value output voltage V... orms It is largely unaffected by the power supply voltage, thus achieving constant RMS output.

[0049] The preset voltage Voset mentioned above is the effective value of the output voltage V. ormsThe preset value, i.e., the ideal effective value output voltage, is set. The preset voltage Voset is, for example, less than or equal to the design value of the power supply voltage VBAT, i.e., Voset ≦ VBAT. According to equation (6), when Voset = VBAT, the duty cycle D is 100%. To achieve an output duty cycle close to 100% and reduce duty cycle output error, the difference between the power supply voltage VBAT and the preset voltage Voset is preferably small, for example, within a limited range. Furthermore, referring to equation (6), to obtain a larger duty cycle D (approximately 100%), the capacitance C of the first capacitor C_a is... a For example, a capacitance C less than the second capacitor C_b b .

[0050] The following combination Figure 1 and Figure 2 This paper introduces a constant effective value output circuit, which can realize the discharge process of the second terminal of the first capacitor C_a and the second capacitor C_b, and use the duty cycle output module 10 to control the duty cycle of the power supply voltage VBAT according to the duty cycle D obtained by equation (6), thereby forming a constant effective value output voltage V. orms However, it should be noted that the present invention can also employ other circuit structures to achieve the discharge process of the second terminals of the first capacitor C_a and the second capacitor C_b, and utilize the duty cycle output module 10 to form a constant effective value output voltage V. orms .

[0051] Reference Figure 1 In one embodiment, the constant RMS output circuit includes a first voltage regulation module 20 and a second voltage regulation module 30. The first voltage regulation module 20 includes a first capacitor C_a, a first current source (corresponding to current Ichrg1, denoted as first current source Ichrg1) connected to the second terminal of the first capacitor C_a, and a first switch M1 connected across the first capacitor C_a. The second voltage regulation module 30 includes a second capacitor C_b, a second current source (corresponding to current Ichrg2, denoted as second current source Ichrg2) connected to the second terminal of the second capacitor C_b, and a second switch M2 connected across the second capacitor C_b. A first voltage regulation point N1 may exist between the first capacitor C_a and the first current source Ichrg1, and a second voltage regulation point N2 may exist between the second capacitor C_b and the second current source Ichrg2.

[0052] The first switch M1 and the second switch M2 are active switches, such as NMOS transistors, PMOS transistors, JFETs (junction field-effect transistors), BJTs (bipolar junction transistors), or other suitable devices or structures. As an example, the first switch M1 and the second switch M2 are PMOS transistors.

[0053] Figure 1In the illustrated embodiment, the first switch M1 responds to the first control signal rst_a to control the opening and closing of the two ends of the first capacitor C_a. Since the first end of the first capacitor C_a is connected to the power supply voltage VBAT, the voltage at the second end of the first capacitor C_a can be adjusted by controlling the opening and closing of the two ends of the first capacitor C_a. As an example, when the two ends of the first capacitor C_a are turned on, the voltage Vsaw_a at the second end of the first capacitor C_a and the first voltage adjustment point N1 can rise to the power supply voltage VBAT. When the two ends of the first capacitor C_a are turned off, the voltage Vsaw_a at the second end of the first capacitor C_a and the first voltage adjustment point N1 is affected by the first current source Ichrg1 (e.g., the first current source Ichrg1 draws charge from the second end of the first capacitor C_a) and decreases, and changes to the preset voltage Voset during the first time period ta.

[0054] Figure 1 In the illustrated embodiment, the second switch M2 responds to the second control signal rst_b to control the switching on and off of the two ends of the second capacitor C_b. Since the first end of the second capacitor C_b is connected to the power supply voltage VBAT, the voltage at the second end of the second capacitor C_b can be adjusted by controlling the switching on and off of the two ends of the second capacitor C_b. As an example, when the two ends of the second capacitor C_a are turned on, the voltage Vsaw_b at the second end of the second capacitor C_b and the second voltage adjustment point N2 can rise to the power supply voltage VBAT. When the two ends of the second capacitor C_b are turned off, the voltage Vsaw_b at the second end of the second capacitor C_b and the second voltage adjustment point N2 is affected by the second current source Ichrg2 (e.g., the second current source Ichrg2 draws charge from the second end of the second capacitor C_b), and the reference voltage Vref drops during the second time period tb.

[0055] Continue to refer to Figure 1 In one embodiment, the constant RMS output circuit may further include a comparison module. The comparison module is used to compare the voltage Vsaw_a at the first voltage adjustment point N1 with a preset voltage Voset to form a first comparison result signal cmp_a, and to compare the voltage Vsaw_b at the second voltage adjustment point N2 with the difference between the power supply voltage VBAT and the reference voltage Vref to form a second comparison result signal cmp_b. As an example, the comparison module includes a first comparator 41 and a second comparator 42. The non-inverting input of the first comparator 41 is connected to the first voltage adjustment point N1, and the inverting input is connected to the preset voltage Voset, and it outputs the first comparison result signal cmp_a. The non-inverting input of the second comparator 42 is connected to the second voltage adjustment point N1, and the inverting input is connected to the difference between the power supply voltage VBAT and the reference voltage Vref (i.e., (VBAT-Vref)), and it outputs the second comparison result signal cmp_b.

[0056] As an example, such as Figure 1 As shown, the constant RMS output circuit may further include a reference voltage module 50. The reference voltage module 50 includes a reference resistor Rref and a reference current source (corresponding to the reference current Iref, denoted as the reference current source Iref). The two ends of the reference resistor Rref are respectively connected to the power supply voltage VBAT and one end of the reference current source Iref. The other end of the reference current source Iref is grounded. The voltage at the connection node of the reference resistor Rref and the reference current source Iref is the difference between the power supply voltage VBAT and the reference voltage Vref. Thus, the inverting input terminal of the second comparator 42 can be connected to the connection node of the reference resistor Rref and the reference current source Iref.

[0057] Reference Figure 1 In one embodiment, the constant RMS output circuit may further include a latch module 60. The latch module 60 is used to generate a first control signal rst_a for controlling the first switch M1 and a second control signal rst_b for controlling the second switch M2 based on the level changes of the first comparison result signal cmp_a and the second comparison result signal cmp_b. When either the first comparison result signal cmp_a or the second comparison result signal cmp_b generates a level-jumping pulse, the level states of the first control signal rst_a and the second control signal rst_b change, and the changing directions of the first control signal rst_a and the second control signal rst_b are opposite. The latch module 60 may include an RS latch, a JK flip-flop, a D flip-flop, or a T flip-flop. As an example, the latch module 60 is an RS latch.

[0058] like Figure 1 As shown, in one embodiment, the second control signal rst_b is not only used to control the second switch M2, but also connected to the duty cycle output module 10 to form the duty cycle D of the PWM wave according to the second control signal rst_b. As an example, the duty cycle output module 10 may include a filtering unit to filter out glitches in the second control signal rst_b.

[0059] Reference Figure 1 and Figure 2 , Figure 1 The working process of the constant RMS output circuit shown is as follows.

[0060] After the constant RMS output circuit is powered on, the power supply signal is the power supply voltage VBAT. All the aforementioned current sources, as well as the first comparator 41 and the second comparator 42, operate. The initial states of the first control signal rst_a and the second control signal rst_b are 0. The first switch M1 and the second switch M2 connect the two ends of the first capacitor C_a and the second capacitor C_b, respectively. The voltage Vsaw_a at the first voltage adjustment point N1 and the voltage Vsaw_b at the second voltage adjustment point N2 are charged and equal to the power supply voltage VBAT, satisfying Vsaw_a = Vsaw_b = VBAT. The voltage difference between the two ends of the first capacitor C_a and the second capacitor C_b is 0.

[0061] The initial states of the first comparison result signal cmp_a and the second comparison result signal cmp_b are 0. As the voltage Vsaw_a at the first voltage adjustment point N1 and the voltage Vsaw_b at the second voltage adjustment point N2 increases, the first comparison result signal cmp_a and the second comparison result signal cmp_b turn high. According to the truth table of the RS latch (taking the RS latch as the latch module 60 as an example), the first control signal rst_a turns high.

[0062] In normal circuit operation, when the first control signal rst_a is high, the first current source Ichrg1 is enabled to discharge (pump charge) from the second terminal of the first capacitor C_a, causing the voltage Vsaw_a at the first voltage adjustment point N1 to decrease. When Vsaw_a changes to the preset voltage Voset in the first time interval ta, the first comparison result signal cmp_a output by the first comparator 41 flips to a low level. After passing through the RS latch, the first control signal rst_a is pulled low, and then the first switch M1 is turned on, causing the voltage Vsaw_a at the first voltage adjustment point N1 to rise instantaneously, thus causing the first comparison result signal cmp_a to flip high, which is manifested as the first comparison result signal cmp_a generating a very short low-level pulse. Similarly, when the second control signal rst_b is high, the second current source Ichrg2 is enabled to discharge (pump charge) from the second terminal of the second capacitor C_b, causing the voltage Vsaw_b at the second voltage adjustment point N2 to decrease. When Vsaw_b decreases to the reference voltage Vref in the second time interval tb, the voltage drops to (VBAT-Vref), and the second comparison result signal cmp_b also generates a very short low-level pulse. It can be seen that the very short low-level pulses generated by the first comparison result signal cmp_a and the second comparison result signal cmp_b, after passing through the RS latch, will both trigger a change in the level states of the first control signal rst_a and the second control signal rst_b, and each time this is triggered, the direction of the level changes of the first control signal rst_a and the second control signal rst_b is opposite.

[0063] In this embodiment, the first current source Ichrg1, the second current source Ichrg2, and the reference current source Iref are, for example, constant current sources. The first capacitor C_a and the second capacitor C_b are controlled to discharge by the constant current sources, and the discharge time is linearly related to the voltage change.

[0064] The second control signal rst_b is input to the duty cycle output module 10 to form a PWM wave. The level change and duty cycle D of the PWM wave are consistent with those of the second control signal rst_b. The extremely short low-level pulses generated by the first comparison result signal cmp_a and the second comparison result signal cmp_b correspond to the rising and falling edges of the PWM wave, respectively. Figure 2 As shown, the working period of the second control signal rst_b is the sum of the first time period ta and the second time period tb. Based on the ratio of the second time period tb to the working period, the duty cycle D can be obtained. The specific calculation process can be referred to the above equations (1) to (6).

[0065] In the constant effective value output circuit described in the above embodiment, the first terminals of the first capacitor C_a and the second capacitor C_b are connected to the power supply voltage VBAT. The second terminals of the first capacitor C_a and the second capacitor C_b are discharged in the first time period ta and the second time period tb of the working cycle, respectively. According to equation (6), the duty cycle D of the PWM wave is related to the capacitance of the first capacitor C_a and the second capacitor C_b and the magnitude of the drop in the second terminals of the first capacitor C_a and the second capacitor C_b from the power supply voltage VBAT during discharge. The duty cycle D and the power supply voltage VBAT have an inverse trend. When the power supply voltage VBAT changes within a certain range, the duty cycle D will be adjusted accordingly, so that the effective value output voltage obtained by the duty cycle output is basically unaffected by the power supply voltage VBAT, thereby the effective value output voltage V orms It can maintain a constant RMS value. The constant RMS output circuit uses an analog circuit to achieve constant RMS output, which has a simple circuit structure, avoids the logical complexity problems of digital circuits, and has low cost.

[0066] This invention also relates to a power control device, which includes the aforementioned constant RMS output circuit. The power control device, for example, uses the RMS output voltage V of the aforementioned constant RMS output circuit. orms This allows for power output and power control. The power control device is supplied with, for example, the power supply voltage VBAT of the constant RMS output voltage circuit described above. When the power supply voltage VBAT fluctuates, the constant RMS output circuit can generate a constant RMS output voltage, which helps stabilize the RMS output voltage of the power control device, improves power control performance, and has a simple circuit structure, avoiding the logical complexity problems of digital circuits, and is low in cost.

[0067] It should be noted that the embodiments in this specification are described in a progressive manner, with each part focusing on the differences from the preceding parts, and relevant parts can be understood by referring to them.

[0068] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A constant effective value output circuit, characterized by, include: The duty cycle output module uses a PWM wave to control the duty cycle of the power supply voltage output, thereby generating an effective value output voltage. A first capacitor has a first terminal connected to the power supply voltage, a second terminal connected to a first current source, and two terminals connected to a first switch. The first switch responds to a first control signal by disconnecting the two terminals of the first capacitor during a first time period (ta) and turning on the two terminals of the first capacitor during a second time period (tb) to adjust the voltage at the second terminal of the first capacitor. as well as A second capacitor has a first terminal connected to the power supply voltage and two terminals connected to a second switch. The second switch responds to a second control signal by turning on the two terminals of the second capacitor during a first time period and turning off the two terminals of the second capacitor during a second time period to adjust the voltage at the second terminal of the second capacitor. The duty cycle of the PWM wave is the second time period divided by the sum of the first time period and the second time period.

2. The constant effective value output circuit of claim 1, wherein, include: During the first time period, the second terminal of the first capacitor is discharged, thereby changing the voltage of the second terminal from the power supply voltage to a preset voltage, and the voltage of the second terminal of the second capacitor is equal to the power supply voltage. During the second time period, the voltage at the second terminal of the first capacitor is equal to the power supply voltage, and the second terminal of the second capacitor is discharged, causing the voltage at the second terminal to drop by a reference voltage.

3. The constant effective value output circuit of claim 2, wherein, Also includes: The comparison module is used to compare the voltage at the first voltage adjustment point between the first capacitor and the first current source with the preset voltage to form a first comparison result signal, and to compare the voltage at the second voltage adjustment point between the second capacitor and the second current source with the difference between the power supply voltage and the reference voltage to form a second comparison result signal; as well as The latch module is used to generate the first control signal and the second control signal based on the level changes of the first comparison result signal and the second comparison result signal, wherein when the first comparison result signal or the second comparison result signal generates a level transition pulse, the level states of the first control signal and the second control signal change, and the change directions of the first control signal and the second control signal are opposite.

4. The constant effective value output circuit of claim 3, wherein, The comparison module includes: A first comparator, wherein the non-inverting input of the first comparator is connected to the first voltage adjustment point and the inverting input is connected to the preset voltage, and outputs the first comparison result signal; and The second comparator has its non-inverting input connected to the second voltage adjustment point and its inverting input connected to the difference between the power supply voltage and the reference voltage, and outputs the second comparison result signal.

5. The constant effective value output circuit of claim 3, wherein, The latching module includes an RS latch, a JK flip-flop, a D flip-flop, or a T flip-flop.

6. The constant effective value output circuit of claim 3, wherein, The constant RMS output circuit includes a reference voltage module, which includes a reference resistor and a reference current source. The two ends of the reference resistor are respectively connected to the power supply voltage and one end of the reference current source, and the other end of the reference current source is grounded. The voltage at the connection node of the reference resistor and the reference current source is the difference between the power supply voltage and the reference voltage.

7. The constant effective value output circuit of claim 2, wherein, The preset voltage is less than or equal to the design value of the power supply voltage.

8. The constant effective value output circuit according to any one of claims 1 to 7, wherein The second control signal is connected to the duty cycle output module to obtain the duty cycle according to the second control signal.

9. The constant effective value output circuit according to any one of claims 1 to 7, wherein The capacitance of the first capacitor is less than the capacitance of the second capacitor.

10. A power control device, characterized by Includes the constant RMS output circuit as described in any one of claims 1 to 9.

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