Temperature-insensitive output drive circuit for high-frequency Buck controller

Abstract

This invention relates to a temperature-insensitive output drive circuit for a high-frequency Buck controller. Based on a traditional output drive circuit, it adds a P-terminal programmable LDO module and an N-terminal programmable LDO module controlled by a temperature code, as well as a temperature detection and quantization module to generate the temperature code. This invention uses a temperature detection circuit to detect temperature changes in real time, obtaining a differential temperature detection signal Vtp-Vtn, which is then quantized into an N-bit temperature code to linearly reflect the temperature change. The N-bit temperature code then controls the P-terminal and N-terminal programmable LDO modules to dynamically adjust the high-side floating ground voltage Vgndh and the low-voltage power supply VCCL. When the temperature rises, the output drive LDMOS transistor Vgs voltage is increased by decreasing the high-side floating ground voltage Vgndh and increasing the low-voltage power supply VCCL, thereby reducing the on-resistance Rds and compensating for the Rds change caused by the temperature rise. Ultimately, the Rds of the output drive LDMOS transistor remains constant, effectively reducing the impact of temperature changes on the output drive characteristics.

Description

Technical Field

[0001] This invention relates to a temperature-insensitive output drive circuit for a high-frequency Buck controller, belonging to the field of integrated circuit technology. Background Technology

[0002] Buck converters are among the most widely used power controllers today. As power modules become smaller, lighter, and more portable, Buck converters need to have higher conversion efficiency, lower output ripple, and faster transient response characteristics.

[0003] A typical buck controller-based switching power supply system can be found in the appendix of Chinese Patent 2022107124813. Figure 2 The Buck controller 00 output drives high-power switching devices. Its internal output drive circuit amplifies the current, providing high-side and low-side output signals with high current drive capability to control the opening and closing of power switches Q1 and Q2, respectively. Therefore, the output drive circuit is usually the circuit module with the largest power consumption and the largest signal transmission delay within the Buck controller 00, and its response speed has the most significant impact on the overall transient response of the high-frequency Buck controller.

[0004] Figure 15 of Chinese Patent 2022107124813 also discloses an output drive circuit with dead-time protection function. For ease of explanation, the present invention is illustrated in Figure 15. Figures 1-3 .

[0005] Figure 1 This is an output drive circuit with dead-time protection. The circuit includes a P-terminal inverter chain consisting of NOR gate Nor1, NAND gate Nand1, inverters Inv2, Inv3, Inv5, Inv6, and Inv10~Inv12, and an N-terminal inverter chain consisting of Inv7~Inv9. These devices together form a dead-time generation circuit. The input terminal of the dead-time generation circuit is the input terminal of inverter Inv2, the P-terminal output terminal of the dead-time generation circuit is the output terminal of inverter Inv12 (signal Vgp), and the N-terminal output terminal of the dead-time generation circuit is the output terminal of inverter Inv9 (signal Vgn). Signals Vgp and Vgn drive the gates of high-voltage LDPMOS transistor HMP1 and high-voltage LDNMOS transistor HMN1, respectively.

[0006] In a typical power supply system, the power switches Q1 and Q2 are usually MOSFET / IGBT devices. To drive these devices, the VCC used in the output drive circuit is typically 10-30V. Figure 1 The schematic diagram of the operating waveform of the circuit shown is as follows: Figure 2After the power supply VCC is powered on, the input pulse signal Dout simultaneously enters the P-terminal inverter chain and the N-terminal inverter chain, respectively, to obtain the gate control signals Vgp and Vgn, which are used to control the conduction and cutoff of HMP1 and HMN1, respectively, to obtain the final output gate voltage control signal GH.

[0007] Typically, the power supply voltage of all inverters in the P-side inverter chain is connected to the power supply VCC, and the ground is the high-side floating ground voltage Vgndh. The power supply voltage of all inverters in the N-side inverter chain is connected to the low-voltage power supply VCCL, and the ground of all inverters is connected to the ground voltage GND. The voltage difference between the high-side floating ground voltage Vgndh and the power supply VCC is VCCL, with the value Vgndh = VCC - VCCL. When VCC is fixed, such as VCC = 20V, VCCL is usually set to a fixed value of 5V, and Vgndh is set to a fixed value of 15V to ensure that HMP1 and HMN1 are in the low-impedance deep linear region when turned on. Since HMN1 and HMP1 need to provide a very large output drive current and withstand a high voltage of VCC, they are typically implemented using high-voltage LDMOS transistors with a withstand voltage of VCC. These two LDMOS transistors are usually the devices with the highest power consumption and the largest signal transmission delay in the output drive circuit.

[0008] Figure 3 Showing Figure 1 The process involves the high-voltage LDNMOS transistor HMN1 turning off and the high-voltage LDPMOS transistor HMP1 turning on, causing the output gate voltage control signal GH to rise from GND to VCC. Vgndh is a fixed value. Assuming the maximum drive current provided by the high-voltage LDPMOS transistor HMP1 when it is turned on is Iout, the rise time is tr. During tr, the dynamic power consumption on the high-voltage LDPMOS transistor HMP1 can be approximately calculated as Iout*VCC / 2. As the Buck controller's output power increases, the switching frequency fsw inevitably increases. Therefore, the dynamic power consumption provided by HMP1 when it is turned on can be calculated as fsw*Iout*VCC / 2. With the increased operating time of the Buck controller, the high-frequency switching frequency leads to increased heat accumulation on HMP1, resulting in a rise in its temperature. With a constant gate voltage of the high-voltage LDMOS transistor, an increase in temperature leads to an increase in its on-resistance Rds(HMP1), reducing the maximum drive current it can provide to Ioutt. Meanwhile, the gate capacitance of the external power switch Q1 driven by the GH signal remains unchanged. This inevitably increases the rise time tr of the gate voltage control signal GH from GND to VCC to trt, ultimately reducing the transient response speed of the Buck controller. Therefore, providing an output drive circuit that is insensitive to temperature changes in transient response is of great significance for improving the transient response speed of the Buck controller. Summary of the Invention

[0009] Based on existing technology, this invention provides a temperature-insensitive output drive circuit for high-frequency Buck controllers, thereby improving the overall reliability and stability of high-frequency Buck controllers.

[0010] According to the technical solution provided by the present invention, the temperature-insensitive output drive circuit for a high-frequency Buck controller includes a P-terminal inverter chain and an N-terminal inverter chain, which respectively output gate control signals Vgp and Vgn, which are connected to the gates of high-voltage LDPMOS transistor HMP51 and high-voltage LDNMOS transistor HMN51, respectively, to control the conduction and turn-off of high-voltage LDPMOS transistor HMP51 and high-voltage LDNMOS transistor HMN51. The drains of high-voltage LDPMOS transistor HMP51 and high-voltage LDNMOS transistor HMN51 are connected to finally output the gate voltage control signal GH. The input pulse signal Dout is connected to the input terminal of inverter Inv52. The output signal Doin of inverter Inv52 is divided into two paths: the first path is connected to the first input terminal of NAND gate Nand52 and the input terminal of inverter Inv55. The output terminal of inverter Inv55 is connected to the second input terminal of NAND gate Nand52 through inverter Inv56. The output terminal of NAND gate Nand52 is connected to the input terminal of P-terminal inverter chain through level shifting circuit. The second path is connected to the first input terminal of NAND gate Nand51 and the input terminal of inverter Inv53. The output terminal of inverter Inv53 is connected to the second input terminal of NAND gate Nand51 through inverter Inv54. The output terminal of NAND gate Nand51 is connected to the input terminal of N-terminal inverter chain through delay compensation circuit. The source of the high-voltage LDPMOS transistor HMP51 and the power supply terminals of the P-terminal inverter chain are both connected to the power supply voltage VCC, and the ground terminals of the P-terminal inverter chain are both connected to the high-side floating ground voltage Vgndh; the source of the high-voltage LDNMOS transistor HMN51 and the ground terminals of the N-terminal inverter chain are both connected to the ground voltage GND port, and the power supply terminals of the N-terminal inverter chain are both connected to the low-voltage power supply VCCL; the high-side floating ground voltage Vgndh is provided by the P-terminal programmable LDO module, and the low-voltage power supply VCCL is provided by the N-terminal programmable LDO module; The temperature detection quantization module generates an N-bit temperature code, which is connected to the P-terminal programmable LDO module and the N-terminal programmable LDO module respectively, and controls the output voltage of the P-terminal programmable LDO module and the N-terminal programmable LDO module, where N is greater than 2.

[0011] The dead time of the Vgp signal is determined by the delay difference between the two input signals of the NAND gate Nand52, which is determined by the propagation delay of inverters Inv55 and Inv56; the dead time of the Vgn signal is determined by the delay difference between the two input signals of the NAND gate Nand51, which is determined by the propagation delay of inverters Inv53 and Inv54.

[0012] When the temperature changes, the N-bit temperature codes Dt1~DtN generated by the temperature detection and quantization module will quantize and follow the temperature changes in real time, and further adjust the high-side floating ground voltage Vgndh provided by the P-side programmable LDO module and the low-voltage power supply VCCL provided by the N-side programmable LDO module in real time. When the chip temperature rises, the N-bit temperature codes Dt1~DtN will decrease the high-side floating ground voltage Vgndh and increase the low-voltage power supply VCCL, thereby increasing the gate-source voltage of the high-voltage LDPMOS transistor HMP51 and the high-voltage LDNMOS transistor HMN51, compensating for the change in on-resistance caused by temperature changes, so that the on-resistance of the high-voltage LDPMOS transistor HMP51 and the high-voltage LDNMOS transistor HMN51 remains constant.

[0013] Specifically, the temperature detection quantization module includes: NPN transistor QN1, NPN transistor QN2, PMOS transistor M1, PMOS transistor M2, PMOS transistor M3, PMOS transistor M4, NMOS transistor M5, NMOS transistor M6, NMOS transistor M7, a programmable gain amplifier, a reference voltage generation circuit, and N differential comparators; the base area ratio of NPN transistor QN2 to NPN transistor QN1 is K, where K is a natural number greater than 2; In this configuration, the gates of PMOS transistors M1 and M2 are simultaneously connected to the reference voltage Vrt; the base of NPN transistor QN1 is connected to its own collector, and then to the drain of PMOS transistor M1 and the gate of NMOS transistor M6; the base of NPN transistor QN2 is connected to its own collector, and then to the drain of PMOS transistor M2 and the gate of NMOS transistor M5; the drain of NMOS transistor M5 is connected to the drain of PMOS transistor M3, the gate of PMOS transistor M3, and the gate of PMOS transistor M4; the drain of PMOS transistor M4 is connected to the drain of NMOS transistors M6, the drain of NMOS transistor M7, and the gate of NMOS transistor M7, generating a temperature detection voltage Vtd, which is simultaneously connected to the analog input of a programmable gain amplifier; the programmable gain amplifier amplifies the temperature detection voltage Vtd and converts it into differential temperature detection signals Vtp and Vtn; signals Vtp and Vtn are simultaneously connected to the first differential analog signal input and the second differential analog signal input of N differential comparators, respectively; The reference voltage generation circuit generates N reference voltage signals Vr1~VrN, wherein the voltage difference between any two adjacent reference voltage signals is equal. The reference voltage signals Vr1~VrN are connected sequentially to the first reference voltage input terminals of the N differential comparators in ascending order of voltage, and sequentially to the second reference voltage input terminals of the N differential comparators in descending order of voltage. The comparator output terminals of the N differential comparators generate N-bit temperature codes Dt1~DtN. The sources of PMOS transistors M1, M2, M3, and M4 are all connected to the power supply voltage VCC, while the emitters of NPN transistors QN1 and QN2, and the sources of NMOS transistors M5, M6, and M7 are all connected to ground voltage GND.

[0014] In the circuit described above, the current of PMOS transistor M3 is equal to the current of PMOS transistor M4 (I2), the current of NMOS transistor M6 is equal to I1, and the current of NMOS transistor M7 is equal to I2 - I1. Temperature is detected using a current difference method, and the temperature detection voltage Vtd can accurately reflect the voltage difference between the PN junctions of NPN transistors QN1 and QN2.

[0015] The advantages of this invention are: It uses a temperature detection circuit to detect temperature changes in real time, obtaining differential temperature detection signals Vtp and Vtn, which are then quantized into N-bit temperature codes Dt1~DtN to linearly reflect temperature changes. Finally, the N-bit temperature codes Dt1~DtN control the P-terminal programmable LDO module and the N-terminal programmable LDO module respectively to dynamically adjust the high-side floating ground voltage Vgndh and the low-voltage power supply VCCL. When the temperature rises, by decreasing Vgndh and increasing VCCL, the output drive LDMOS transistor Vgs voltage is increased, thereby reducing the on-resistance Rds. This compensates for the change in on-resistance Rds caused by temperature increases, ultimately keeping the current output drive LDMOS transistor Rds constant, effectively reducing the sensitivity of the output drive characteristics to temperature changes. This invention can be widely applied to various power management controllers and high-voltage chip systems. Attached Figure Description

[0016] Figure 1 This is an existing output drive circuit structure with dead-time protection.

[0017] Figure 2 for Figure 1 A schematic diagram of the circuit's operating waveforms.

[0018] Figure 3 for Figure 1 A magnified schematic diagram of the circuit's operating waveform.

[0019] Figure 4 This is a block diagram of the temperature-insensitive output drive circuit of the present invention.

[0020] Figure 5 for Figure 4 One embodiment of a medium-temperature detection quantization module.

[0021] Figure 6 This is a schematic diagram illustrating the working principle of an embodiment of the present invention. Detailed Implementation

[0022] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0023] like Figure 4 As shown, in the temperature-insensitive output drive circuit of the present invention, the input pulse signal Dout to be driven is connected to the input terminal of the inverter Inv52, and the output signal Doin of the inverter Inv52 is split into two paths: The first signal is connected to the first input of the NAND gate Nand52 and the input of the inverter Inv55. The output of the inverter Inv55 is connected to the second input of the NAND gate Nand52 via the inverter Inv56. The output of the NAND gate Nand52 is connected to the input of the level shift circuit 1. The output of the level shift circuit 1 is connected to the input of the P-terminal inverter chain Inv510-Inv512. The output signal Vgp of the inverter Inv512 is connected to the gate of the high-voltage LDPMOS transistor HMP51. The second signal is connected to the first input of the NAND gate Nand51 and the input of the inverter Inv53. The output of the inverter Inv53 is connected to the second input of the NAND gate Nand51 via the inverter Inv54. The output of the NAND gate Nand51 is connected to the input of the delay compensation circuit 2. The output of the delay compensation circuit 2 is connected to the input of the N-terminal inverter chain Inv57-Inv59. The output signal Vgn of the inverter Inv59 is connected to the gate of the high-voltage LDNMOS transistor HMN51. The drain of HMP51 is connected to the drain of HMN51 and serves as the output of the temperature-insensitive output drive circuit, outputting the gate voltage control signal GH.

[0024] The source of HMP51 and the power supply terminals of the P-side inverter chains Inv510-Inv512 are both connected to the power supply voltage VCC, and the ground terminals of the P-side inverter chains Inv510-Inv512 are both connected to the high-side floating ground voltage Vgndh. The source of HMN51 and the ground terminals of the N-side inverter chains Inv57-Inv59 are both connected to the ground voltage GND port, and the power supply terminals of the N-side inverter chains Inv57-Inv59 are both connected to the low-voltage power supply VCCL. The high-side floating ground voltage Vgndh is provided by the P-side programmable LDO module 3, and the low-voltage power supply VCCL is provided by the N-side programmable LDO module 4. The outputs of the P-side programmable LDO module 3 and the N-side programmable LDO module 4 are controlled by N-bit temperature codes Dt1~DtN, where N>2, and the control of the N-bit temperature codes Dt1~DtN is generated by the temperature detection and quantization module 5.

[0025] Figure 4 The scheme shown is in Figure 1 Based on this, a P-terminal programmable LDO module 3 and an N-terminal programmable LDO module 4, controlled by N-bit temperature codes Dt1~DtN, and a temperature detection quantization module 5 that generates N-bit temperature codes were added; at the same time, the cross-coupled feedback loop between signal Vgp and inverter Inv53, and between signal Vgn and inverter Inv55 was disconnected; the input terminals of inverter Inv53 and inverter Inv55 were simultaneously connected to the output signal Doin of inverter Inv52, and the NOR gate was changed to a NAND gate Nand52.

[0026] Figure 1 In the existing technical solution shown, the cross-coupled feedback loops of Vgp and inverter Inv3, and Vgn and inverter Inv5 are used to form a certain dead-time protection time. However, the absolute voltages of the high and low levels of signals Vgp and Vgn are inconsistent in this solution, which will cause a level error when inverter Inv3 recognizes the low level of Vgp, limiting the maximum voltage setting range of Vgndh; at the same time, it will also cause a level error when inverter Inv5 recognizes the high level of Vgn, limiting the minimum voltage setting range of VCCL. Usually, the settings of Vgndh and VCCL depend on the voltage withstand capability of the logic devices selected in the inverter chain, and the types of logic devices in conventional BCD technology are relatively limited, which will ultimately limit the selectable voltage range of VCC.

[0027] Figure 4 In the proposed scheme, the dead time of Vgp is determined by the delay difference between the two input signals of the NAND gate Nand52, which is determined by the propagation delay of inverters Inv55 and Inv56; the dead time of Vgn is determined by the delay difference between the two input signals of the NAND gate Nand51, which is determined by the propagation delay of inverters Inv53 and Inv54. Figure 4In this design, the signal Doin generates a dead time after passing through the NAND gate Nand52, and then passes through the level shift circuit 1 and the P-terminal inverter chain to obtain the Vgp signal. The absolute values ​​of the high and low levels of the Vgp signal are not directly related to Doin, so the selection range of the VCC voltage can be greatly expanded, completely covering the drain-source withstand voltage range of HMP51 and HMN51.

[0028] According to existing technology, assuming the Buck controller chip temperature rises, if Vgndh and VCCL remain constant, the on-resistances Rdsmp51 and Rdsmn51 corresponding to HMP51 and HMN51 will increase, thereby changing the output drive characteristics of the Buck controller chip. However, in the embodiment of this invention, when the temperature changes, the temperature detection and quantization module 5 generates N-bit temperature codes Dt1~DtN, which quantize and follow the temperature changes in real time, and adjusts the high-side floating ground voltage Vgndh provided by the P-terminal programmable LDO module 3 and the low-voltage power supply VCCL provided by the N-terminal programmable LDO module 4 in real time. When the chip temperature rises, the temperature detection and quantization module 5 generates N-bit temperature codes Dt1~DtN, which decreases the high-side floating ground voltage Vgndh and increases the low-voltage power supply VCCL, thereby increasing the gate-source voltage of HMP51 and HMN51 and decreasing Rdsmp51 and Rdsmn51 to compensate for the on-resistance changes caused by temperature variations, keeping the on-resistances of HMP51 and HMN51 constant.

[0029] Taking a typical 180nm BCD process as an example, the on-resistance Rds of a high-voltage LDMOS transistor changes with temperature at a rate of approximately 0.2-0.4% / ℃. A temperature change of 100℃ will cause a 20%-40% change in on-resistance Rds. Since the on-resistance Rds in the deep linear region of an LDMOS transistor is linearly inversely proportional to the gate-source voltage Vgs, increasing the gate-source voltage Vgs by 20%-40% is sufficient to fully compensate for the temperature-induced change in Rds. Assuming VCC = 20V, Figure 1 In the output drive circuit shown, Vgndh is typically set to a fixed value of 15V and VCCL of 5V. Figure 4 In the embodiment of the present invention shown, assuming that the on-resistance Rds changes with temperature at a rate of approximately 0.25% / ℃, Vgndh can be set to 16V and VCCL to 4V at 40℃. When the temperature rises to 100℃, Vgndh will decrease to 15.4V and VCCL will increase to 4.6V, compensating for the change in the on-resistance Rds of HMP51 and HMN51 caused by the temperature increase, so that the on-resistance Rds of HMP51 and HMN51 does not change with temperature.

[0030] like Figure 5The diagram illustrates one embodiment of the temperature detection and quantization module 5 of the present invention. The temperature detection and quantization module 5 includes: NPN transistors QN1 and QN2, PMOS transistors M1, M2, M3, M4, M5, M6, and M7, an NMOS transistor M5, M6, and M7, a programmable gain amplifier 52, a reference voltage generation circuit 51, and N differential comparators. The base area ratio of NPN transistor QN2 to NPN transistor QN1 is K, where K is a natural number greater than 2.

[0031] The circuit connections are as follows: the gates of PMOS transistors M1 and M2 are simultaneously connected to the reference voltage Vrt; the base and collector of NPN transistor QN1 are connected, and then connected to the drain of PMOS transistor M1 and the gate of NMOS transistor M6; the base and collector of NPN transistor QN2 are connected, and then connected to the drain of PMOS transistor M2 and the gate of NMOS transistor M5; the drain of NMOS transistor M5 is connected to the drain of PMOS transistor M3 and the gates of PMOS transistors M3 and M4. The drain of PMOS transistor M4 is connected to the drains of NMOS transistors M6 and M7, and the gate of NMOS transistor M7, generating a temperature detection voltage Vtd, which is also connected to the analog input of programmable gain amplifier 52. Programmable gain amplifier 52 amplifies the analog input temperature detection voltage Vtd and converts it into differential temperature detection signals Vtp and Vtn. Vtp and Vtn are respectively connected to the first differential analog signal input and the second differential analog signal input of N differential comparators. The reference voltage generation circuit 51 generates N reference voltage signals Vr1~VrN with equal voltage differences between adjacent pairs. The reference voltage signals Vr1~VrN are connected sequentially to the first reference voltage input terminals of the N differential comparators in ascending order of voltage, and sequentially to the second reference voltage input terminals of the N differential comparators in descending order of voltage. The comparator output terminals of the N differential comparators output Dt1~DtN respectively, which are the N-bit temperature codes generated by the temperature detection quantization module 5.

[0032] The sources of PMOS transistors M1, M2, M3, and M4 are all connected to the power supply voltage VCC. The emitters of NPN transistors QN1 and QN2, and the sources of NMOS transistors M5, M6, and M7 are all connected to the ground voltage GND.

[0033] Figure 5The temperature detection and quantization module 5 shown operates on the principle of temperature detection and quantization: the Vbe junction voltage of a transistor has a negative temperature coefficient, and the negative temperature coefficient differs for Vbe junctions with different current densities. Therefore, under the same bias voltage conditions, the voltage generated on two Vbe junctions with different current densities will produce a voltage difference as the temperature changes, and this voltage difference increases linearly with temperature. The base area ratio of transistors QN1 and QN2 is 1:K. The output voltages of their respective PN junctions are connected to the gates of NMOS transistors M5 and M6, respectively, generating currents I2 flowing through NMOS transistor M5 and I1 flowing through NMOS transistor M6. The temperature coefficients of the currents I1 and I2 are the same as the temperature coefficients of the voltages of transistors QN1 and QN2, respectively.

[0034] Figure 5 In this implementation scheme, the drains of NMOS transistors M6 and M7, and the gate of M7 are simultaneously connected to the drain of M4. The current of M4 equals the current of M3 (I2), and the current of M6 equals I1. Since the current of M4 is the sum of the currents of M6 and M7, the current of M7 equals the difference between the currents of M4 and M6 (I2 - I1). This means the drain voltage of M7 is the temperature detection voltage Vtd, and Vtd accurately reflects the voltage difference between the PN junctions of transistors QN1 and QN2. Furthermore, using a current difference method for temperature detection results in lower noise and offset, avoiding the offset voltage effect caused by directly calculating the voltage difference between the PN junction voltages of transistors QN1 and QN2, thus achieving higher temperature detection accuracy.

[0035] In practical implementation, K=8 can be selected, which allows transistors QN1 and QN2 to achieve better layout matching and reduce the impact of offset. Similarly, N=8 can be set, and the reference voltage signals Vr1~Vr8 can be arranged in ascending order of voltage. This will result in the comparator output signals Dt1~Dt8 of the eight differential comparators, with Dt1 being the most significant bit and Dt8 being the least significant bit. When the chip temperature is high, the Vtd voltage is large, and the resulting differential temperature detection signal Vtp-Vtn will be a large amplitude voltage signal. When Vtp-Vtn is greater than Vr1-Vr8, the 8-bit temperature code Dt1~Dt8 outputs the maximum value of "11111111". When the chip temperature decreases, the differential temperature detection signal Vtp-Vtn will be a smaller amplitude voltage signal. When Vtp-Vtn is less than Vr8-Vr1, the 8-bit temperature code Dt1~Dt8 outputs the minimum value of "00000000". In this way, the magnitude of the 8-bit temperature code Dt1~Dt8 can linearly reflect the chip temperature.

[0036] like Figure 6As shown, the operating temperature range of conventional chips is -40 to 150℃. In existing output drive circuits, Vgndh and VCCL are fixed voltages. Therefore, when the chip temperature rises, the on-resistances Rds(HMP1) and Rds(HMN1) of the high-voltage LDMOS transistor change with temperature. In this invention, a temperature detection circuit detects temperature changes in real time, obtaining a differential temperature signal Vtp-Vtn, which is quantized into an N-bit temperature code Dt1~DtN. This N-bit temperature code Dt1~DtN linearly reflects the temperature change. Finally, the voltages of Vgndh and VCCL are dynamically adjusted using the N-bit temperature code Dt1~DtN. When the temperature rises, Vgndh is decreased and VCCL is increased to raise the voltage Vgs of the output drive LDMOS transistor, thereby reducing the on-resistance Rds and compensating for the Rds change caused by temperature rise. Ultimately, the Rds of the output drive LDMOS transistor remains constant, effectively reducing the impact of temperature changes on the output drive characteristics.

[0037] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A temperature-insensitive output drive circuit for a high-frequency Buck controller, comprising a P-terminal inverter chain and an N-terminal inverter chain, which respectively output gate control signals Vgp and Vgn, connected to the gates of a high-voltage LDPMOS transistor HMP51 and a high-voltage LDNMOS transistor HMN51, for controlling the on and off states of the two transistors. The drains of the high-voltage LDPMOS transistors HMP51 and HMN51 are connected to ultimately output a gate voltage control signal GH; characterized in that... The input pulse signal Dout is connected to the input terminal of inverter Inv52. The output signal Doin of inverter Inv52 is divided into two paths: the first path is connected to the first input terminal of NAND gate Nand52 and the input terminal of inverter Inv55. The output terminal of inverter Inv55 is connected to the second input terminal of NAND gate Nand52 through inverter Inv56. The output terminal of NAND gate Nand52 is connected to the input terminal of P-terminal inverter chain through level shifting circuit. The second path is connected to the first input terminal of NAND gate Nand51 and the input terminal of inverter Inv53. The output terminal of inverter Inv53 is connected to the second input terminal of NAND gate Nand51 through inverter Inv54. The output terminal of NAND gate Nand51 is connected to the input terminal of N-terminal inverter chain through delay compensation circuit. The source of the high-voltage LDPMOS transistor HMP51 and the power supply terminals of the P-terminal inverter chain are both connected to the power supply voltage VCC, and the ground terminals of the P-terminal inverter chain are both connected to the high-side floating ground voltage Vgndh; the source of the high-voltage LDNMOS transistor HMN51 and the ground terminals of the N-terminal inverter chain are both connected to the ground voltage GND port, and the power supply terminals of the N-terminal inverter chain are both connected to the low-voltage power supply VCCL; the high-side floating ground voltage Vgndh is provided by the P-terminal programmable LDO module, and the low-voltage power supply VCCL is provided by the N-terminal programmable LDO module; The temperature detection quantization module generates an N-bit temperature code, which is connected to the P-terminal programmable LDO module and the N-terminal programmable LDO module respectively, and controls the output voltage of the P-terminal programmable LDO module and the N-terminal programmable LDO module, where N is greater than 2.

2. The temperature-insensitive output drive circuit for a high-frequency Buck controller according to claim 1, characterized in that, The dead time of the Vgp signal is determined by the delay difference between the two input signals of the NAND gate Nand52, which is determined by the propagation delay of inverters Inv55 and Inv56; the dead time of the Vgn signal is determined by the delay difference between the two input signals of the NAND gate Nand51, which is determined by the propagation delay of inverters Inv53 and Inv54.

3. The temperature-insensitive output drive circuit for a high-frequency Buck controller according to claim 1, characterized in that, When the temperature changes, the N-bit temperature codes Dt1~DtN generated by the temperature detection and quantization module will quantize and follow the temperature changes in real time, and further adjust the high-side floating ground voltage Vgndh provided by the P-side programmable LDO module and the low-voltage power supply VCCL provided by the N-side programmable LDO module in real time. When the chip temperature rises, the N-bit temperature codes Dt1~DtN will decrease the high-side floating ground voltage Vgndh and increase the low-voltage power supply VCCL, thereby increasing the gate-source voltage of the high-voltage LDPMOS transistor HMP51 and the high-voltage LDNMOS transistor HMN51, compensating for the change in on-resistance caused by temperature changes, so that the on-resistance of the high-voltage LDPMOS transistor HMP51 and the high-voltage LDNMOS transistor HMN51 remains constant.

4. The temperature-insensitive output drive circuit for a high-frequency Buck controller according to claim 3, characterized in that, The temperature detection quantization module includes: NPN transistor QN1, NPN transistor QN2, PMOS transistor M1, PMOS transistor M2, PMOS transistor M3, PMOS transistor M4, NMOS transistor M5, NMOS transistor M6, NMOS transistor M7, a programmable gain amplifier, a reference voltage generation circuit, and N differential comparators; the base area ratio of NPN transistor QN2 to NPN transistor QN1 is K, where K is a natural number greater than 2; In this configuration, the gates of PMOS transistors M1 and M2 are simultaneously connected to the reference voltage Vrt; the base of NPN transistor QN1 is connected to its own collector, and then to the drain of PMOS transistor M1 and the gate of NMOS transistor M6; the base of NPN transistor QN2 is connected to its own collector, and then to the drain of PMOS transistor M2 and the gate of NMOS transistor M5; the drain of NMOS transistor M5 is connected to the drain of PMOS transistor M3, the gate of PMOS transistor M3, and the gate of PMOS transistor M4; the drain of PMOS transistor M4 is connected to the drain of NMOS transistors M6, the drain of NMOS transistor M7, and the gate of NMOS transistor M7, generating a temperature detection voltage Vtd, which is simultaneously connected to the analog input of a programmable gain amplifier; the programmable gain amplifier amplifies the temperature detection voltage Vtd and converts it into differential temperature detection signals Vtp and Vtn; signals Vtp and Vtn are simultaneously connected to the first differential analog signal input and the second differential analog signal input of N differential comparators, respectively; The reference voltage generation circuit generates N reference voltage signals Vr1~VrN, wherein the voltage difference between any two adjacent reference voltage signals is equal. The reference voltage signals Vr1~VrN are connected sequentially to the first reference voltage input terminals of the N differential comparators in ascending order of voltage, and sequentially to the second reference voltage input terminals of the N differential comparators in descending order of voltage. The comparator output terminals of the N differential comparators generate N-bit temperature codes Dt1~DtN. The sources of PMOS transistors M1, M2, M3, and M4 are all connected to the power supply voltage VCC, while the emitters of NPN transistors QN1 and QN2, and the sources of NMOS transistors M5, M6, and M7 are all connected to ground voltage GND.

5. The temperature-insensitive output drive circuit for a high-frequency Buck controller according to claim 4, characterized in that, The current of PMOS transistor M3 is equal to the current of PMOS transistor M4 (I2), the current of NMOS transistor M6 is equal to I1, and the current of NMOS transistor M7 is equal to I2 - I1. Temperature is detected using the current difference method, and the temperature detection voltage Vtd can accurately reflect the PN junction voltage difference between NPN transistors QN1 and QN2.

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