A digital synchronous rectification control method and power supply device

Abstract

This invention discloses a digital synchronous rectification control method and power supply device, relating to the field of digital power supply control technology. The method includes: acquiring the driving signal edge timing, gate voltage, and drain-source voltage of the synchronous rectifier field-effect transistor (MOSFET) during the operation phase of each driving channel, and jointly determining the actual switching action timing of the MOSFET; accordingly, acquiring the actual drive propagation delay during conduction and the actual drive propagation delay during turn-off, and identifying the dominant delay growth window; acquiring the channel delay coupling coefficient based on the channel electrical coupling relationship table and the allowable hysteresis range, counting the number of channels with delay risks, and generating a real-time drive delay judgment value to adjust the drive edge during conduction, the drive edge during turn-off, or the dead time. This invention addresses the problem of inaccurate delay risk identification and compensation when the delay variation of multiple driving channels is constrained by topological coupling, and reduces the risk of increased body diode freewheeling time and timing overlap of complementary channels.

Description

Technical Field

[0001] This invention relates to the field of digital power supply control technology, specifically to a digital synchronous rectification control method and power supply device. Background Technology

[0002] In the field of digital synchronous rectifier power supplies, multiple synchronous rectifier field-effect transistors are usually controlled separately by a digital controller through a drive circuit. Their turn-on and turn-off timing directly affects the freewheeling time of the body diode, the timing overlap between complementary drive channels, and the operational stability of the power supply device.

[0003] Existing synchronous rectification control typically uses output voltage, output current, switching node voltage, or preset dead time for drive control. However, due to the combined effects of propagation delay of the isolation driver chip, gate drive resistance, gate capacitance of the synchronous rectifier MOSFET, temperature changes, and load changes, an actual drive propagation delay will occur between the edge of the same drive signal and the actual turn-on or turn-off of the synchronous rectifier MOSFET.

[0004] If control is based solely on the drive signal itself, it is difficult to reflect whether the synchronous rectifier field-effect transistor has actually turned on or off. If only the operating intervals between different switching devices are compared, the normal commutation time within the switching cycle may be included in the drive propagation delay, causing subsequent compensation to deviate from the actual switching process.

[0005] Furthermore, in a multi-drive channel synchronous rectification structure, the influence between different drive channels is not arbitrary, but is limited by complementary conduction relationships, same-arm relationships, primary-to-secondary commutation relationships, and secondary-to-primary feedback relationships. If the same correlation processing is applied to all drive channels, channels without direct coupling relationships may be included in the compensation judgment, causing the real-time drive delay judgment value to be affected by irrelevant data.

[0006] Therefore, a digital synchronous rectification control scheme is needed to determine the turn-on and turn-off delay risks and output compensation actions based on the driving signal edge, the actual switching action of the synchronous rectifier MOSFET, the topological coupling relationship, and the delay growth trend. Summary of the Invention

[0007] In view of the technical problems described in the background art, the present invention provides a digital synchronous rectification control method and power supply device to solve the problem that existing control methods are insufficient in identifying and compensating for the risks corresponding to turn-on delay and turn-off delay when there is a propagation delay between the edge of the drive signal and the actual switching action of the synchronous rectifier field-effect transistor in the digital synchronous rectification power supply, and when the delay variation of multiple drive channels is constrained by the topological coupling relationship.

[0008] A digital synchronous rectification control method includes: acquiring the timing of the drive signal edge, the gate voltage, and the drain-source voltage of the synchronous rectifier field-effect transistor (MOSFET) for each drive channel during operation; determining the actual switching action time of the MOSFET based on the gate voltage and drain-source voltage; acquiring the actual drive propagation delay for turn-on and turn-off based on the time difference between the actual switching action time and the corresponding drive signal edge, and identifying the dominant delay growth window; acquiring the channel delay coupling coefficient based on the channel electrical coupling relationship table and the allowable hysteresis range, and counting the number of delay-risk channels; acquiring a real-time drive delay judgment value based on the number of delay-risk channels, and adjusting the turn-on drive edge, turn-off drive edge, or dead time based on the real-time drive delay judgment value.

[0009] Optionally, the operation phase is determined in the following ways: within the preset startup shielding period after the power supply is started, channel delay coupling calculation is not performed, and the synchronous rectifier field-effect transistor array is driven by a preset dead time; when the output voltage reaches a preset proportion of the rated output voltage, and the change in output current is less than a preset change threshold in multiple consecutive control cycles, the operation phase closed-loop compensation mode is entered; when the power supply enters an undervoltage state, overcurrent state, restart state, or protection state, the operation phase closed-loop compensation mode is suspended.

[0010] Optionally, determining the actual switching time of the synchronous rectifier field-effect transistor (SFET) based on its gate voltage and drain-source voltage includes: when the gate voltage rises to the turn-on determination threshold and the drain-source voltage falls below the turn-on confirmation threshold, the time when the latter condition is met is taken as the actual turn-on time; when the gate voltage falls below the turn-off determination threshold and the drain-source voltage rises above the turn-off confirmation threshold, the time when the latter condition is met is taken as the actual turn-off time; if the difference between the gate voltage determination time and the drain-source voltage confirmation time in the same switching event exceeds a preset consistency tolerance, the corresponding switching event is marked as an invalid event.

[0011] Optionally, the method further includes a step for determining the validity of a switching event when the branch current is less than a preset effective current threshold: obtaining the branch current of the synchronous rectifier field-effect transistor; when the branch current is less than the preset effective current threshold, using the gate voltage determination time as the actual switching action time of the candidate synchronous rectifier field-effect transistor, and obtaining the candidate actual drive propagation delay based on the actual switching action time of the candidate synchronous rectifier field-effect transistor; if the candidate actual drive propagation delay is within the allowable variation range determined by the actual drive propagation delay of adjacent valid events and the preset delay tolerance, then the corresponding switching event is considered a valid event; if the candidate actual drive propagation delay exceeds the allowable variation range determined by the actual drive propagation delay of adjacent valid events and the preset delay tolerance, then the corresponding switching event is marked as an invalid event.

[0012] Optionally, identifying the dominant delay growth window includes: for the same drive channel and the same switching event type, comparing adjacent actual drive propagation delays according to the order of the switching events; if the later actual drive propagation delay is greater than the earlier actual drive propagation delay, then recording a positive delay change; forming a continuous propagation delay growth window from multiple consecutive positive delay changes, and not using a single positive delay change as a continuous propagation delay growth window; when there are multiple continuous propagation delay growth windows under the same drive channel and the same switching event type, selecting the continuous propagation delay growth window with the longest duration as the dominant delay growth window; when there are two or more continuous propagation delay growth windows with the longest duration, selecting the continuous propagation delay growth window with the later end time as the dominant delay growth window.

[0013] Optionally, the channel electrical coupling relationship table is used to represent the type of electrical coupling relationship between any two drive channels. The types of electrical coupling relationships include complementary conduction relationship, same-arm relationship, primary-to-secondary commutation relationship, secondary-to-primary feedback relationship, and no direct coupling relationship. When there is a complementary conduction relationship, same-arm relationship, primary-to-secondary commutation relationship, or secondary-to-primary feedback relationship between the i-th drive channel and the j-th drive channel, the j-th drive channel is configured as the effective coupled drive channel of the i-th drive channel. When there is no direct coupling relationship between the i-th drive channel and the j-th drive channel, the j-th drive channel does not participate in the calculation of the real-time drive delay determination value of the i-th drive channel.

[0014] Optionally, obtaining the channel delay coupling coefficient includes: determining the allowable hysteresis range based on the electrical coupling relationship type between the i-th drive channel and the j-th drive channel; shifting the drive delay window to be compared of the j-th drive channel within the allowable hysteresis range, and calculating the degree of overlap between the shifted drive delay window to be compared and the main drive delay window of the i-th drive channel; only adopting the degree of overlap whose shift direction conforms to the commutation sequence of the power supply device, and taking the largest value of the adopted degree of overlap as the channel delay coupling coefficient between the i-th drive channel and the j-th drive channel.

[0015] Optionally, obtaining the real-time drive delay judgment value based on the number of delay risk channels includes: when the number of effectively coupled drive channels is zero, maintaining the real-time drive delay judgment value as the calibration delay compensation value, or maintaining it as the real-time drive delay judgment value determined in the previous control cycle; when the number of effectively coupled drive channels is greater than zero, dividing the difference between the calibration delay compensation value and the delay judgment lower limit value equally according to the number of effectively coupled drive channels to obtain the single-channel adjustment step size; accumulating the single-channel adjustment step size according to the number of delay risk channels to obtain the cumulative adjustment time, and subtracting the cumulative adjustment time from the calibration delay compensation value to obtain the candidate judgment value; when the candidate judgment value is less than the delay judgment lower limit value, using the delay judgment lower limit value as the real-time drive delay judgment value; when the candidate judgment value is not less than the delay judgment lower limit value, using the candidate judgment value as the real-time drive delay judgment value.

[0016] A power supply device is also provided, including a digital controller, a drive circuit, a synchronous rectified field-effect transistor (MOSFET) array, a timing acquisition circuit, and a current detection circuit. The timing acquisition circuit is used to acquire the edge timing of the drive signal, the gate voltage of the synchronous rectified MOSFET, and the drain-source voltage of the synchronous rectified MOSFET. The digital controller is used to determine the actual switching action time of the synchronous rectified MOSFET based on the gate voltage and drain-source voltage of the synchronous rectified MOSFET, acquire the actual drive propagation delay for conduction and the actual drive propagation delay for turn-off based on the actual switching action time of the synchronous rectified MOSFET and the corresponding edge timing of the drive signal, count the number of delay risk channels based on the channel electrical coupling relationship table and the allowable hysteresis range, and generate a real-time drive delay judgment value based on the number of delay risk channels. The drive circuit is used to drive the synchronous rectified MOSFET array according to the pulse width modulation signal output by the digital controller.

[0017] Optionally, the digital controller includes a timing data processing module, an actual drive propagation delay calculation module, a dominant delay growth window identification module, a channel electrical coupling relationship table storage module, a channel delay coupling coefficient calculation module, a real-time drive delay judgment value generation module, an edge correction module, a dead time correction module, and a protection output module. The timing data processing module is used to determine the actual turn-on time and actual turn-off time of the synchronous rectifier field-effect transistor (SFET) based on the gate voltage and drain-source voltage of the SFET, and to mark switching events that do not meet the common confirmation conditions as invalid events. The actual drive propagation delay calculation module is used to obtain the actual drive propagation delay for turn-on and actual drive propagation delay for turn-off based on the actual switching action time of the SFET and the corresponding drive signal edge time. The dominant delay growth window identification module is used to identify the dominant delay growth window based on the actual drive propagation delay sequence for turn-on and the actual drive propagation delay sequence for turn-off, respectively. The channel electrical coupling relationship table storage module is used to store the electrical coupling relationship types between each drive channel and to determine the effective coupled drive channel based on the electrical coupling relationship type. The delayed coupling coefficient calculation module is used to shift the comparison drive delay window of the effectively coupled drive channel within the allowable hysteresis range, and determine the channel delay coupling coefficient based on the degree of overlap between the shifted comparison drive delay window and the main drive delay window; the real-time drive delay judgment value generation module is used to generate the real-time drive delay judgment value based on the number of effectively coupled drive channels, the number of delay risk channels, the calibrated delay compensation value, and the delay judgment lower limit value; the edge correction module is used to adjust the conduction drive edge based on the current actual drive propagation delay and the corresponding real-time drive delay judgment value, and to adjust the shutdown drive edge based on the current actual drive propagation delay and the corresponding real-time drive delay judgment value; the dead time correction module is used to increase the dead time between complementary drive channels when edge correction cannot make the current actual drive propagation delay less than or equal to the corresponding real-time drive delay judgment value; the protection output module is used to output a protection shutdown signal when the current actual drive propagation delay is greater than the corresponding real-time drive delay judgment value for multiple consecutive control cycles, or when the current actual drive propagation delay is still greater than the corresponding real-time drive delay judgment value after the dead time reaches the preset dead time upper limit.

[0018] The beneficial effects of this invention are reflected in: In this digital synchronous rectification control method, the actual switching action time of the synchronous rectifier MOSFET is obtained, distinguishing between the actual drive propagation delay during conduction and the actual drive propagation delay during turn-off. A real-time drive delay judgment value is generated by combining the channel electrical coupling relationship table, the allowable hysteresis range, and the number of channels with delay risks. This allows drive compensation to be adjusted based on the actual switching action and topology-related delay risks. When the conduction delay increases, the digital controller adjusts the conduction drive edge; when the turn-off delay increases and complementary coupling risks exist, the digital controller adjusts the turn-off drive edge or dead time to reduce the operational risks caused by the increase in body diode freewheeling time and the timing overlap of complementary drive channels. Attached Figure Description

[0019] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0020] Figure 1 This is a schematic diagram illustrating the steps of the digital synchronous rectification control method of the present invention; Figure 2 This is a schematic diagram of a portion of steps S1 in the digital synchronous rectification control method of the present invention; Figure 3 This is a schematic diagram of a portion of steps S2 in the digital synchronous rectification control method of the present invention; Figure 4 This is a schematic diagram of a portion of step S3 in the digital synchronous rectification control method of the present invention; Figure 5 This is a schematic diagram of a portion of step S4 in the digital synchronous rectification control method of the present invention; Figure 6 This is a schematic diagram of the power supply device of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0022] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0023] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0024] This invention provides a digital synchronous rectification control method, such as... Figure 1 As shown, in one specific embodiment, the method includes: S1. Obtain the timing of the driving signal edge, gate voltage and drain-source voltage of the synchronous rectifier field-effect transistor during the operation phase of each driving channel, and determine the actual switching action time of the synchronous rectifier field-effect transistor based on the gate voltage and drain-source voltage of the synchronous rectifier field-effect transistor. S2. Based on the time difference between the actual switching action time of the synchronous rectifier field-effect transistor and the corresponding drive signal edge time, obtain the actual drive propagation delay for conduction and the actual drive propagation delay for turn-off, and identify the dominant delay growth window. S3. Based on the channel electrical coupling relationship table and the allowable hysteresis range, obtain the channel delay coupling coefficient and count the number of channels with delay risks; S4. Obtain the real-time drive delay judgment value based on the number of delay risk channels, and adjust the turn-on drive edge, turn-off drive edge, or dead time based on the real-time drive delay judgment value.

[0025] Among them, synchronous rectifier field-effect transistor refers to metal-oxide-semiconductor field-effect transistor used for synchronous rectification; actual switching action refers to the conduction or turn-off action formed by the synchronous rectifier field-effect transistor after both the gate drive state and the drain-source channel state meet the corresponding judgment conditions.

[0026] In this embodiment, it should be noted that in S1, the drive channel refers to the drive path that starts from the output drive control signal of the digital controller, passes through the drive circuit, and reaches the gate node of the corresponding synchronous rectifier field-effect transistor. The operation phase refers to the working phase in which the power supply device has exited the startup process and entered the working phase where closed-loop compensation judgment can be performed. The digital controller does not only use the edge of the drive signal as the basis for the completion of the synchronous rectifier field-effect transistor's operation, but also synchronously acquires the timing of the drive signal edge, the gate voltage of the synchronous rectifier field-effect transistor, and the drain-source voltage of the synchronous rectifier field-effect transistor during the operation phase, and combines the drive state corresponding to the gate voltage with the power channel state corresponding to the drain-source voltage to determine the actual switching time of the synchronous rectifier field-effect transistor. For example, when the input voltage is Output voltage is Rated output current is The switching frequency is In a full-bridge synchronous rectifier power supply, during a certain turn-off event of the secondary-side positive arm drive channel, the falling edge of the drive signal is at time [time missing]. The moment when the gate voltage of the synchronous rectifier field-effect transistor drops to the turn-off threshold is The moment when the drain-source voltage of the synchronous rectifier field-effect transistor rises to the turn-off confirmation threshold is Then This serves as the actual turn-off time of the synchronous rectifier MOSFET. This ensures that subsequent delay calculations are based on the actual state of the power devices, reducing timing deviations caused by relying solely on control signals.

[0027] In S2, the actual drive propagation delay during conduction refers to the time difference between the actual turn-on time of the synchronous rectifier MOSFET and the rising edge of the drive signal in the same conduction event. The actual drive propagation delay during turn-off refers to the time difference between the actual turn-off time of the synchronous rectifier MOSFET and the falling edge of the drive signal in the same turn-off event. The digital controller pairs the actual switching action time of the synchronous rectifier MOSFET with the edge time of the drive signal in the same switching event to obtain the actual drive propagation delay during conduction and the actual drive propagation delay during turn-off, respectively. Since the electrical consequences of the two are different, the digital controller establishes separate sequences for the actual drive propagation delay during conduction and the actual drive propagation delay during turn-off. The dominant delay growth window refers to the continuous propagation delay growth window that ranks first in duration within the same drive channel and the same switching event type, used to characterize the main delay rise process within the current control cycle. For example, within a control cycle, the actual drive propagation delay during turn-off of the secondary-side positive arm drive channel is as follows: , , , , As adjacent data continues to rise, the digital controller identifies the corresponding interval as a continuous propagation delay growth window, and determines it as the dominant delay growth window after meeting the window length requirement. This processing is used to distinguish between single jitter and continuous delay changes, and provides a timing basis for subsequent compensation.

[0028] In S3, the channel electrical coupling relationship table is a data table used to record the types of electrical coupling relationships between any two drive channels. These relationships include complementary conduction, same-arm relationship, primary-to-secondary commutation, secondary-to-primary feedback, and no direct coupling. The allowable hysteresis range refers to the sampling period range within which the drive delay window to be compared is allowed to shift relative to the primary drive delay window under a specific electrical coupling relationship type. The channel delay coupling coefficient refers to the degree of overlap between the drive delay window to be compared and the primary drive delay window within the allowable hysteresis range. The number of delay risk channels refers to the number of drive channels that meet the effective coupling drive channel conditions, whose channel delay coupling coefficient reaches the coupling confirmation threshold, and conform to the power supply commutation sequence. The digital controller does not indiscriminately associate all drive channels; instead, it first determines the effective coupling drive channels based on the channel electrical coupling relationship table, and then compares the primary drive delay window and the drive delay window to be compared within the allowable hysteresis range. For example, if there is a complementary conduction relationship between the secondary positive arm drive channel and the secondary negative arm drive channel, the allowable hysteresis range is set to... Each sampling period to Each sampling period; the secondary positive arm drive channel and other drive channels without direct coupling do not participate in the calculation of real-time drive delay determination value. When the drive delay window to be compared of the secondary negative arm drive channel overlaps with the main drive delay window of the secondary positive arm drive channel after translation, the degree of overlap is... Furthermore, the translation direction conforms to the complementary commutation sequence, and the coupling confirmation threshold is... At that time, the secondary side negative arm drive channel is included in the number of delay risk channels.

[0029] In S4, the real-time drive delay judgment value refers to the time judgment value generated by the digital controller based on the number of delay risk channels, used to determine whether the current actual drive propagation delay needs compensation. The digital controller obtains the real-time drive delay judgment value based on the number of delay risk channels and compares the current on-time or current off-time actual drive propagation delay with the corresponding real-time drive delay judgment value to determine the adjustment method for the on-time drive edge, off-time drive edge, or dead time. For example, the calibration delay compensation value for the off-time type of the secondary side positive arm drive channel is... The lower limit of the delay judgment value is The number of effective coupling drive channels is The number of delayed risk channels is The single-channel downsizing step size is The cumulative reduction time is Candidate decision value If the current shutdown actually drives the propagation delay to be... The digital controller first adjusts the shutdown drive edge of the secondary side positive arm drive channel; if the edge adjustment still cannot make the current shutdown actual drive propagation delay less than or equal to the real-time drive delay judgment value, then the dead time between the complementary drive channels is increased. This compensation sequence corresponds to the handling path for shutdown delay risk.

[0030] In summary, this invention obtains the actual switching action time of the synchronous rectifier MOSFET, distinguishes between the actual drive propagation delay during conduction and the actual drive propagation delay during turn-off, and generates a real-time drive delay judgment value by combining the channel electrical coupling relationship table, the allowable hysteresis range, and the number of channels with delay risks. This transforms drive compensation from simply relying on a preset dead time to adjusting based on the actual switching action and topology-related delay risks. In this scheme, there is a clear input-output relationship between the drive signal edge time, the actual switching action time of the synchronous rectifier MOSFET, the actual drive propagation delay, the dominant delay growth window, the channel delay coupling coefficient, the number of channels with delay risks, and the real-time drive delay judgment value. Those skilled in the art can implement this through timing capture, comparator detection, sequence comparison, window matching, quantity statistics, and pulse width modulation updates. This technical solution can adjust the conduction drive edge when the conduction delay increases, and adjust the turn-off drive edge or dead time when the turn-off delay increases and there is a complementary coupling risk, thereby reducing the operational risks caused by the increase in body diode freewheeling time and the timing overlap of complementary drive channels.

[0031] like Figure 2 As shown, in one specific embodiment, S1 includes: S11. Determine whether the power supply unit has entered the closed-loop compensation mode during the operation phase.

[0032] S12. Obtain the driving signal edge time, gate voltage of synchronous rectifier field-effect transistor, and drain-source voltage of synchronous rectifier field-effect transistor for each driving channel.

[0033] S13. Determine the actual switching time of the synchronous rectifier field-effect transistor based on the gate voltage and drain-source voltage of the synchronous rectifier field-effect transistor, and mark invalid events.

[0034] In this embodiment, it should be noted that in S11, the closed-loop compensation mode during the operation phase refers to a control mode in which the digital controller allows updating the drive timing based on the actual drive propagation delay and the number of delay risk channels after the power supply device enters a stable output condition. The preset startup shielding period and preset dead time are determined based on the historical waveforms of the power supply device during the startup phase. Specifically, during the prototype debugging phase, the output voltage establishment time, drain-source voltage stabilization time, and branch current stabilization time are collected during a limited number of startup processes. The longest of these three times is converted into the number of switching cycles and rounded up to obtain the preset startup shielding period. The minimum safe interval when complementary drive channels are not overlapping during conduction is used as the preset dead time. For example, continuous... The longest stabilization time during the first startup was The switching cycle is The preset startup blocking period is then set to... One switching cycle; if the measured minimum safe interval of the complementary channel is... Then the preset dead time is taken .

[0035] The digital controller first identifies the operating status of the power supply unit and does not perform channel delay coupling calculations during a preset startup shielding period after the power supply unit starts up. For example, the preset startup shielding period is set to... Number of switching cycles, switching frequency is The corresponding time is During this period, the output voltage is still in the build-up process, and the drain-source voltage waveform and branch current waveform may be affected by the startup process, making them unsuitable as a basis for judging delay risk. Wait until the output voltage reaches the rated output voltage... ,Right now and continuously The change in output current within each control cycle is less than the rated output current. That is, the preset threshold for change is The digital controller enters the closed-loop compensation mode during operation. The preset ratio of the rated output voltage, the number of continuous control cycles, and the preset change threshold are determined based on stable operation samples. Specifically, the output voltage and output current sequences of the power supply unit under different load steps are collected. The lower limit of the ratio before the output voltage enters the steady-state error band is used as the preset ratio. The number of cycles required for the current change to continuously fall below the upper limit of noise and load fluctuation is used as the number of continuous control cycles. The product of the rated output current and the allowable fluctuation ratio is used as the preset change threshold. For example, the rated output voltage is... Before steady state The above waveform can stably enter the closed loop, and the rated output current is... The allowable fluctuation ratio is Then the preset ratio is taken The number of continuous control cycles is taken as The preset threshold for change is taken as follows: .

[0036] If the power supply enters an undervoltage state, overcurrent state, restart state, or protection state, the closed-loop compensation mode of the operation phase will be suspended, so that the subsequent actual drive propagation delay calculation is based on the operation phase data.

[0037] In S12, the digital controller acquires the rising and falling edges of the drive signal in closed-loop compensation mode during operation, and simultaneously acquires the corresponding gate voltage and drain-source voltage of the synchronous rectifier MOSFET. The drive signal edge moment refers to the moment when the drive control signal experiences a rising or falling edge. The rising edge moment is used to calculate the actual drive propagation delay for turn-on, and the falling edge moment is used to calculate the actual drive propagation delay for turn-off. The drive signal edge moment, gate threshold moment, and drain-source confirmation moment are obtained through timing capture or comparator latching under the same time base. Specifically, the timing acquisition circuit uses the controller timer as the time base and latches the signal when the drive signal experiences a rising or falling edge. The system latches the corresponding decision time when the gate voltage and drain-source voltage cross the corresponding thresholds, and then groups them into the same switching event according to the switching event index. For example, the timer resolution is... Latching on the falling edge The gate voltage crosses the turn-off threshold and is latched. The drain-source voltage crosses the turn-off confirmation threshold and is latched. If all three are involved, they will be classified into the same shutdown event.

[0038] The gate voltage of the synchronous rectifier MOSFET is used to determine whether the gate drive has reached the turn-on or turn-off condition, while the drain-source voltage of the synchronous rectifier MOSFET is used to confirm the power channel status. For example, in a certain turn-on event, the rising edge of the drive signal for the secondary-side positive arm drive channel is... The moment when the gate voltage of the synchronous rectifier field-effect transistor reaches the conduction threshold is The moment when the drain-source voltage of the synchronous rectifier field-effect transistor drops below the conduction confirmation threshold is By recording these moments simultaneously, the digital controller can avoid characterizing actual turn-on solely by the rising edge of the drive signal or a single gate threshold moment.

[0039] In S13, the actual switching timing of the synchronous rectifier MOSFET is determined jointly by the MOSFET's gate voltage and drain-source voltage. The turn-on and turn-off thresholds are determined based on the MOSFET's datasheet threshold voltage, drive voltage plateau, and the measured switching inflection point of the prototype. The turn-on confirmation and turn-off confirmation thresholds are determined based on the distinguishable voltage between the low-voltage turn-on plateau and the high-voltage turn-off plateau. The preset consistency tolerance is determined based on the upper bound of the historical difference between the gate determination timing and the drain-source confirmation timing in valid events. For example, the drive high level is... The device threshold range is to The measured stable conduction inflection point is at If it is nearby, the conduction determination threshold is taken as follows: The leak-source conduction platform is smaller than Then the conduction confirmation threshold is taken as The maximum time difference of historical valid events is Then the preset consistency tolerance is taken as .

[0040] For the actual turn-on time of the synchronous rectifier field-effect transistor (SFET), the time when the gate voltage rises to the turn-on determination threshold and the drain-source voltage drops below the turn-on confirmation threshold is taken as the actual turn-on time. Similarly, for the actual turn-off time, the time when the gate voltage drops below the turn-off determination threshold and the drain-source voltage rises above the turn-off confirmation threshold is taken as the actual turn-off time. For example, the turn-on determination threshold is set to... The conduction confirmation threshold is set to If the gate voltage reaches The time is The drain-source voltage drops to The following times are The actual turn-on time of the synchronous rectifier field-effect transistor is taken as If the difference between the gate voltage determination time and the drain-source voltage confirmation time exceeds... If the preset consistency tolerance is not met, the corresponding switching event is marked as an invalid event. An invalid event is a switching event that does not participate in the calculation of the actual driving propagation delay, the dominant delay growth window, and the number of delay risk channels.

[0041] When the branch current is less than the preset effective current threshold, the digital controller performs a switch event validity judgment. The preset effective current threshold is determined based on the minimum branch current required for the drain-source voltage to form an identifiable turn-on or turn-off platform, and the preset delay tolerance is determined based on the natural fluctuations of the actual drive propagation delay between adjacent effective events. Specifically, branch current, drain-source voltage, and actual drive propagation delay are collected at different percentages of rated load. The minimum branch current at which the drain-source voltage confirmation reliability reaches a preset percentage is taken as the preset effective current threshold, and an integer multiple of the standard deviation of the effective event delay is taken as the preset delay tolerance. For example, when the branch current is not less than... The reliability of the drain-source voltage confirmation reached [percentage missing]. The preset effective current threshold is then taken as... The standard deviation of the delay between adjacent valid events is The preset delay tolerance is then taken as .

[0042] The branch current refers to the current in the power branch where the synchronous rectifier MOSFET is located. The preset effective current threshold is a current threshold used to distinguish whether the drain-source voltage meets the stability confirmation condition. The digital controller obtains the branch current where the synchronous rectifier MOSFET is located; when the branch current is less than the preset effective current threshold, the gate voltage determination time is used as the actual switching action time of the candidate synchronous rectifier MOSFET, and the candidate actual drive propagation delay is obtained based on the candidate actual switching action time; if the candidate actual drive propagation delay is within the allowable variation range determined by the actual drive propagation delay of adjacent valid events and the preset delay tolerance, the corresponding switching event is considered a valid event; if the candidate actual drive propagation delay exceeds the allowable variation range determined by the actual drive propagation delay of adjacent valid events and the preset delay tolerance, the corresponding switching event is marked as an invalid event. This process is used to reduce the impact of insufficient drain-source voltage variation on the confirmation of the switching action time when the branch current is small.

[0043] like Figure 3 As shown, in one specific embodiment, S2 includes: S21. Obtain the actual drive propagation delay based on the actual switching action time of the synchronous rectifier field-effect transistor and the corresponding drive signal edge time.

[0044] S22. Identify the continuous propagation delay growth window based on the relationship between adjacent actual driving propagation delay changes.

[0045] S23. Determine the dominant delay growth window based on the duration and end time of the continuous propagation delay growth window.

[0046] In this embodiment, it should be noted that in S21, the digital controller establishes a switching event index for each drive channel and pairs the actual switching action time of the synchronous rectifier field-effect transistor (SFET) in the same switching event with the corresponding drive signal edge time. The switching event index is used to classify the drive signal edge, the gate voltage change of the synchronous rectifier field-effect transistor (SFET), and the drain-source voltage change of the synchronous rectifier field-effect transistor (SFET) into the same turn-on or turn-off event. For the turn-on type, the drive signal edge time is the rising edge time of the drive signal, and the actual switching action time of the synchronous rectifier field-effect transistor (SFET) is the actual turn-on time of the synchronous rectifier field-effect transistor (SFET); for the turn-off type, the drive signal edge time is the falling edge time of the drive signal, and the actual switching action time of the synchronous rectifier field-effect transistor (SFET) is the actual turn-off time of the synchronous rectifier field-effect transistor (SFET). The actual drive propagation delay is obtained according to the following expression:

[0047] in, This represents the actual drive propagation delay of the k-th switching event of the i-th drive channel under type x, in time units; x represents the switching event type, where x is the actual drive propagation delay for the on type and x is the actual drive propagation delay for the off type; i represents the drive channel number; k represents the switching event number. This indicates the actual switching action time of the synchronous rectifier field-effect transistor under type x for the k-th switching event of the i-th drive channel, in time units; This indicates the actual switching action of the synchronous rectifier field-effect transistor; This indicates the timing of the k-th switching event of the i-th drive channel at the edge of the drive signal under type x, in units of time. This indicates the edge of the drive signal.

[0048] The expression uses the subtraction of two moments within the same switching event because the actual drive propagation delay describes the time from the control edge to the synchronous rectifier MOSFET completing its actual switching action, not the commutation interval between the actions of two different devices. Taking the turn-off type of the secondary-side positive arm drive channel as an example, if... for , for ,but for This value is in units of time, corresponding to the propagation of the gate drive link and the charging and discharging process of the gate of the synchronous rectified MOSFET. If, in another conduction event, the rising edge of the drive signal is... The actual conduction time is The actual drive propagation delay is then... By storing the actual drive propagation delay sequence for conduction and the actual drive propagation delay sequence for turn-off within the same drive channel according to the switching event sequence number, the digital controller can separately track the risks associated with body diode freewheeling and the timing overlap risks associated with complementary drive channels. This calculation uses only the subtraction of similar time quantities, with a clear unit relationship. The input consists of two time points, and the output is a delay time, which can be directly implemented by the timing capture unit and the digital controller.

[0049] In S22, the continuous propagation delay growth window refers to the time interval consisting of multiple consecutive positive delay changes within the same drive channel and the same switching event type. The preset window length requirement is determined based on the number of effective switching events and delay measurement noise within the control cycle. Specifically, under stable operating conditions without compensation, the actual drive propagation delay sequence within a finite number of control cycles is collected. The length of the brief continuous rise caused by measurement jitter is statistically analyzed, and the smallest continuous rise segment exceeding this jitter length is taken as the preset window length requirement. For example, under stable operating conditions, occasional jitter typically only causes... The positive delay change occurred repeatedly, while the risk conditions occurred continuously. Then, at least one positive delay change can be specified. A series of consecutive positive delay changes, with a window duration of not less than [number missing]. Only then will the preset window segment length requirement be met.

[0050] The digital controller performs adjacent comparisons of the actual drive propagation delay sequence under the same drive channel and the same switching event type. If the subsequent actual drive propagation delay is greater than the previous actual drive propagation delay, a positive delay change is recorded; if the subsequent actual drive propagation delay is less than or equal to the previous actual drive propagation delay, no positive delay change is recorded. The digital controller groups multiple consecutive positive delay changes into a continuous propagation delay growth window, and a single positive delay change is not considered part of the continuous propagation delay growth window. For example, within one control cycle, the actual drive propagation delays of the secondary side positive arm drive channel shutdown are sequentially... , , , , Each subsequent value is greater than the previous value, and the digital controller records the continuous positive delay changes, forming a continuous propagation delay growth window. If the sequence is... , , , In this case, only interrupted local changes exist and do not directly constitute the dominant delay growth window. This processing is used to reduce the impact of single-measurement jitter on compensation judgment.

[0051] In S23, when multiple continuous propagation delay growth windows exist under the same drive channel and the same switching event type, the digital controller selects the continuous propagation delay growth window with the longest duration as the dominant delay growth window. When there are two or more continuous propagation delay growth windows with the longest duration, the continuous propagation delay growth window with the later end time is selected as the dominant delay growth window. "Longest duration" means it is the first window in the window duration order within the same control cycle, and "later end time" means that among two or more continuous propagation delay growth windows with the same duration, the window with the end time closer to the end of the current control cycle is selected. For example, in the secondary-side positive arm drive channel turn-off type, the first half of the control cycle forms a continuous... The continuous propagation delay growth window, the second half of the control cycle forms a continuous If the propagation delay growth window is continuous, then the window in the latter half of the control cycle is determined as the dominant delay growth window. If both windows are continuous... If the window with the later end time is selected, the dominant delay growth window will reflect delay changes closer to the end of the current control cycle. If there is no continuous propagation delay growth window, or if the continuous propagation delay growth window does not meet the preset window length requirement, the corresponding drive channel will be configured under the corresponding switch event type as having no dominant delay growth window and will not participate in the delay risk channel number statistics for this control cycle.

[0052] like Figure 4 As shown, in one specific embodiment, S3 includes: S31. Determine the effective coupling drive channel based on the channel electrical coupling relationship table.

[0053] S32. Obtain the channel delay coupling coefficient based on the degree of overlap between the driving delay window to be compared and the main driving delay window of the effectively coupled driving channel.

[0054] S33. Calculate the number of delay risk channels based on the channel delay coupling coefficient, and obtain the real-time drive delay judgment value based on the number of delay risk channels.

[0055] In this embodiment, it should be noted that in S31, an effectively coupled drive channel refers to a drive channel that has a complementary conduction relationship, a same bridge arm relationship, a primary-to-secondary commutation relationship, or a secondary-to-primary feedback relationship with the i-th drive channel, and participates in the calculation of the real-time drive delay determination value of the i-th drive channel. The channel electrical coupling relationship table is pre-generated based on the topology connection relationship of the power supply device, the drive channel connection objects, and the commutation sequence relationship within a switching cycle. Specifically, the switching device, bridge arm position, primary and secondary side positions, and complementary channel number corresponding to each drive channel are written into the configuration data, and then the table entry type is determined according to whether they share a bridge arm, whether they are complementary, whether they participate in the primary and secondary side energy transfer, and whether there is feedback influence. For example, in a four-channel full-bridge synchronous rectifier power supply, the secondary positive arm channel and the secondary negative arm channel are configured as complementary conduction relationships, the primary positive arm channel and the secondary positive arm channel are configured as primary-to-secondary commutation relationships, and auxiliary channels unrelated to the above commutation paths are configured as having no direct coupling relationship.

[0056] The digital controller reads the channel electrical coupling relationship table and determines the electrical coupling relationship type between any two drive channels based on the table. Electrical coupling relationship types include complementary conduction, same-arm relationship, primary-to-secondary commutation relationship, secondary-to-primary feedback relationship, and no direct coupling. When there is a complementary conduction relationship, same-arm relationship, primary-to-secondary commutation relationship, or secondary-to-primary feedback relationship between the i-th drive channel and the j-th drive channel, the j-th drive channel is configured as an effective coupled drive channel of the i-th drive channel; when there is no direct coupling between the i-th drive channel and the j-th drive channel, the j-th drive channel does not participate in the calculation of the real-time drive delay determination value of the i-th drive channel. For example, in a four-channel full-bridge synchronous rectifier power supply, the secondary positive arm drive channel and the secondary negative arm drive channel are complementary conduction channels, and the primary positive arm drive channel and the secondary positive arm drive channel are primary-to-secondary commutation channels. These channels can enter subsequent window matching; while the i-th drive channel and the j-th drive channel are not directly coupled. Other drive channels that are not directly coupled to a given drive channel are not included in subsequent statistics.

[0057] In S32, the main drive delay window refers to the dominant delay growth window of the i-th drive channel under the corresponding switching event type, and the comparison drive delay window refers to the dominant delay growth window of the j-th drive channel used for comparison with the main drive delay window under the corresponding switching event type. The overlap degree refers to the ratio of the overlap time between the shifted comparison drive delay window and the main drive delay window to the length of the main drive delay window. The digital controller determines the allowable hysteresis range based on the electrical coupling relationship type between the i-th and j-th drive channels, and shifts the comparison drive delay window of the j-th drive channel within the allowable hysteresis range. The allowable hysteresis range is determined based on the theoretical timing difference, sampling period, and historical delay offset between the two drive channels on the commutation path. The sampling period is determined by the timing resolution of the timing acquisition circuit or the controller's sampling cycle. Whether the shift direction conforms to the power supply commutation sequence is determined based on the sequential action relationship recorded in the channel electrical coupling relationship table. For example, the timing acquisition period is... In a complementary conduction relationship, the two delay growth windows may shift by no more than [a certain value]. For each sampling period, the allowable hysteresis range is [number]. One sampling period; the commutation relationship from the primary side to the secondary side requires the secondary side window to lag behind the primary side window, so only the sampling period is adopted. to The forward shift result for each sampling period.

[0058] For complementary conduction relationships, the allowable hysteresis range can be set to... Each sampling period to One sampling period; for the primary-to-secondary commutation relationship, the allowable hysteresis range can be set to [value missing]. Each sampling period to Each sampling period. The digital controller calculates the overlap between the translated drive delay window to be compared and the main drive delay window of the i-th drive channel, and only adopts the overlap where the translation direction conforms to the commutation sequence of the power supply unit. For example, the translation of the drive delay window to be compared for the secondary negative arm drive channel. After one sampling period, there exists a delay window between the main drive and the secondary arm drive channel. The overlap, while the main drive delay window continues The corresponding degree of overlap is If the translation direction conforms to the complementary commutation sequence, then the degree of overlap can be used as the candidate channel delay coupling coefficient.

[0059] In S33, if the j-th drive channel is an effective coupled drive channel of the i-th drive channel, and the channel delay coupling coefficient between the i-th and j-th drive channels reaches the coupling confirmation threshold, and the drive delay window to be compared of the j-th drive channel conforms to the power supply commutation sequence of the i-th drive channel, then the j-th drive channel is counted in the number of delay risk channels of the i-th drive channel. The coupling confirmation threshold is determined based on the distribution of historical window overlap. Specifically, the overlap between the main drive delay window and the drive delay window to be compared is collected under normal operating conditions and known coupling disturbance conditions, and the critical value that can distinguish between random overlap and true coupling overlap is used as the coupling confirmation threshold. For example, under normal operating conditions, the overlap of irrelevant channels is mainly distributed in... to It is known that the degree of overlap under complementary coupling perturbation is mainly distributed in to Then the coupling confirmation threshold can be taken as follows: When the calculated channel delay coupling coefficient is The number of channels with delay risk is included in the calculation. Time is not included.

[0060] For example, the coupling confirmation threshold is The channel delay coupling coefficient of a certain effectively coupled driving channel is If the window translation direction conforms to the commutation sequence, then the effective coupled drive channel is included in the number of delay risk channels; if the channel delay coupling coefficient of another effective coupled drive channel is... If the number of effective coupled drive channels is zero, the real-time drive delay judgment value will be maintained as the calibrated delay compensation value, or as the real-time drive delay judgment value determined in the previous control cycle. When the number of effective coupled drive channels is greater than zero, the digital controller obtains the real-time drive delay judgment value according to the following expression:

[0061] in, This represents the real-time drive delay determination value of the i-th drive channel under type x, in time units; x represents the switch event type, where x is the conduction type and corresponds to the actual drive propagation delay when conduction is active, and x is the shutdown type and corresponds to the actual drive propagation delay when shutdown is passive; i represents the drive channel number. This indicates taking the larger of the two values ​​within the parentheses; This represents the lower limit of the delay determination value for the i-th drive channel under type x, in time units; Indicates the lower limit of the delay judgment; This represents the calibration delay compensation value of the i-th drive channel under type x, in time units; Indicates calibration; This represents the number of latency-risk channels for the i-th driving channel under type x, and is a count value. This indicates a delayed risk channel; This represents the number of effectively coupled drive channels for the i-th drive channel under type x, and is a count value. This indicates the effective coupling drive channel. The calibration delay compensation value and delay judgment lower limit are determined based on a finite number of calibration data sets. Specifically, the actual drive propagation delay during conduction and the actual drive propagation delay during turn-off of each drive channel are collected under rated input voltage, rated output current, and several load points. The average delay under stable operating conditions, plus a safety margin, is used as the calibration delay compensation value. The effective delay lower limit of the device drive link under low temperature, light load, or minimum propagation delay conditions, plus a measurement margin, is used as the delay judgment lower limit. For example, the turn-off delay of the secondary-side positive arm under rated operating conditions... The mean of the samples is The maximum fluctuation is Then the calibration delay compensation value is taken as The minimum effective delay is Measurement margin is Then the lower limit of the delay judgment is taken as .

[0062] This expression is used when the number of effectively coupled drive channels is greater than zero. Both the calibration delay compensation value and the delay judgment lower limit are in time units, and their difference remains in time units. The difference is divided equally according to the number of effectively coupled drive channels to obtain the single-channel adjustment step size. The single-channel adjustment step size is accumulated according to the number of delay risk channels to obtain the cumulative adjustment time. The cumulative adjustment time is subtracted from the calibration delay compensation value to obtain the candidate judgment value. Finally, the larger value is taken to ensure that the real-time drive delay judgment value is not less than the delay judgment lower limit. For example, for the secondary side positive arm drive channel shutdown type... for , for , for , for ,but and The difference is Single channel downsizing step size is The cumulative reduction time is Candidate decision value The real-time drive latency judgment value is If the number of delay risk channels is Candidate decision value The real-time drive latency judgment value is This calculation logic converts the number of risks in the effectively coupled driving channels into the magnitude of the decision value reduction, and excludes channels with no direct coupling relationship.

[0063] like Figure 5 As shown, in one specific embodiment, S4 includes: S41. Perform edge adjustment based on the real-time drive delay determination value.

[0064] S42. When the edge adjustment cannot meet the shutdown delay determination requirements, perform dead time adjustment or protection output.

[0065] S43, output the drive control results and update the data for the next control cycle.

[0066] In this embodiment, it should be noted that in S41, edge adjustment refers to the digital controller performing timing correction on the turn-on or turn-off drive edge based on the comparison result between the current actual drive propagation delay and the corresponding real-time drive delay determination value. The digital controller compares the current actual drive propagation delay for turn-on with the corresponding real-time drive delay determination value, and also compares the current actual drive propagation delay for turn-off with the corresponding real-time drive delay determination value. For the turn-on type, if the current actual drive propagation delay for turn-on exceeds the corresponding real-time drive delay determination value, the digital controller adjusts the turn-on drive edge of the corresponding drive channel. The edge adjustment amount is determined based on the amount of time difference between the current actual drive propagation delay and the real-time drive delay determination value, and is limited by a preset edge correction amount upper limit. Specifically, the amount of time difference is multiplied by the edge correction ratio to obtain the edge adjustment amount for the current cycle, and then compared with the preset edge correction amount upper limit, taking the smaller value. The preset edge correction amount upper limit is determined based on the switching cycle, minimum pulse width, and complementary channel safety interval. For example, the current actual drive propagation delay for turn-on is... The real-time drive latency judgment value is The time exceeded is Edge correction ratio taken The adjustment amount at the edge of this cycle is If the preset edge correction upper limit is Then the actual execution The edge correction is either ahead or behind.

[0067] Meanwhile, the lower limit of the preset dead time is determined based on the safe interval between complementary channels to prevent overlapping conduction under the minimum delay difference, and the upper limit of the preset dead time is determined based on the output efficiency degradation and the allowable upper limit of the body diode freewheeling time. The increase in dead time is determined based on the remaining excess time after edge adjustment. Specifically, the minimum interval between the turn-off and turn-on edges of the complementary channels is collected, and a measurement margin is added to obtain the lower limit; then, the maximum dead time when the efficiency degradation does not exceed a set proportion is used as the upper limit. For example, the measured safe interval of the complementary channels is... Measurement margin is Then the lower limit of the dead time is taken as When the dead time exceeds If the efficiency drop exceeds the allowable range, then the upper limit of the dead time is set to... If the edge still exceeds the limit after adjustment The dead time in this cycle will increase. Or increase by step size .

[0068] For example, the actual drive propagation delay when the primary side positive arm drive channel is turned on is The corresponding real-time drive latency judgment value is The digital controller then according to The excessive time value adjusts the turn-on drive edge of the primary side positive arm drive channel. For the turn-off type, if the actual drive propagation delay of the current turn-off exceeds the corresponding real-time drive delay judgment value, and the channel delay coupling coefficient with the complementary drive channel reaches the coupling confirmation threshold, the digital controller adjusts the turn-off drive edge of the corresponding drive channel. The edge adjustment amount must not exceed the preset edge correction amount upper limit.

[0069] In S42, dead-time adjustment refers to adding a time interval between complementary drive channels that are not simultaneously turned on, to handle situations where the turn-off delay exceeds the limit even after edge adjustment. When edge adjustment cannot make the actual turn-off propagation delay less than or equal to the corresponding real-time drive delay judgment value, the digital controller increases the dead time between complementary drive channels. For example, the actual turn-off propagation delay of the secondary side positive arm drive channel is... The corresponding real-time drive latency judgment value is If, after edge adjustment, the dead time still exceeds the limit, the digital controller increases the dead time between the secondary positive arm drive channel and the secondary negative arm drive channel. The increased dead time must not be less than the preset lower limit of dead time, nor greater than the preset upper limit of dead time. If the actual drive propagation delay of the current shutdown exceeds the corresponding real-time drive delay judgment value for multiple consecutive control cycles, or if the actual drive propagation delay of the current shutdown still exceeds the corresponding real-time drive delay judgment value after the dead time reaches the preset upper limit of dead time, the digital controller outputs a protection shutdown signal. This process links the continuous over-limit of shutdown delay with the dead time boundary, giving the protection output a clear trigger condition.

[0070] The number of consecutive control cycles used to trigger protection is determined based on the probability of false triggering and the duration of shutdown delay risk. Specifically, the duration of exceeding limits is counted in three types of samples: normal load disturbance, short-time noise, and actual shutdown delay anomaly. The maximum number of consecutive exceeding limits that can be self-recovered from normal disturbance is added to the number of cycles exceeding limits. This serves as the number of protection trigger cycles. For example, during normal load disturbances, the actual drive propagation delay is shut down for a maximum of [number] consecutive cycles. The control cycle exceeds the real-time drive delay judgment value, while real anomalies usually last for a period of time. If there are more than one control cycle, then the number of protection trigger cycles is taken as... If continuous If all control cycles exceed the limit, a protection shutdown signal will be output.

[0071] In S43, the digital controller generates an updated pulse width modulation (PWM) signal based on edge adjustment, dead time adjustment, or protection output results, and outputs the updated PWM signal to the drive circuit. The PWM signal is the drive control signal output by the digital controller to the drive circuit, used to control the switching on and off of the synchronous rectifier MOSFET array. The drive circuit drives the synchronous rectifier MOSFET array to perform synchronous rectification based on the updated PWM signal. The digital controller stores the drive signal edge timing, the actual switching timing of the synchronous rectifier MOSFETs, the actual drive propagation delay during on-time, the actual drive propagation delay during off-time, the dominant delay growth window, the channel delay coupling coefficient, the number of delay-risk channels, the real-time drive delay judgment value, and the compensation strategy for the next control cycle. For example, when the secondary side positive arm drive channel is continuously... When there is no dominant delay growth window within a control cycle, and the current actual drive propagation delay is less than the corresponding real-time drive delay judgment value, the digital controller gradually cancels the edge adjustment amount and dead time increase amount to reduce the abrupt changes in drive timing between adjacent control cycles.

[0072] The gradual removal of edge adjustment and dead time increments is determined based on the compensated stabilization period and maximum backoff step size. Specifically, when there is no dominant delay growth window for several consecutive control cycles and the current actual drive propagation delay is lower than the real-time drive delay judgment value, the applied edge adjustment or dead time increment is reduced in each control cycle by an amount not exceeding the maximum backoff step size until the calibration state is restored. For example, the applied turn-off edge correction is... The increase in dead time is ,continuous The control cycle has no dominant delayed growth window, and the maximum backoff step size is taken as... Then, each cycle will revert separately. , , The edge correction amount, and according to Increase in dead zone time due to step size back.

[0073] like Figure 6 As shown, the present invention also provides a power supply device, including: a digital controller, a drive circuit, a synchronous rectifier field-effect transistor array, a timing acquisition circuit, and a current detection circuit.

[0074] The timing acquisition circuit is used to acquire the edge timing of the drive signal, the gate voltage of the synchronous rectifier field-effect transistor, and the drain-source voltage of the synchronous rectifier field-effect transistor; the current detection circuit is used to acquire the current of the branch where the synchronous rectifier field-effect transistor is located; the drive circuit is used to drive the synchronous rectifier field-effect transistor array according to the pulse width modulation signal output by the digital controller.

[0075] The digital controller includes a timing data processing module, an actual drive propagation delay calculation module, a dominant delay growth window identification module, a channel electrical coupling relationship table storage module, a channel delay coupling coefficient calculation module, a real-time drive delay judgment value generation module, an edge correction module, a dead time correction module, and a protection output module.

[0076] The timing data processing module is used to determine the actual turn-on time and the actual turn-off time of the synchronous rectifier field-effect transistor based on the gate voltage and drain-source voltage of the synchronous rectifier field-effect transistor, and to mark the switching events that do not meet the common confirmation conditions as invalid events.

[0077] The actual drive propagation delay calculation module is used to obtain the actual drive propagation delay for conduction and the actual drive propagation delay for turn-off based on the actual switching action time of the synchronous rectifier field-effect transistor and the corresponding drive signal edge time.

[0078] The dominant delay growth window identification module is used to identify the dominant delay growth window based on the actual drive propagation delay sequence when the device is turned on and the actual drive propagation delay sequence when the device is turned off.

[0079] The channel electrical coupling relationship table storage module is used to store the electrical coupling relationship types between each drive channel and to determine the effective coupled drive channel based on the electrical coupling relationship type.

[0080] The channel delay coupling coefficient calculation module is used to shift the comparison drive delay window of the effectively coupled drive channel within the allowable hysteresis range, and determine the channel delay coupling coefficient based on the degree of overlap between the shifted comparison drive delay window and the main drive delay window.

[0081] The real-time drive delay judgment value generation module is used to generate real-time drive delay judgment values ​​based on the number of effectively coupled drive channels, the number of delay risk channels, the calibrated delay compensation value, and the delay judgment lower limit value.

[0082] The edge correction module is used to adjust the turn-on drive edge according to the current actual drive propagation delay and the corresponding real-time drive delay judgment value, and to adjust the turn-off drive edge according to the current actual drive propagation delay and the corresponding real-time drive delay judgment value.

[0083] The dead time correction module is used to increase the dead time between complementary drive channels when edge correction cannot make the current shutdown actual drive propagation delay less than or equal to the corresponding real-time drive delay judgment value.

[0084] The protection output module is used to output a protection shutdown signal when the actual drive propagation delay of the current shutdown is greater than the corresponding real-time drive delay judgment value for multiple consecutive control cycles, or when the dead time reaches the preset dead time upper limit and the actual drive propagation delay of the current shutdown is still greater than the corresponding real-time drive delay judgment value.

[0085] To further clarify the operating mechanism and physical quantification process of the technical solution of the present invention, the following analysis will be conducted using a scenario containing specific parameters and data to explain the underlying processing logic of the digital synchronous rectification control method and the power supply device.

[0086] Taking a full-bridge synchronous rectifier power supply as an example, the input voltage is... The output voltage is Rated output current is The switching frequency is The control cycle is The power supply unit includes primary-side positive arm drive channels, primary-side negative arm drive channels, secondary-side positive arm drive channels, and secondary-side negative arm drive channels. After the power supply unit starts up, the digital controller... During each switching cycle, a preset dead time is used for operation, and channel delay coupling calculations are not performed. Because the switching frequency is... A single switching cycle is Therefore, the shielding is activated continuously. When the output voltage reaches and continuously The change in output current within each control cycle is less than At this point, the digital controller enters the closed-loop compensation mode of the operation phase. This operation phase determines that the timing data acquisition originates from the relatively stable operating range of output voltage and output current.

[0087] After entering the closed-loop compensation mode during operation, the digital controller performs timing acquisition on the secondary side positive arm drive channel. In a shutdown event, the falling edge of the drive signal is at... The moment when the gate voltage of the synchronous rectifier field-effect transistor drops to the turn-off threshold is The moment when the drain-source voltage of the synchronous rectifier field-effect transistor rises to the turn-off confirmation threshold is Since the actual turn-off time of the synchronous rectifier field-effect transistor (SFET) requires the simultaneous fulfillment of two conditions—a drop in the gate voltage and a rise in the drain-source voltage—and the time when the latter condition is met is taken as the cutoff time, the actual turn-off time of the SFET in this study is: According to the actual drive propagation delay acquisition logic in S21, the actual drive propagation delay for this shutdown is... In another conduction event, the rising edge of the drive signal is at... The actual turn-on time of the synchronous rectifier field-effect transistor is The actual drive propagation delay is Both delay values ​​are obtained by subtracting the actual switching action time of the synchronous rectifier field-effect transistor and the edge time of the drive signal in the same switching event.

[0088] Within one control cycle, the actual drive propagation delay of the secondary arm drive channel shut-off is as follows: , , , , The digital controller compares adjacent data in the order of switching events. It finds that each subsequent data point is greater than the previous one, thus creating a continuous propagation delay growth window. If this continuous propagation delay growth window continues... If the preset window length requirement is met, then the continuous propagation delay growth window is determined as the dominant delay growth window for the secondary-side positive arm drive channel under the turn-off type. In contrast, the actual drive propagation delay of the primary-side positive arm drive channel during conduction is from... Increase to However, the actual drive propagation delay of the complementary drive channel does not form a dominant delay growth window. Based on this, the digital controller treats it as a turn-on edge adjustment scenario and does not enter the dead time increase path.

[0089] During topology processing, the channel electrical coupling table configures the secondary-side positive arm drive channel and the secondary-side negative arm drive channel as complementary conduction channels, and configures the primary-side positive arm drive channel and the secondary-side positive arm drive channel as primary-to-secondary commutation channels. Regarding the turn-off type of the secondary-side positive arm drive channel, the secondary-side negative arm drive channel is considered an effectively coupled drive channel. Assuming the secondary-side negative arm drive channel has a drive delay window to be compared, the digital controller... Each sampling period to The comparison drive delay window is shifted within the allowable hysteresis range of each sampling period. When shifting... After one sampling period, the overlap time between the drive delay window to be compared and the main drive delay window of the secondary side positive arm drive channel is: The main drive delay window length is The degree of overlap is If the coupling confirmation threshold is If the translation direction conforms to the complementary commutation sequence, then the secondary side negative arm drive channel is included in the number of delay risk channels.

[0090] In the process of obtaining the real-time drive delay determination value, it is assumed that the calibration delay compensation value of the secondary side positive arm drive channel shutdown type is... The lower limit of the delay judgment value is The number of effective coupling drive channels is The number of delayed risk channels is According to the processing logic in S33, the distance between the calibrated delay compensation value and the lower limit of the delay judgment value is first... The difference is divided equally according to the number of effective coupled drive channels, resulting in Adjust the single-channel step size; then follow The cumulative delay risk channels have received The cumulative amount of time for the downward adjustment; then from After deducting the cumulative reduction time, we get The candidate decision value. Since the candidate decision value is not less than... Therefore, the real-time drive latency determination value is The process does not directly add data from different physical units; the statistical analysis is only used to determine the cumulative number of times the step size is reduced.

[0091] During the compensation output process, if the actual drive propagation delay of the secondary side positive arm drive channel is currently off, it is... The corresponding real-time drive latency judgment value is The digital controller first determines the relationship between the two. The differential adjustment controls the shutdown drive edge of the secondary positive arm drive channel. If, after the shutdown drive edge adjustment reaches the preset edge correction limit, the current actual shutdown drive propagation delay is still greater than the real-time drive delay judgment value, the digital controller increases the dead time between the secondary positive arm drive channel and the secondary negative arm drive channel. If, after the dead time reaches the preset dead time limit, the current actual shutdown drive propagation delay still cannot be less than or equal to the corresponding real-time drive delay judgment value, a protection shutdown signal is output. If continuously... If there is no dominant delay growth window within a control cycle, and the current actual drive propagation delay is lower than the real-time drive delay judgment value, then the digital controller gradually cancels the edge adjustment amount and dead time increase amount, so that the drive control returns to the vicinity of the calibration state.

[0092] In the above application scenario, S1 outputs the actual switching action time of the synchronous rectifier MOSFET; S2 outputs the actual drive propagation delay for turn-on, the actual drive propagation delay for turn-off, and the dominant delay growth window; S3 outputs the channel delay coupling coefficient, the number of delay-risk channels, and the real-time drive delay judgment value; and S4 outputs the adjustment results of the turn-on drive edge, the turn-off drive edge, the dead time, or the protection turn-off signal. The inputs and outputs of each stage consist of time acquisition, threshold judgment, sequence comparison, window matching, quantity statistics, and pulse width modulation updates. Those skilled in the art can implement this data processing logic in a digital signal processor, a field-programmable gate array, or a microcontroller with timing capture functionality.

[0093] The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the specific details of the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all fall within the protection scope of the present invention.

[0094] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.

[0095] Furthermore, various different embodiments of the present invention can be combined in any way, as long as they do not violate the spirit of the present invention, they should also be regarded as the content disclosed by the present invention.

[0096] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be covered within the scope of the claims and specification of the present invention.

Claims

1. A digital synchronous rectification control method, characterized in that, The methods include: The timing of the drive signal edge, gate voltage and drain-source voltage of the synchronous rectifier field-effect transistor (SFET) are obtained during the operation phase of each drive channel. The actual switching action time of the SFET is determined based on the gate voltage and drain-source voltage of the SFET. Based on the time difference between the actual switching action time of the synchronous rectifier field-effect transistor and the corresponding drive signal edge time, the actual drive propagation delay for turn-on and the actual drive propagation delay for turn-off are obtained respectively, and the dominant delay growth window is identified. Based on the channel electrical coupling relationship table and the allowable hysteresis range, obtain the channel delay coupling coefficient and count the number of channels with delay risks; The real-time drive delay judgment value is obtained based on the number of delay risk channels, and the turn-on drive edge, turn-off drive edge, or dead time is adjusted based on the real-time drive delay judgment value.

2. The digital synchronous rectification control method according to claim 1, characterized in that, The operational phase is determined in the following ways: During the preset startup shielding period after the power supply device is started, the channel delay coupling calculation is not performed, and the synchronous rectifier field-effect transistor array is driven by a preset dead time. When the output voltage reaches the preset ratio of the rated output voltage, and the change in output current is less than the preset change threshold in multiple consecutive control cycles, the closed-loop compensation mode of the operation phase is entered. When the power supply enters an undervoltage state, overcurrent state, restart state, or protection state, the closed-loop compensation mode is suspended during the operation phase.

3. The digital synchronous rectification control method according to claim 1, characterized in that, The actual switching timing of the synchronous rectifier field-effect transistor (SFET) is determined by combining its gate voltage and drain-source voltage. When the gate voltage of the synchronous rectifier field-effect transistor rises to the conduction determination threshold and the drain-source voltage of the synchronous rectifier field-effect transistor drops to below the conduction confirmation threshold, the moment when the latter of the two conditions is met is taken as the actual conduction moment of the synchronous rectifier field-effect transistor. When the gate voltage of the synchronous rectifier field-effect transistor drops below the turn-off determination threshold and the drain-source voltage of the synchronous rectifier field-effect transistor rises above the turn-off confirmation threshold, the moment when the latter condition is met is taken as the actual turn-off time of the synchronous rectifier field-effect transistor. If the difference between the gate voltage determination time and the drain-source voltage confirmation time in the same switching event exceeds the preset consistency tolerance, the corresponding switching event will be marked as an invalid event.

4. The digital synchronous rectification control method according to claim 3, characterized in that, It also includes a step for determining the validity of a switching event when the branch current is less than a preset effective current threshold: Obtain the current in the branch where the synchronous rectifier field-effect transistor is located; When the branch current is less than the preset effective current threshold, the gate voltage determination time is taken as the actual switching action time of the candidate synchronous rectifier field-effect transistor, and the candidate actual drive propagation delay is obtained based on the actual switching action time of the candidate synchronous rectifier field-effect transistor. If the candidate actual drive propagation delay is within the allowable variation range determined by the actual drive propagation delay of adjacent valid events and the preset delay tolerance, then the corresponding switch event is regarded as a valid event. If the candidate actual drive propagation delay exceeds the allowable variation range determined by the actual drive propagation delay of adjacent valid events and the preset delay tolerance, the corresponding switch event will be marked as an invalid event.

5. The digital synchronous rectification control method according to claim 1, characterized in that, Identifying the dominant delay growth window includes: For the same drive channel and the same switching event type, compare the propagation delay of adjacent actual drives in the order of the switching events. If the propagation delay of the later actual drive is greater than the propagation delay of the earlier actual drive, then record a positive delay change. Multiple consecutive positive delay changes are combined into a continuous propagation delay growth window, and a single positive delay change is not considered as a continuous propagation delay growth window; When there are multiple continuous propagation delay growth windows under the same driving channel and the same switching event type, the continuous propagation delay growth window with the longest duration is selected as the dominant delay growth window; when there are more than two continuous propagation delay growth windows with the longest duration, the continuous propagation delay growth window with the later end time is selected as the dominant delay growth window.

6. The digital synchronous rectification control method according to claim 1, characterized in that, The channel electrical coupling relationship table is used to represent the electrical coupling relationship type between any two drive channels. The electrical coupling relationship types include complementary conduction relationship, same bridge arm relationship, primary side to secondary side commutation relationship, secondary side to primary side feedback relationship, and no direct coupling relationship. When there is a complementary conduction relationship, a bridge arm relationship, a primary-to-secondary commutation relationship, or a secondary-to-primary feedback relationship between the i-th drive channel and the j-th drive channel, the j-th drive channel is configured as an effective coupling drive channel of the i-th drive channel. When there is no direct coupling between the i-th drive channel and the j-th drive channel, the j-th drive channel does not participate in the calculation of the real-time drive delay determination value of the i-th drive channel.

7. The digital synchronous rectification control method according to claim 6, characterized in that, Obtaining the channel delay coupling coefficient includes: The allowable hysteresis range is determined based on the type of electrical coupling relationship between the i-th drive channel and the j-th drive channel; Within the allowable hysteresis range, shift the comparison drive delay window of the j-th drive channel and calculate the degree of overlap between the shifted comparison drive delay window and the main drive delay window of the ith drive channel. Only the degree of overlap that conforms to the commutation sequence of the power supply device in the translation direction is adopted, and the degree of overlap with the largest value among the adopted degrees of overlap is used as the channel delay coupling coefficient between the i-th drive channel and the j-th drive channel.

8. The digital synchronous rectification control method according to claim 1, characterized in that, The real-time drive latency judgment value is obtained based on the number of latency risk channels, including: When the number of effective coupled drive channels is zero, the real-time drive delay judgment value is maintained as the calibration delay compensation value, or as the real-time drive delay judgment value determined in the previous control cycle. When the number of effective coupled drive channels is greater than zero, the difference between the calibrated delay compensation value and the delay judgment lower limit value is divided equally according to the number of effective coupled drive channels to obtain the single-channel down adjustment step size; The step size of a single channel is adjusted down according to the number of delay risk channels to obtain the cumulative adjustment time. The cumulative adjustment time is then deducted from the calibrated delay compensation value to obtain a candidate judgment value. When the candidate judgment value is less than the delay judgment lower limit, the delay judgment lower limit is used as the real-time driving delay judgment value. When the candidate judgment value is not less than the delay judgment lower limit, the candidate judgment value is used as the real-time driving delay judgment value.

9. A power supply device, characterized in that, It includes a digital controller, a drive circuit, a synchronous rectifier field-effect transistor array, a timing acquisition circuit, and a current detection circuit; The timing acquisition circuit is used to acquire the edge timing of the drive signal, the gate voltage of the synchronous rectifier field-effect transistor, and the drain-source voltage of the synchronous rectifier field-effect transistor; The digital controller is used to determine the actual switching action time of the synchronous rectifier field-effect transistor (SRT) based on the gate voltage and drain-source voltage of the SRT, obtain the actual drive propagation delay for conduction and the actual drive propagation delay for turn-off based on the actual switching action time of the SRT and the corresponding drive signal edge time, count the number of delay risk channels based on the channel electrical coupling relationship table and the allowable hysteresis range, and generate a real-time drive delay judgment value based on the number of delay risk channels. The driving circuit is used to drive the synchronous rectifier field-effect transistor array according to the pulse width modulation signal output by the digital controller.

10. The power supply device according to claim 9, characterized in that, The digital controller includes a timing data processing module, an actual drive propagation delay calculation module, a dominant delay growth window identification module, a channel electrical coupling relationship table storage module, a channel delay coupling coefficient calculation module, a real-time drive delay judgment value generation module, an edge correction module, a dead time correction module, and a protection output module. The timing data processing module is used to determine the actual turn-on time and the actual turn-off time of the synchronous rectifier field-effect transistor based on the gate voltage and drain-source voltage of the synchronous rectifier field-effect transistor, and to mark the switching events that do not meet the common confirmation conditions as invalid events. The actual drive propagation delay calculation module is used to obtain the actual drive propagation delay during conduction and the actual drive propagation delay during shutdown based on the actual switching action time of the synchronous rectifier field-effect transistor and the corresponding drive signal edge time. The dominant delay growth window identification module is used to identify the dominant delay growth window based on the actual drive propagation delay sequence when the actual drive is turned on and the actual drive propagation delay sequence when the actual drive is turned off, respectively. The channel electrical coupling relationship table storage module is used to store the electrical coupling relationship types between each drive channel and to determine the effective coupled drive channel based on the electrical coupling relationship types. The channel delay coupling coefficient calculation module is used to shift the comparison drive delay window of the effectively coupled drive channel within the allowable hysteresis range, and determine the channel delay coupling coefficient based on the degree of overlap between the shifted comparison drive delay window and the main drive delay window. The real-time drive delay judgment value generation module is used to generate a real-time drive delay judgment value based on the number of effectively coupled drive channels, the number of delay risk channels, the calibration delay compensation value, and the delay judgment lower limit value. The edge correction module is used to adjust the turn-on drive edge according to the current actual drive propagation delay and the corresponding real-time drive delay determination value, and to adjust the turn-off drive edge according to the current actual drive propagation delay and the corresponding real-time drive delay determination value. The dead time correction module is used to increase the dead time between complementary drive channels when edge correction cannot make the current shutdown actual drive propagation delay less than or equal to the corresponding real-time drive delay judgment value. The protection output module is used to output a protection shutdown signal when the actual drive propagation delay of the current shutdown is greater than the corresponding real-time drive delay judgment value for multiple consecutive control cycles, or when the dead time reaches the preset dead time upper limit and the actual drive propagation delay of the current shutdown is still greater than the corresponding real-time drive delay judgment value.

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