Control method of single-stage converter, single-stage converter and vehicle

Abstract

This application provides a control method for a single-stage converter, a single-stage converter, and a vehicle. Based on the control loop output value of the single-stage converter, it determines whether to use a continuous waveform generation mode or an intermittent waveform generation mode within the current power frequency cycle. When intermittent waveform generation mode is selected, at least one waveform generation phase interval within the current power frequency cycle is determined based on the control loop output value. The waveform generation phase interval is configured such that the hiccup position starts or ends at the zero-crossing point of the AC side voltage of the single-stage converter, and the hiccup phase is calculated based on the control loop output value. Wave generation occurs within the zero-crossing point region. Then, intermittent waveform generation control is performed on the single-stage converter according to the waveform generation phase interval. Based on this, waveform generation can occur in the zero-crossing point region, and waveform blocking occurs in the peak region, limiting the voltage across the inductor and effectively suppressing the AC side overcurrent problem during startup in forward charging mode, ensuring normal operation of the converter with a purely resistive load.

Description

Technical Field

[0001] This application relates to the field of voltage conversion technology, and in particular to a control method for a single-stage converter, a single-stage converter, and a vehicle. Background Technology

[0002] With the rapid development of automotive power electronics technology, increasingly higher requirements are being placed on converters. In forward operating mode, they are required not only to charge the power battery, but also to drive auxiliary loads. For example, when driving a PTC (Positive Temperature Coefficient) load that has a battery heating function, the normal operation of the PTC must also be guaranteed.

[0003] Since PTC loads are purely resistive loads, their voltage and other characteristics, as well as their impact on converter components, differ significantly from those of battery loads during startup, leading to startup overcurrent protection or high current surges.

[0004] Existing strategies for addressing startup overcurrent issues are not applicable to achieving reliable, shock-free startup of single-stage converters with purely resistive loads. Summary of the Invention

[0005] This application provides a control method for a single-stage converter, a single-stage converter, and a vehicle, to effectively suppress the problem of AC side overcurrent during startup in the forward charging mode.

[0006] In a first aspect, embodiments of this application provide a control method for a single-stage converter, including:

[0007] Based on the output value of the control loop of the single-stage converter, determine whether to use continuous wave generation mode or intermittent wave generation mode within the current power frequency cycle;

[0008] When the interval waveform mode is determined, at least one waveform phase interval within the current power frequency cycle is determined based on the control loop output value. The waveform phase interval is configured such that the hiccup position is the starting point or ending point of the zero-crossing point of the AC side voltage of the single-stage converter, and the hiccup phase is calculated according to the control loop output value, and a waveform is generated within the region of the zero-crossing point.

[0009] Based on the emission phase interval, interval emission control is performed on the single-stage converter.

[0010] Optionally, determining whether to use continuous or intermittent transmission mode within the current power frequency cycle based on the control loop output value of the single-stage converter includes:

[0011] When the output value of the control loop is greater than or equal to a first threshold, it is determined that the continuous transmission mode is adopted in the current power frequency cycle; the first threshold is a preset critical value between the continuous transmission mode and the interval transmission mode.

[0012] When the output value of the control loop is greater than 0 and less than the first threshold, it is determined that the interval transmission mode is adopted in the current power frequency cycle.

[0013] Optionally, determining at least one transmission phase interval within the current power frequency cycle based on the control loop output value includes:

[0014] Based on the output value of the control loop, the hiccup phase within half a cycle of the current power frequency cycle is determined;

[0015] Based on the hiccup phase and the position of the zero crossing point, two symmetrical wave emission phase intervals are generated within the half-cycle, such that the two wave emission phase intervals are located at the beginning and end of the half-cycle, respectively.

[0016] Optionally, determining the hiccup phase within half a cycle of the current power frequency cycle based on the control loop output value includes:

[0017] The hiccup phase is determined by multiplying the ratio of a preset reference phase value to a first threshold value with the output value of the control loop.

[0018] The step of generating two symmetrical wave phase intervals within the half-cycle based on the hiccup phase and the position of the zero crossing point includes:

[0019] Based on the hiccup phase and the position of the zero crossing point, the wave transmission phase interval within half a cycle of the current power frequency cycle is determined to be [0, hiccup phase] and [π-hiccup phase, π], wherein the hiccup phase is less than the reference phase value.

[0020] Optionally, before determining whether to use continuous or intermittent transmission mode within the current power frequency cycle based on the control loop output value of the single-stage converter, the method further includes:

[0021] Obtain the first control quantity output by the PI controller, which is determined based on the difference between the voltage reference value output by the voltage loop and the actual voltage value;

[0022] Obtain the second control quantity output by the PI controller, which is determined based on the difference between the current reference value output by the current loop and the actual current value;

[0023] The control loop output value is determined based on the smaller of the first control value and the second control value.

[0024] Secondly, this application provides a controller, including: a memory and a processor;

[0025] The memory stores computer-executed instructions;

[0026] The processor executes computer execution instructions stored in the memory, causing the processor to perform the method described in the first aspect.

[0027] Thirdly, this application provides a single-stage converter, including: a primary-side circuit, a center-tapped transformer, a secondary-side circuit, and the controller described in the second aspect;

[0028] The center tap of the center-tapped transformer is connected to the first terminal of the AC power supply.

[0029] The two input terminals of the primary circuit are respectively connected to the two ends of the primary winding of the center tap transformer, and the output terminal of the primary circuit is connected to the second terminal of the AC power supply.

[0030] The two input terminals of the secondary circuit are respectively connected to the two ends of the secondary winding of the center tap transformer, and the output terminal of the secondary circuit is used to connect to the load.

[0031] The controller is connected to the control terminals of each power switch in the primary circuit and the secondary circuit, and is configured to perform interval wave transmission control on each power switch according to the wave transmission phase interval.

[0032] Optionally, the primary-side circuit includes: a first bridge arm, a second bridge arm, and a third bridge arm;

[0033] The first end of the first bridge arm, the first end of the second bridge arm, and the third end of the third bridge arm are connected to each other; the second end of the first bridge arm, the second end of the second bridge arm, and the second end of the third bridge arm are connected to each other.

[0034] The midpoints of the first bridge arm and the second bridge arm serve as the two input terminals of the primary circuit, respectively, and the midpoint of the third bridge arm serves as the output terminal of the primary circuit.

[0035] The secondary-side circuit includes a fourth bridge arm and a fifth bridge arm;

[0036] The midpoint of the fourth bridge arm and the midpoint of the fifth bridge arm serve as the two input terminals of the secondary circuit, respectively.

[0037] The first end of the fourth bridge arm is connected to the first end of the fifth bridge arm, serving as one output terminal of the secondary circuit. The second end of the fourth bridge arm is connected to the second end of the fifth bridge arm, serving as the other output terminal of the secondary circuit.

[0038] Optionally, the first bridge arm includes a first switch and a second switch; a first end of the first switch is connected to a first end of the first bridge arm, and a second end of the first switch is connected to a first end of the second switch, serving as the midpoint of the first bridge arm; a second end of the second switch is connected to a second end of the first bridge arm.

[0039] The second bridge arm includes a third switch and a fourth switch; the first end of the third switch is connected to the first end of the second bridge arm, and the second end of the third switch is connected to the first end of the fourth switch, serving as the midpoint of the second bridge arm; the second end of the fourth switch is connected to the second end of the second bridge arm.

[0040] The fourth bridge arm includes a fifth switch and a sixth switch; the first end of the fifth switch is connected to the first end of the fourth bridge arm, and the second end of the fifth switch is connected to the first end of the sixth switch, serving as the midpoint of the fourth bridge arm; the second end of the sixth switch is connected to the second end of the fourth bridge arm.

[0041] The fifth bridge arm includes a seventh switch and an eighth switch; the first end of the seventh switch is connected to the first end of the fifth bridge arm, and the second end of the seventh switch is connected to the first end of the eighth switch, serving as the midpoint of the fifth bridge arm; the second end of the eighth switch is connected to the second end of the fifth bridge arm.

[0042] The third bridge arm includes a ninth switch and a tenth switch; the first end of the ninth switch is connected to the first end of the third bridge arm, and the second end of the ninth switch is connected to the first end of the tenth switch, serving as the midpoint of the third bridge arm; the second end of the tenth switch is connected to the second end of the third bridge arm.

[0043] Fourthly, this application provides a vehicle including the single-stage converter described in the third aspect.

[0044] Fifthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the first aspect and / or various possible implementations of the first aspect.

[0045] In a sixth aspect, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the first aspect and / or various possible implementations of the first aspect.

[0046] The control method, single-stage converter, and vehicle provided in this application determine whether to use continuous or intermittent waveform generation mode within the current power frequency cycle based on the control loop output value of the single-stage converter. When intermittent waveform generation mode is selected, at least one waveform generation phase interval within the current power frequency cycle is determined based on the control loop output value. The waveform generation phase interval is configured such that the hiccup position starts or ends at the zero-crossing point of the AC side voltage of the single-stage converter, and the hiccup phase is calculated based on the control loop output value, generating waveforms within the zero-crossing point region. Then, intermittent waveform generation control is performed on the single-stage converter according to the waveform generation phase interval. Based on this, waveforms can be generated in the zero-crossing point region and blocked in the peak region, limiting the voltage across the inductor and effectively suppressing the AC side overcurrent problem during startup in the forward charging mode, ensuring normal operation of the converter with a purely resistive load. Attached Figure Description

[0047] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0048] Figure 1 A flowchart of the single-stage converter provided in this application;

[0049] Figure 2 A schematic diagram of the emission phase interval provided in this application;

[0050] Figure 3 A schematic diagram of the control device for the single-stage converter provided in this application;

[0051] Figure 4 This is a schematic diagram of the controller provided in this application;

[0052] Figure 5 This is a schematic diagram of the single-stage converter provided in this application.

[0053] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0054] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0055] With the rapid development of automotive power electronics technology, the application scope of new energy vehicles is becoming increasingly wide, and the diverse application scenarios are placing increasingly higher demands on converters. In forward operating mode (charging mode, such as when the grid supplies electricity to the vehicle), it is required not only to have the ability to charge the power battery, but also to drive auxiliary loads. For example, when driving a PTC (Positive Temperature Coefficient) load that has the function of heating the battery, it is also necessary to ensure the normal operation of the PTC.

[0056] Because PTC loads are purely resistive loads, their voltage characteristics and impact on converter components (such as bus capacitors) differ significantly from those of battery loads during startup. In traditional two-stage converters consisting of a Dual Active Bridge (DAB) and a Power Factor Correction (PFC) stage, these characteristics can generate a large voltage drop across the DAB, leading to startup overcurrent protection or high current surges.

[0057] Existing strategies for addressing startup overcurrent issues typically include soft-start via DC bus capacitor voltage, adjusting switching frequency, and phase shifting, ultimately controlling the maximum inductor current. Soft-start via DC bus voltage involves controlling the PFC circuit to slowly increase its output voltage, thereby gradually reducing the voltage difference across the DAB. Adjusting the switching frequency or phase shift angle directly limits the rate of change of current in the power transfer inductor by changing the switching frequency of the DAB or the phase shift angle across the entire bridge.

[0058] In a traditional two-stage topology (DAB+PFC circuit), the above strategy enables the converter to operate stably under purely resistive load conditions.

[0059] However, for the new single-stage converter, (1) since the voltage difference across the inductor is mainly determined by the AC side voltage, the bus voltage, and the voltage across the load, due to its topological characteristics, the AC side voltage and the bus voltage (the bus voltage is close to 0 during startup) cannot be soft-started, and the load side voltage cannot suppress the inductor current overcurrent. Specifically, the AC input voltage originates from the power grid, and its amplitude and phase are uncontrollable; the DC bus voltage is approximately zero in the initial stage of startup, and its establishment process is limited by the circuit coupling relationship, so it cannot be soft-started independently; only the load side voltage is soft-started, which cannot change the main source of the voltage difference across the inductor, so it cannot effectively suppress the inrush current.

[0060] (2) Since the inductor of a single-stage converter is equivalent to that of a DAB, its inductance is less than half that of a traditional two-stage topology. Under the influence of a large port voltage difference at startup, even if the switching frequency is increased significantly or the phase shift angle is adjusted, the inductor current will still rise sharply and quickly reach the system protection threshold, resulting in startup failure.

[0061] Therefore, existing strategies for addressing startup overcurrent issues are not applicable to achieving reliable, shock-free startup of single-stage converters with purely resistive loads.

[0062] To address this issue, this application provides a control method for a unipolar converter. When the waveform generation mode is determined to be interval waveform generation mode based on the control loop output value, waveform generation occurs in the zero-crossing region, and waveform blocking occurs in the peak region, limiting the voltage across the inductor and effectively suppressing the AC side overcurrent problem during startup in forward charging mode. Compared to the traditional method of limiting the voltage difference across the inductor through soft start, the solution in this application provides a smooth startup current without large current surges, ensuring normal startup and guaranteeing normal operation of the converter with a purely resistive load.

[0063] Among them, the inductor voltage V L =L×di / dt,V L This is the voltage across the inductor, where L is the inductance value and di / dt is the rate of change of current. At peak voltage: assume the AC input voltage is Vac = Vpk × sin(θ). When θ = π / 2 (peak value), Vac ≈ Vpk. When the switching transistor is on: the voltage across the inductor V... L ≈Vpk (ignoring other voltage drops), and correspondingly the current rise rate di / dt = Vpk / L.

[0064] Under very high Vpk conditions, the inductor current will rise linearly at an extremely rapid rate. Even a very short conduction time can cause the current to surge to a dangerously high value, triggering overcurrent protection or damaging the device.

[0065] Near the zero-crossing point: θ≈0 or θ≈π, at which point Vac≈0. When the switching transistor is on: the voltage across the inductor V L ≈0. Correspondingly, the rate of rise of the current di / dt ≈ 0 / L ≈ 0. Therefore, near the zero crossing point, even if the controller outputs a large duty cycle, the inductor current will hardly rise rapidly.

[0066] The strategy of zero-crossing waveform generation and peak-suppression actively selects the moment when the inductor voltage is lowest for energy transfer. By controlling the waveform phase interval, the operation of the switching transistor is limited to a phase window with a very low Vac. In the peak region with a very high Vac, waveform suppression (preventing the switching transistor from conducting) fundamentally cuts off the voltage source that generates a large di / dt, thereby effectively clamping the current.

[0067] The technical solution of the present application and how the technical solution of the present application solves the above technical problems will be described in detail with specific embodiments below. These specific embodiments below can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0068] Figure 1 Flow schematic of the single-stage converter provided by the present application Figure 1 as Figure 1 shown, the method includes:

[0069] S101. Determine whether to adopt a continuous wave generation mode or an intermittent wave generation mode within the current power frequency cycle according to the output value of the control loop of the single-stage converter.

[0070] Among them, the output value of the control loop of the single-stage converter is generated based on the competition strategy of the voltage loop and the current loop in the charging mode, and is the competition result of the voltage loop and the current loop, which is an instruction signal for controlling the duty cycle of the power switch tube in the single-stage converter.

[0071] The current power frequency cycle refers to the cycle that is being controlled and processed in the AC side voltage cycle. The continuous wave generation mode means continuous wave generation within the current power frequency cycle, that is, continuously generating a high-frequency pulse width modulation signal to drive the power switch tube. The intermittent wave generation mode means non-continuous wave generation within the current power frequency cycle, and there is a period without wave generation, that is, switching between the wave generation phase interval and the wave blocking interval.

[0072] In some embodiments, when the output value of the control loop is greater than or equal to the first threshold, it is determined to adopt the continuous wave generation mode within the current power frequency cycle, and the first threshold is the critical value of the preset continuous wave generation mode and the intermittent wave generation mode; when the output value of the control loop is greater than 0 and less than the first threshold, it is determined to adopt the intermittent wave generation mode within the current power frequency cycle. Through the first threshold, the system can clearly switch between the two working modes when the load changes.

[0073] For example, assuming that the critical point between the intermittent wave generation mode and the continuous wave generation mode is dburst, then when the output value d of the control loop is greater than or equal to dburst, the single-stage converter will enter the continuous wave generation mode, and when 0 ≤ d < dburst, the single-stage converter will enter the Burst mode.

[0074] It should be noted that when the load power on the DC output side of the single-stage converter increases (for example, switching from the standby state to the normal working mode, or transitioning from the light load condition to the heavy load condition), the load will draw more current from the output capacitor, resulting in a downward trend in the DC output voltage of the converter.

[0075] As the outer loop control, the core responsibility of the voltage loop is to maintain the output voltage stable at the set value. Once a drop in output voltage is detected, the voltage loop error amplifier will rapidly increase its output signal, which represents the amount of power compensation required to compensate for the output voltage drop and maintain voltage regulation.

[0076] The current loop, as the inner loop control, primarily regulates the input current waveform to maintain it in phase with the input voltage waveform, thereby achieving a high power factor. The output signal of the current loop represents the upper limit of the instantaneous current (or duty cycle) allowed to meet the unity power factor constraint at the current instantaneous input voltage value.

[0077] The outputs of the voltage loop and the current loop typically employ a smaller selection mechanism, and the final loop control output value is determined by the competition between the two.

[0078] Based on the above mechanism, the dynamic level of the control loop output directly reflects the real-time power demand of the system: when the load is light, the voltage loop output is small, and the control loop output value is mainly determined by the voltage loop, resulting in a low overall level; as the load power increases, the power compensation required to maintain voltage regulation increases, and the voltage loop output continues to rise. When it exceeds the current loop output at certain phase points, the control loop output value will be clamped by the current loop output. At this time, the average value or envelope amplitude of the control loop output value over one power frequency cycle will increase synchronously with the increase in the overall power balance demand of the system.

[0079] Therefore, the average value or envelope of the control loop output value at the power frequency cycle is positively correlated with the load power. The greater the load power, the more energy the system needs to transfer, and the overall level of the duty cycle command generated by the control circuit (i.e., the control loop output value) will also increase accordingly.

[0080] In other embodiments, two different thresholds can be set, one as an upper threshold and the other as a lower threshold, with the lower threshold being less than or equal to the upper threshold. When the control loop output value crosses the upper threshold from below, a continuous waveform mode is selected; when the control loop output value crosses the lower threshold from above, a continuous waveform mode is selected. This effectively prevents frequent mode switching at critical load points due to noise or slight fluctuations, thus improving stability.

[0081] Optionally, a first control quantity is obtained from the output of the PI (Proportional-Integral Controller), which is determined based on the difference between the voltage reference value output by the voltage loop and the actual voltage value; a second control quantity is obtained from the output of the PI controller, which is determined based on the difference between the current reference value output by the current loop and the actual current value; and the control loop output value is determined based on the smaller of the first and second control quantities.

[0082] The first control variable (voltage loop PI output) directly reflects the total power requirement or average duty cycle reference needed to stabilize the DC output voltage. A larger value indicates a heavier load or a more severe output voltage drop, requiring the system to provide more power. The second control variable (current loop PI output) directly reflects the upper limit of the instantaneous duty cycle allowed at the current input voltage instantaneous value to achieve unity power factor; essentially, it is a sinusoidal reference in phase with the input voltage waveform.

[0083] By competing to select the control targets of the two synchronization loops, the system can prioritize power factor when the current loop has stricter constraints (such as near the peak of the input voltage), and stabilize the voltage while meeting the power factor requirements when the voltage loop has stricter requirements (such as near the zero-crossing point of the input voltage or under heavy load).

[0084] It should be noted that the PI controller is the core execution unit of loop control. Its function is to convert system deviation (error) into control commands with specific dynamic characteristics, thereby ensuring the stable and accurate operation of the system.

[0085] As long as the error exists, the integral term will continue to accumulate and output an ever-increasing control quantity until the error is completely eliminated (returns to zero). Whether it is the voltage loop or the current loop, the PI controller can ensure that the output voltage eventually stabilizes at the reference value and the input current eventually tracks the reference waveform.

[0086] The proportional term provides an immediate, proportional response to errors. The larger the error, the greater the adjustment range of the output control quantity, and the faster the response. When there are sudden load changes or input voltage fluctuations, the proportional term can quickly generate a large change in the control quantity, suppressing further expansion of the deviation and accelerating the system response speed.

[0087] For example, in the forward charging mode, a competitive strategy of voltage loop (i.e., voltage control loop) and current loop (i.e., current control loop) is used for control. The voltage loop calculates the difference between the battery voltage reference value and the actual battery voltage value. The resulting deviation is processed by the PI controller to obtain the first control quantity d1. The current loop calculates the difference between the battery current reference value and the actual battery current value. The resulting deviation is processed by the PI controller to obtain the second control quantity d2. The smaller of the first control quantity d1 and the second control quantity d2 is taken as the final output d of the loop, i.e., the control loop output value.

[0088] S102. When the interval waveform mode is determined, at least one waveform phase interval within the current power frequency cycle is determined based on the control loop output value. The hiccup position is taken as the zero-crossing point of the AC side voltage of the single-stage converter as the starting point or ending point. The hiccup phase is calculated according to the control loop output value, and the waveform is generated within the region of the zero-crossing point.

[0089] It should be noted that the waveform phase is updated every time the AC voltage zero-crossing is detected, meaning there is a corresponding waveform phase interval for each power frequency cycle. The phase interval outside the waveform phase interval within the current power frequency cycle is the waveform blocking interval.

[0090] The wave generation phase interval refers to the range of phase angles on the phase axis of the current power frequency cycle during which a high-frequency pulse drive signal is allowed to be output. The zero-crossing region of the AC side voltage refers to the interval where the voltage amplitude is close to 0 when the AC input voltage waveform switches from the positive half-cycle to the negative half-cycle (or from the negative half-cycle to the positive half-cycle).

[0091] In some embodiments, the hiccup phase within half a cycle of the current power frequency cycle is determined based on the control loop output value; and two symmetrical emission phase intervals within half a cycle are generated according to the hiccup phase and the position of the zero crossing point, such that the two emission phase intervals are located at the beginning and end of the half cycle, respectively.

[0092] For example, within half a cycle of [0, π], starting from the zero-crossing point, extending the hiccup phase 'a' forward yields the emission phase interval [0, a]; ending at the zero-crossing point, extending the hiccup phase 'a' backward yields the emission phase interval [π-a, π]. The initial segment begins at the zero-crossing point; the final segment ends at the zero-crossing point.

[0093] The algorithm only requires calculating a boundary phase 'a' based on the control loop output value. The boundary of the second interval can be obtained by a single subtraction of π - 'a', which minimizes the computational requirements of the processor and reduces the hardware cost of the system. Furthermore, it can achieve the goal of transmitting waves in the zero-crossing region. Since the two intervals are symmetrical and located at the beginning and end of half a cycle, the two transmission phase intervals are situated near the zero-crossing point.

[0094] It should be noted that, assuming a power frequency cycle is 2π, after determining the transmission phase interval of half a cycle of the current power frequency cycle, the transmission phase interval of the current power frequency cycle can be determined. The two transmission phase intervals of half a cycle are mirror images of each other. For example, the interval [0, a] of the positive half cycle corresponds to the interval [π, π+a] of the negative half cycle; the interval [π-a, π] of the positive half cycle corresponds to the interval [2π-a, 2π] of the negative half cycle. Accordingly, there are four transmission phase intervals for the entire power frequency cycle: [0, a], [π-a, π], [π, π+a], [2π-a, 2π], and two blocking intervals: (a, π-a) and (π+a, 2π-a).

[0095] In some examples, the hiccup phase is determined based on the product of the ratio of a preset reference phase value to a first threshold and the control loop output value. Correspondingly, based on the hiccup phase and the position of the zero crossing point, the wave generation phase interval within half a power frequency cycle of the current power frequency cycle is determined to be [0, hiccup phase] and [π - hiccup phase, π], where the hiccup phase is less than the reference phase value.

[0096] Based on a simple division operation, a monotonically decreasing convex function relationship is established, where the control loop output value is the independent variable and the boundary of the wave generation phase interval is the dependent variable. Then in the extremely light load region where efficiency is most sensitive, the algorithm can spontaneously compress the wave generation phase interval to the narrowest, being extremely sensitive to load changes. A slight increase in load immediately triggers a small expansion of the interval, achieving fine optimization of efficiency. When the control loop output value approaches the threshold, the wave generation phase interval approaches a full half cycle, smoothly approaching the continuous wave generation mode and avoiding current or voltage steps during mode switching.

[0097] Exemplarily, assume that a power frequency cycle is 2π, with π / 2 as unit 1, that is, the wave generation is symmetric centered on π / 2. Assume the loop output value d = dbrust, then waves will be generated throughout the 1 / 4 power frequency cycle of [0, π / 2], because symmetric wave generation occurs for half a power frequency cycle centered on π / 2, which means waves will also be generated throughout [π / 2, π], that is, half a power frequency cycle is in the continuous wave generation mode, and thus the entire power frequency cycle is in the continuous wave generation mode.

[0098] Assume the loop output value is d < dbrust, then the wave generation phase interval for half a power frequency cycle is [0, (π / 2) / dburst)×d] and [π - ((π / 2) / dburst)×d), π], and wave blocking will occur within the interval [((π / 2) / dburst)×d, π - ((π / 2) / dburst)×d], as Figure 2 shown, Figure 2 where θ1 is ((π / 2) / dburst)×d.

[0099] In other examples, the control loop output value is multiplied by a preset proportionality coefficient to obtain the hiccup phase. Specifically, it is preset that the hiccup phase a has a linear proportional relationship with the control loop output value d. That is, a = k×d, where k is the proportionality coefficient, and k = K (reference phase value) to satisfy a = K when d = 1, and the calculation is simple.

[0100] In other embodiments, a preset phase interval mapping table is consulted based on the control loop output value to obtain the corresponding emission phase interval parameters. Specifically, the control loop output value is pre-divided into several discrete levels through experiments. Each level corresponds to a set of preset emission phase interval boundary parameters (e.g., start angle and end angle), and these are stored in a table. During runtime, the emission phase interval is directly obtained by looking up the table based on the level to which the current control loop output value belongs. Based on this, complex online calculations can be bypassed, potentially resulting in a faster response speed. Furthermore, the optimal interval at each load point can be finely tuned experimentally, avoiding deviations from theoretical formulas.

[0101] For example, the power frequency cycle is divided into multiple sub-intervals, and the presence or absence of waveform generation within each sub-interval is dynamically adjusted based on the control loop output value, ensuring that the waveform phase interval avoids the peak voltage region on the AC side. Stepped waveform generation can more accurately match load requirements, reduce current fluctuations, and avoid current oscillations caused by abrupt changes in the waveform phase interval.

[0102] S103. Based on the emission phase interval, perform interval emission control on the single-stage converter.

[0103] For example, such as Figure 2 As shown, when the loop output value d = dburst, it is the boundary between continuous wave transmission mode and continuous wave transmission mode. When 0 ≤ d < dburst, the wave transmission phase is proportional to the loop output, where θ1 = ((π / 2) / dburst) × d. The wave transmission situation in the interval [π / 2, π] is symmetrical to that in [0, π / 2] about π / 2. Figure 3 The shaded area represents the wave generation phase interval, and the white area in the middle of the shaded area represents the wave blocking interval. This figure vividly illustrates the wave generation method of the optimized interval wave generation mode, which generates waves near the zero crossing point and blocks waves near the peak value, effectively reducing the voltage difference across the inductor and avoiding overcurrent phenomena.

[0104] For example, the inductor current of a single-stage converter is monitored in real time, and when an excessively rapid rise in inductor current is detected, the waveform phase interval within the current power frequency cycle is shortened or a waveform blocking state is entered. By adding hardware-level protection, the risk of overcurrent is further reduced, and the introduction of inductor current feedback can shorten the overcurrent response time to the microsecond level.

[0105] The control method for the single-stage converter provided in this application, when determining the wave generation mode as the interval wave generation mode based on the output value of the control loop, generates waves in the zero-crossing region and blocks waves in the peak region, limiting the voltage across the inductor and effectively suppressing the AC side overcurrent problem during startup in the forward charging mode.

[0106] The embodiments of this application are as follows: Figure 1Based on the embodiments shown, the control method for a single-stage converter provided in this application is further described. The control method for a single-stage converter provided in this application includes:

[0107] S201. Read the sampling data, which includes the actual voltage and current values ​​on the battery side.

[0108] For example, after entering the main interrupt, the sampled data is read. The main interrupt is a time-based interrupt, which is usually automatically triggered by a hardware timer (such as the PWM timer in the MCU, a general-purpose timer, or a dedicated ePWM module) configured to have a fixed period.

[0109] The sampled data is read immediately at the start of the interrupt, ensuring that all control variables are captured at strictly identical and deterministic times, thus eliminating calculation errors caused by asynchronous sampling.

[0110] S202, Execute the loop output section to obtain the control loop output value.

[0111] In forward charging mode, a competition strategy between the voltage loop and the current loop is used for control. The voltage control loop calculates the difference between the battery voltage reference value Vbattref and the actual battery voltage value Vbattreal, and the resulting deviation is processed by the PI controller to obtain d1. The current control loop calculates the difference between the battery current reference value Ibattref and the actual battery current value Ibattreal, and the resulting deviation is processed by the PI controller to obtain d2. The smaller of d1 and d2 is taken as the final output d of the loop.

[0112] S203. Determine whether the output value of the control loop is less than the critical point.

[0113] The critical point, also known as the first threshold mentioned above, can be determined based on the actual situation and is not limited here.

[0114] S204. When the output value of the control loop is greater than 0 and less than the critical point, the interval wave generation mode is determined to be used.

[0115] Then, proceed to step S206.

[0116] S205. When the output value of the control loop is greater than or equal to the critical point, the continuous wave generation mode is determined to be used.

[0117] Then, proceed to step S207.

[0118] S206. Based on the output value of the control loop, determine at least one wave transmission phase interval within the current power frequency cycle, perform wave transmission control on the single-stage converter within the wave transmission phase interval, and stop wave transmission within the wave blocking interval.

[0119] S207. Continue to generate waves within the current power frequency cycle.

[0120] The control method for a single-stage converter provided in this application selects the timing of wave generation based on the characteristics of the input voltage, generates waves near the zero-crossing point of the AC voltage, and determines the phase magnitude of the wave generation based on the closed-loop control output to limit the voltage across the inductor, effectively suppressing the AC side overcurrent problem during startup in the forward charging mode.

[0121] Figure 3 A schematic diagram of the control device for the single-stage converter provided in this application is shown below. Figure 3 As shown, the control device 40 for the single-stage converter provided in this embodiment includes:

[0122] The first processing module 41 is used to determine whether to use continuous wave generation mode or intermittent wave generation mode in the current power frequency cycle based on the control loop output value of the single-stage converter; wherein, the control loop output value is obtained in the charging mode by using a voltage loop and current loop competition control strategy;

[0123] The second processing module 42 is used to determine at least one transmission phase interval within the current power frequency cycle based on the control loop output value when the interval transmission mode is determined to be adopted. The transmission phase interval is configured such that the hiccup position is the starting point or ending point of the zero crossing point of the AC side voltage of the single-stage converter, and the hiccup phase is calculated according to the control loop output value, and the transmission is performed within the region of the zero crossing point.

[0124] The third processing module 43 is used to perform interval wave transmission control on the single-stage converter according to the wave transmission phase interval.

[0125] In one possible implementation, the first processing module 41 is specifically used to determine that a continuous wave transmission mode is adopted in the current power frequency cycle when the output value of the control loop is greater than or equal to a first threshold; the first threshold is a preset threshold between the continuous wave transmission mode and the interval wave transmission mode.

[0126] When the output value of the control loop is greater than 0 and less than the first threshold, the interval transmission mode is determined to be used in the current power frequency cycle.

[0127] In one possible implementation, the second processing module 42 is specifically used to determine the hiccup phase within half a cycle of the current power frequency cycle based on the output value of the control loop; and to generate two symmetrical emission phase intervals within half a cycle according to the hiccup phase and the position of the zero crossing point, such that the two emission phase intervals are located at the beginning and end of the half cycle, respectively.

[0128] In one possible implementation, the second processing module 42 is specifically used to determine the hiccup phase based on the product between the ratio of a preset reference phase value and a first threshold value and the output value of the control loop.

[0129] Based on the hiccup phase and the position of the zero crossing, the wave generation phase interval within half a cycle of the current power frequency cycle is determined to be [0, hiccup phase] and [π-hiccup phase, π], where the hiccup phase is less than the reference phase value.

[0130] In one possible implementation, the first processing module 41 is further configured to acquire a first control quantity output by the PI controller, the first control quantity being determined based on the difference between the voltage reference value output by the voltage loop and the actual voltage value.

[0131] Obtain the second control value output by the PI controller. The second control value is determined based on the difference between the current reference value output by the current loop and the actual current value.

[0132] The control loop output value is determined based on the smaller of the first control value and the second control value.

[0133] The control device for the single-stage converter provided in this embodiment can execute the method provided in the above method embodiment. Its implementation principle and technical effect are similar, and will not be described in detail here.

[0134] Figure 4 This is a schematic diagram of the controller provided in this application. Figure 4 As shown, the controller 50 provided in this embodiment includes at least one processor 501 and a memory 502. Optionally, the controller 50 further includes a communication component 503. The processor 501, memory 502, and communication component 503 are connected via a bus.

[0135] In a specific implementation, at least one processor 501 executes computer execution instructions stored in memory 502, causing at least one processor 501 to perform the above-described method.

[0136] The specific implementation process of processor 501 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0137] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0138] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0139] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0140] Figure 5 A schematic diagram of the single-stage converter provided in this application is shown below. Figure 5 As shown, the single-stage converter provided in this application embodiment includes:

[0141] Primary circuit 101, center tap transformer 102, secondary circuit 103, and the aforementioned controller (not shown in the figure).

[0142] The center tap of the center-tapped transformer 102 is connected to the first terminal of the AC power supply.

[0143] The two input terminals of the primary circuit 101 are respectively connected to the two ends of the primary winding of the center tap transformer 102, and the output terminal of the primary circuit 101 is connected to the second end of the AC power supply.

[0144] The two input terminals of the secondary circuit 103 are respectively connected to the two ends of the secondary winding of the center tap transformer 102, and the output terminal of the secondary circuit 103 is used to connect the load.

[0145] The controller connects to the control terminals of each power switch in the primary circuit 101 and the secondary circuit 103, and is configured to perform interval wave transmission control on each power switch according to the wave transmission phase interval.

[0146] In this embodiment, the controller controls the on / off state of each power switch based on the wave generation phase interval. The wave generation phase interval is configured to generate waves in the zero-crossing region and block waves in the peak region. Therefore, it can limit the voltage across the inductor in the single-stage converter and effectively suppress the AC side overcurrent problem during the startup of the single-stage converter in the forward charging mode.

[0147] For example, the load can be a battery or other electrical equipment.

[0148] Optionally, the primary-side circuit 101 includes a first bridge arm, a second bridge arm, and a third bridge arm; the first ends of the first bridge arm, the first ends of the second bridge arm, and the first ends of the third bridge arm are interconnected, and the second ends of the first bridge arm, the second ends of the second bridge arm, and the second ends of the third bridge arm are interconnected; the midpoints of the first and second bridge arms serve as the two input terminals of the primary-side circuit 101, respectively, and the terminal of the third bridge arm serves as the output terminal of the primary-side circuit 101. Based on this, while achieving flexible and coordinated power supply from dual input sources, the system cost, size, and complexity are significantly reduced, and the integration and reliability of the control are improved.

[0149] For example, the primary-side circuit 101 includes a first input terminal and a second input terminal, the midpoint of the first bridge arm serves as the first input terminal A of the primary-side circuit 101, and the midpoint of the second bridge arm serves as the second input terminal B of the primary-side circuit 101.

[0150] In some examples, the first bridge arm includes a first switch Q1 and a second switch Q2; the first end of the first switch Q1 is connected to the first end of the first bridge arm, and the second end of the first switch Q1 is connected to the first end of the second switch Q2, serving as the midpoint of the first bridge arm; the second end of the second switch Q2 is connected to the second end of the first bridge arm.

[0151] The second bridge arm includes a third switch Q3 and a fourth switch Q4; the first end of the third switch Q3 is connected to the first end of the second bridge arm, and the second end of the third switch Q3 is connected to the first end of the fourth switch Q4, serving as the midpoint between the first and second bridge arms; the second end of the fourth switch Q4 is connected to the second end of the second bridge arm.

[0152] The third bridge arm includes a ninth switch Q9 and a tenth switch Q10; the first end of the ninth switch Q9 is connected to the first end of the third bridge arm, and the second end of the ninth switch Q9 is connected to the first end of the tenth switch Q10, serving as the midpoint of the third bridge arm; the second end of the tenth switch Q10 is connected to the second end of the third bridge arm.

[0153] Optionally, the secondary circuit 103 includes a fourth bridge arm and a fifth bridge arm; the midpoint of the fourth bridge arm and the midpoint of the fifth bridge arm serve as two input terminals of the secondary circuit 103, respectively; the first end of the fourth bridge arm and the first end of the fifth bridge arm are connected to serve as one output terminal of the secondary circuit 103, and the second end of the fourth bridge arm and the second end of the fifth bridge arm are connected to serve as the other output terminal of the secondary circuit 103.

[0154] For example, the first end of the fourth bridge arm and the first end of the fifth bridge arm are connected as the first output terminal C of the secondary circuit 103, and the second end of the fourth bridge arm and the second end of the fifth bridge arm are connected as the second output terminal D of the secondary circuit 103.

[0155] In some examples, the fourth bridge arm includes a fifth switch Q5 and a sixth switch Q6; the first end of the fifth switch Q5 is connected to the first end of the fourth bridge arm, and the second end of the fifth switch Q5 is connected to the first end of the sixth switch Q6, serving as the midpoint of the fourth bridge arm; the second end of the sixth switch Q6 is connected to the second end of the fourth bridge arm.

[0156] The fifth bridge arm includes a seventh switch Q7 and an eighth switch Q8; the first end of the seventh switch Q7 is connected to the first end of the fifth bridge arm, and the second end of the seventh switch Q7 is connected to the first end of the eighth switch Q8, serving as the midpoint of the fifth bridge arm; the second end of the eighth switch Q8 is connected to the second end of the fifth bridge arm.

[0157] It should be noted that the first switch Q1, the second switch Q2, the third switch Q3, the fourth switch Q4, the fifth switch Q5, the sixth switch Q6, the seventh switch Q7, and the eighth switch Q8 are fast-cycle switching transistors, while the ninth switch Q9 and the tenth switch Q10 are slow-cycle switching transistors at power frequency.

[0158] For example, each switch may include at least one of Si MOS (Metal Oxide Semiconductor), SiC MOS, IGBT (Insulated Gate Bipolar Transistor), and FRD (Fast Recovery Diode). The source of the MOS transistor may serve as the first terminal of the corresponding switch, and the drain of the MOS transistor may serve as the second terminal of the corresponding switch.

[0159] For example, a single-stage converter may also include a filtering unit, which includes a filtering inductor Lac and a filtering capacitor Cac. The filtering inductor Lac is connected between the first terminal of the AC power supply and the center tap, and the filtering capacitor Cac is connected between the first terminal and the second terminal of the AC power supply, thereby achieving a filtering effect on the AC power supplied by the AC power supply.

[0160] For example, the primary-side circuit 101 may include a bus capacitor Cbus, which is connected between the first and second ends of the third bridge arm. It is a filter / energy storage capacitor that connects the AC power supply and the power conversion circuit, and is used to stabilize the bus voltage, filter out high-frequency ripple and buffer energy fluctuations.

[0161] For example, the single-stage converter also includes a first inductor L1 and a second inductor L2. The first inductor L1 is connected between the first input terminal of the primary circuit 101 and the first terminal of the primary winding, and the second inductor L2 is connected between the second input terminal of the primary circuit 101 and the second terminal of the primary winding. The first inductor L1 and the second inductor L2 are used to achieve current symmetry balance, bidirectional energy transfer, ripple suppression, and switch protection.

[0162] For example, the primary winding of the center-tapped transformer 102 includes a first primary winding and a second primary winding. The same-name terminal of the first primary winding serves as the first terminal of the primary winding, and the same-name terminal of the second primary winding is connected to the opposite-name terminal of the first primary winding and connected to the center tap. The opposite-name terminal of the second primary winding serves as the second terminal of the primary winding. The same-name terminal of the secondary winding is connected to the first input terminal of the secondary circuit 101, and the opposite-name terminal of the secondary winding is connected to the second input terminal of the secondary circuit 101. Through the primary and secondary windings, voltage conversion can be achieved, for example, the voltage can be increased or decreased to convert the voltage to the voltage required by the load.

[0163] For example, the single-stage converter also includes a DC blocking capacitor C1, which is connected between the first end of the secondary winding and the first output end of the secondary circuit 103, allowing AC signals to pass through and DC current to pass through, ensuring the correct transmission of signals and the normal operation of the circuit.

[0164] For example, a filter unit is provided between the output terminal of the secondary circuit 103 and the load. The filter unit here includes a filter capacitor Cdc and a filter inductor Cdc. The filter capacitor Cdc is connected between the first output terminal and the second output terminal of the secondary circuit 103, and the filter inductor Cdc is connected between the first output terminal of the secondary circuit 103 and the load (such as the positive terminal of an electrode), so as to achieve a filtering effect on the output DC current of the secondary circuit 103.

[0165] For example, the controller connects to the control terminal (gate) of each power switch through its output port, and generates a drive signal based on the emission phase interval and closed-loop control results to control the on / off state of each switch.

[0166] Specifically, the controller tracks the AC side voltage phase in real time and calculates the current power frequency phase angle θ. By comparing θ with the waveform phase interval, a binary waveform enable signal is generated. When θ is within any waveform phase interval, the signal is valid (e.g., high level), allowing the output of PWM pulses; otherwise, the signal is invalid (e.g., low level), forcibly turning off all relevant switches (i.e., waveform blocking).

[0167] Within the effective phase range of the waveform enable, the controller synchronously executes the closed-loop control algorithm to determine the duty cycle command required for the current switching cycle. For example, the voltage loop compares the actual output voltage value with the voltage reference value, and the deviation is processed by a PI regulator and output as a reference command for the current inner loop. This command reflects the instantaneous power required by the system to maintain voltage regulation. The current inner loop compares the actual input current value with the current reference value, and the deviation is processed by another PI regulator to directly generate a real-time duty cycle command to achieve fast and accurate current tracking.

[0168] The controller's PWM modulation module receives two core input ripple enable signals and a duty cycle command. During the enable signal's active period, it generates a high-frequency PWM pulse sequence with the corresponding duty cycle; during the enable signal's inactive period, it outputs a constant off-level. The resulting final drive pulse signal is applied to the control terminal of the corresponding switching transistor, precisely controlling its on / off timing. This achieves the control objective of both efficient energy transfer within a specified phase range and meeting the system's voltage regulation and current limiting requirements.

[0169] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0170] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.

[0171] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0172] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0173] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0174] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0175] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0176] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0177] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0178] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A control method of a single-stage converter, characterized by, include: Based on the control loop output value of the single-stage converter, it is determined whether to use continuous wave generation mode or intermittent wave generation mode within the current power frequency cycle; wherein, the control loop output value is obtained in charging mode using a voltage loop and current loop competitive control strategy; When the interval waveform mode is determined, at least one waveform phase interval within the current power frequency cycle is determined based on the control loop output value. The waveform phase interval is configured such that the hiccup position is the starting point or ending point of the zero-crossing point of the AC side voltage of the single-stage converter, and the hiccup phase is calculated according to the control loop output value, and a waveform is generated within the region of the zero-crossing point. Based on the emission phase interval, interval emission control is performed on the single-stage converter.

2. The method of claim 1, wherein, The step of determining whether to use continuous or intermittent transmission mode within the current power frequency cycle based on the control loop output value of the single-stage converter includes: When the output value of the control loop is greater than or equal to a first threshold, it is determined that the continuous transmission mode is adopted in the current power frequency cycle; the first threshold is a preset critical value between the continuous transmission mode and the interval transmission mode. When the output value of the control loop is greater than 0 and less than the first threshold, it is determined that the interval transmission mode is adopted in the current power frequency cycle.

3. The method according to claim 1 or 2, characterized in that, Determining at least one transmission phase interval within the current power frequency cycle based on the control loop output value includes: Based on the output value of the control loop, the hiccup phase within half a cycle of the current power frequency cycle is determined; Based on the hiccup phase and the position of the zero crossing point, two symmetrical wave emission phase intervals are generated within the half-cycle, such that the two wave emission phase intervals are located at the beginning and end of the half-cycle, respectively.

4. The method of claim 3, wherein, Determining the hiccup phase within half a cycle of the current power frequency cycle based on the control loop output value includes: The hiccup phase is determined by multiplying the ratio of a preset reference phase value to a first threshold value with the output value of the control loop. The step of generating two symmetrical wave phase intervals within the half-cycle based on the hiccup phase and the position of the zero crossing point includes: Based on the hiccup phase and the position of the zero crossing point, the wave transmission phase interval within half a cycle of the current power frequency cycle is determined to be [0, hiccup phase] and [π-hiccup phase, π], wherein the hiccup phase is less than the reference phase value.

5. The method according to claim 1, characterized in that, Before determining whether to use continuous or intermittent transmission mode within the current power frequency cycle based on the control loop output value of the single-stage converter, the process also includes: Obtain the first control quantity output by the PI controller, which is determined based on the difference between the voltage reference value output by the voltage loop and the actual voltage value; Obtain the second control quantity output by the PI controller, which is determined based on the difference between the current reference value output by the current loop and the actual current value; The control loop output value is determined based on the smaller of the first control value and the second control value.

6. A controller, characterized in that, include: Memory, processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory, causing the processor to perform the method as described in any one of claims 1-5.

7. A single-stage converter, characterized in that, include: The primary circuit, the center-tapped transformer, the secondary circuit, and the controller as described in claim 6; The center tap of the center-tapped transformer is connected to the first terminal of the AC power supply. The two input terminals of the primary circuit are respectively connected to the two ends of the primary winding of the center tap transformer, and the output terminal of the primary circuit is connected to the second terminal of the AC power supply. The two input terminals of the secondary circuit are respectively connected to the two ends of the secondary winding of the center tap transformer, and the output terminal of the secondary circuit is used to connect to the load. The controller is connected to the control terminals of each power switch in the primary circuit and the secondary circuit, and is configured to perform interval wave transmission control on each power switch according to the wave transmission phase interval.

8. The single-stage converter according to claim 7, characterized in that, The primary-side circuit includes: a first bridge arm, a second bridge arm, and a third bridge arm; The first end of the first bridge arm, the first end of the second bridge arm, and the third end of the third bridge arm are connected to each other; the second end of the first bridge arm, the second end of the second bridge arm, and the second end of the third bridge arm are connected to each other. The midpoints of the first bridge arm and the second bridge arm serve as the two input terminals of the primary circuit, respectively, and the midpoint of the third bridge arm serves as the output terminal of the primary circuit. The secondary-side circuit includes a fourth bridge arm and a fifth bridge arm; The midpoint of the fourth bridge arm and the midpoint of the fifth bridge arm serve as the two input terminals of the secondary circuit, respectively. The first end of the fourth bridge arm is connected to the first end of the fifth bridge arm, serving as one output terminal of the secondary circuit. The second end of the fourth bridge arm is connected to the second end of the fifth bridge arm, serving as the other output terminal of the secondary circuit.

9. The single-stage converter according to claim 8, characterized in that, The first bridge arm includes a first switch and a second switch; the first end of the first switch is connected to the first end of the first bridge arm, and the second end of the first switch is connected to the first end of the second switch, serving as the midpoint of the first bridge arm; the second end of the second switch is connected to the second end of the first bridge arm. The second bridge arm includes a third switch and a fourth switch; the first end of the third switch is connected to the first end of the second bridge arm, and the second end of the third switch is connected to the first end of the fourth switch, serving as the midpoint of the second bridge arm; the second end of the fourth switch is connected to the second end of the second bridge arm. The fourth bridge arm includes a fifth switch and a sixth switch; the first end of the fifth switch is connected to the first end of the fourth bridge arm, and the second end of the fifth switch is connected to the first end of the sixth switch, serving as the midpoint of the fourth bridge arm; the second end of the sixth switch is connected to the second end of the fourth bridge arm. The fifth bridge arm includes a seventh switch and an eighth switch; the first end of the seventh switch is connected to the first end of the fifth bridge arm, and the second end of the seventh switch is connected to the first end of the eighth switch, serving as the midpoint of the fifth bridge arm; the second end of the eighth switch is connected to the second end of the fifth bridge arm. The third bridge arm includes a ninth switch and a tenth switch; the first end of the ninth switch is connected to the first end of the third bridge arm, and the second end of the ninth switch is connected to the first end of the tenth switch, serving as the midpoint of the third bridge arm; the second end of the tenth switch is connected to the second end of the third bridge arm.

10. A vehicle, characterized in that, Includes the single-stage converter according to any one of claims 7-9.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1-5.

12. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method described in any one of claims 1-5.

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