Power tube on power protection circuit, chip and electronic equipment

Abstract

A power tube power-on protection circuit, chip and electronic equipment belong to the technical field of electronic circuit, the power tube is powered on based on the supply voltage, and the power tube includes a high-side drive tube and a low-side drive tube, the voltage of the first node connected by the high-side drive tube and the low-side drive tube is the port voltage; the first voltage is the port voltage after current limiting of the resistance component; the first switch circuit outputs the first switch signal in response to that the first voltage is greater than the preset value, so that the high-side drive tube is turned on; the second switch circuit outputs the second switch signal in response to that the first voltage is greater than the preset value, so that the low-side drive tube is turned on; the under-voltage protection circuit stops pulling down the first voltage to the power supply ground in response to that the supply voltage is less than the preset voltage; the possibility of false opening and damage of the power device connected with the first node is reduced, and the reliability of the system is improved.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to a power transistor power-on protection circuit, chip and electronic equipment. Background Technology

[0002] When a high-voltage signal is connected to the high-voltage terminal of a power device (such as the collector of an insulated-gate bipolar transistor (IGBT) or the drain of a metal-oxide-semiconductor (MOS) transistor), this high-voltage signal may power on faster than the power supply of the gate driver chip when the system is powered on. At this time, the output terminal (port voltage) of the gate driver chip is in a floating state. When the high-voltage terminal of the power device rises rapidly, there is a parasitic capacitance between the high-voltage terminal and the gate of the power device. This rapidly rising voltage will affect the gate of the power device through the Miller effect of the parasitic capacitance, causing the gate voltage of the power device to rise accordingly. Before the chip's power supply reaches normal operating conditions, the output terminal of the driver chip cannot effectively control the gate voltage of the power device. When the gate voltage of the power device rises above the threshold voltage of the power device, the power device turns on. This abnormal turn-on can easily damage the power device.

[0003] Therefore, there is an urgent need to provide a power transistor power-on protection circuit to reduce the possibility of power devices being turned on accidentally and damaged. Summary of the Invention

[0004] The purpose of this application is to provide a power transistor power-on protection circuit, chip, and electronic device, which aims to solve the problem that related power transistor power-on protection circuits cannot reduce the possibility of power devices being turned on and damaged by accident.

[0005] This application provides a power transistor power-on protection circuit. The power transistor is powered on based on the supply voltage, and the power transistor includes a high-side driving transistor and a low-side driving transistor. The voltage of the first node where the high-side driving transistor and the low-side driving transistor are connected is the port voltage. The power transistor power-on protection circuit includes a resistor assembly, a first switching circuit, a second switching circuit, and an undervoltage protection circuit. A first switching circuit is connected to the resistor assembly and the high-side driving transistor. In response to a first voltage being greater than a preset value, it outputs a first switching signal to turn on the high-side driving transistor. The first voltage is the port voltage of the resistor assembly after current limiting. The second switching circuit is connected to the resistor assembly and the low-side driving transistor. In response to the first voltage being greater than a preset value, it outputs a second switching signal to turn on the low-side driving transistor. The undervoltage protection circuit, in response to the supply voltage being less than a preset voltage, stops pulling the first voltage down to the power supply ground.

[0006] In one embodiment, the undervoltage protection circuit is specifically used to pull the first voltage down to power ground in response to the supply voltage being greater than a preset voltage; The first switching circuit, in response to the first voltage after pull-down, disconnects the first switching signal so that the high-side driving transistor can operate normally; The second switching circuit, in response to the first voltage after pull-down, disconnects the second switching signal to enable the low-side drive transistor to operate normally.

[0007] In one embodiment, the undervoltage protection circuit includes: A current mirror is used to connect to the supply voltage, shift the supply voltage to output a first shifted voltage, and mirror the first current to output a second current. A voltage divider circuit, connected to the current mirror, is used to output a first current based on the first shift voltage, and to divide the first shift voltage to output a voltage divider signal. The third switching circuit is connected to the voltage divider circuit and shares a second node with the current mirror. It is used to stop transmitting the second current to the power supply ground in response to the voltage divider signal being less than the threshold voltage, so that the current mirror pulls up the voltage of the second node, and outputs a switching signal from the second node. An inverter, connected to the second node, the current mirror, and the third switching circuit, is used to invert the switching signal to output a first decision signal; The fourth switching circuit, in response to the first decision signal, pulls the first voltage down to the power supply ground; Wherein, when the supply voltage is less than the preset voltage, the voltage divider signal is less than the threshold voltage.

[0008] In one embodiment, the undervoltage protection circuit further includes: A potential shifting circuit, connected to the voltage divider circuit and the power supply ground, is used to shift the potential of the power supply ground to output a second shifted voltage. The voltage divider circuit is specifically used to output the first current based on the voltage difference between the first shift voltage and the second shift voltage, and to divide the voltage difference between the first shift voltage and the second shift voltage to output the voltage divider signal.

[0009] In one embodiment, the undervoltage protection circuit further includes: The regulating circuit, in response to the switching signal, adjusts the voltage division coefficient of the voltage divider circuit; The voltage divider circuit is specifically used to output a first current based on the first shifted voltage, and to divide the first shifted voltage based on the adjusted voltage division coefficient to output a voltage divider signal.

[0010] In one embodiment, the current mirror includes a first PMOS transistor and a second PMOS transistor; The source of the first PMOS transistor and the source of the second PMOS transistor are connected and together form the power supply terminal of the current mirror to receive the supply voltage; the gate, drain, and gate of the first PMOS transistor are connected and together form the first terminal of the current mirror, which is connected to the voltage divider circuit to receive the first current and output the first shifted voltage; the drain of the second PMOS transistor forms the second terminal of the current mirror, which is connected to the switching circuit and the second node to output the second current and the switching signal.

[0011] In one embodiment, the first switching circuit includes a first NMOS transistor; The gate of the first NMOS transistor forms the control terminal of the first switching circuit, and is connected to the undervoltage protection circuit and the resistor assembly to receive the first voltage; The drain of the first NMOS transistor forms the first terminal of the first switching circuit and is connected to the gate of the high-side driving transistor to output the first switching signal. The source of the first NMOS transistor is connected to the power supply ground.

[0012] In one embodiment, the second switching circuit includes a second NMOS transistor, a third PMOS transistor, and a first resistor; The gate of the second NMOS transistor N2 forms the control terminal of the second switching circuit, and is connected to the undervoltage protection circuit and the resistor assembly to receive the first voltage; The first end of the first resistor and the drain of the third PMOS transistor are connected to form the first end of the second switching circuit, which is connected to the power transistor and the undervoltage protection circuit to access the power supply voltage. The drain of the second NMOS transistor is connected to the second terminal of the first resistor and the gate of the third PMOS transistor; The source of the third PMOS transistor forms the second terminal of the second switching circuit and is connected to the gate of the low-side driving transistor to output the second switching signal.

[0013] This invention also provides a chip, which includes the power transistor power-on protection circuit described above.

[0014] This invention also provides an electronic device, which includes the power transistor power-on protection circuit described above.

[0015] The beneficial effects of this invention compared to the prior art are as follows: Since the first voltage is the port voltage after current limiting by the resistor component, the second switching circuit responds to the first voltage being greater than a preset value by outputting a second switching signal to turn on the low-side driving transistor, effectively controlling the gate voltage of the external power device, causing the gate voltage of the power device to drop below the threshold voltage of the power device, reducing the possibility of the power device being turned on incorrectly or damaged; at the same time, the first switching circuit responds to the first voltage being greater than a preset value by outputting a first switching signal to turn on the high-side driving transistor, thereby causing the supply voltage to drop along with the voltage of the first node; thus improving the reliability of the power transistor power-on protection circuit. Attached Figure Description

[0016] To more clearly illustrate the technical inventions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of a power transistor power-on protection circuit provided in an embodiment of this application; Figure 2 This is a schematic diagram of an undervoltage protection circuit in a power transistor power-on protection circuit provided in an embodiment of this application; Figure 3 This is a schematic diagram of another structure of the undervoltage protection circuit in the power transistor power-on protection circuit provided in an embodiment of this application; Figure 4 This is a schematic diagram of another structure of the undervoltage protection circuit in the power transistor power-on protection circuit provided in an embodiment of this application; Figure 5 This is a partial example circuit schematic diagram of a power transistor power-on protection circuit provided in an embodiment of this application. Detailed Implementation

[0018] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0019] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0020] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] Furthermore, the terms "first" and "second" are configured for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0022] Figure 1 A schematic diagram of the power transistor power-on protection circuit provided in a preferred embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below: The power transistor power-on protection circuit described above is based on the supply voltage. The power transistor includes a high-side driving transistor P01 and a low-side driving transistor N01. The voltage of the first node A, which is connected to both the high-side driving transistor P01 and the low-side driving transistor N01, is the port voltage. The power transistor power-on protection circuit includes a resistor assembly 10, a first switching circuit 20, a second switching circuit 30, and an undervoltage protection circuit 40.

[0023] The first switching circuit 20 is connected to the resistor assembly 10 and the high-side driving transistor P01. In response to a first voltage being greater than a preset value, it outputs a first switching signal to turn on the high-side driving transistor P01. The first voltage is the port voltage of the resistor assembly 10 after current limiting.

[0024] The second switching circuit 30 is connected to the resistor assembly 10 and the low-side drive transistor N01. In response to the first voltage being greater than a preset value, it outputs a second switching signal to turn on the low-side drive transistor N01.

[0025] The undervoltage protection circuit 40 stops pulling the first voltage down to ground in response to the supply voltage being lower than the preset voltage.

[0026] It is understood that the first node A is connected to the gate of the power device (not shown in the figure). When the supply voltage is less than the preset voltage, the undervoltage protection circuit 40 stops pulling the first voltage down to the power supply ground, turns on the first switching circuit 20 and the second switching circuit 30, and then outputs a switching signal to turn on the power transistor.

[0027] Through the above technical solution, since the first voltage is the port voltage after current limiting by the resistor component 10, the second switching circuit 30 responds to the first voltage being greater than the preset value by outputting a second switching signal to turn on the low-side driving transistor N01, effectively controlling the gate voltage of the external power device, so that the gate voltage of the power device drops below the threshold voltage of the power device, reducing the possibility of the power device being turned on incorrectly and damaged; at the same time, the first switching circuit 20 responds to the first voltage being greater than the preset value by outputting a first switching signal to turn on the high-side driving transistor P01, thereby causing the supply voltage to drop along with the voltage of the first node A; thus improving the reliability of the power transistor power-on protection circuit.

[0028] In one embodiment, the undervoltage protection circuit 40 is specifically configured to pull down a first voltage to power ground in response to a supply voltage greater than a preset voltage.

[0029] The first switching circuit 20, in response to the first voltage after pull-down, disconnects the first switching signal so that the high-side drive transistor P01 can work normally.

[0030] The second switching circuit 30, in response to the first voltage after pull-down, disconnects the second switching signal so that the low-side power transistor can operate normally.

[0031] With the above technical solution, when the power supply voltage is greater than the preset voltage after power-on, the undervoltage protection circuit 40 pulls the first voltage down to the power supply ground, so that the first switching circuit 20 and the second switching circuit 30 stop working, thereby allowing the high-side drive transistor P01 and the low-side power transistor to work normally.

[0032] like Figure 2 As shown, the undervoltage protection circuit 40 includes a current mirror 41, a voltage divider circuit 42, a third switching circuit 43, an inverter 44, and a fourth switching circuit 45.

[0033] The current mirror 41 is used to connect to the power supply voltage, and to perform potential shifting on the power supply voltage to output a first shifted voltage, and to mirror the first current to output a second current.

[0034] Voltage divider circuit 42, connected to current mirror 41, is used to output a first current based on a first shift voltage, and to divide the first shift voltage to output a voltage divider signal.

[0035] The third switching circuit 43 is connected to the voltage divider circuit 42 and is connected to the second node B along with the current mirror 41. It is used to stop transmitting the second current to the power supply ground in response to the voltage divider signal being less than the threshold voltage, so that the current mirror 41 pulls up the voltage of the second node B and outputs a switching signal from the second node B.

[0036] Inverter 44, connected to the second node B, current mirror 41 and third switching circuit 43, is used to invert the switching signal to output the first decision signal.

[0037] The fourth switching circuit 45, in response to the first decision signal, pulls the first voltage down to the power supply ground.

[0038] Specifically, when the supply voltage is lower than the preset voltage, the voltage divider signal is lower than the threshold voltage.

[0039] The above technical solution provides fast undervoltage protection without relying on the voltage provided by the bandgap reference or establishing a bandgap reference, thus eliminating the protection blind zone in the low-voltage region.

[0040] like Figure 3 As shown, the undervoltage protection circuit 40 also includes a potential shifting circuit 46.

[0041] The potential shifting circuit 46 is connected to the voltage divider circuit 42 and the power supply ground, and is used to shift the potential of the power supply ground to output a second shifted voltage.

[0042] The voltage divider circuit 42 is specifically used to output a first current based on the voltage difference between the first translation voltage and the second translation voltage, and to divide the voltage difference between the first translation voltage and the second translation voltage to output a voltage divider signal.

[0043] The above technical solution can adjust the voltage range of the voltage divider signal, thereby adjusting the threshold of the third switching circuit 43, and can also adjust the current flowing through the voltage divider circuit 42, thereby adjusting the current of the first decision signal, so as to adapt to the lower-level circuit modules with different power.

[0044] like Figure 4 As shown, the undervoltage protection circuit 40 also includes an adjustment circuit 47.

[0045] The regulating circuit 47 adjusts the voltage division coefficient of the voltage divider circuit 42 in response to the switching signal.

[0046] The voltage divider circuit 42 is specifically used to output a first current based on a first shift voltage, and to divide the first shift voltage based on the adjusted voltage division coefficient to output a voltage divider signal.

[0047] Through the above technical solution, when the power supply voltage is greater than the preset value, a switching signal is output and the voltage division coefficient of the voltage divider circuit 42 is adjusted, thereby adjusting the voltage of the voltage divider signal, generating a hysteresis effect, and improving the anti-interference capability of the undervoltage protection circuit 40.

[0048] Figure 5 The diagram illustrates a partial example circuit structure of a power transistor power-on protection circuit provided in an embodiment of the present invention. For ease of explanation, only the parts relevant to the embodiment of the present invention are shown, and are described in detail below: The current mirror 41 includes a first P-channel metal oxide semiconductor (PMOS) transistor P1 and a second PMOS transistor P2.

[0049] The source of the first PMOS transistor P1 and the source of the second PMOS transistor P2 are connected and together form the power supply terminal of the current mirror 41 to receive the supply voltage; the gate, drain, and gate of the first PMOS transistor P1 are connected and together form the first terminal of the current mirror 41, which is connected to the voltage divider circuit 42 to receive the first current and output the first shifted voltage; the drain of the second PMOS transistor P2 forms the second terminal of the current mirror 41, which is connected to the switching circuit and the second node B to output the second current and the switching signal.

[0050] The first switching circuit 20 includes a first N-channel metal-oxide-semiconductor (NMOS) transistor N1.

[0051] The gate of the first NMOS transistor N1 forms the control terminal of the first switching circuit 20 and is connected to the undervoltage protection circuit 40 and the resistor assembly 10 to receive the first voltage; the drain of the first NMOS transistor N1 forms the first terminal of the first switching circuit 20 and is connected to the gate of the high-side driving transistor P01 to output the first switching signal; the source of the first NMOS transistor N1 is connected to the power supply ground.

[0052] The second switching circuit 30 includes a second NMOS transistor N2, a third PMOS transistor P3, and a first resistor R1.

[0053] The gate of the second NMOS transistor N2 forms the control terminal of the second switching circuit 30, and is connected to the undervoltage protection circuit 40 and the resistor assembly 10 to receive the first voltage; the first terminal of the first resistor R1 and the drain of the third PMOS transistor P3 are connected and together form the first terminal of the second switching circuit 30, which is connected to the power transistor and the undervoltage protection circuit 40 to receive the supply voltage; the drain of the second NMOS transistor N2 is connected to the second terminal of the first resistor R1 and the gate of the third PMOS transistor P3; the source of the third PMOS transistor P3 forms the second terminal of the second switching circuit 30, and is connected to the gate of the low-side drive transistor N01 to output the second switching signal.

[0054] The voltage divider circuit 42 includes a second resistor R2, a third resistor R3, and a fourth resistor R4. The first end of the second resistor R2 forms the first end of the voltage divider circuit 42 and is connected to the current mirror 41 to output a first current and connect to a first shifted voltage. The second end of the second resistor R2 is connected to the first end of the third resistor R3 and together they form the output end of the voltage divider circuit 4212, which is connected to the switching circuit to output a voltage divider signal. The second end of the third resistor R3 is connected to the first end of the fourth resistor R4, and the second end of the fourth resistor R4 forms the second end of the voltage divider circuit 42, which is connected to the voltage shifting circuit to connect to a second shifted voltage.

[0055] The third switching circuit 43 includes a third NMOS transistor N3; the gate of the third NMOS transistor N3 forms the control terminal of the third switching circuit 43 and is connected to the voltage divider circuit 42 to receive the voltage divider signal; the drain of the third NMOS transistor N3 forms the first terminal of the third switching circuit 43 and is connected to the second node B, the current mirror 41 and the inverter 44 to receive the second current; the source of the third NMOS transistor N3 is connected to the power supply ground.

[0056] The inverter 44 includes a fourth PMOS transistor P4 and a fourth NMOS transistor N4; the source of the fourth PMOS transistor P4 forms the power supply terminal of the inverter 44 to be connected to the supply voltage Vin; the source of the fourth NMOS transistor N4 is connected to the power supply ground; the gates of the fourth PMOS transistor P4 and the fourth NMOS transistor N4 are connected and together form the input terminal of the inverter 44, which is connected to the second node B, the current mirror 41 and the third switching circuit 43 to receive the switching signal; the drains of the fourth PMOS transistor P4 and the fourth NMOS transistor N4 are connected and together form the output terminal of the inverter 44, which is connected to the fourth switching circuit 45 to output the first decision signal.

[0057] The fourth switching circuit 45 includes a fifth NMOS transistor N5; the gate of the fifth NMOS transistor N5 constitutes the control terminal of the fourth switching circuit 45 and is connected to the inverter 44 to receive the first decision signal; the drain of the fifth NMOS transistor N5 constitutes the first terminal of the fourth switching circuit 45 and is connected to the first switching circuit 20, the second switching circuit 30 and the resistor assembly 10 to receive the first voltage; the source of the fifth NMOS transistor N5 is connected to the power supply ground.

[0058] The regulating circuit 47 includes a sixth NMOS transistor N6; the gate of the sixth NMOS transistor N6 forms the control terminal of the regulating circuit 47, and is connected to the second node B, the current mirror 41, the third switching circuit 43 and the inverter 44 to receive a switching signal; the drain and source of the sixth NMOS transistor N6 are respectively connected to the two ends of a resistor in the voltage divider circuit 42. Specifically, the drain and source of the sixth NMOS transistor N6 are connected to the two ends of the fourth resistor R4.

[0059] It should be noted that the undervoltage protection circuit 40 also includes a fifth resistor R5 and a first capacitor C1; the first end of the first capacitor C1 is used to connect to the power supply voltage, the first end of the fifth resistor R5 is connected to the first end of the third switching circuit 43 and the second end of the current mirror 41, and the second end of the fifth resistor R5 is connected to the second end of the first capacitor C1, the control end of the adjustment circuit 47, and the input end of the inverter 44.

[0060] The resistor assembly 10 includes a sixth resistor R6.

[0061] The following is based on the working principle. Figure 5 Further explanation is provided below: During the power-on phase of the supply voltage Vin, the source of the first PMOS transistor P1 is connected to the supply voltage Vin. The first PMOS transistor P1 performs a potential shift on the input voltage Vin (usually the gate-source voltage of the field-effect transistor is a preset value), and inputs the first shifted voltage to the first terminal of the second resistor R2. The first NMOS transistor N1 performs a potential shift on the voltage of the power supply ground (the gate-source voltage of the field-effect transistor is a preset value), and inputs the second shifted voltage to the second terminal of the fourth resistor R4. The second resistor R2 to the fourth resistor R4 output a first current to the first terminal of the current mirror 41 according to the voltage difference between the first shifted voltage and the second shifted voltage, so that the second terminal of the current mirror 41... The drain of the second PMOS transistor P2 outputs a second current and divides the voltage difference between the first and second shifted voltages to output a voltage divider signal. Since the supply voltage Vin is in the power-on stage, the voltage of the voltage divider signal is less than the threshold voltage of the third NMOS transistor N3. The third NMOS transistor N3 is turned off, and the second node BB is pulled up so that the second PMOS transistor P2 outputs a switching signal (high level) to the inverter 44, which includes the fourth PMOS transistor P4 and the fourth NMOS transistor N4. The inverter 44 inverts the switching signal to output a first decision signal (low level) to the gate of the fifth NMOS transistor N5. The fifth NMOS transistor N5 is turned off. When the gate of the power device connected to the first node A experiences a voltage rise due to high voltage, the voltage at the first node A will boost the supply voltage through the parasitic PN junction of the high-side drive transistor P01. Because the voltage at the first node A (port voltage) is too high, the port voltage after current limiting by the sixth resistor R1 (the first voltage being greater than a preset value) causes the first NMOS transistor N1 to conduct and pull the gate of the high-side drive transistor P01 down to ground, thus causing the supply voltage to decrease along with the voltage at the first node A. Simultaneously, because the first voltage is greater than the preset value, the second NMOS transistor N2 conducts and pulls down the gate of the third PMOS transistor P3. The third PMOS transistor P3 then conducts and pulls up the gate of the low-side drive transistor N01, turning on N01. This effectively controls the gate voltage of the external power device, causing it to drop below the threshold voltage of the power device, reducing the possibility of accidental power-on and damage.

[0062] After the supply voltage Vin is powered on and within the normal range, the source of the first PMOS transistor P1 is connected to the supply voltage Vin. The first PMOS transistor P1 performs a potential shift on the supply voltage Vin (usually the gate-source voltage of the field-effect transistor is a preset value), and inputs the first shifted voltage to the first terminal of the second resistor R4. The first NMOS transistor N1 performs a potential shift on the voltage of the power supply ground (the gate-source voltage of the field-effect transistor is a preset value), and inputs the second shifted voltage to the second terminal of the fourth resistor R4. The second resistor R2 to the fourth resistor R4 output a first current to the first terminal of the current mirror 41 according to the voltage difference between the first shifted voltage and the second shifted voltage, so that the second terminal of the current mirror 41 (the second PMOS transistor)... The drain of P2 outputs a second current and divides the voltage difference between the first and second shifted voltages to output a voltage divider signal. Since the supply voltage Vin is in the normal range, the voltage of the voltage divider signal is greater than or equal to the threshold voltage of the third NMOS transistor N3. The third NMOS transistor N3 turns on and pulls down the voltage of the second node B to disconnect the output of the switching signal. The inverter 44 stops outputting the first decision signal (high level) to the gate of the fifth NMOS transistor N5. The fifth NMOS transistor N5 turns on and pulls the first voltage down to the power supply ground. The first NMOS transistor N1 turns off and stops pulling down the gate of the high-side drive transistor P01 to the power supply ground, so the high-side drive transistor P01 works normally based on the high-side drive signal DH. At the same time, the second NMOS transistor N2 turns off and stops pulling down the gate of the third PMOS transistor P3. The third PMOS transistor P3 turns off and stops pulling up the gate of the low-side drive transistor N01. The low-side drive transistor N01 works normally based on the low-side drive signal DL.

[0063] This invention also provides a chip that includes the power transistor power-on protection circuit described above.

[0064] The present invention also provides an electronic device, which includes the power transistor power-on protection circuit described above.

[0065] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0066] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A power tube on power protection circuit, characterized in that, The power transistor is powered on based on the supply voltage, and the power transistor includes a high-side driving transistor and a low-side driving transistor. The voltage of the first node where the high-side driving transistor and the low-side driving transistor are connected is the port voltage. The power transistor power-on protection circuit includes a resistor assembly, a first switching circuit, a second switching circuit, and an undervoltage protection circuit. A first switching circuit is connected to the resistor assembly and the high-side driving transistor. In response to a first voltage being greater than a preset value, it outputs a first switching signal to turn on the high-side driving transistor. The first voltage is the port voltage of the resistor assembly after current limiting. The second switching circuit is connected to the resistor assembly and the low-side driving transistor. In response to the first voltage being greater than a preset value, it outputs a second switching signal to turn on the low-side driving transistor. The undervoltage protection circuit, in response to the supply voltage being less than a preset voltage, stops pulling the first voltage down to the power supply ground.

2. The power-on protection circuit for a power tube according to claim 1, wherein, The undervoltage protection circuit is specifically used to pull the first voltage down to power ground in response to the supply voltage being greater than a preset voltage. The first switching circuit, in response to the first voltage after pull-down, disconnects the first switching signal so that the high-side driving transistor can operate normally; The second switching circuit, in response to the first voltage after pull-down, disconnects the second switching signal to enable the low-side drive transistor to operate normally.

3. The power transistor power-on protection circuit as described in claim 2, characterized in that, The undervoltage protection circuit includes: A current mirror is used to connect to the supply voltage, shift the supply voltage to output a first shifted voltage, and mirror the first current to output a second current. A voltage divider circuit, connected to the current mirror, is used to output a first current based on the first shift voltage, and to divide the first shift voltage to output a voltage divider signal. The third switching circuit is connected to the voltage divider circuit and shares a second node with the current mirror. It is used to stop transmitting the second current to the power supply ground in response to the voltage divider signal being less than the threshold voltage, so that the current mirror pulls up the voltage of the second node, and outputs a switching signal from the second node. An inverter, connected to the second node, the current mirror, and the third switching circuit, is used to invert the switching signal to output a first decision signal; The fourth switching circuit, in response to the first decision signal, pulls the first voltage down to the power supply ground; Wherein, when the supply voltage is less than the preset voltage, the voltage divider signal is less than the threshold voltage.

4. The power-on protection circuit for a power tube according to claim 3, wherein The undervoltage protection circuit also includes: A potential shifting circuit, connected to the voltage divider circuit and the power supply ground, is used to shift the potential of the power supply ground to output a second shifted voltage. The voltage divider circuit is specifically used to output the first current based on the voltage difference between the first shift voltage and the second shift voltage, and to divide the voltage difference between the first shift voltage and the second shift voltage to output the voltage divider signal.

5. The power-on protection circuit for a power tube according to claim 4, wherein The undervoltage protection circuit also includes: The regulating circuit, in response to the switching signal, adjusts the voltage division coefficient of the voltage divider circuit; The voltage divider circuit is specifically used to output a first current based on the first shifted voltage, and to divide the first shifted voltage based on the adjusted voltage division coefficient to output a voltage divider signal.

6. The power-on protection circuit for a power tube according to claim 3, wherein The current mirror includes a first PMOS transistor and a second PMOS transistor; The source of the first PMOS transistor and the source of the second PMOS transistor are connected and together form the power supply terminal of the current mirror to receive the supply voltage; the gate, drain, and gate of the first PMOS transistor are connected and together form the first terminal of the current mirror, which is connected to the voltage divider circuit to receive the first current and output the first shifted voltage; the drain of the second PMOS transistor forms the second terminal of the current mirror, which is connected to the switching circuit and the second node to output the second current and the switching signal.

7. The power transistor power-on protection circuit as described in any one of claims 1 to 6, characterized in that, The first switching circuit includes a first NMOS transistor; The gate of the first NMOS transistor forms the control terminal of the first switching circuit, and is connected to the undervoltage protection circuit and the resistor assembly to receive the first voltage; The drain of the first NMOS transistor forms the first terminal of the first switching circuit and is connected to the gate of the high-side driving transistor to output the first switching signal. The source of the first NMOS transistor is connected to the power supply ground.

8. The power-on protection circuit for a power tube according to any one of claims 1 to 6, wherein, The second switching circuit includes a second NMOS transistor, a third PMOS transistor, and a first resistor; The gate of the second NMOS transistor N2 forms the control terminal of the second switching circuit, and is connected to the undervoltage protection circuit and the resistor assembly to receive the first voltage; The first end of the first resistor and the drain of the third PMOS transistor are connected to form the first end of the second switching circuit, which is connected to the power transistor and the undervoltage protection circuit to access the power supply voltage. The drain of the second NMOS transistor is connected to the second terminal of the first resistor and the gate of the third PMOS transistor; The source of the third PMOS transistor forms the second terminal of the second switching circuit and is connected to the gate of the low-side driving transistor to output the second switching signal.

9. A chip, characterized by The chip includes a power transistor power-on protection circuit as described in any one of claims 1 to 8.

10. An electronic device, comprising: The electronic device includes a power transistor power-on protection circuit as described in any one of claims 1 to 8.

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