A charge pump

Abstract

This application discloses a charge pump, comprising at least one charge pump unit, each charge pump unit including: an input terminal configured to receive an input voltage signal; an output terminal configured to generate a corresponding output voltage signal; and at least two charge pump processing paths arranged in parallel between the input terminal and the output terminal. Each charge pump processing path includes a charge / discharge input module, an intermediate node, and a charge / discharge output module connected in series. The at least two charge pump processing paths sequentially and alternately perform charge / discharge input operations and charge / discharge output operations. At least one charge pump processing path further includes a charge / discharge output control module configured to perform a charge / discharge output operation in response to the corresponding charge pump processing path. The charge / discharge output control module controls the charge / discharge output module to be in a fully conductive state based on a corresponding clock signal to perform the charge / discharge output operation. Based on the above method, the transmission efficiency of the charge pump can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor circuit technology, and in particular to a charge pump. Background Technology

[0002] In the prior art, charge pump circuits are typically used to output voltage signals with the required positive or negative voltage amplitudes to the corresponding devices.

[0003] The drawback of the existing technology is that the existing charge pump circuits usually use an internal voltage signal associated with the output voltage signal of the charge pump circuit to control the switches in the charge pump circuit. When the output voltage signal with positive voltage is low or the output voltage signal with negative voltage is high during the operation of the charge pump circuit, it is easy for the switch controlled by the internal voltage signal to fail to conduct completely when it needs to be fully turned on. This can easily lead to insufficient charge transfer and low transfer efficiency of the existing charge pump. Summary of the Invention

[0004] The main technical problem addressed in this application is how to improve the transfer efficiency of charge pumps.

[0005] To solve the above-mentioned technical problems, the technical solution adopted in this application is: a charge pump, including at least one charge pump unit, each charge pump unit including: an input terminal configured to receive an input voltage signal; an output terminal configured to generate a corresponding output voltage signal; at least two charge pump processing paths, arranged in parallel between the input terminal and the output terminal, each charge pump processing path including a charge / discharge input module, an intermediate node and a charge / discharge output module connected in series, the at least two charge pump processing paths sequentially and alternately performing charge / discharge input operations and charge / discharge output operations; at least one charge pump processing path further includes: a charge / discharge output control module, configured to perform a charge / discharge output operation in response to the corresponding charge pump processing path, the charge / discharge output control module controlling the charge / discharge output module to be in a fully conductive state based on a corresponding clock signal to perform the charge / discharge output operation.

[0006] When the charge pump is working: at least two charge pump processing paths sequentially and alternately perform charge and discharge input operations, and at any given time there is a unique corresponding charge pump processing path performing charge and discharge input operations; at least two charge pump processing paths sequentially and alternately perform charge and discharge output operations, and at any given time there is a unique corresponding charge pump processing path performing charge and discharge output operations; no charge pump processing path performs charge and discharge input operations and charge and discharge output operations simultaneously.

[0007] Specifically, the difference between the high-level or low-level amplitude of the clock signal and the output voltage signal is greater than the threshold of the charge / discharge output module, so as to ensure that the charge / discharge output module is in a fully conductive state when performing charge / discharge output operations.

[0008] Each charge pump processing path further includes a voltage switching module, which receives a first clock signal and is connected to an intermediate node. The voltage switching module is used to: before performing a charge / discharge input operation, reduce the voltage of the intermediate node by a downward pulse of the first clock signal, so as to charge the intermediate node based on the input terminal when the charge / discharge input module is turned on; and before performing a charge / discharge output operation, raise the voltage of the intermediate node by an upward pulse of the first clock signal, so as to charge the output terminal based on the intermediate node when the charge / discharge output module is turned on, generating a corresponding output voltage signal with a positive voltage; or, before performing a charge / discharge input operation, raise the voltage of the intermediate node by an upward pulse of the first clock signal, so as to discharge the input terminal based on the intermediate node when the charge / discharge input module is turned on; and before performing a charge / discharge output operation, reduce the voltage of the intermediate node by a downward pulse of the first clock signal, so as to discharge the intermediate node based on the output terminal when the charge / discharge output module is turned on, generating a corresponding output voltage signal with a negative voltage.

[0009] The charge / discharge output control module includes: a first capacitor, one end of which receives a second clock signal, and the other end of which is connected to the control terminal of the charge / discharge output module; a second capacitor, one end of which receives a third clock signal; and a first switch connected between the other end of the first capacitor and the output terminal, the control terminal of which is connected to the other end of the second capacitor. In response to the second clock signal being in a first logic state and the third clock signal being in a second logic state, the first switch is turned on, and the output voltage signal is transmitted to the other end of the first capacitor via the turned-on first switch. In response to the second clock signal being in a second logic state and the third clock signal being in a first logic state, the signal from the other end of the first capacitor is transmitted to the control terminal of the charge / discharge output module to turn on the charge / discharge output module and make it fully conductive, while the first switch is turned off. The second clock signal and the third clock signal are inverse signals.

[0010] The charge pump is used to output a positive output voltage signal. Each charge pump unit includes two charge pump processing paths, namely a first path and a second path. In the first path, the voltage switching module includes a first switching capacitor, and the charge / discharge output module includes a first PMOS switch. In the second path, the voltage switching module includes a second switching capacitor, and the charge / discharge output module includes a second PMOS switch. The charge / discharge output control module also includes a second switch, and both the first and second switches are PMOS switches. One end of the first switching capacitor is used to receive a first clock signal, and the other end of the first switching capacitor is connected to the intermediate node of the first path. One end of the second switching capacitor is used to receive the first clock signal after inversion. The other end is connected to the middle node of the second path. The first end of the first PMOS switch is connected to the middle node of the first path. The first end of the second PMOS switch is connected to the middle node of the second path. One end of the first capacitor receives the second clock signal. The first end of the first switch is connected to the other end of the first capacitor. One end of the second capacitor receives the third clock signal. The first end of the second switch is connected to the other end of the second capacitor. The second ends of the first PMOS switch, the second PMOS switch, the first switch, and the second switch are respectively connected to the output terminal. The other end of the first capacitor is respectively connected to the control terminal of the second PMOS switch and the control terminal of the second switch. The other end of the second capacitor is respectively connected to the control terminal of the first PMOS switch and the control terminal of the first switch.

[0011] The charge pump unit further includes a charge / discharge input control module. In the first path, the charge / discharge input module includes a first NMOS switch, and the charge / discharge input control module includes a third capacitor and a third switch. In the second path, the charge / discharge input module includes a second NMOS switch, and the charge / discharge input control module includes a fourth capacitor and a fourth switch. Both the third and fourth switches are NMOS switches. The first terminal of the first NMOS switch is connected to the intermediate node of the first path, the first terminal of the second NMOS switch is connected to the intermediate node of the second path, one terminal of the third capacitor receives a second clock signal, the first terminal of the third switch is connected to the other terminal of the third capacitor, one terminal of the fourth capacitor receives a third clock signal, the first terminal of the fourth switch is connected to the other terminal of the fourth capacitor, the second terminals of the first NMOS switch, the second terminals of the second NMOS switch, the second terminals of the third switch, and the second terminals of the fourth switch are respectively connected to the input terminals, the other terminal of the third capacitor is respectively connected to the control terminals of the second NMOS switch and the fourth switch, and the other terminal of the fourth capacitor is respectively connected to the control terminals of the first NMOS switch and the third switch.

[0012] The charge pump is used to output a negative voltage signal. Each charge pump unit includes two charge pump processing paths, namely a first path and a second path. In the first path, the voltage switching module includes a first switching capacitor, and the charge / discharge output module includes a first NMOS switch. In the second path, the voltage switching module includes a second switching capacitor, and the charge / discharge output module includes a second NMOS switch. The charge / discharge output control module also includes a second switch, and both the first and second switches are NMOS switches. One end of the first switching capacitor is used to receive a first clock signal, and the other end of the first switching capacitor is connected to the intermediate node of the first path. One end of the second switching capacitor is used to receive the first clock signal after inversion. The other end is connected to the middle node of the second path. The first end of the first NMOS switch is connected to the middle node of the first path. The first end of the second NMOS switch is connected to the middle node of the second path. One end of the first capacitor receives the second clock signal. The first end of the first switch is connected to the other end of the first capacitor. One end of the second capacitor receives the third clock signal. The first end of the second switch is connected to the other end of the second capacitor. The second ends of the first NMOS switch, the second NMOS switch, the first switch, and the second switch are respectively connected to the output terminal. The other end of the first capacitor is respectively connected to the control terminal of the second NMOS switch and the control terminal of the second switch. The other end of the second capacitor is respectively connected to the control terminal of the first NMOS switch and the control terminal of the first switch.

[0013] The charge pump unit further includes a charge / discharge input control module. In the first path, the charge / discharge input module includes a first PMOS switch, and the charge / discharge input control module includes a third capacitor and a third switch. In the second path, the charge / discharge input module includes a second PMOS switch, and the charge / discharge input control module includes a fourth capacitor and a fourth switch. Both the third and fourth switches are PMOS switches. The first terminal of the first PMOS switch is connected to the intermediate node of the first path, the first terminal of the second PMOS switch is connected to the intermediate node of the second path, one terminal of the third capacitor receives a second clock signal, the first terminal of the third switch is connected to the other terminal of the third capacitor, one terminal of the fourth capacitor receives a third clock signal, the first terminal of the fourth switch is connected to the other terminal of the fourth capacitor, the second terminals of the first, second, third, and fourth PMOS switches are respectively connected to the input terminals, the other terminal of the third capacitor is respectively connected to the control terminals of the second PMOS switch and the fourth switch, and the other terminal of the fourth capacitor is respectively connected to the control terminals of the first PMOS switch and the third switch.

[0014] The first clock signal and the second clock signal are the same signal, and the first clock signal and the third clock signal after inversion are the same signal.

[0015] The at least one charge pump unit includes at least two charge pump units connected in series; in two adjacent charge pump units, the output terminal of one charge pump unit is connected to the input terminal of the other charge pump unit.

[0016] The beneficial effects of this application are as follows: Unlike existing technologies, the technical solution of this application includes a charge pump comprising at least one charge pump unit, each charge pump unit comprising an input terminal, an output terminal, and at least two charge pump processing paths; the input terminal is configured to receive an input voltage signal; the output terminal is configured to generate a corresponding output voltage signal; at least two charge pump processing paths are arranged in parallel between the input terminal and the output terminal, each charge pump processing path comprising a charge / discharge input module, an intermediate node, and a charge / discharge output module connected in series, and the at least two charge pump processing paths sequentially and alternately perform charge / discharge input operations and charge / discharge output operations; wherein, at least one charge pump processing path further includes a charge / discharge output control module, configured to perform a charge / discharge output operation in response to the corresponding charge pump processing path, the charge / discharge output control module controlling the charge / discharge output module to be in a fully conductive state based on a corresponding clock signal to perform the charge / discharge output operation. Based on the above method, during the charging and discharging output operation, the charging and discharging output module can be controlled to be in a fully conducting state based on the corresponding clock signal. The clock signal will not change due to the change of the output voltage signal, thus reducing or eliminating the possibility that the charging and discharging output module will not be fully conducting during the charging and discharging output operation due to the change of the output voltage signal. This reduces or eliminates the possibility of insufficient charge transfer and improves the transfer efficiency of the charge pump. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of one embodiment of the charge pump unit of this application;

[0019] Figure 2 This is a second schematic diagram of the structure of an embodiment of the charge pump unit of this application;

[0020] Figure 3 This is a third schematic diagram of the structure of an embodiment of the charge pump unit of this application;

[0021] Figure 4 This is the fourth schematic diagram of the structure of an embodiment of the charge pump unit of this application;

[0022] Figure 5This is a schematic diagram of the structure of one embodiment of the charge pump of this application. Detailed Implementation

[0023] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be particularly noted that the following embodiments are for illustrative purposes only and do not limit the scope of the application. Similarly, the following embodiments are only some, not all, embodiments of the present application, and all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present application.

[0024] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0025] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "setting," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or a connection through an intermediate medium. Those skilled in the art will understand the specific meanings of the above terms within the context of this application.

[0026] This application discloses a charge pump, which includes at least one charge pump unit, see [link]. Figure 1 , Figure 1 This is a schematic diagram of one embodiment of the charge pump unit of this application, as shown below. Figure 1 As shown, each charge pump unit includes an input terminal, an output terminal, and at least two charge pump processing paths 1.

[0027] The input terminal is configured to receive an input voltage signal VIN, and the output terminal is configured to generate a corresponding output voltage signal VOUT. Specifically, the input voltage signal VIN can be the input signal to the charge pump unit, and the output voltage signal VOUT is the output signal obtained by performing charge pump processing on the input signal to increase the absolute value of its voltage amplitude.

[0028] At least two charge pump processing paths 1 are arranged in parallel between the input and output terminals. Each charge pump processing path 1 includes a charge / discharge input module, an intermediate node, and a charge / discharge output module connected in series. The at least two charge pump processing paths 1 sequentially and alternately perform charge / discharge input operations and charge / discharge output operations. Wherein, as Figure 1As shown, in a charge pump processing path 1, one end of the charge / discharge input module is connected to the input terminal to receive the input voltage signal VIN. The intermediate nodes are connected to the other end of the charge / discharge input module and one end of the charge / discharge output module, respectively. The other end of the charge / discharge output module is connected to the output terminal to send the output voltage signal VOUT.

[0029] At least one of the charge pump processing paths 1 also includes a charge / discharge output control module.

[0030] The charge / discharge output control module is configured to perform charge / discharge output operations in response to the corresponding charge pump processing path 1. The charge / discharge output control module controls the charge / discharge output module to be in a fully on state based on an external voltage signal to perform the charge / discharge output operations.

[0031] Specifically, the clock signal can be an externally provided voltage signal that is not affected by the output voltage signal VOUT, the input voltage signal VIN, the voltage signal of the intermediate node, or the internal voltage signal of other charge pump units. It can be set according to the conditions of the voltage signal required when the corresponding module controlled by the clock signal is fully turned on, and is not limited here.

[0032] For example, when the charge / discharge output module is a PMOS switch, when the charge / discharge output module needs to be in a fully on state to perform the charge / discharge output operation, a stable and continuous control of the charge / discharge output module's full on state can be achieved by sending the clock signal of the first logic state or a signal that changes accordingly based on the clock signal switching to the first logic state to the control terminal of the charge / discharge output module. When the charge / discharge output module is an NMOS switch, when the charge / discharge output module needs to be in a fully on state to perform the charge / discharge output operation, a stable and continuous control of the charge / discharge output module's full on state can be achieved by sending the clock signal of the second logic state or a signal that changes accordingly based on the clock signal switching to the second logic state to the control terminal of the charge / discharge output module.

[0033] Based on the above approach, in traditional technology, an internal voltage signal provided at an intermediate node or other location within the charge pump unit is typically used to control the charge / discharge output module to be fully turned on. However, the amplitude of the internal voltage signal is easily affected by the devices connected to the output terminal. That is, the amplitude of the internal voltage signal easily changes with the output voltage signal VOUT. This can cause the charge / discharge output module to disconnect prematurely or not be fully turned on when it needs to be in a fully turned-on state, which can easily lead to insufficient charge transfer and reduced transfer efficiency.

[0034] In the technical solution of this application, since the clock signal is an externally provided voltage signal with stable high and low level amplitudes that does not change with the output voltage signal VOUT, by setting up a charging and discharging input control module, the charging and discharging output module is fully turned on based on the clock signal. This ensures that the fully turned-on state of the charging and discharging output module is only affected by the clock signal and the control method of the corresponding control module, and is not affected by changes in the output voltage signal VOUT. This allows the charging and discharging output module to be stably turned on when needed, reducing the possibility of the charging and discharging output module being disconnected prematurely or not fully turned on, thereby reducing the possibility of insufficient charge transfer and improving the transfer efficiency.

[0035] Unlike existing technologies, the technical solution of this application includes a charge pump comprising at least one charge pump unit, each charge pump unit comprising an input terminal, an output terminal, and at least two charge pump processing paths; the input terminal is configured to receive an input voltage signal; the output terminal is configured to generate a corresponding output voltage signal; at least two charge pump processing paths are arranged in parallel between the input terminal and the output terminal, each charge pump processing path comprising a charge / discharge input module, an intermediate node, and a charge / discharge output module connected in series, and the at least two charge pump processing paths alternately perform charge / discharge input operations and charge / discharge output operations; wherein, at least one charge pump processing path further comprises: a charge / discharge output control module, configured to perform a charge / discharge output operation in response to the corresponding charge pump processing path, the charge / discharge output control module controlling the charge / discharge output module to be in a fully conductive state based on a corresponding clock signal to perform the charge / discharge output operation. Based on the above method, during the charging and discharging output operation, the charging and discharging output module can be controlled to be in a fully conducting state based on the corresponding clock signal. The clock signal will not change due to the change of the output voltage signal, thus reducing or eliminating the possibility that the charging and discharging output module will not be fully conducting during the charging and discharging output operation due to the change of the output voltage signal. This reduces or eliminates the possibility of insufficient charge transfer and improves the transfer efficiency of the charge pump.

[0036] In one embodiment, when the charge pump is operating:

[0037] At least two charge pump processing paths sequentially and alternately perform charge and discharge input operations, and at any given time there is only one corresponding charge pump processing path performing the charge and discharge input operation.

[0038] At least two charge pump processing paths sequentially and alternately perform charge and discharge output operations, and at any given time there is only one corresponding charge pump processing path performing the charge and discharge output operation.

[0039] No charge pump processing path can simultaneously perform charge / discharge input operations and charge / discharge output operations.

[0040] Specifically, at the same time, in at least two charge pump processing paths 1, at least one charge pump processing path 1 performs a charge / discharge input operation, and at least one charge pump processing path 1 performs a charge / discharge output operation.

[0041] At any given moment, within the same charge pump processing path 1, no operation may be performed, or only the charge / discharge input operation may be performed without the charge / discharge output operation, or the charge / discharge output operation may be performed without the charge / discharge input operation, but the charge / discharge input operation and the charge / discharge output operation may not be performed simultaneously.

[0042] Based on the above method, the charge pump unit can perform charge and discharge output operations through at least one charge pump processing path 1 to send an output voltage signal VOUT, thereby realizing the current round output of the charge pump. At the same time, it can also perform charge and discharge input operations through at least one charge pump processing path 1 to adjust the voltage of the intermediate node of the corresponding path in order to realize the next round output of the charge pump. The complete cycle of the charge pump can be divided into a preset number of output rounds, and the output voltage signal VOUT is sent by the combination of at least one charge pump processing path 1 in at least two charge pump processing paths 1 respectively. The specific method can be determined according to actual needs and is not limited here.

[0043] For example, when there are at least two charge pump processing paths 1, the first charge pump processing path 1 and the second charge pump processing path 1 alternately perform charge and discharge input operations, and the first charge pump processing path 1 and the second charge pump processing path 1 alternately perform charge and discharge output operations.

[0044] When the number of at least two charge pump processing paths 1 is 3, a cycle can be divided into three time periods. First, the first charge pump processing path 1 performs charge-discharge output operation in the first time period and performs charge-discharge input operation in the second and third time periods. Second, the second charge pump processing path 1 performs charge-discharge output operation in the second time period and performs charge-discharge input operation in the first and third time periods. Finally, the third charge pump processing path 1 performs charge-discharge output operation in the third time period and performs charge-discharge input operation in the first and second time periods.

[0045] The above are just examples. Other examples that meet the above conditions when the charge pump is working will not be elaborated here. The specific conditions can be determined according to the actual situation, and no limitation is made here.

[0046] In one embodiment, the difference between the high-level amplitude or low-level amplitude of the clock signal and the output voltage signal is greater than the threshold of the charge / discharge output module, so as to ensure that the charge / discharge output module is in a fully conductive state when performing the charge / discharge output operation.

[0047] Specifically, the charge / discharge output module can be a MOS switch or other device that requires ensuring that the voltage difference between the control terminal and the corresponding terminal is greater than the corresponding threshold.

[0048] By controlling the charging and discharging output module to be fully turned on when the difference between the high-level or low-level amplitude of the clock signal and the output voltage signal is greater than the threshold of the charging and discharging output module, it is possible to ensure that the charging and discharging output module can be in a relatively stable fully turned-on state. This reduces the possibility that the charging and discharging output module may fail to turn on, disconnect prematurely, or fail to turn on completely due to a small difference between the high-level or low-level amplitude of the clock signal and the output voltage signal. This further reduces the possibility of insufficient charge transfer and improves the transmission efficiency.

[0049] In one embodiment, Figure 2 This is a second schematic diagram of the structure of an embodiment of the charge pump unit of this application, as shown below. Figure 2 As shown, each charge pump processing path 1 also includes a voltage switching module.

[0050] The voltage switching module receives the first clock signal and connects to the intermediate node. The voltage switching module is used for:

[0051] Before performing the charge / discharge input operation, the voltage of the intermediate node is reduced by the pulse transition of the first clock signal to charge the intermediate node based on the input terminal when the charge / discharge input module is turned on. Before performing the charge / discharge output operation, the voltage of the intermediate node is increased by the pulse transition of the first clock signal to charge the output terminal based on the intermediate node when the charge / discharge output module is turned on, thereby generating a corresponding output voltage signal with positive voltage.

[0052] or,

[0053] Before performing the charge / discharge input operation, the voltage of the intermediate node is raised by the pulse transition of the first clock signal so that the input terminal is discharged based on the intermediate node when the charge / discharge input module is turned on. Before performing the charge / discharge output operation, the voltage of the intermediate node is lowered by the pulse transition of the first clock signal so that the intermediate node is discharged based on the output terminal when the charge / discharge output module is turned on, thereby generating a corresponding output voltage signal with negative voltage.

[0054] Specifically, when the charge pump is a positive voltage charge pump, that is, when the charge pump is used to output an output voltage signal with a positive voltage, before performing the charge / discharge input operation, the voltage of the intermediate node is reduced by the pulse down-jump of the first clock signal so that the intermediate node is charged based on the input terminal when the charge / discharge input module is turned on. And before performing the charge / discharge output operation, the voltage of the intermediate node is increased by the pulse up-jump of the first clock signal so that the output terminal is charged based on the intermediate node when the charge / discharge output module is turned on, thereby generating a corresponding output voltage signal with a positive voltage. Based on the above method, for the same charge pump processing path 1, when the voltage of the intermediate node is reduced by the pulse transition of the first clock signal, the voltage of the intermediate node can reach the voltage of the input voltage signal VIN. Then, the voltage of the intermediate node is raised by the pulse transition of the first clock signal, so that the output voltage signal VOUT is boosted relative to the input voltage signal VIN based on this boost. That is, the absolute value of the positive voltage amplitude of the output voltage signal VOUT is higher than the absolute value of the positive voltage amplitude of the input voltage signal VIN, thus realizing the function of the positive voltage charge pump.

[0055] When the charge pump is a negative voltage charge pump, that is, when the charge pump is used to output a negative voltage signal, before performing the charge / discharge input operation, the voltage of the intermediate node is raised by the pulse transition of the first clock signal so that the input terminal is discharged based on the intermediate node when the charge / discharge input module is turned on. Conversely, before performing the charge / discharge output operation, the voltage of the intermediate node is lowered by the pulse transition of the first clock signal so that the intermediate node is discharged based on the output terminal when the charge / discharge output module is turned on, generating a corresponding negative voltage signal. Based on the above method, for the same charge pump processing path 1, when the voltage of the intermediate node is raised by the pulse transition of the first clock signal, the voltage of the intermediate node reaches the voltage of the input voltage signal VIN. Then, the voltage of the intermediate node is lowered by the pulse transition of the first clock signal so that the output voltage signal VOUT is lowered relative to the input voltage signal VIN. That is, the absolute value of the negative voltage amplitude of the output voltage signal VOUT is higher than the absolute value of the negative voltage amplitude of the input voltage signal VIN, thus realizing the function of a negative voltage charge pump.

[0056] Optionally, the charge / discharge output control module includes a first capacitor, a second capacitor, and a first switch.

[0057] One end of the first capacitor receives the second clock signal, and the other end of the first capacitor is connected to the control terminal of the charge / discharge output module.

[0058] One end of the second capacitor receives the third clock signal.

[0059] The first switch is connected between the other end of the first capacitor and the output terminal, and the control terminal of the first switch is connected to the other end of the second capacitor.

[0060] In response to the second clock signal being in the first logic state and the third clock signal being in the second logic state, the first switch is turned on, and the output voltage signal is transmitted to the other end of the first capacitor through the turned-on first switch.

[0061] In response to the second clock signal being in the second logic state and the third clock signal being in the first logic state, the signal at the other end of the first capacitor is transmitted to the control terminal of the charge / discharge output module to turn on the charge / discharge output module and put it in a fully conducting state, while the first switch is turned off.

[0062] The second clock signal and the third clock signal are inverses of each other.

[0063] For specific examples, see [link to relevant documentation]. Figure 3 , Figure 3 This is a third schematic diagram of the structure of an embodiment of the charge pump unit of this application, as shown below. Figure 3 As shown, taking one of the charge pump processing paths 1 as an example, the second clock signal is CLK1, the third clock signal is CLK2, CLK1 and CLK2 are inverse signals, the intermediate node is V11, the voltage switching module can be C11, the charge and discharge output control module connected to the charge and discharge output control module is MP12, the first logic state is a high level state and the second logic state is a low level state, the first switch of the charge and discharge output control module can be MP13, the first capacitor of the charge and discharge output control module can be C15, and the second capacitor of the charge and discharge output control module can be C16.

[0064] When CLK2 is in a low-level state, MP13 is turned on. Based on the voltage jump of CLK1 in the high-level state, V15 is raised and reaches the voltage of the output voltage signal VOUT through MP13.

[0065] When CLK2 is high, MP13 is disconnected. The V15, which is reduced by the voltage jump of CLK1 when it is low, is sent to the control terminal of MP12. MP12 is turned on, realizing the full conduction of the charge and discharge output control module. During this period, since the other end of the first capacitor is disconnected from the output terminal of the charge pump unit (MP13 is disconnected), the voltage signal V15 received by the control terminal of MP12 will not change with the change of the output voltage signal VOUT.

[0066] Based on the above method, the possibility of incomplete conduction of the charge / discharge output module during charge / discharge operation due to changes in the output voltage signal can be reduced or eliminated, thereby reducing or eliminating the possibility of insufficient charge transfer and improving the transfer efficiency of the charge pump.

[0067] Furthermore, the charge pump is used to output a positive voltage signal; that is, the charge pump is a positive voltage charge pump.

[0068] Each charge pump unit includes two charge pump processing paths, namely a first path and a second path.

[0069] In the first path, the voltage switching module includes a first switching capacitor, and the charge / discharge output module includes a first PMOS switch.

[0070] In the second path, the voltage switching module includes a second switching capacitor, and the charge / discharge output module includes a second PMOS switch.

[0071] The charge / discharge output control module also includes a second switch, and both the first and second switches are PMOS switches.

[0072] One end of the first switching capacitor is used to receive the first clock signal, and the other end of the first switching capacitor is connected to the intermediate node of the first path. One end of the second switching capacitor is used to receive the first clock signal after inversion, and the other end of the second switching capacitor is connected to the intermediate node of the second path. The first end of the first PMOS switch is connected to the intermediate node of the first path, and the first end of the second PMOS switch is connected to the intermediate node of the second path. One end of the first capacitor receives the second clock signal, and the first end of the first switch is connected to the other end of the first capacitor. One end of the second capacitor receives the third clock signal, and the first end of the second switch is connected to the other end of the second capacitor. The second ends of the first PMOS switch, the second end of the second PMOS switch, the second end of the first switch, and the second end of the second switch are respectively connected to the output terminals. The other end of the first capacitor is respectively connected to the control terminals of the second PMOS switch and the second switch. The other end of the second capacitor is respectively connected to the control terminals of the first PMOS switch and the first switch.

[0073] Specifically, such as Figure 3 As shown, in the first path: the first switching capacitor is C11, the intermediate node is V11, and the first PMOS switch is MP11.

[0074] In the second path, the second switching capacitor is C12, and the second PMOS switch is MP12.

[0075] In the charge / discharge output control module: the first capacitor is C15, the second capacitor is C16, the first switch is MP13, and the second switch is MP14.

[0076] The second clock signal and the first clock signal are both CLK1, the third clock signal and the first clock signal after inversion are both CLK2, the node at the other end of the first capacitor is V15, and the node at the other end of the second capacitor is V16.

[0077] Both VIN and VOUT are positive voltage signals.

[0078] When CLK1 is high and CLK2 is low, V16 decreases due to the downward transition of CLK2, turning on MP11 and MP13. V15 increases due to the upward transition of CLK1, turning off MP12 and MP14. V11 increases due to the upward transition of CLK1, and can charge the output terminal through the conducting MP11, so that the output voltage signal VOUT reaches the voltage of V11 after the increase. That is, the output voltage signal VOUT increases relative to the input voltage signal VIN, realizing the first path to perform charge and discharge output operation. At this time, the second path does not perform charge and discharge output operation, but can perform charge and discharge input operation. At the same time, the voltage of V15 reaches the voltage of the output voltage signal VOUT through the conducting MP13, so as to turn on the corresponding switch when the second path performs charge and discharge output operation in the future.

[0079] When CLK1 is low and CLK2 is high, V15 decreases due to the downward transition of CLK1, turning on MP12 and MP14. V16 increases due to the upward transition of CLK2, turning off MP11 and MP13. V12 increases due to the upward transition of CLK2, and V12 can charge the output terminal through the conducting MP12, so that the voltage of the output voltage signal VOUT reaches the voltage of the increased V12. That is, the output voltage signal VOUT is increased relative to the input voltage signal VIN, realizing the second path to perform charge and discharge output operation. At this time, the first path does not perform charge and discharge output operation, but can perform charge and discharge input operation. At the same time, the voltage of V16 reaches the voltage of the output voltage signal VOUT through the conducting MP14, so as to turn on the corresponding switch when the first path performs charge and discharge output operation in the future.

[0080] Based on the above method, charge / discharge input and output operations can be performed alternately on the same path, and charge / discharge output operations can be performed alternately on the first and second paths, thereby achieving uninterrupted operation of the charge pump unit and improving the charge transfer stability of the charge pump.

[0081] Furthermore, since V15 and V16 are disconnected from the output terminal when performing the corresponding switch conduction control, V15 and V16 will not change due to changes in the output voltage signal at the output terminal. This reduces or eliminates the possibility that the charge and discharge output module will not be fully turned on during the charge and discharge output operation due to changes in the output voltage signal, thereby reducing or eliminating the possibility of insufficient charge transfer and improving the transfer efficiency of the charge pump.

[0082] Furthermore, the charge pump unit also includes a charge / discharge input control module.

[0083] In the first path, the charge / discharge input module includes a first NMOS switch, and the charge / discharge input control module includes a third capacitor and a third switch.

[0084] In the second path, the charge / discharge input module includes a second NMOS switch, and the charge / discharge input control module includes a fourth capacitor and a fourth switch.

[0085] Both the third and fourth switches are NMOS switches.

[0086] The first terminal of the first NMOS switch is connected to the middle node of the first path, the first terminal of the second NMOS switch is connected to the middle node of the second path, one terminal of the third capacitor receives the second clock signal, the first terminal of the third switch is connected to the other terminal of the third capacitor, one terminal of the fourth capacitor receives the third clock signal, the first terminal of the fourth switch is connected to the other terminal of the fourth capacitor, the second terminals of the first NMOS switch, the second terminal of the second NMOS switch, the second terminal of the third switch and the second terminal of the fourth switch are respectively connected to the input terminal, the other terminal of the third capacitor is respectively connected to the control terminal of the second NMOS switch and the control terminal of the fourth switch, and the other terminal of the fourth capacitor is respectively connected to the control terminal of the first NMOS switch and the control terminal of the third switch.

[0087] Specifically, such as Figure 3 As shown, in the first path: the first switching capacitor is C11, the intermediate node is V11, and the first NMOS switch is MN11.

[0088] In the second path, the second switching capacitor is C12, and the second NMOS switch is MN12.

[0089] In the charge / discharge output control module: the third capacitor is C13, the fourth capacitor is C14, the third switch is MN13, and the fourth switch is MN14.

[0090] The second clock signal and the first clock signal are both CLK1, the third clock signal and the first clock signal after inversion are both CLK2, the node at the other end of the third capacitor is V13, and the node at the other end of the fourth capacitor is V14.

[0091] Both VIN and VOUT are positive voltage signals.

[0092] When CLK1 is low and CLK2 is high, V14 rises due to the upward transition of CLK2, causing MN11 and MN13 to conduct. V13 falls due to the downward transition of CLK1, causing MN12 and MN14 to disconnect. V11 falls due to the downward transition of CLK1, and the input terminal can charge V11 through the conducting MN11, so that the voltage of the reduced V11 reaches the voltage of the input voltage signal VIN, realizing the first path to perform charge / discharge input operation. At this time, the second path does not perform charge / discharge input operation, but can perform charge / discharge output operation. At the same time, the voltage of V13, which also falls due to the downward transition of CLK1, reaches the voltage of the input voltage signal VIN through the conducting MN13, so as to turn on the corresponding switch when the second path performs charge / discharge input operation in the future.

[0093] When CLK1 is high and CLK2 is low, V13 rises due to the upward transition of CLK1, causing MN12 and MN14 to conduct. V14 decreases due to the downward transition of CLK2, causing MN11 and MN13 to disconnect. V12 decreases due to the downward transition of CLK2, and the input terminal can charge V12 through the conducting MN12, so that the voltage of the reduced V12 reaches the voltage of the input voltage signal VIN, realizing the second path to perform charge / discharge input operation. At this time, the first path does not perform charge / discharge input operation, but can perform charge / discharge output operation. At the same time, the voltage of V14, which also decreases due to the downward transition of CLK2, reaches the voltage of the input voltage signal VIN through the conducting MN14, so as to turn on the corresponding switch when the first path performs charge / discharge input operation in the future.

[0094] Based on the above method, charge-discharge input operations and charge-discharge input operations can be performed alternately on the same path, and the charge-discharge input operations can be performed alternately on the first path and the second path, thereby realizing uninterrupted operation of the charge pump unit and improving the charge transfer stability of the charge pump.

[0095] Furthermore, since V13 and V14 are disconnected from the input terminal when performing the corresponding switch conduction control, V13 and V14 will not change due to changes in the input voltage signal at the input terminal. This reduces or eliminates the possibility that the charge and discharge input module will not be fully turned on during the charge and discharge input operation due to changes in the input voltage signal, thereby reducing or eliminating the possibility of insufficient charge transfer and improving the transfer efficiency of the charge pump.

[0096] Furthermore, the charge pump is used to output a negative voltage signal; that is, the charge pump is a negative voltage charge pump.

[0097] Each charge pump unit includes two charge pump processing paths, namely a first path and a second path.

[0098] In the first path, the voltage switching module includes a first switching capacitor, and the charge / discharge output module includes a first NMOS switch.

[0099] In the second path, the voltage switching module includes a second switching capacitor, and the charge / discharge output module includes a second NMOS switch.

[0100] The charge / discharge output control module also includes a second switch, and both the first and second switches are NMOS switches.

[0101] One end of the first switching capacitor is used to receive the first clock signal, and the other end of the first switching capacitor is connected to the intermediate node of the first path. One end of the second switching capacitor is used to receive the first clock signal after inversion, and the other end of the second switching capacitor is connected to the intermediate node of the second path. The first end of the first NMOS switch is connected to the intermediate node of the first path, and the first end of the second NMOS switch is connected to the intermediate node of the second path. One end of the first capacitor receives the second clock signal, and the first end of the first switch is connected to the other end of the first capacitor. One end of the second capacitor receives the third clock signal, and the first end of the second switch is connected to the other end of the second capacitor. The second ends of the first NMOS switch, the second NMOS switch, the first switch, and the second switch are respectively connected to the output terminals. The other end of the first capacitor is respectively connected to the control terminals of the second NMOS switch and the second switch. The other end of the second capacitor is respectively connected to the control terminals of the first NMOS switch and the first switch.

[0102] Specifically, see Figure 4 , Figure 4 This is the fourth schematic diagram of an embodiment of the charge pump unit of this application, as shown below. Figure 4 As shown, in the first path: the first switching capacitor is C21, the intermediate node is V21, and the first NMOS switch is MN21.

[0103] In the second path, the second switching capacitor is C22, and the second NMOS switch is MN22.

[0104] In the charge / discharge output control module: the first capacitor is C25, the second capacitor is C26, the first switch is MN23, and the second switch is MN24.

[0105] The second clock signal and the first clock signal are both CLK1, the third clock signal and the first clock signal after inversion are both CLK2, the node at the other end of the first capacitor is V25, and the node at the other end of the second capacitor is V26.

[0106] Both VIN and VOUT are negative voltage signals.

[0107] When CLK1 is low and CLK2 is high, V26 rises due to the upward transition of CLK2, causing MN21 and MN23 to conduct. V25 decreases due to the downward transition of CLK1, causing MN22 and MN24 to disconnect. V21 decreases due to the downward transition of CLK1. The output terminal can discharge V21 through the conducting MN21, so that the voltage of the output voltage signal VOUT reaches the voltage of the reduced V21. That is, the output voltage signal VOUT is reduced relative to the input voltage signal VIN, realizing the first path to perform charge and discharge output operation. At this time, the second path does not perform charge and discharge output operation, but can perform charge and discharge input operation. At the same time, the voltage of V25 reaches the voltage of the output voltage signal VOUT through the conducting MN23, so as to turn on the corresponding switch when the second path performs charge and discharge output operation in the future.

[0108] When CLK1 is high and CLK2 is low, V25 rises due to the upward transition of CLK1, turning on MN22 and MN24. V26 decreases due to the downward transition of CLK2, turning off MN21 and MN23. V22 decreases due to the downward transition of CLK2. The output terminal can discharge V22 through the conducting MN22, so that the voltage of the output voltage signal VOUT reaches the voltage of the reduced V22. That is, the output voltage signal VOUT is reduced relative to the input voltage signal VIN, realizing the second path to perform charge and discharge output operation. At this time, the first path does not perform charge and discharge output operation, but can perform charge and discharge input operation. At the same time, the voltage of V26 reaches the voltage of the output voltage signal VOUT through the conducting MN24, so as to turn on the corresponding switch when the first path performs charge and discharge output operation in the future.

[0109] Based on the above method, charge / discharge input and output operations can be performed alternately on the same path, and charge / discharge output operations can be performed alternately on the first and second paths, thereby achieving uninterrupted operation of the charge pump unit and improving the charge transfer stability of the charge pump.

[0110] Furthermore, since V25 and V26 are disconnected from the output terminal when performing the corresponding switch conduction control, V25 and V26 will not change due to changes in the output voltage signal at the output terminal. This reduces or eliminates the possibility that the charge and discharge output module will not be fully turned on during the charge and discharge output operation due to changes in the output voltage signal, thereby reducing or eliminating the possibility of insufficient charge transfer and improving the transfer efficiency of the charge pump.

[0111] Furthermore, the charge pump unit also includes a charge / discharge input control module.

[0112] In the first path, the charge / discharge input module includes a first PMOS switch, and the charge / discharge input control module includes a third capacitor and a third switch.

[0113] In the second path, the charge / discharge input module includes a second PMOS switch, and the charge / discharge input control module includes a fourth capacitor and a fourth switch.

[0114] Both the third and fourth switches are PMOS switches.

[0115] The first terminal of the first PMOS switch is connected to the middle node of the first path, the first terminal of the second PMOS switch is connected to the middle node of the second path, one terminal of the third capacitor receives the second clock signal, the first terminal of the third switch is connected to the other terminal of the third capacitor, one terminal of the fourth capacitor receives the third clock signal, the first terminal of the fourth switch is connected to the other terminal of the fourth capacitor, the second terminals of the first PMOS switch, the second terminals of the second PMOS switch, the second terminals of the third switch and the second terminals of the fourth switch are respectively connected to the input terminals, the other terminal of the third capacitor is respectively connected to the control terminals of the second PMOS switch and the fourth switch, and the other terminal of the fourth capacitor is respectively connected to the control terminals of the first PMOS switch and the third switch.

[0116] Specifically, such as Figure 4 As shown, in the first path: the first switching capacitor is C21, the intermediate node is V21, and the first PMOS switch is MP21.

[0117] In the second path, the second switching capacitor is C22, and the second PMOS switch is MP22.

[0118] In the charge / discharge output control module: the third capacitor is C23, the fourth capacitor is C24, the third switch is MP23, and the fourth switch is MP24.

[0119] The second clock signal and the first clock signal are both CLK1, the third clock signal and the first clock signal after inversion are both CLK2, the node at the other end of the third capacitor is V23, and the node at the other end of the fourth capacitor is V24.

[0120] Both VIN and VOUT are negative voltage signals.

[0121] When CLK1 is high and CLK2 is low, V24 decreases due to the downward transition of CLK2, causing MP21 and MP23 to conduct. V23 increases due to the upward transition of CLK1, causing MP22 and MP24 to disconnect. V21 increases due to the upward transition of CLK1, and can discharge to the input terminal through the conducting MP21, so that the voltage of the increased V21 reaches the voltage of the input voltage signal VIN, realizing the first path to perform charge / discharge input operation. At this time, the second path does not perform charge / discharge input operation, but can perform charge / discharge output operation. At the same time, the voltage of V23, which also increases due to the upward transition of CLK1, reaches the voltage of the input voltage signal VIN through the conducting MP23, so as to turn on the corresponding switch when the second path performs charge / discharge input operation in the future.

[0122] When CLK1 is low and CLK2 is high, V23 decreases due to the downward transition of CLK1, causing MP22 and MP24 to conduct. V24 increases due to the upward transition of CLK2, causing MP21 and MP23 to disconnect. V22 increases due to the upward transition of CLK2, and can discharge through the conducting MP22 to reach the voltage of the input voltage signal VIN, thus enabling the second path to perform charge / discharge input operation. At this time, the first path does not perform charge / discharge input operation, but can perform charge / discharge output operation. Simultaneously, the voltage of V24, which also increases due to the upward transition of CLK2, reaches the voltage of the input voltage signal VIN through the conducting MP24, so that the corresponding switch can be turned on when the first path performs charge / discharge input operation later.

[0123] Based on the above method, charge-discharge input operations and charge-discharge input operations can be performed alternately on the same path, and the charge-discharge input operations can be performed alternately on the first path and the second path, thereby realizing uninterrupted operation of the charge pump unit and improving the charge transfer stability of the charge pump.

[0124] Furthermore, since V23 and V24 are disconnected from the input terminal when performing the corresponding switch conduction control, V23 and V24 will not change due to changes in the input voltage signal at the input terminal. This reduces or eliminates the possibility that the charge and discharge input module will not be fully turned on during the charge and discharge input operation due to changes in the input voltage signal, thereby reducing or eliminating the possibility of insufficient charge transfer and improving the transfer efficiency of the charge pump.

[0125] In one embodiment, based on the embodiments of the first clock signal, second clock signal and third clock signal mentioned above, the first clock signal and second clock signal are the same signal, and the first clock signal and third clock signal after inversion are the same signal.

[0126] Specifically, for example, in such Figure 3 or Figure 4 In the circuit of the charge pump unit shown, the first clock signal and the second clock signal can both be CLK1, while the signal obtained by inverting the first clock signal and the third clock signal can both be CLK2.

[0127] Based on the above method, the entire charge pump can be controlled using two signals, reducing the complexity and difficulty of signal control and improving the stability of charge pump operation.

[0128] In one embodiment, see Figure 5 , Figure 5 This is a schematic diagram of the structure of one embodiment of the charge pump of this application, as shown below. Figure 5 As shown, at least one charge pump unit includes at least two charge pump units connected in series.

[0129] In two adjacent charge pump units, the output of one charge pump unit is connected to the input of the other charge pump unit.

[0130] Specifically, such as Figure 5 As shown, at least two charge pump units are connected in series, with adjacent charge pump units connected end to end. For example, the input voltage signal of the first charge pump unit is VIN1 and the output voltage signal is VOUT1. The output voltage signal VOUT1 of the first charge pump unit is the input voltage signal VIN2 of the second charge pump unit, and so on. The output voltage signal VOUTX of the last charge pump unit is the final output signal of the charge pump.

[0131] Based on this approach, each charge pump unit can be configured to boost or reduce the received input voltage signal for output, thereby enabling the construction of any desired positive voltage charge pump or negative voltage charge pump, which improves the flexibility of charge pump construction.

[0132] In the description of this application, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0133] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0134] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the function involved, as will be understood by those skilled in the art to which embodiments of this application pertain.

[0135] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (which may be a personal computer, server, network device, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0136] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A charge pump characterized by, Includes at least one charge pump unit, each of the charge pump units comprising: The input terminal is configured to receive an input voltage signal; The output terminal is configured to generate a corresponding output voltage signal; At least two charge pump processing paths are arranged in parallel between the input terminal and the output terminal. Each charge pump processing path includes a charge / discharge input module, an intermediate node, and a charge / discharge output module connected in series. The at least two charge pump processing paths sequentially and alternately perform charge / discharge input operations and charge / discharge output operations. At least one of the charge pump processing paths further includes: A charge / discharge output control module is configured to perform a charge / discharge output operation in response to the corresponding charge pump processing path. The charge / discharge output control module controls the charge / discharge output module to be in a fully on state based on a corresponding clock signal to perform the charge / discharge output operation.

2. The charge pump of claim 1, wherein, When the charge pump is operating The at least two charge pump processing paths sequentially and alternately perform charge and discharge input operations, and at any given time there is a unique charge pump processing path that performs the charge and discharge input operation. The at least two charge pump processing paths sequentially and alternately perform charge and discharge output operations, and at any given time there is a unique charge pump processing path that performs the charge and discharge output operation. The charge pump processing path does not simultaneously perform the charge / discharge input operation and the charge / discharge output operation.

3. The charge pump according to claim 1, characterized in that, The difference between the high-level or low-level amplitude of the clock signal and the output voltage signal is greater than the threshold of the charge / discharge output module, so as to ensure that the charge / discharge output module is in a fully conductive state when the charge / discharge output operation is performed.

4. The charge pump of claim 1, wherein, Each of the charge pump processing paths further includes: The voltage switching module receives a first clock signal and is connected to the intermediate node. The voltage switching module is used for: Before performing the charge / discharge input operation, the voltage of the intermediate node is reduced by the pulse down-jump of the first clock signal so that the intermediate node is charged based on the input terminal when the charge / discharge input module is turned on. Before performing the charge / discharge output operation, the voltage of the intermediate node is increased by the pulse up-jump of the first clock signal so that the output terminal is charged based on the intermediate node when the charge / discharge output module is turned on, thereby generating the corresponding output voltage signal with positive voltage. or, Before performing the charge / discharge input operation, the voltage of the intermediate node is raised by the pulse transition of the first clock signal so that the input terminal is discharged based on the intermediate node when the charge / discharge input module is turned on. Before performing the charge / discharge output operation, the voltage of the intermediate node is lowered by the pulse transition of the first clock signal so that the intermediate node is discharged based on the output terminal when the charge / discharge output module is turned on, thereby generating the corresponding output voltage signal with negative voltage.

5. The charge pump of claim 4, wherein, The charge / discharge output control module includes: A first capacitor, one end of which receives a second clock signal, and the other end of which is connected to the control terminal of the charge / discharge output module; The second capacitor has one end receiving the third clock signal; A first switch is connected between the other end of the first capacitor and the output terminal, and the control terminal of the first switch is connected to the other end of the second capacitor; In response to the second clock signal being in the first logic state and the third clock signal being in the second logic state, the first switch is turned on, and the output voltage signal is transmitted to the other end of the first capacitor through the turned-on first switch; In response to the second clock signal being in the second logic state and the third clock signal being in the first logic state, the signal at the other end of the first capacitor is transmitted to the control terminal of the charge / discharge output module to turn on the charge / discharge output module and make it fully conductive, while the first switch is turned off. The second clock signal and the third clock signal are inverses of each other.

6. The charge pump of claim 5, wherein, The charge pump is used to output the output voltage signal with a positive voltage. Each of the charge pump units includes two charge pump processing paths, the two charge pump processing paths including a first path and a second path; In the first path, the voltage switching module includes a first switching capacitor, and the charge / discharge output module includes a first PMOS switch; In the second path, the voltage switching module includes a second switching capacitor, and the charge / discharge output module includes a second PMOS switch; The charge / discharge output control module further includes a second switch, and both the first switch and the second switch are PMOS switches; One end of the first switching capacitor is used to receive the first clock signal, and the other end of the first switching capacitor is connected to the intermediate node of the first path. One end of the second switching capacitor is used to receive the first clock signal after inversion, and the other end of the second switching capacitor is connected to the intermediate node of the second path. The first end of the first PMOS switch is connected to the intermediate node of the first path, and the first end of the second PMOS switch is connected to the intermediate node of the second path. One end of the first capacitor receives the second clock signal, and the first end of the first switch is connected to the other end of the first capacitor. One end of the second capacitor receives the third clock signal, and the first end of the second switch is connected to the other end of the second capacitor. The second ends of the first PMOS switch, the second ends of the second PMOS switch, the first end of the second switch, and the second end of the second switch are respectively connected to the output terminal. The other end of the first capacitor is respectively connected to the control terminal of the second PMOS switch and the control terminal of the second switch. The other end of the second capacitor is respectively connected to the control terminal of the first PMOS switch and the control terminal of the first switch.

7. The charge pump of claim 6, wherein, The charge pump unit also includes a charge / discharge input control module; In the first path, the charge / discharge input module includes a first NMOS switch, and the charge / discharge input control module includes a third capacitor and a third switch; In the second path, the charge / discharge input module includes a second NMOS switch, and the charge / discharge input control module includes a fourth capacitor and a fourth switch; Both the third switch and the fourth switch are NMOS switches; The first terminal of the first NMOS switch is connected to the intermediate node of the first path, the first terminal of the second NMOS switch is connected to the intermediate node of the second path, one terminal of the third capacitor receives the second clock signal, the first terminal of the third switch is connected to the other terminal of the third capacitor, one terminal of the fourth capacitor receives the third clock signal, the first terminal of the fourth switch is connected to the other terminal of the fourth capacitor, the second terminals of the first NMOS switch, the second terminals of the second NMOS switch, the second terminals of the third switch and the second terminals of the fourth switch are respectively connected to the input terminal, the other terminal of the third capacitor is respectively connected to the control terminal of the second NMOS switch and the control terminal of the fourth switch, and the other terminal of the fourth capacitor is respectively connected to the control terminal of the first NMOS switch and the control terminal of the third switch.

8. The charge pump of claim 5, wherein, The charge pump is used to output the output voltage signal with a negative voltage. Each of the charge pump units includes two charge pump processing paths, the two charge pump processing paths including a first path and a second path; In the first path, the voltage switching module includes a first switching capacitor, and the charge / discharge output module includes a first NMOS switch; In the second path, the voltage switching module includes a second switching capacitor, and the charge / discharge output module includes a second NMOS switch; The charge / discharge output control module further includes a second switch, and both the first switch and the second switch are NMOS switches; One end of the first switching capacitor is used to receive the first clock signal, and the other end of the first switching capacitor is connected to the intermediate node of the first path. One end of the second switching capacitor is used to receive the first clock signal after inversion, and the other end of the second switching capacitor is connected to the intermediate node of the second path. The first end of the first NMOS switch is connected to the intermediate node of the first path, and the first end of the second NMOS switch is connected to the intermediate node of the second path. One end of the first capacitor receives the second clock signal, and the first end of the first switch is connected to the other end of the first capacitor. One end of the second capacitor receives the third clock signal, and the first end of the second switch is connected to the other end of the second capacitor. The second ends of the first NMOS switch, the second end of the second NMOS switch, the first end of the second switch, and the second end of the second switch are respectively connected to the output terminal. The other end of the first capacitor is respectively connected to the control terminal of the second NMOS switch and the control terminal of the second switch. The other end of the second capacitor is respectively connected to the control terminal of the first NMOS switch and the control terminal of the first switch.

9. The charge pump of claim 8, wherein, The charge pump unit also includes a charge / discharge input control module; In the first path, the charge / discharge input module includes a first PMOS switch, and the charge / discharge input control module includes a third capacitor and a third switch; In the second path, the charge / discharge input module includes a second PMOS switch, and the charge / discharge input control module includes a fourth capacitor and a fourth switch; Both the third switch and the fourth switch are PMOS switches; The first terminal of the first PMOS switch is connected to the intermediate node of the first path, the first terminal of the second PMOS switch is connected to the intermediate node of the second path, one terminal of the third capacitor receives the second clock signal, the first terminal of the third switch is connected to the other terminal of the third capacitor, one terminal of the fourth capacitor receives the third clock signal, the first terminal of the fourth switch is connected to the other terminal of the fourth capacitor, the second terminals of the first PMOS switch, the second terminals of the second PMOS switch, the second terminals of the third switch and the second terminals of the fourth switch are respectively connected to the input terminal, the other terminal of the third capacitor is respectively connected to the control terminal of the second PMOS switch and the control terminal of the fourth switch, and the other terminal of the fourth capacitor is respectively connected to the control terminal of the first PMOS switch and the control terminal of the third switch.

10. The charge pump according to any one of claims 5 to 9, characterized in that, The first clock signal and the second clock signal are the same signal, and the first clock signal and the third clock signal after inversion are the same signal.

11. Charge pump according to any one of claims 1 to 9, characterized in that The at least one charge pump unit includes at least two charge pump units connected in series. In two adjacent charge pump units, the output terminal of one charge pump unit is connected to the input terminal of the other charge pump unit.

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