A charge pump

Abstract

This application discloses a charge pump, comprising at least one charge pump unit, each charge pump unit including: an input terminal configured to receive an input voltage signal; an output terminal configured to generate a corresponding output voltage signal; at least two charge pump processing paths arranged in parallel between the input terminal and the output terminal, each charge pump processing path including a charge / discharge input module, an intermediate node, and a charge / discharge output module connected in series, the at least two charge pump processing paths sequentially and alternately performing charge / discharge input operations and charge / discharge output operations; at least one charge pump processing path further includes: a charge / discharge input control module configured to perform a charge / discharge input operation in response to the corresponding charge pump processing path, the charge / discharge input control module controlling the charge / discharge input module to be in a fully conductive state based on a corresponding clock signal to perform the charge / discharge input operation. Based on the above method, the transmission efficiency of the charge pump can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor circuit technology, and in particular to a charge pump. Background Technology

[0002] In the prior art, charge pump circuits are typically used to output voltage signals with the required positive or negative voltage amplitudes to the corresponding devices.

[0003] The drawback of the existing technology is that the existing charge pump circuits usually use an internal voltage signal associated with the output voltage signal of the charge pump circuit to control the switches in the charge pump circuit. When the output voltage signal with positive voltage is low or the output voltage signal with negative voltage is high during the operation of the charge pump circuit, it is easy for the switch controlled by the internal voltage signal to fail to conduct completely when it needs to be fully turned on. This can easily lead to insufficient charge transfer and low transfer efficiency of the existing charge pump. Summary of the Invention

[0004] The main technical problem addressed in this application is how to improve the transfer efficiency of charge pumps.

[0005] To solve the above-mentioned technical problems, the technical solution adopted in this application is: a charge pump, including at least one charge pump unit, each charge pump unit including: an input terminal configured to receive an input voltage signal; an output terminal configured to generate a corresponding output voltage signal; at least two charge pump processing paths, arranged in parallel between the input terminal and the output terminal, each charge pump processing path including a charge / discharge input module, an intermediate node and a charge / discharge output module connected in series, the at least two charge pump processing paths sequentially and alternately performing charge / discharge input operations and charge / discharge output operations; at least one charge pump processing path further includes: a charge / discharge input control module, configured to perform a charge / discharge input operation in response to the corresponding charge pump processing path, the charge / discharge input control module controlling the charge / discharge input module to be in a fully conductive state based on a corresponding clock signal to perform the charge / discharge input operation.

[0006] When the charge pump is working: at least two charge pump processing paths sequentially and alternately perform charge and discharge input operations, and at any given time there is a unique corresponding charge pump processing path performing charge and discharge input operations; at least two charge pump processing paths sequentially and alternately perform charge and discharge output operations, and at any given time there is a unique corresponding charge pump processing path performing charge and discharge output operations; no charge pump processing path performs charge and discharge input operations and charge and discharge output operations simultaneously.

[0007] Specifically, the difference between the high-level or low-level amplitude of the clock signal and the input voltage signal is greater than the threshold of the charge / discharge input module, so as to ensure that the charge / discharge input module is in a fully conductive state when performing charge / discharge input operations.

[0008] Each charge pump processing path further includes a voltage switching module, which receives a first clock signal and is connected to an intermediate node. The voltage switching module is used to: before performing a charge / discharge input operation, reduce the voltage of the intermediate node by a downward pulse of the first clock signal, so as to charge the intermediate node based on the input terminal when the charge / discharge input module is turned on; and before performing a charge / discharge output operation, raise the voltage of the intermediate node by an upward pulse of the first clock signal, so as to charge the output terminal based on the intermediate node when the charge / discharge output module is turned on, generating a corresponding output voltage signal with a positive voltage; or, before performing a charge / discharge input operation, raise the voltage of the intermediate node by an upward pulse of the first clock signal, so as to discharge the input terminal based on the intermediate node when the charge / discharge input module is turned on; and before performing a charge / discharge output operation, reduce the voltage of the intermediate node by a downward pulse of the first clock signal, so as to discharge the intermediate node based on the output terminal when the charge / discharge output module is turned on, generating a corresponding output voltage signal with a negative voltage.

[0009] The charge / discharge input control module includes: a first capacitor, which receives a second clock signal and is connected to the control terminal of the charge / discharge input module; a first switch, whose control terminal receives a signal from an intermediate node and is connected between the first node and the intermediate node; the first node is the node between the first capacitor and the control terminal of the charge / discharge input module; a second switch, whose control terminal receives a third clock signal and is connected between the first node and the intermediate node; in response to the second clock signal being in a first logic state, the charge / discharge input module is turned on and placed in a fully conductive state, thereby causing both the first and second switches to be turned off; in response to the second clock signal being in a second logic state, the charge / discharge input module is turned off and placed in a high-impedance state; in response to the second clock signal being in a second logic state, the first clock signal switches from the first logic state to the second logic state, and the third clock signal switches from the second logic state to the first logic state.

[0010] The charge pump is used to output a positive output voltage signal. Each charge pump unit includes two charge pump processing paths, namely a first path and a second path. In the first path: the charge / discharge input module includes a first PMOS switch, the voltage switching module includes a first switching capacitor, the charge / discharge output module includes a second PMOS switch, and the charge / discharge input control module includes a first capacitor, a first switch, and a second switch, both of which are PMOS switches. The first terminal of the first PMOS switch is connected to the input terminal. One terminal of the first capacitor is used to receive a second clock signal, and the other terminal of the first capacitor is connected to the first terminal of the first switch, the first terminal of the second switch, and the control terminal of the first PMOS switch. The second terminal of the first PMOS switch is connected to the intermediate node of the first path, the control terminal of the first switch, the second terminal of the first switch, and the second terminal of the second switch. The control terminal of the second switch is used to receive a third clock signal. The first terminal of the second PMOS switch is connected to the intermediate node of the first path, and the second terminal of the second PMOS switch is connected to the output terminal. One terminal of the first switching capacitor is used to receive a third clock signal. The system receives a first clock signal, and the other end of the first switching capacitor is connected to the intermediate node of the first path. In the second path: the charge / discharge input module includes a third PMOS switch, the voltage switching module includes a second switching capacitor, the charge / discharge output module includes a fourth PMOS switch, and the charge / discharge input control module includes a second capacitor, a third switch, and a fourth switch, both of which are PMOS switches. The first end of the third PMOS switch is connected to the input terminal, one end of the second capacitor is used to receive the fourth clock signal, and the other end of the second capacitor is connected to the first end of the third switch, the first end of the fourth switch, and the control terminal of the third PMOS switch. The second end of the third PMOS switch is connected to the intermediate node of the second path, the control terminal of the third switch, the second end of the third switch, and the second end of the fourth switch. The control terminal of the fourth switch is used to receive the first clock signal, the first end of the fourth PMOS switch is connected to the intermediate node of the first path, and the second end of the fourth PMOS switch is connected to the output terminal. One end of the second switching capacitor is used to receive the third clock signal, and the other end of the second switching capacitor is connected to the intermediate node of the second path.

[0011] Wherein, the first logic state is a low level state, and the second logic state is a high level state; after the fourth clock signal switches from a low level state to a high level state, the third clock signal switches from a low level state to a high level state; after the third clock signal switches from a low level state to a high level state, the first clock signal switches from a high level state to a low level state; after the first clock signal switches from a high level state to a low level state, the second clock signal switches from a high level state to a low level state; and / or, after the second clock signal switches from a low level state to a high level state, the first clock signal switches from a low level state to a high level state; after the first clock signal switches from a low level state to a high level state, the third clock signal switches from a high level state to a low level state; after the third clock signal switches from a high level state to a low level state, the fourth clock signal switches from a high level state to a low level state.

[0012] The charge pump is used to output a negative voltage signal. Each charge pump unit includes two charge pump processing paths, namely a first path and a second path. In the first path: the charge / discharge input module includes a first NMOS switch, the voltage switching module includes a first switching capacitor, the charge / discharge output module includes a second NMOS switch, and the charge / discharge input control module includes a first capacitor, a first switch, and a second switch, both of which are NMOS switches. The first terminal of the first NMOS switch is connected to the input terminal. One terminal of the first capacitor is used to receive a second clock signal, and the other terminal of the first capacitor is connected to the first terminal of the first switch, the first terminal of the second switch, and the control terminal of the first NMOS switch. The second terminal of the first NMOS switch is connected to the intermediate node of the first path, the control terminal of the first switch, the second terminal of the first switch, and the second terminal of the second switch. The control terminal of the second switch is used to receive a third clock signal. The first terminal of the second NMOS switch is connected to the intermediate node of the first path, and the second terminal of the second NMOS switch is connected to the output terminal. One terminal of the first switching capacitor is used to receive a third clock signal. The system receives a first clock signal, and the other end of the first switching capacitor is connected to the intermediate node of the first path. In the second path: the charge / discharge input module includes a third NMOS switch, the voltage switching module includes a second switching capacitor, the charge / discharge output module includes a fourth NMOS switch, and the charge / discharge input control module includes a second capacitor, a third switch, and a fourth switch, both of which are NMOS switches. The first end of the third NMOS switch is connected to the input terminal, one end of the second capacitor is used to receive the fourth clock signal, and the other end of the second capacitor is connected to the first end of the third switch, the first end of the fourth switch, and the control terminal of the third NMOS switch. The second end of the third NMOS switch is connected to the intermediate node of the second path, the control terminal of the third switch, the second end of the third switch, and the second end of the fourth switch. The control terminal of the fourth switch is used to receive the first clock signal, the first end of the fourth NMOS switch is connected to the intermediate node of the first path, and the second end of the fourth NMOS switch is connected to the output terminal. One end of the second switching capacitor is used to receive the third clock signal, and the other end of the second switching capacitor is connected to the intermediate node of the second path.

[0013] Wherein, the first logic state is a high level state, and the second logic state is a low level state; after the fourth clock signal switches from a high level state to a low level state, the third clock signal switches from a high level state to a low level state; after the third clock signal switches from a high level state to a low level state, the first clock signal switches from a low level state to a high level state; after the first clock signal switches from a low level state to a high level state, the second clock signal switches from a low level state to a high level state; and / or, after the second clock signal switches from a high level state to a low level state, the first clock signal switches from a high level state to a low level state; after the first clock signal switches from a high level state to a low level state, the third clock signal switches from a low level state to a high level state; after the third clock signal switches from a low level state to a high level state, the fourth clock signal switches from a low level state to a high level state.

[0014] The at least one charge pump unit includes at least two charge pump units connected in series; in two adjacent charge pump units, the output terminal of one charge pump unit is connected to the input terminal of the other charge pump unit.

[0015] The at least one charge pump unit includes at least two charge pump units connected in series; in two adjacent charge pump units, the output terminal of one charge pump unit is connected to the input terminal of the other charge pump unit; in the first charge pump unit of the at least two charge pump units, the control terminal of the second switch is used to receive a third clock signal, and the control terminal of the fourth switch is used to receive a first clock signal; in the charge pump units of the at least two charge pump units other than the first charge pump unit, the control terminal of the second switch is connected to the intermediate node of the second path of the previous charge pump unit, and the control terminal of the fourth switch is connected to the intermediate node of the first path of the previous charge pump unit.

[0016] The beneficial effects of this application are as follows: Unlike existing technologies, the technical solution of this application includes at least one charge pump unit, each charge pump unit including an input terminal, an output terminal, and at least two charge pump processing paths; the input terminal is configured to receive an input voltage signal; the output terminal is configured to generate a corresponding output voltage signal; at least two charge pump processing paths are arranged in parallel between the input terminal and the output terminal, each charge pump processing path including a charge / discharge input module, an intermediate node, and a charge / discharge output module connected in series, and the at least two charge pump processing paths sequentially and alternately perform charge / discharge input operations and charge / discharge output operations; at least one charge pump processing path further includes a charge / discharge input control module, configured to perform a charge / discharge input operation in response to the corresponding charge pump processing path, the charge / discharge input control module controlling the charge / discharge input module to be in a fully conductive state based on a corresponding clock signal to perform the charge / discharge input operation. Based on the above method, during the charging and discharging input operation, the charging and discharging input module can be controlled to be in a fully conducting state based on the corresponding clock signal. The clock signal will not change due to changes in the output voltage signal. Therefore, the possibility of the charging and discharging input module not being fully conducting during the charging and discharging input operation due to changes in the output voltage signal is reduced or eliminated. This reduces or eliminates the possibility of insufficient charge transfer and improves the transfer efficiency of the charge pump. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of one embodiment of the charge pump unit of this application;

[0019] Figure 2 This is a second schematic diagram of the structure of an embodiment of the charge pump unit of this application;

[0020] Figure 3 This is a third schematic diagram of the structure of an embodiment of the charge pump unit of this application;

[0021] Figure 4 This is one of the waveform diagrams of an embodiment of the charge pump unit of this application;

[0022] Figure 5 This is the fourth schematic diagram of the structure of an embodiment of the charge pump unit of this application;

[0023] Figure 6This is a second waveform diagram of an embodiment of the charge pump unit of this application;

[0024] Figure 7 This is a schematic diagram of the structure of one embodiment of the charge pump of this application;

[0025] Figure 8 This is a schematic diagram of an embodiment of two charge pump units in a positive pressure charge pump;

[0026] Figure 9 This is a schematic diagram of an embodiment of two charge pump units in a negative pressure charge pump. Detailed Implementation

[0027] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be particularly noted that the following embodiments are for illustrative purposes only and do not limit the scope of the application. Similarly, the following embodiments are only some, not all, embodiments of the present application, and all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present application.

[0028] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0029] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "setting," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or a connection through an intermediate medium. Those skilled in the art will understand the specific meanings of the above terms within the context of this application.

[0030] This application discloses a charge pump, which includes at least one charge pump unit, see [link]. Figure 1 , Figure 1 This is a schematic diagram of one embodiment of the charge pump unit of this application, as shown below. Figure 1 As shown, each charge pump unit includes an input terminal, an output terminal, and at least two charge pump processing paths 1.

[0031] The input terminal is configured to receive an input voltage signal VIN, and the output terminal is configured to generate a corresponding output voltage signal VOUT. Specifically, the input voltage signal VIN can be the input signal to the charge pump unit, and the output voltage signal VOUT is the output signal obtained by performing charge pump processing on the input signal to increase the absolute value of its voltage amplitude.

[0032] At least two charge pump processing paths 1 are arranged in parallel between the input and output terminals. Each charge pump processing path 1 includes a charge / discharge input module, an intermediate node, and a charge / discharge output module connected in series. The at least two charge pump processing paths 1 sequentially and alternately perform charge / discharge input operations and charge / discharge output operations. Wherein, as Figure 1 As shown, in a charge pump processing path 1, one end of the charge / discharge input module is connected to the input terminal to receive the input voltage signal VIN. The intermediate nodes are connected to the other end of the charge / discharge input module and one end of the charge / discharge output module, respectively. The other end of the charge / discharge output module is connected to the output terminal to send the output voltage signal VOUT.

[0033] At least one of the charge pump processing paths 1 also includes a charge / discharge output control module.

[0034] The charge / discharge input control module is configured to perform charge / discharge input operations in response to the corresponding charge pump processing path 1. The charge / discharge input control module controls the charge / discharge input module to be in a fully on state based on the corresponding clock signal to perform the charge / discharge input operations.

[0035] Specifically, the clock signal can be an externally provided voltage signal that is not affected by the output voltage signal VOUT, the input voltage signal VIN, the voltage signal of the intermediate node, or the internal voltage signal of other charge pump units. It can be set according to the conditions of the voltage signal required when the corresponding module controlled by the clock signal is fully turned on, and is not limited here.

[0036] For example, when the charge / discharge input module is a PMOS switch, when the charge / discharge input module needs to be in a fully on state to perform a charge / discharge input operation, a stable and continuous control of the charge / discharge input module's full on state can be achieved by sending the clock signal of the first logic state or a signal that changes accordingly based on the clock signal switching to the first logic state to the control terminal of the charge / discharge input module. When the charge / discharge input module is an NMOS switch, when the charge / discharge input module needs to be in a fully on state to perform a charge / discharge input operation, a stable and continuous control of the charge / discharge input module's full on state can be achieved by sending the clock signal of the second logic state or a signal that changes accordingly based on the clock signal switching to the second logic state to the control terminal of the charge / discharge input module.

[0037] Based on the above approach, in traditional technology, an internal voltage signal provided at an intermediate node or other location within the charge pump unit is typically used to control the charge / discharge input module to be fully turned on. However, the amplitude of the internal voltage signal is easily affected by the devices connected to the output terminal. That is, the amplitude of the internal voltage signal easily changes with the output voltage signal VOUT. This can cause the charge / discharge input module to be prematurely disconnected or not fully turned on when it is required to be fully turned on, which can easily lead to insufficient charge transfer and reduced transfer efficiency.

[0038] In the technical solution of this application, since the clock signal is an externally provided voltage signal with stable high and low level amplitudes that does not change with the output voltage signal VOUT, by setting up a charging and discharging input control module, the charging and discharging input module is fully turned on based on the clock signal. This ensures that the fully turned-on state of the charging and discharging input module is only affected by the clock signal and the control method of the corresponding control module, and is not affected by changes in the output voltage signal VOUT. This allows the charging and discharging input module to be stably turned on when needed, reducing the possibility of premature disconnection or incomplete conduction of the charging and discharging input module, thereby reducing the possibility of insufficient charge transfer and improving transmission efficiency.

[0039] Unlike existing technologies, the technical solution of this application includes at least one charge pump unit, each charge pump unit including an input terminal, an output terminal, and at least two charge pump processing paths; the input terminal is configured to receive an input voltage signal; the output terminal is configured to generate a corresponding output voltage signal; at least two charge pump processing paths are arranged in parallel between the input terminal and the output terminal, each charge pump processing path including a charge / discharge input module, an intermediate node, and a charge / discharge output module connected in series, and the at least two charge pump processing paths alternately perform charge / discharge input operations and charge / discharge output operations; at least one charge pump processing path further includes a charge / discharge input control module, configured to perform a charge / discharge input operation in response to the corresponding charge pump processing path, the charge / discharge input control module controlling the charge / discharge input module to be in a fully conductive state based on a corresponding clock signal to perform the charge / discharge input operation. Based on the above method, during the charging and discharging input operation, the charging and discharging input module can be controlled to be in a fully conducting state based on the corresponding clock signal. The clock signal will not change due to changes in the output voltage signal. Therefore, the possibility of the charging and discharging input module not being fully conducting during the charging and discharging input operation due to changes in the output voltage signal is reduced or eliminated. This reduces or eliminates the possibility of insufficient charge transfer and improves the transfer efficiency of the charge pump.

[0040] In one embodiment, when the charge pump is operating:

[0041] At least two charge pump processing paths sequentially and alternately perform charge and discharge input operations, and at any given time there is only one corresponding charge pump processing path performing the charge and discharge input operation.

[0042] At least two charge pump processing paths sequentially and alternately perform charge and discharge output operations, and at any given time there is only one corresponding charge pump processing path performing the charge and discharge output operation.

[0043] No charge pump processing path can simultaneously perform charge / discharge input operations and charge / discharge output operations.

[0044] Specifically, at the same time, in at least two charge pump processing paths 1, at least one charge pump processing path 1 performs a charge / discharge input operation, and at least one charge pump processing path 1 performs a charge / discharge output operation.

[0045] At any given moment, within the same charge pump processing path 1, no operation may be performed, or only the charge / discharge input operation may be performed without the charge / discharge output operation, or the charge / discharge output operation may be performed without the charge / discharge input operation, but the charge / discharge input operation and the charge / discharge output operation may not be performed simultaneously.

[0046] Based on the above method, the charge pump unit can perform charge and discharge output operations through at least one charge pump processing path 1 to send an output voltage signal VOUT, thereby realizing the current round output of the charge pump. At the same time, it can also perform charge and discharge input operations through at least one charge pump processing path 1 to adjust the voltage of the intermediate node of the corresponding path in order to realize the next round output of the charge pump. The complete cycle of the charge pump can be divided into a preset number of output rounds, and the output voltage signal VOUT is sent by the combination of at least one charge pump processing path 1 in at least two charge pump processing paths 1 respectively. The specific method can be determined according to actual needs and is not limited here.

[0047] For example, when there are at least two charge pump processing paths 1, the first charge pump processing path 1 and the second charge pump processing path 1 alternately perform charge and discharge input operations, and the first charge pump processing path 1 and the second charge pump processing path 1 alternately perform charge and discharge output operations.

[0048] When the number of at least two charge pump processing paths 1 is 3, a cycle can be divided into three time periods. First, the first charge pump processing path 1 performs charge-discharge output operation in the first time period and performs charge-discharge input operation in the second and third time periods. Second, the second charge pump processing path 1 performs charge-discharge output operation in the second time period and performs charge-discharge input operation in the first and third time periods. Finally, the third charge pump processing path 1 performs charge-discharge output operation in the third time period and performs charge-discharge input operation in the first and second time periods.

[0049] The above are just examples. Other examples that meet the above conditions when the charge pump is working will not be elaborated here. The specific conditions can be determined according to the actual situation, and no limitation is made here.

[0050] In one embodiment, the difference between the high-level or low-level amplitude of the clock signal and the input voltage signal is greater than the threshold of the charge / discharge input module, so as to ensure that the charge / discharge input module is in a fully conductive state when performing a charge / discharge input operation.

[0051] Specifically, the charge / discharge input module can be a MOS switch or other device that requires ensuring that the voltage difference between the control terminal and the corresponding terminal is greater than the corresponding threshold.

[0052] By controlling the charging and discharging input module to be fully turned on when the difference between the high-level or low-level amplitude of the clock signal and the output voltage signal is greater than the threshold of the charging and discharging input module, it is possible to ensure that the charging and discharging input module can be in a relatively stable fully turned-on state. This reduces the possibility that the charging and discharging input module may fail to turn on, disconnect prematurely, or fail to turn on completely due to a small difference between the high-level or low-level amplitude of the clock signal and the output voltage signal. This further reduces the possibility of insufficient charge transfer and improves the transfer efficiency.

[0053] In one embodiment, see Figure 2 , Figure 2 This is a second schematic diagram of the structure of an embodiment of the charge pump unit of this application, as shown below. Figure 2 As shown, each charge pump processing path 1 also includes a voltage switching module.

[0054] The voltage switching module receives the first clock signal and connects to the intermediate node. The voltage switching module is used for:

[0055] Before performing the charge / discharge input operation, the voltage of the intermediate node is reduced by the pulse transition of the first clock signal to charge the intermediate node based on the input terminal when the charge / discharge input module is turned on. Before performing the charge / discharge output operation, the voltage of the intermediate node is increased by the pulse transition of the first clock signal to charge the output terminal based on the intermediate node when the charge / discharge output module is turned on, thereby generating a corresponding output voltage signal with positive voltage.

[0056] or,

[0057] Before performing the charge / discharge input operation, the voltage of the intermediate node is raised by the pulse transition of the first clock signal so that the input terminal is discharged based on the intermediate node when the charge / discharge input module is turned on. Before performing the charge / discharge output operation, the voltage of the intermediate node is lowered by the pulse transition of the first clock signal so that the intermediate node is discharged based on the output terminal when the charge / discharge output module is turned on, thereby generating a corresponding output voltage signal with negative voltage.

[0058] Specifically, when the charge pump is a positive voltage charge pump, that is, when the charge pump is used to output an output voltage signal with a positive voltage, before performing the charge / discharge input operation, the voltage of the intermediate node is reduced by the pulse down-jump of the first clock signal so that the intermediate node is charged based on the input terminal when the charge / discharge input module is turned on. And before performing the charge / discharge output operation, the voltage of the intermediate node is increased by the pulse up-jump of the first clock signal so that the output terminal is charged based on the intermediate node when the charge / discharge output module is turned on, thereby generating a corresponding output voltage signal with a positive voltage. Based on the above method, for the same charge pump processing path 1, when the voltage of the intermediate node is reduced by the pulse transition of the first clock signal, the voltage of the intermediate node can reach the voltage of the input voltage signal VIN. Then, the voltage of the intermediate node is raised by the pulse transition of the first clock signal, so that the output voltage signal VOUT is boosted relative to the input voltage signal VIN based on this boost. That is, the absolute value of the positive voltage amplitude of the output voltage signal VOUT is higher than the absolute value of the positive voltage amplitude of the input voltage signal VIN, thus realizing the function of the positive voltage charge pump.

[0059] When the charge pump is a negative voltage charge pump, that is, when the charge pump is used to output a negative voltage signal, before performing the charge / discharge input operation, the voltage of the intermediate node is raised by the pulse transition of the first clock signal so that the input terminal is discharged based on the intermediate node when the charge / discharge input module is turned on. Conversely, before performing the charge / discharge output operation, the voltage of the intermediate node is lowered by the pulse transition of the first clock signal so that the intermediate node is discharged based on the output terminal when the charge / discharge output module is turned on, generating a corresponding negative voltage signal. Based on the above method, for the same charge pump processing path 1, when the voltage of the intermediate node is raised by the pulse transition of the first clock signal, the voltage of the intermediate node reaches the voltage of the input voltage signal VIN. Then, the voltage of the intermediate node is lowered by the pulse transition of the first clock signal so that the output voltage signal VOUT is lowered relative to the input voltage signal VIN. That is, the absolute value of the negative voltage amplitude of the output voltage signal VOUT is higher than the absolute value of the negative voltage amplitude of the input voltage signal VIN, thus realizing the function of a negative voltage charge pump.

[0060] Optionally, the charge / discharge input control module includes a first capacitor, a first switch, and a second switch.

[0061] The first capacitor receives the second clock signal and is connected to the control terminal of the charge / discharge input module.

[0062] The control terminal of the first switch receives the signal from the intermediate node and is connected between the first node and the intermediate node. The first node is the node between the first capacitor and the control terminal of the charge / discharge input module.

[0063] The control terminal of the second switch receives the third clock signal and is connected between the first node and the intermediate node.

[0064] In response to the second clock signal being in the first logic state, the first clock signal being in the first logic state, and the third clock signal being in the second logic state, the charging and discharging input module is turned on and put into a fully conducting state, thereby causing both the first switch and the second switch to be turned off.

[0065] In response to the second clock signal being in the second logic state, the charge / discharge input module is turned off and placed in a high-impedance state.

[0066] In response to the second clock signal being in the second logic state, the first clock signal switches from the first logic state to the second logic state, and the third clock signal switches from the second logic state to the first logic state.

[0067] Specifically, see Figure 3 , Figure 3This is a third schematic diagram of the structure of an embodiment of the charge pump unit of this application, as shown below. Figure 3 As shown, taking one of the charge pump processing paths 1 as an example, the first clock signal is CLKB, the second clock signal is CLKB1, the third clock signal is CLK, the intermediate node is PG12, the voltage switching module can be C1, the charge and discharge input module connected to the charge and discharge input control module is P11 (PMOS switch), the first capacitor can be C3, the first switch can be P15 (PMOS switch), the second switch can be P13 (PMOS switch), the first logic state is a low level state and the second logic state is a high level state.

[0068] In response to CLKB1 being low, CLKB being low, and CLK being high, P11 is turned on and fully conducted, thereby turning off P13 and P15. In summary, the full conduction of P11 can be controlled based on the voltage signal on C3 that decreases due to the downward transition of CLKB1. Since the end of C3 used to send the voltage signal that decreases due to the downward transition of CLKB1 is not connected to the output of the charge pump unit or PG12, the voltage signal received by the control terminal of P11 will not change with the output voltage signal VOUT or PG12. This reduces or eliminates the possibility of incomplete conduction of the charge / discharge input module during charge / discharge input operations due to changes in the output voltage signal, thereby reducing or eliminating the possibility of insufficient charge transfer and improving the transfer efficiency of the charge pump.

[0069] In response to CLKB1 being high, the charge / discharge input module is turned off and placed in a high-impedance state. In response to CLKB1 being high, CLKB switches from low to high, and CLK switches from high to low. In summary, after completing the above-mentioned control P11 to fully conduct to realize the charging and discharging input operation, and making the voltage of PG12 reach the voltage of the input voltage signal VIN, before executing the subsequent charging and discharging output operation, CLKB1 can be switched from a low level to a high level first, and then CLKB can be switched from a low level to a high level. That is, P11 is first turned off, and then the voltage of PG12 rises due to the upward transition of CLKB. This avoids the situation where the voltage of PG12 tends to change towards the voltage of the input voltage signal VIN when PG12 rises but P11 is still in the conducting state. This avoids the backflow phenomenon between PG12 and the input terminal before executing the charging and discharging output operation, further improves the fullness of charge transfer, improves the degree of change of the output voltage signal VOUT relative to the input voltage signal VIN when the subsequent charging and discharging output operation is executed, and further improves the transfer efficiency of the charge pump.

[0070] Furthermore, the charge pump is used to output a positive voltage signal; that is, the charge pump is a positive voltage charge pump.

[0071] Each charge pump unit includes two charge pump processing paths, namely a first path and a second path.

[0072] In the first path:

[0073] The charge / discharge input module includes a first PMOS switch, the voltage switching module includes a first switching capacitor, the charge / discharge output module includes a second PMOS switch, and the charge / discharge input control module includes a first capacitor, a first switch, and a second switch, both of which are PMOS switches.

[0074] The first terminal of the first PMOS switch is connected to the input terminal. One end of the first capacitor is used to receive the second clock signal. The other end of the first capacitor is connected to the first terminal of the first switch, the first terminal of the second switch, and the control terminal of the first PMOS switch. The second terminal of the first PMOS switch is connected to the intermediate node of the first path, the control terminal of the first switch, the second terminal of the first switch, and the second terminal of the second switch. The control terminal of the second switch is used to receive the third clock signal. The first terminal of the second PMOS switch is connected to the intermediate node of the first path. The second terminal of the second PMOS switch is connected to the output terminal. One end of the first switching capacitor is used to receive the first clock signal. The other end of the first switching capacitor is connected to the intermediate node of the first path.

[0075] In the second path:

[0076] The charge / discharge input module includes a third PMOS switch, the voltage switching module includes a second switching capacitor, the charge / discharge output module includes a fourth PMOS switch, and the charge / discharge input control module includes a second capacitor, a third switch, and a fourth switch, both of which are PMOS switches.

[0077] The first terminal of the third PMOS switch is connected to the input terminal. One terminal of the second capacitor is used to receive the fourth clock signal. The other terminal of the second capacitor is connected to the first terminal of the third switch, the first terminal of the fourth switch, and the control terminal of the third PMOS switch. The second terminal of the third PMOS switch is connected to the intermediate node of the second path, the control terminal of the third switch, the second terminal of the third switch, and the second terminal of the fourth switch. The control terminal of the fourth switch is used to receive the first clock signal. The first terminal of the fourth PMOS switch is connected to the intermediate node of the first path. The second terminal of the fourth PMOS switch is connected to the output terminal. One terminal of the second switching capacitor is used to receive the third clock signal. The other terminal of the second switching capacitor is connected to the intermediate node of the second path.

[0078] Specifically, such as Figure 3As shown, the first clock signal is CLKB, the second clock signal is CLKB1, the third clock signal is CLK, the fourth clock signal is CLK1, the intermediate node of the first path is PG12, the control terminal of the first PMOS switch is PG12G, the control terminal of the third PMOS switch is PG11G, the intermediate node of the first path is PG11, the first switching capacitor is C1, the second switching capacitor is C2, the first capacitor is C3, the second capacitor is C4, the first PMOS switch is P11, the second PMOS switch is P17, the third PMOS switch is P12, the fourth PMOS switch is P18, the first switch is P15, the second switch is P13, the third switch is P16, and the fourth switch is P14.

[0079] Based on the above method, when P11 is controlled to be fully on in the first path based on its charge / discharge input control module to perform charge / discharge input operation, and when P12 is controlled to be fully on in the second path based on its charge / discharge input control module, the voltage signals received by the control terminals of P11 or P12 are not affected by changes in the voltage signals at the output terminals of PG12 or PG11. This reduces or eliminates the possibility that the charge / discharge input module may not be fully on during the charge / discharge input operation due to changes in the output voltage signal, thereby reducing or eliminating the possibility of insufficient charge transfer and improving the transfer efficiency of the charge pump.

[0080] Furthermore, based on the above method, while the first path turns on P11 and turns off P17 to perform the charge / discharge input operation, the second path turns off P12 and turns on P18 to perform the charge / discharge output operation. Then, while the first path turns off P11 and turns on P17 to perform the charge / discharge output operation, the second path turns on P12 and turns off P18 to perform the charge / discharge input operation. This allows the charge pump to operate continuously or nearly continuously based on the two paths, that is, to output the required output voltage signal VOUT continuously or nearly continuously, thereby improving the stability and reliability of the charge pump.

[0081] Furthermore, the first logic state is a low level state, and the second logic state is a high level state.

[0082] After the fourth clock signal switches from a low level to a high level, the third clock signal switches from a low level to a high level.

[0083] After the third clock signal switches from a low level to a high level, the first clock signal switches from a high level to a low level.

[0084] After the first clock signal switches from a high level to a low level, the second clock signal switches from a high level to a low level.

[0085] And / or,

[0086] After the second clock signal switches from a low level to a high level, the first clock signal switches from a low level to a high level.

[0087] After the first clock signal switches from a low level to a high level, the third clock signal switches from a high level to a low level.

[0088] After the third clock signal switches from a high level to a low level, the fourth clock signal switches from a high level to a low level.

[0089] Specifically, see Figure 4 , Figure 4 This is one of the waveform diagrams of an embodiment of the charge pump unit of this application, as shown below. Figure 3 and Figure 4 As shown, the first clock signal is CLKB, the second clock signal is CLKB1, the third clock signal is CLK, and the fourth clock signal is CLK1. It is assumed that the amplitude difference between the high and low levels of each clock signal is VDD, the voltage amplitude of the input voltage signal is VDD, and VTHP is the threshold voltage of the PMOS switch.

[0090] In the first case, when CLKB is high, CLK is low, CLK1 is low, and CLKB1 is high, PG12 is connected to PG12G through the conducting P13, keeping the voltage consistent so that P11 is disconnected. At this time, P12 is turned on, so that PG11 is connected to the input terminal through the conducting P12, so that the second path performs the charge / discharge input operation.

[0091] After CLK1 switches from a low level to a high level, CLK switches from a low level to a high level. After completing the charge / discharge input operation, P12 is first disconnected, and then the voltage of PG11 is raised through the CLK transition to prepare for subsequent charge / discharge output operations. Based on this method, the situation where PG11 flows back to the input terminal after the voltage is raised can be avoided, further improving the sufficiency of charge transfer from PG11 to the output terminal and improving the transfer efficiency.

[0092] After CLK switches from a low level to a high level, CLKB switches from a high level to a low level. Before performing the second path charging / discharging output operation, CLK is first switched upwards to disconnect P17, and then CLKB is switched downwards to turn on P18, so that the output terminal is connected to PG11 after the voltage is boosted by the upward switch of CLK. This ensures that the output voltage signal VOUT reaches the voltage of PG11 after the voltage is boosted, preventing the output terminal from flowing back to PG12 after the voltage is reduced due to the downward switch of CLKB, thus realizing the second path charging / discharging output operation.

[0093] After CLKB switches from a high level to a low level, CLKB1 switches from a high level to a low level. At this time, PG12 can be connected to the input terminal after the voltage of PG12 drops due to the CLKB transition, so that the voltage of PG12 reaches the voltage of the input voltage signal VIN. This avoids the current flowing back from PG12 before the voltage drop to the input terminal, further improving the fullness of charge transfer and increasing the transfer efficiency of the charge pump.

[0094] In the second case, when CLK is high, CLKB is low, CLKB1 is low, and CLK1 is high, PG11 is connected to PG11G through the conducting P14, keeping the voltage consistent so that P12 is disconnected. At this time, P11 is turned on, so that PG12 is connected to the input terminal through the conducting P11, so that the first path performs the charge / discharge input operation.

[0095] After CLKB1 switches from a low level to a high level, CLKB switches from a low level to a high level. After completing the charge / discharge input operation, P11 is first disconnected, and then the voltage of PG12 is raised through the CLKB transition to prepare for subsequent charge / discharge output operations. Based on this method, the situation where PG12 flows back to the input terminal after the voltage is raised can be avoided, further improving the sufficiency of charge transfer from PG12 to the output terminal and improving the transfer efficiency.

[0096] After CLKB switches from a low level to a high level, CLK switches from a high level to a low level. Before performing the first path's charge / discharge output operation, CLKB is first switched upwards to disconnect P17, and then CLK is switched downwards to turn on P18, so that the output terminal is connected to PG12 after the voltage is boosted by the upward switch of CLKB. This ensures that the output voltage signal VOUT reaches the voltage of PG12 after the voltage is boosted, preventing the output terminal from flowing back to PG11 after the voltage is reduced due to the downward switch of CLK, thus realizing the first path's charge / discharge output operation.

[0097] After CLK switches from a high level to a low level, CLK1 switches from a high level to a low level. At this time, PG11 can be connected to the input terminal after its voltage drops due to the CLK down-transition. This ensures that the voltage of PG11 reaches the voltage of the input voltage signal VIN, preventing current from flowing back from PG11 before the voltage drop to the input terminal. This further improves the fullness of charge transfer and increases the transfer efficiency of the charge pump.

[0098] Furthermore, the charge pump is used to output a negative voltage signal; that is, the charge pump is a negative voltage charge pump.

[0099] Each charge pump unit includes two charge pump processing paths, namely a first path and a second path.

[0100] In the first path:

[0101] The charge / discharge input module includes a first NMOS switch, the voltage switching module includes a first switching capacitor, the charge / discharge output module includes a second NMOS switch, and the charge / discharge input control module includes a first capacitor, a first switch, and a second switch, both of which are NMOS switches.

[0102] The first terminal of the first NMOS switch is connected to the input terminal. One end of the first capacitor is used to receive the second clock signal. The other end of the first capacitor is connected to the first terminal of the first switch, the first terminal of the second switch, and the control terminal of the first NMOS switch. The second terminal of the first NMOS switch is connected to the intermediate node of the first path, the control terminal of the first switch, the second terminal of the first switch, and the second terminal of the second switch. The control terminal of the second switch is used to receive the third clock signal. The first terminal of the second NMOS switch is connected to the intermediate node of the first path. The second terminal of the second NMOS switch is connected to the output terminal. One end of the first switching capacitor is used to receive the first clock signal. The other end of the first switching capacitor is connected to the intermediate node of the first path.

[0103] In the second path:

[0104] The charge / discharge input module includes a third NMOS switch, the voltage switching module includes a second switching capacitor, the charge / discharge output module includes a fourth NMOS switch, and the charge / discharge input control module includes a second capacitor, a third switch, and a fourth switch, both of which are NMOS switches.

[0105] The first terminal of the third NMOS switch is connected to the input terminal. One terminal of the second capacitor is used to receive the fourth clock signal. The other terminal of the second capacitor is connected to the first terminal of the third switch, the first terminal of the fourth switch, and the control terminal of the third NMOS switch. The second terminal of the third NMOS switch is connected to the intermediate node of the second path, the control terminal of the third switch, the second terminal of the third switch, and the second terminal of the fourth switch. The control terminal of the fourth switch is used to receive the first clock signal. The first terminal of the fourth NMOS switch is connected to the intermediate node of the first path. The second terminal of the fourth NMOS switch is connected to the output terminal. One terminal of the second switching capacitor is used to receive the third clock signal. The other terminal of the second switching capacitor is connected to the intermediate node of the second path.

[0106] Specifically, see Figure 5 , Figure 5 This is the fourth schematic diagram of an embodiment of the charge pump unit of this application, as shown below. Figure 5 As shown, the first clock signal is CLKB, the second clock signal is CLKB1, the third clock signal is CLK, the fourth clock signal is CLK1, the intermediate node of the first path is NG12, the control terminal of the first NMOS switch is NG12G, the control terminal of the third NMOS switch is NG11G, the intermediate node of the first path is NG11, the first switching capacitor is C1, the second switching capacitor is C2, the first capacitor is C3, the second capacitor is C4, the first NMOS switch is N11, the second NMOS switch is N17, the third NMOS switch is N12, the fourth NMOS switch is N18, the first switch is N15, the second switch is N13, the third switch is N16, and the fourth switch is N14.

[0107] Based on the above method, when N11 is controlled to be fully on in the first path based on its charge / discharge input control module to perform charge / discharge input operation, and when N12 is controlled to be fully on in the second path based on its charge / discharge input control module, the voltage signals received by the control terminals of N11 or N12 are not affected by changes in the voltage signals at the output terminals of NG12 or NG11. This reduces or eliminates the possibility that the charge / discharge input module may not be fully on during the charge / discharge input operation due to changes in the output voltage signal, thereby reducing or eliminating the possibility of insufficient charge transfer and improving the transfer efficiency of the charge pump.

[0108] Furthermore, based on the above method, while the first path turns on N11 and turns off N17 to perform the charge / discharge input operation, the second path turns off N12 and turns on N18 to perform the charge / discharge output operation. Then, while the first path turns off N11 and turns on N17 to perform the charge / discharge output operation, the second path turns on N12 and turns off N18 to perform the charge / discharge input operation. This allows the charge pump to operate continuously or nearly continuously based on the two paths, that is, to output the required output voltage signal VOUT continuously or nearly continuously, thereby improving the stability and reliability of the charge pump.

[0109] Furthermore, the first logic state is a high-level state, and the second logic state is a low-level state.

[0110] After the fourth clock signal switches from a high level to a low level, the third clock signal switches from a high level to a low level.

[0111] After the third clock signal switches from a high level to a low level, the first clock signal switches from a low level to a high level.

[0112] After the first clock signal switches from a low level to a high level, the second clock signal switches from a low level to a high level.

[0113] And / or,

[0114] After the second clock signal switches from a high level to a low level, the first clock signal switches from a high level to a low level.

[0115] After the first clock signal switches from a high level to a low level, the third clock signal switches from a low level to a high level.

[0116] After the third clock signal switches from a low level to a high level, the fourth clock signal switches from a low level to a high level.

[0117] Specifically, see Figure 6 , Figure 6 This is a second waveform diagram of an embodiment of the charge pump unit of this application, as shown below. Figure 5 and Figure 6 As shown, the first clock signal is CLKB, the second clock signal is CLKB1, the third clock signal is CLK, and the fourth clock signal is CLK1. It is assumed that the amplitude difference between the high and low levels of each clock signal is VDD, the voltage amplitude of the input voltage signal is GND, and VTHN is the threshold voltage of the NMOS switch.

[0118] In the first case, when CLKB is low, CLK is high, CLK1 is high, and CLKB1 is low, NG12 is connected to NG12G through the conducting N13, keeping the voltage consistent so that N11 is disconnected. At this time, N12 is turned on, so that NG11 is connected to the input terminal through the conducting N12, so that the second path performs the charge / discharge input operation.

[0119] After CLK1 switches from a high level to a low level, CLK switches from a high level to a low level. After completing the charge / discharge input operation, N12 is first disconnected, and then the voltage of NG11 is reduced by the down-switching of CLK to prepare for subsequent charge / discharge output operations. Based on this method, the situation where the input terminal flows back to the NG11 after the voltage is reduced can be avoided, further improving the sufficiency of charge transfer from NG11 to the output terminal and improving the transfer efficiency.

[0120] After CLK switches from a high level to a low level, CLKB switches from a low level to a high level. Before performing the second path charging / discharging output operation, CLK is first switched down to disconnect N17, and then CLKB is switched up to turn on N18, so that the output terminal is connected to NG11 after the voltage is reduced by the CLK switching down. This ensures that the output voltage signal VOUT reaches the voltage of NG11 after the voltage is reduced, preventing the NG12 voltage from rising due to the CLKB switching up from flowing back to the output terminal, thus realizing the second path charging / discharging output operation.

[0121] After CLKB switches from a low level to a high level, CLKB1 switches from a low level to a high level. At this time, after the voltage of NG12 rises due to the transition of CLKB, NG12 can be connected to the input terminal so that the voltage of NG12 reaches the voltage of the input voltage signal VIN. This avoids the current flowing back from the input terminal to NG12 before the voltage rise, further improving the fullness of charge transfer and increasing the transfer efficiency of the charge pump.

[0122] In the second case, when CLK is low, CLKB is high, CLKB1 is high, and CLK1 is low, NG11 is connected to NG11G through the conducting N14, keeping the voltage consistent so that N12 is disconnected. At this time, N11 is turned on, so that NG12 is connected to the input terminal through the conducting N11, so that the first path performs the charge / discharge input operation.

[0123] After CLKB1 switches from a high level to a low level, CLKB switches from a high level to a low level. After completing the charge / discharge input operation, N11 is first disconnected, and then the voltage of NG12 is reduced through the CLKB down-switching to prepare for subsequent charge / discharge output operations. Based on this method, the situation where the input terminal flows back to the NG12 after the voltage is reduced can be avoided, further improving the sufficiency of charge transfer from NG12 to the output terminal and improving the transfer efficiency.

[0124] After CLKB switches from a high level to a low level, CLK switches from a low level to a high level. Before performing the first path's charge / discharge output operation, CLKB is first switched down to disconnect N17, and then CLK is switched up to turn on N18, so that the output terminal is connected to NG12 after the voltage is reduced by the CLKB switch down. This ensures that the output voltage signal VOUT reaches the voltage of NG12 after the voltage is reduced, preventing the NG11 voltage from rising due to the CLK switch from flowing back to the output terminal, thus realizing the first path's charge / discharge output operation.

[0125] After CLK switches from a low level to a high level, CLK1 switches from a low level to a high level. At this time, after the voltage of NG11 rises due to the CLK transition, NG11 can be connected to the input terminal so that the voltage of NG11 reaches the voltage of the input voltage signal VIN. This avoids current flowing back from the input terminal to NG11 before the voltage rise, further improving the fullness of charge transfer and increasing the transfer efficiency of the charge pump.

[0126] In one embodiment, see Figure 7 , Figure 7 This is a schematic diagram of the structure of one embodiment of the charge pump of this application, as shown below. Figure 7 As shown, at least one charge pump unit includes at least two charge pump units connected in series.

[0127] In two adjacent charge pump units, the output of one charge pump unit is connected to the input of the other charge pump unit.

[0128] Specifically, such as Figure 7 As shown, at least two charge pump units are connected in series, with adjacent charge pump units connected end to end. For example, the input voltage signal of the first charge pump unit is VIN1 and the output voltage signal is VOUT1. The output voltage signal VOUT1 of the first charge pump unit is the input voltage signal VIN2 of the second charge pump unit, and so on. The output voltage signal VOUTX of the last charge pump unit is the final output signal of the charge pump.

[0129] Based on this approach, each charge pump unit can be configured to boost or reduce the received input voltage signal for output, thereby enabling the construction of any desired positive voltage charge pump or negative voltage charge pump, which improves the flexibility of charge pump construction.

[0130] In one embodiment, based on the embodiment described above where the charge / discharge input control module includes a second capacitor, a third switch, and a fourth switch, at least one charge pump unit includes at least two charge pump units connected in series.

[0131] In two adjacent charge pump units, the output of one charge pump unit is connected to the input of the other charge pump unit.

[0132] In the first charge pump unit of at least two charge pump units, the control terminal of the second switch is used to receive the third clock signal, and the control terminal of the fourth switch is used to receive the first clock signal.

[0133] In at least two charge pump units, excluding the first charge pump unit, the control terminal of the second switch is connected to the intermediate node of the second path of the previous charge pump unit, and the control terminal of the fourth switch is connected to the intermediate node of the first path of the previous charge pump unit.

[0134] Specifically, firstly, when the charge pump is a positive voltage charge pump, see [reference needed]. Figure 8 , Figure 8 This is a schematic diagram of one embodiment of two charge pump units in a positive pressure charge pump, as shown below. Figure 8 As shown, the two charge pump units are the first charge pump unit and the second charge pump unit.

[0135] In the first charge pump unit, the input voltage signal received at the input terminal is VIN1, and the output voltage signal sent at the output terminal is VOUT1.

[0136] In the second charge pump unit, the input voltage signal received at the input terminal is VIN2, the output voltage signal sent at the output terminal is VOUT2, the second switch is P23, and the fourth switch is P24.

[0137] The control terminal of the second switch P23 in the second charge pump unit is connected to the intermediate node PG11 of the second path in the first charge pump unit, and the control terminal of the fourth switch P24 in the second charge pump unit is connected to the intermediate node PG12 of the second path in the first charge pump unit. Similarly, in the subsequent two adjacent charge pump units, the control terminal of the second switch in the latter charge pump unit is connected to the intermediate node of the second path in the former charge pump unit, and the control terminal of the fourth switch in the latter charge pump unit is connected to the intermediate node of the second path in the former charge pump unit, thus forming a charge pump composed of any number of charge pump units.

[0138] Based on the above method, the possibility of the second or fourth switch failing to turn off properly when needed due to excessively high voltage amplitude of the input voltage signal received by the subsequent charge pump unit can be reduced, thereby improving the reliability of the charge pump.

[0139] Second, when the charge pump is a negative pressure charge pump, see [reference needed]. Figure 9 , Figure 9 This is a schematic diagram of one embodiment of two charge pump units in a negative pressure charge pump, as shown below. Figure 9 As shown, the two charge pump units are the first charge pump unit and the second charge pump unit.

[0140] In the first charge pump unit, the input voltage signal received at the input terminal is VIN1, and the output voltage signal sent at the output terminal is VOUT1.

[0141] In the second charge pump unit, the input voltage signal received at the input terminal is VIN2, the output voltage signal sent at the output terminal is VOUT2, the second switch is N23, and the fourth switch is N24.

[0142] The control terminal of the second switch N23 in the second charge pump unit is connected to the intermediate node NG11 of the second path in the first charge pump unit, and the control terminal of the fourth switch N24 in the second charge pump unit is connected to the intermediate node NG12 of the second path in the first charge pump unit. Similarly, in the subsequent two adjacent charge pump units, the control terminal of the second switch in the latter charge pump unit is connected to the intermediate node of the second path in the former charge pump unit, and the control terminal of the fourth switch in the latter charge pump unit is connected to the intermediate node of the second path in the former charge pump unit, thus forming a charge pump composed of any number of charge pump units.

[0143] Based on the above method, the possibility of the second or fourth switch failing to turn off properly when needed due to the low voltage amplitude of the input voltage signal received by the subsequent charge pump unit can be reduced, thus improving the reliability of the charge pump.

[0144] In the description of this application, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0145] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0146] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the function involved, as will be understood by those skilled in the art to which embodiments of this application pertain.

[0147] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (which may be a personal computer, server, network device, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0148] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A charge pump characterized by, Includes at least one charge pump unit, each of the charge pump units comprising: The input terminal is configured to receive an input voltage signal; The output terminal is configured to generate a corresponding output voltage signal; At least two charge pump processing paths are arranged in parallel between the input terminal and the output terminal. Each charge pump processing path includes a charge / discharge input module, an intermediate node, and a charge / discharge output module connected in series. The at least two charge pump processing paths sequentially and alternately perform charge / discharge input operations and charge / discharge output operations. At least one of the charge pump processing paths further includes: A charge / discharge input control module is configured to perform a charge / discharge input operation in response to the corresponding charge pump processing path. The charge / discharge input control module controls the charge / discharge input module to be in a fully on state based on a corresponding clock signal to perform the charge / discharge input operation.

2. The charge pump of claim 1, wherein, When the charge pump is operating The at least two charge pump processing paths sequentially and alternately perform charge and discharge input operations, and at any given time there is a unique charge pump processing path that performs the charge and discharge input operation. The at least two charge pump processing paths sequentially and alternately perform charge and discharge output operations, and at any given time there is a unique charge pump processing path that performs the charge and discharge output operation. The charge pump processing path does not simultaneously perform the charge / discharge input operation and the charge / discharge output operation.

3. The charge pump according to claim 1, characterized in that, The difference between the high-level or low-level amplitude of the clock signal and the input voltage signal is greater than the threshold of the charge / discharge input module, so as to ensure that the charge / discharge input module is in a fully conductive state when the charge / discharge input operation is performed.

4. The charge pump of claim 1, wherein, Each of the charge pump processing paths further includes: The voltage switching module receives a first clock signal and is connected to the intermediate node. The voltage switching module is used for: Before performing the charge / discharge input operation, the voltage of the intermediate node is reduced by the pulse down-jump of the first clock signal so that the intermediate node is charged based on the input terminal when the charge / discharge input module is turned on. Before performing the charge / discharge output operation, the voltage of the intermediate node is increased by the pulse up-jump of the first clock signal so that the output terminal is charged based on the intermediate node when the charge / discharge output module is turned on, thereby generating the corresponding output voltage signal with positive voltage. or, Before performing the charge / discharge input operation, the voltage of the intermediate node is raised by the pulse transition of the first clock signal so that the input terminal is discharged based on the intermediate node when the charge / discharge input module is turned on. Before performing the charge / discharge output operation, the voltage of the intermediate node is lowered by the pulse transition of the first clock signal so that the intermediate node is discharged based on the output terminal when the charge / discharge output module is turned on, thereby generating the corresponding output voltage signal with negative voltage.

5. The charge pump of claim 4, wherein, The charge / discharge input control module includes: The first capacitor receives the second clock signal and is connected to the control terminal of the charge / discharge input module; A first switch, the control terminal of the first switch receives the signal from the intermediate node and is connected between the first node and the intermediate node; wherein, the first node is the node between the first capacitor and the control terminal of the charge / discharge input module; The second switch, the control terminal of the second switch receives the third clock signal and is connected between the first node and the intermediate node; In response to the second clock signal being in the first logic state, the first clock signal being in the first logic state, and the third clock signal being in the second logic state, the charging and discharging input module is turned on and put into a fully conducting state, thereby causing both the first switch and the second switch to be turned off. In response to the second clock signal being in the second logic state, the charge / discharge input module is turned off and placed in a high-impedance state; In response to the second clock signal being in the second logic state, the first clock signal switches from the first logic state to the second logic state, and the third clock signal switches from the second logic state to the first logic state.

6. The charge pump of claim 5, wherein, The charge pump is used to output the output voltage signal with a positive voltage. Each of the charge pump units includes two charge pump processing paths, the two charge pump processing paths including a first path and a second path; In the first path: The charge / discharge input module includes a first PMOS switch, the voltage switching module includes a first switching capacitor, the charge / discharge output module includes a second PMOS switch, and the charge / discharge input control module includes the first capacitor, the first switch, and the second switch, wherein the first switch and the second switch are both PMOS switches; The first terminal of the first PMOS switch is connected to the input terminal. One terminal of the first capacitor is used to receive the second clock signal. The other terminal of the first capacitor is connected to the first terminal of the first switch, the first terminal of the second switch, and the control terminal of the first PMOS switch. The second terminal of the first PMOS switch is connected to the intermediate node of the first path, the control terminal of the first switch, the second terminal of the first switch, and the second terminal of the second switch. The control terminal of the second switch is used to receive the third clock signal. The first terminal of the second PMOS switch is connected to the intermediate node of the first path. The second terminal of the second PMOS switch is connected to the output terminal. One terminal of the first switching capacitor is used to receive the first clock signal. The other terminal of the first switching capacitor is connected to the intermediate node of the first path. In the second path: The charge / discharge input module includes a third PMOS switch, the voltage switching module includes a second switching capacitor, the charge / discharge output module includes a fourth PMOS switch, and the charge / discharge input control module includes a second capacitor, a third switch, and a fourth switch, wherein the third switch and the fourth switch are both PMOS switches. The first terminal of the third PMOS switch is connected to the input terminal. One terminal of the second capacitor is used to receive the fourth clock signal. The other terminal of the second capacitor is connected to the first terminal of the third switch, the first terminal of the fourth switch, and the control terminal of the third PMOS switch. The second terminal of the third PMOS switch is connected to the intermediate node of the second path, the control terminal of the third switch, the second terminal of the third switch, and the second terminal of the fourth switch. The control terminal of the fourth switch is used to receive the first clock signal. The first terminal of the fourth PMOS switch is connected to the intermediate node of the first path. The second terminal of the fourth PMOS switch is connected to the output terminal. One terminal of the second switching capacitor is used to receive the third clock signal. The other terminal of the second switching capacitor is connected to the intermediate node of the second path.

7. The charge pump of claim 6, wherein, The first logic state is a low level state, and the second logic state is a high level state; After the fourth clock signal switches from a low level state to a high level state, the third clock signal switches from a low level state to a high level state. After the third clock signal switches from a low level state to a high level state, the first clock signal switches from a high level state to a low level state. After the first clock signal switches from a high level state to a low level state, the second clock signal switches from a high level state to a low level state. And / or, After the second clock signal switches from a low level state to a high level state, the first clock signal switches from a low level state to a high level state. After the first clock signal switches from a low level state to a high level state, the third clock signal switches from a high level state to a low level state. After the third clock signal switches from a high level state to a low level state, the fourth clock signal switches from a high level state to a low level state.

8. The charge pump of claim 5, wherein, The charge pump is used to output the output voltage signal with a negative voltage. Each of the charge pump units includes two charge pump processing paths, the two charge pump processing paths including a first path and a second path; In the first path: The charge / discharge input module includes a first NMOS switch, the voltage switching module includes a first switching capacitor, the charge / discharge output module includes a second NMOS switch, and the charge / discharge input control module includes the first capacitor, the first switch, and the second switch, wherein the first switch and the second switch are both NMOS switches; The first terminal of the first NMOS switch is connected to the input terminal. One terminal of the first capacitor is used to receive the second clock signal. The other terminal of the first capacitor is connected to the first terminal of the first switch, the first terminal of the second switch, and the control terminal of the first NMOS switch. The second terminal of the first NMOS switch is connected to the intermediate node of the first path, the control terminal of the first switch, the second terminal of the first switch, and the second terminal of the second switch. The control terminal of the second switch is used to receive the third clock signal. The first terminal of the second NMOS switch is connected to the intermediate node of the first path. The second terminal of the second NMOS switch is connected to the output terminal. One terminal of the first switching capacitor is used to receive the first clock signal. The other terminal of the first switching capacitor is connected to the intermediate node of the first path. In the second path: The charge / discharge input module includes a third NMOS switch, the voltage switching module includes a second switching capacitor, the charge / discharge output module includes a fourth NMOS switch, and the charge / discharge input control module includes a second capacitor, a third switch, and a fourth switch, wherein the third switch and the fourth switch are both NMOS switches; The first terminal of the third NMOS switch is connected to the input terminal. One terminal of the second capacitor is used to receive the fourth clock signal. The other terminal of the second capacitor is connected to the first terminal of the third switch, the first terminal of the fourth switch, and the control terminal of the third NMOS switch. The second terminal of the third NMOS switch is connected to the intermediate node of the second path, the control terminal of the third switch, the second terminal of the third switch, and the second terminal of the fourth switch. The control terminal of the fourth switch is used to receive the first clock signal. The first terminal of the fourth NMOS switch is connected to the intermediate node of the first path. The second terminal of the fourth NMOS switch is connected to the output terminal. One terminal of the second switching capacitor is used to receive the third clock signal. The other terminal of the second switching capacitor is connected to the intermediate node of the second path.

9. The charge pump of claim 8, wherein, The first logic state is a high level state, and the second logic state is a low level state; After the fourth clock signal switches from a high level state to a low level state, the third clock signal switches from a high level state to a low level state. After the third clock signal switches from a high level state to a low level state, the first clock signal switches from a low level state to a high level state. After the first clock signal switches from a low level state to a high level state, the second clock signal switches from a low level state to a high level state. And / or, After the second clock signal switches from a high level state to a low level state, the first clock signal switches from a high level state to a low level state. After the first clock signal switches from a high level state to a low level state, the third clock signal switches from a low level state to a high level state. After the third clock signal switches from a low level state to a high level state, the fourth clock signal switches from a low level state to a high level state.

10. The charge pump according to any one of claims 1 to 9, characterized in that, The at least one charge pump unit includes at least two charge pump units connected in series. In two adjacent charge pump units, the output terminal of one charge pump unit is connected to the input terminal of the other charge pump unit.

11. Charge pump according to any one of claims 6 to 9, characterized in that The at least one charge pump unit includes at least two charge pump units connected in series. In two adjacent charge pump units, the output terminal of one charge pump unit is connected to the input terminal of the other charge pump unit; In the first charge pump unit of the at least two charge pump units, the control terminal of the second switch is used to receive the third clock signal, and the control terminal of the fourth switch is used to receive the first clock signal; In the at least two charge pump units excluding the first charge pump unit, the control terminal of the second switch is connected to the intermediate node of the second path of the previous charge pump unit, and the control terminal of the fourth switch is connected to the intermediate node of the first path of the previous charge pump unit.

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