A kind of dynamic adjustment secondary power supply circuit for negative pressure DCDC

Abstract

This invention provides a dynamically adjustable secondary power supply circuit for negative voltage DC-DC converters, comprising a zero-temperature drift matching current generation module, a dynamic voltage generation and comparison module, and a level shifting and buffered output module. The zero-temperature drift reference current generation module generates a reference current. The dynamic voltage generation and comparison module compares VA and VB to determine the voltage difference between VIN and VOUT, outputting a mode selection signal SEL. The level shifting and buffered output module selects VA or VIN as the voltage follower target and outputs VAUX based on the mode selection signal SEL and the target voltage. This invention maximizes power efficiency while ensuring chip reliability and solves the transient response problem of internal power supply in negative voltage systems. It is particularly suitable for powering the gate drive circuit in negative voltage DC-DC converters with high switching frequencies and high dynamic loads. This invention effectively solves the core contradictions in the design of internal secondary power supplies for negative voltage DC-DC converters regarding process compatibility, dynamic response, and efficiency optimization, and has high practical value and market competitiveness.

Description

Technical Field

[0001] This invention relates to the field of electrical components technology, and more specifically to a dynamically adjustable secondary power supply circuit for negative voltage DC-DC converters. Background Technology

[0002] In advanced display driving, sensor biasing, and other applications, DC-DC converters with positive input and negative output are often required. The power switches and control circuitry within these converters require a dedicated secondary power supply (VAUX). To ensure chip reliability, the voltage of this secondary power supply and the voltage across the gate of the power transistor (typically the voltage difference between VIN and VOUT) must conform to the process-permitted voltage range (e.g., not exceeding 6V).

[0003] Traditional LDO solutions face multiple challenges: First, process limitations. In standard CMOS or BCD processes, the chip substrate is typically grounded (0V). If the circuit node voltage drops below -0.7V, the parasitic diodes of transistors or MOSFETs may conduct, causing the node to be unexpectedly clamped and the circuit to malfunction. This makes it difficult to directly generate accurate reference voltages, level shifts, and outputs in the negative voltage domain. Second, dynamic response and ripple issues. To save chip area and application costs, the secondary power supply is usually not connected to large external capacitors. When the load (such as a digital logic gate) experiences a large current jump of 0-50mA within nanoseconds, traditional low-dropout linear regulators (LDOs) will produce output voltage drops and ripples of up to several volts due to insufficient slew rate and untimely switching of power transistor on-resistance, failing to meet power supply requirements. Third, efficiency optimization. To minimize system power consumption, the secondary power supply voltage should be as high as possible while meeting process safety requirements to reduce dynamic losses in the drive circuit. This requires the secondary power supply voltage VAUX to be dynamically adjusted according to the input voltage VIN and output voltage VOUT of the main converter.

[0004] While existing technologies have focused on optimizing the topology and drive circuit of negative voltage converters, or utilizing Darlington structures for level conversion and current driving, no effective solution has yet been found to provide a complete power supply with dynamic adjustability, ultra-fast response, and low ripple for negative voltage converters under strict process constraints and without external capacitors.

[0005] Therefore, a circuit is needed to provide a dynamically adjustable, ultra-fast response, low ripple, and high-efficiency secondary power supply for negative voltage converters. Summary of the Invention

[0006] This invention addresses the limitations of power supply circuit manufacturing processes, dynamic response, ripple, and efficiency optimization by providing a dynamically adjustable secondary power supply circuit for negative voltage DC-DC converters. This circuit dynamically adjusts the output voltage according to the operating state of the main converter, ensuring that the power transistor always operates within a safe gate voltage range. Simultaneously, its unique output stage design provides nanosecond-level transient response, achieves extremely low output voltage ripple without the need for external large capacitors, and is fully compatible with standard chip manufacturing processes.

[0007] This invention provides a dynamically adjustable secondary power supply circuit for negative voltage DC-DC converters, comprising a zero-temperature drift matching current generation module, a dynamic voltage generation and comparison module, and a level transfer and buffer output module connected in sequence. The zero-temperature-drift reference current generation module operates between the input voltage VIN and ground, and outputs I based on a bandgap reference structure. PTAT Generate reference current The output is then sent to the dynamic voltage generation and comparison module. The zero-temperature drift voltage of the zero-temperature drift reference current generation module is... V bg The negative feedback loop of the zero-temperature drift reference current generation module includes resistor R1, and the voltage across resistor R1 is related to... V bg equal, Including the same reference current I ref1 and reference current I ref2 ; The dynamic voltage generation and comparison module uses a current mirror to generate the reference current. The voltage is copied to the negative voltage domain to generate voltage nodes A and B. A comparator compares the first reference voltage VA of voltage node A with the second reference voltage VB of voltage node B to determine the voltage difference between VIN and VOUT and outputs a mode selection signal SEL to the level shift and buffer output module. VOUT is a negative voltage output. Resistor R2 is connected between VOUT and node A. Node B receives the reference current. Connect resistor R3 between node B and VIN; The output terminals of the level shift and buffer output module and the dynamic voltage generation and comparison module are all connected to VIN. The level shift and buffer output module selects VA or VIN as the voltage follower target and outputs the secondary power supply VAUX according to the mode selection signal SEL and the target voltage.

[0008] In the present invention, a dynamically adjustable secondary power supply circuit for a negative voltage DC-DC converter is preferably described in which the zero-temperature drift reference current generation module operates in the positive voltage domain. For a temperature-independent reference current, I ref1The current mirror input to the dynamic voltage generation and comparison module outputs to resistor R2 connected to node VOUT, thereby generating the first reference voltage VA at node A. ref2 The output is sent to node B to generate the second reference voltage VB.

[0009] The present invention provides a dynamic adjustment secondary power supply circuit for negative voltage DC-DC converters. In a preferred embodiment, the zero-temperature drift matching current generation module includes a diode D1, a resistor R0, a resistor R1, an operational amplifier OP1, an NMOS transistor MN1, an NMOS transistor MN2, and an NMOS transistor MN3. The positive terminal of diode D1 is connected to VIN, and the negative terminal is connected to the positive terminal of resistor R0; the negative terminal of resistor R0 is also connected to I. PTAT And the inverting input terminal of operational amplifier OP1, I PTAT The negative terminal of the transistor is grounded, the positive terminal of resistor R1 is connected to VIN, the positive input terminal of operational amplifier OP1 is connected to the negative terminal of resistor R1 and the drain of transistor MN1, the output terminal of operational amplifier OP1 is connected to the gates of transistors MN1, MN2, and MN3, and the sources of transistors MN1, MN2, and MN3 are all grounded; the drains of transistors MN2 and MN3 output reference current I. ref1 and reference current I ref2 Reference current I ref1 and reference current I ref2 All outputs are sent to the dynamic voltage generation and comparison module; Operational amplifier OP1, transistor MN1, and resistor R1 form a negative feedback loop, forcing the voltage across resistor R1 to equal V bg This generates a reference current. .

[0010] In the present invention, a dynamic adjustment secondary power supply circuit for negative voltage DC-DC converters is provided, in a preferred embodiment, in which transistors MN1, MN2, and MN3 are identical NMOS transistors.

[0011] The present invention provides a dynamic adjustment secondary power supply circuit for negative voltage DC-DC converters. As a preferred embodiment, when the voltage difference between VIN and VOUT is less than... When SEL outputs a high level, the level transfer and buffer output module controls the secondary power supply VAUX to directly connect to VIN; When the pressure difference between VIN and VOUT is greater than or equal to When SEL outputs a low level, the level shifting and buffering output module uses the first reference voltage VA as the target voltage. This is the breakdown voltage of the low-voltage device.

[0012] The present invention provides a dynamic adjustment secondary power supply circuit for negative voltage DC-DC converters. In a preferred embodiment, the dynamic voltage generation and comparison module includes: a current mirror unit, a voltage divider unit, a voltage comparator COMP1, and a clamping protection unit. The current mirror unit will reference current I ref1 The voltage is mirrored to resistor R2 connected to node VOUT. The resistance of R2 is K times the resistance of resistor R1, forming the first reference voltage VA at node A. ; The voltage divider unit divides VIN to form a second reference voltage VB at node B: ; The non-inverting input of voltage comparator COMP1 is connected to node B, the inverting input is connected to node A, and the output terminal outputs the mode selection signal SEL. The clamping protection unit is connected to node A, when At that time, the voltage at node A will be clamped to 0V or above.

[0013] In a preferred embodiment of the dynamic adjustment secondary power supply circuit for negative voltage DC-DC converters described in this invention, the current mirror unit includes PMOS transistors MP1, MP2, and MP3, both with their sources connected to VIN, node A, and resistor R2. The drain and gate of transistor MP1 are both connected to a reference current I. ref1 The gates of transistors MP2 and MP3 are connected. The drain of transistor MP2 is connected to the clamping protection unit. The drain of transistor MP3 is connected to node A and the positive terminal of resistor R2. The negative terminal of resistor R2 is connected to VOUT. The voltage divider unit includes resistor R3 and node B, with a reference current I. ref2 Connect node B and the negative terminal of resistor R3 in sequence, and connect the positive terminal of resistor R3 to VIN; The clamping protection unit includes NPN transistors Q4 and Q5. The collectors and bases of transistors Q4 and Q5 are connected to the drain of transistor MP2. The emitter of transistor Q4 is grounded, and the emitter of Q5 is connected to node A. when When VA > 0V, the current in transistor MP2 flows through the collector and base of transistor Q4, and transistor Q5 is in the off state; when When VA < 0V, transistor Q5 is turned on, injecting current into node A to stabilize node A at 0V.

[0014] In a preferred embodiment of the dynamic adjustment secondary power supply circuit for negative voltage DC-DC converters described in this invention, the level shifting and buffer output module follows the target voltage through operational amplifier OP2 and outputs the secondary power supply VAUX through a composite buffer, which is composed of a PNP transistor and a Darlington NPN transistor. The level shifting and buffered output module reduces the small-signal drive current required by operational amplifier OP2 to 1 / (1+β) of the load current. 3 , where β is the current gain of the transistor in the composite buffer.

[0015] In a preferred embodiment of the dynamic adjustment sub-power supply circuit for negative voltage DC-DC converters described in this invention, the negative input terminal of operational amplifier OP2 receives a first reference voltage VA, and the positive input terminal outputs VAUX. The composite buffer includes PMOS transistor MP4, PMOS transistor MP5, PNP transistor Q1, NPN transistor Q2, and NPN transistor Q3; The gate of transistor MP4 is connected to the output of operational amplifier OP2, its source is connected to VIN, and its drain is connected to the base of Q1 and I. b1 The positive electrode; The gate of transistor MP5 is connected to node SEL, and the source is connected to VIN; The emitter of transistor Q1 is connected to I b2 The negative electrode of Q1 and the base of Q2; The emitter of transistor Q2 is connected to I b3 The positive electrode of Q1 and the base of Q2; The emitter of transistor Q3, the drain of transistor MP5, the positive input terminal of OP2, and I b4 The positive terminals are all connected to node VAUX and ultimately output; I b1 I b3 I b4 Negative terminals are all grounded, I b2 Collectors Q2 and Q3 are both connected to VIN; The output of operational amplifier OP2 is driven by a Darlington buffer consisting of transistors Q1, Q2, and Q3. Transistor Q1 performs an initial level shift, and the emitter of Q2 is connected to the base of Q3 to form a Darlington pair. The current amplification factor is... .

[0016] To avoid the problems of existing technologies, it is necessary to redesign and optimize the entire circuit based on the traditional secondary power supply LDO, and solve the problem of providing a complete solution for a negative voltage converter with dynamically adjustable, ultra-fast response, low ripple, and high efficiency under strict process constraints and without external capacitors. Therefore, this invention provides a secondary power supply circuit for use inside a positive-to-negative voltage DC-DC converter, and in particular, a negative voltage secondary power supply design that can dynamically adjust the output voltage and has ultra-fast transient response and low ripple characteristics.

[0017] This invention relates to a dynamically adjustable low-ripple power supply circuit for a negative voltage DC-DC converter, comprising a zero-temperature drift matching current generation module, a dynamic voltage generation and comparison module, and a level shifting and buffered output module.

[0018] The zero-temperature-drift matching current generation module 100 generates a matching current that is independent of temperature and acts on a specific resistor within the positive voltage domain, based on a bandgap reference. The dynamic voltage generation and comparison module is connected to the output terminal, positive voltage input VIN terminal, and negative voltage output VOUT terminal of the zero-temperature drift reference current generation module. It is used to generate a first reference voltage VOUT+4.8V and a second reference voltage VIN-1.2V, and compare the two to select an output mode signal, thereby dynamically controlling the secondary power supply output voltage VAUX. The dynamic voltage generation and comparison module 200 mirrors the reference current to the negative voltage domain through a high-voltage current mirror to generate two key voltage nodes, VOUT+4.8V and VIN-1.2V. After being judged by a comparator, when the input-output voltage difference (VIN-VOUT) is less than 6V, the secondary power supply output voltage VAUX is directly connected to VIN; otherwise, VAUX is dynamically adjusted to VOUT+4.8V. The circuit is highly efficient in multiplexing and has a dynamic adjustment function. The level shifting and buffered output module 300 is connected to the output and VIN terminals of the dynamic voltage generation and comparison module 200. It receives the mode selection signal and the target voltage, and performs level shifting and power driving through a composite buffer structure, outputting a VAUX voltage with low ripple characteristics. The level shifting and buffered output module 300 employs a buffer structure based on a combination of PNP and Darlington NPN amplifiers to amplify the small-signal output current of the operational amplifier by (1+β). 3 This invention enables nanosecond-level fast response and low output voltage ripple by driving the load after multiplication, achieving this without the need for a large capacitor. It solves the technical challenge of providing a high-efficiency, reliable, and high-dynamic-performance secondary power supply for a negative voltage converter under standard process negative voltage limitations and without the need for an external large capacitor.

[0019] The present invention has the following advantages: This invention maximizes power efficiency while ensuring chip reliability and solves the transient response problem of internal power supply in negative voltage systems. It is particularly suitable for powering the gate drive circuit in negative voltage DC-DC converters with high switching frequencies and high dynamic loads. This invention effectively solves the core contradictions in the design of the internal secondary power supply of negative voltage DC-DC converters regarding process compatibility, dynamic response, and efficiency optimization, and has high practical value and market competitiveness. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the overall circuit structure of a dynamically adjustable secondary power supply circuit for negative voltage DC-DC converters. Figure 2This is a circuit diagram of a zero-temperature-drift reference current generation module for a dynamically adjustable secondary power supply circuit used in negative voltage DC-DC converters. Figure 3 This is a circuit diagram of a dynamic voltage generation and comparison module for a dynamic adjustment secondary power supply circuit used in negative voltage DC-DC converters. Figure 4 This is a circuit diagram of a level shifting and buffered output module for a dynamically adjusted secondary power supply circuit used in negative voltage DC-DC converters. Figure 5 A simulation comparison of the output voltage ripple of a dynamically adjusted secondary power supply circuit for negative voltage DC-DC converters and a traditional LDO under nanosecond-level load step conditions. Figure 6 This is a timing diagram showing the dynamic adjustment of the secondary power supply output voltage VAUX of a dynamic adjustment secondary power supply circuit for negative voltage DC-DC converter as the input VIN and output VOUT of the main converter change. Figure label: 100. Zero-temperature-drift reference current generation module; 200. Dynamic voltage generation and comparison module; 300. Level shifting and buffered output module. Detailed Implementation

[0021] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Example 1

[0022] like Figures 1-4 As shown, a dynamically adjustable secondary power supply circuit for negative voltage DC-DC converters mainly consists of three parts: The zero-temperature-drift matching current generation module 100 operates entirely in the positive voltage domain, using a bandgap reference to generate a precise matching current with zero temperature drift, laying the foundation for subsequent circuits.

[0023] The dynamic voltage generation and comparison module 200 includes: The high-voltage current mirror unit mirrors the reference current onto the resistor R2 connected to the VOUT node, where the resistance of R2 is 4 times the resistance of the resistor R1 in the zero-temperature drift matching current generation module 100, thereby forming the first reference voltage VA = VOUT + 4.8V at node A. The voltage divider unit divides VIN to form a second reference voltage VB = VIN - 1.2V at node B; A voltage comparator, with its non-inverting input connected to node B and its inverting input connected to node A, outputs the mode selection signal SEL. The clamping protection unit, connected to node A, is used to clamp the voltage of node A to 0V or above when VOUT < -4.8V.

[0024] The dynamic voltage generation and comparison module 200 safely "copies" the reference current to the negative voltage domain via a high-voltage current mirror, generating the critical VOUT+4.8V and VIN-1.2V voltage nodes. A comparator compares these two nodes to intelligently determine the voltage difference between VIN and VOUT. If the voltage difference is less than 6V, the secondary power supply VAUX is controlled to directly supply VIN for maximum efficiency; if the voltage difference is greater than or equal to 6V, VOUT+4.8V is used as the target voltage to ensure gate voltage safety. This module also integrates a 0V clamp to prevent negative voltage output when VOUT is too low.

[0025] Level shifting and buffered output module 300: This module uses an operational amplifier to follow the target voltage and outputs the signal through a composite buffer consisting of a PNP transistor and a Darlington NPN transistor. This ingenious structure reduces the small-signal drive current required by the operational amplifier to 1 / (1+β) of the load current. 3 This enables an extremely fast response to nanosecond-level large load current changes, suppressing output ripple to a low level.

[0026] Figure 1 This is the overall architecture of the present invention. The positive voltage input VIN (2V~6V) and negative voltage output VOUT (-2V to -6V) are the interfaces of the main DC-DC converter. The secondary power supply circuit of the present invention comprises three core modules: a zero-temperature drift matching current generation module 100, a dynamic voltage generation and comparison module 200, and a level shifting and buffered output module 300. The zero-temperature drift matching current generation module 100 generates a reference current. The dynamic voltage generation and comparison module 200 utilizes... The system generates a judgment voltage and outputs a mode selection signal SEL and a dynamic reference voltage VA (VOUT+4.8V). The level shifting and buffer output module 300 selects VA or VIN as the voltage follower target based on the SEL signal and outputs a stable VAUX (auxiliary voltage) through a high-bandwidth buffer.

[0027] Figures 2-4 In this circuit, MP1~MP4 are all PMOS transistors, MN1~MN3 are NMOS transistors, Q1 is a PNP transistor, Q2~Q5 are NPN transistors, D1 is a diode, OP1~OP2 are operational amplifiers, COMP1 is a comparator, and I... PTAT and I b1 ~ I b4 It is a bias current source from other modules, and the current source flows from the positive terminal to the negative terminal.

[0028] Figure 2This describes a specific implementation of the zero-temperature drift matching current generation module 100. A PTAT current is generated by the bandgap core of other modules. This current flows through resistor R0 and diode D1, generating... V bg =1.2V zero-temperature drift voltage. Operational amplifier OP1, NMOS transistor MN1, and resistor R1 form a negative feedback loop, forcing the voltage across R1 to equal... V bg This generates a precise reference current. All components in this section operate between VIN and ground and are unaffected by negative voltage.

[0029] The circuit connection is as follows: the positive terminal of D1 is connected to VIN, and the negative terminal is connected to the positive terminal of R0; the negative terminal of R0 is simultaneously connected to I from the bandgap. PTAT The bias is applied to the inverting input of op-amp OP1; I PTAT The negative terminal of the bias is grounded; the positive terminal of R1 is connected to VIN; the positive input terminal of OP1 is connected to the negative terminal of R1 and also to the drain of MN1; the output terminal of OP1 is connected to the gates of MN1, MN2, and MN3; the sources of MN1, MN2, and MN3 are all grounded; the drains of MN2 and MN3 output current I respectively. ref1 and I ref2 .

[0030] Figure 3 For the dynamic voltage generation and comparison module 200, high-voltage PMOS transistors MP3, MP2, and MP1 form a current mirror, which... Mirror image. The current from the MP3 player flows into resistor R2 connected to VOUT. Through careful design, If K is 4, then the pressure drop across R2 is Therefore, the voltage at node A is Meanwhile, through resistor R3 = R1, a voltage drop of 1.2V is generated across R3, resulting in a voltage at node B. Comparator CMP1 compares VA and VB. Based on the following relationship: When VIN - VOUT < 6V, VB > VA, SEL outputs a high level, selecting the VIN path.

[0031] When VIN - VOUT ≥ 6V, VB ≤ VA, SEL outputs a low level, selecting the VA path.

[0032] The clamping circuit monitors node A. When VOUT > -4.8V, VA > 0V. At this time, the current of MP2 flows through the collector and base of the self-biased transistor QN2, and the clamping transistor QN1 is in the off state. When VOUT < -4.8V, VA < 0V, the clamping transistor QN1 is turned on, injecting current into node A and stabilizing it at approximately 0V, thereby protecting the subsequent circuits.

[0033] The circuit connection relationship is as follows: I ref1 Connect the drain and gate of MP1, and also connect them to the gates of MP2 and MP3; the sources of MP1~MP3 are all connected to VIN; the drain of MP2 is connected to the collector and base of Q4 and Q5; the emitter of Q4 is grounded; the emitter of Q5 is connected to node A; the drain of MP3, the positive terminal of R2, and the inverting input of COMP1 are connected to node A; the negative terminal of R2 is connected to VOUT; the negative terminal of R3, the positive input of COMP1, and I... ref2 Connect to node B; connect the positive terminal of R3 to VIN; connect the output terminal of COMP1 to node SEL.

[0034] Figure 4 This is a level shifting and buffered output module 300. Operational amplifier OP2 receives the target voltage VA at its negative input and connects to the output VAUX at its positive input, forming a system loop voltage follower. The output of OP2 drives a Darlington buffer composed of PNP transistor Q1 and NPN transistors Q2 and Q3. Q1 performs initial level shifting to obtain a wider output voltage range. The emitter of Q2 is connected to the base of Q3, forming a Darlington pair with a current amplification factor of [missing information]. This means that when the load requires current... At that time, the small signal current required by the power transistor MP4 at the output terminal of OP2 is only This greatly reduces the driving burden on the op-amp, allowing for a smaller op-amp design to achieve high bandwidth, while also avoiding the need for large external capacitors to handle high-speed load changes. When the load current... When the voltage jumps from 0 to 50mA within 1 nanosecond, the structure can respond immediately through the rapid current amplification of Q1, Q2, and Q3, avoiding excessive voltage drop caused by op-amp slew rate limitation and power transistor turn-on delay.

[0035] In traditional LDOs, rapid transient changes in load current cannot be promptly transmitted to the gate voltage of the power transistor via the operational amplifier. Consequently, the output voltage ripple problem cannot be solved by adjusting the impedance of the power transistor. Therefore, during rapid load changes, the source-drain small-signal impedance of the power transistor can be considered as a constant. ,when The voltage drop that occurs when the voltage changes from 0 mA to 50 mA within 1 nanosecond can be calculated as follows: After a sufficiently long period of time, the output voltage will once again meet the target requirements, when... The voltage rise caused by a jump from 50mA to 0mA within 1 nanosecond can be calculated as follows: This makes the ripple size The small-signal source drain resistance of the MOSFET The ripple is often very large, typically 1kΩ to 10kΩ or even higher, resulting in a large ripple effect.

[0036] In this invention, when the load is carried out within 1 nanosecond... When the value changes, the current at the base of Q3 changes as follows: The change in base current of Q2 is The change in base current of Q1 is That is, the small signal amplitude acting on the power transistor MOS is only The current gain β of a high-gain transistor is typically between 10 and 100, therefore the voltage drop and rise of the MP4 drain voltage caused by an excessively small ∆I1 are negligible. The output voltage drop in this invention is mainly caused by changes in the transistor's current. Changes, Q1-Q3 ,in This is the small-signal impedance from the base to the emitter of a transistor, typically ranging from 100Ω to 1kΩ. Therefore, when When undergoing rapid changes, the voltage drop can be calculated as follows: ; Considering that rbe is often significantly smaller than r o The current gain of the Q3 transistor under high current in the process is... Therefore, it can be concluded that The structure of this invention can significantly reduce the problem of large drops caused by rapid load response.

[0037] The circuit connections are as follows: the inverting input of OP2 is connected to node A; the output of OP2 is connected to the gate of MP4; the gate of MP5 is connected to node SEL; the sources of MP4 and MP5 are connected to VIN; the drain of MP4 is connected to the base of Q1 and I. b1 The positive terminal of Q1; the emitter of Q1 is connected to I. b2 The negative electrode of Q1 and the base of Q2; the emitter of Q2 is connected to I. b3 The positive terminal of Q3 and the base of Q3; the emitter of Q3, the drain of MP5, the positive input terminal of OP2 and I b4 The positive terminal is connected to node VAUX and ultimately output. The above I... b1 I b3 I b4 Negative terminals are all grounded; I b2 Collectors Q2 and Q3 are both connected to VIN.b1 I b2 I b3 I b4 This is the bias current.

[0038] Figure 5 The simulation comparison waveforms demonstrate the superiority of the present invention. Figure 5 The traditional LDO circuit in this context refers to a circuit where the preceding stage remains unchanged, only the [missing information - likely a specific component or stage] is replaced. Figure 4 The drain of the MP4 transistor is directly connected to VAUX. While reducing the size of the Q1-Q3 circuit, the aspect ratio of the MP4 power transistor is increased to achieve the same layout area as before the modification. During simulation, the input voltage VIN is set to 5V and the output voltage VOUT to -3.3V. Under the same 1ns rise / fall time, 20ns pulse width, and 50mA load step condition, the output voltage VAUX of the traditional LDO experiences severe sag and overshoot, with a voltage drop of up to 3V and a peak-to-peak ripple of 6V, recovering after a 1µs delay. In contrast, the VAUX generated by the circuit of this invention exhibits significantly reduced sag and overshoot, with a sag of only 0.38V, and recovers at a nanosecond speed after the load current decreases, with a peak-to-peak ripple of only 0.45V, resulting in greatly improved voltage stability.

[0039] Figure 6 To ensure VAUX dynamically adjusts with the main circuit, VIN is always set to 3V. Within 0-30us, VOUT changes slowly, decreasing from 0V to -3.5V. Before 25us, VIN-VOUT < 6V, the voltage difference is less than 6V, SEL output is low, and VAUX is directly connected to VIN (3V). After 25us, the voltage difference VIN-VOUT > 6V, SEL output is high, and the circuit quickly switches the output to VAUX = VA = VOUT + 4.8V.

[0040] During the 55µs-80µs period, the VOUT voltage continued to slowly decrease from -3.3V to -6V. When VA followed suit and decreased to 0V, it was clamped, and thereafter VAUX = VA and did not decrease further. Throughout the entire process, VAUX remained greater than 0V, and the voltage difference between VAUX and VOUT was always ensured to be within a safe range.

[0041] In summary, this invention, through its innovative circuit architecture, effectively solves the core contradictions in the design of the internal secondary power supply of a negative voltage DC-DC converter regarding process compatibility, dynamic response, and efficiency optimization, and has high practical value and market competitiveness.

[0042] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A dynamic adjustment secondary power supply circuit for negative voltage DCDC, characterized by: It includes a zero-temperature drift matching current generation module (100), a dynamic voltage generation and comparison module (200), and a level transfer and buffer output module (300) that are connected in sequence. The zero-temperature-drift reference current generation module (100) operates between the input voltage VIN and ground, and outputs I based on the bandgap reference structure. PTAT Generate reference current And output to the dynamic voltage generation and comparison module (200), the zero-temperature drift voltage of the zero-temperature drift reference current generation module (100) is V bg The negative feedback loop of the zero-temperature drift reference current generation module (100) includes a resistor R1, and the voltage across the resistor R1 is related to... V bg equal, Including the same reference current I ref1 and reference current I ref2 ; The dynamic voltage generation and comparison module (200) uses a current mirror to generate a reference current. The voltage is copied to the negative voltage domain to generate voltage nodes A and B. The comparator compares the first reference voltage VA of voltage node A and the second reference voltage VB of voltage node B to determine the voltage difference between VIN and VOUT and outputs the mode selection signal SEL to the level shift and buffer output module (300). VOUT is a negative voltage output. A resistor R2 is connected between VOUT and node A. The input reference current is at node B. Connect resistor R3 between node B and VIN; The level shifting and buffering output module (300) is connected to the output terminal and VIN of the dynamic voltage generation and comparison module (200). The level shifting and buffering output module (300) selects VA or VIN as the voltage follower target and outputs the secondary power supply VAUX according to the mode selection signal SEL and the target voltage.

2. The dynamic adjustment secondary power supply circuit for negative voltage DCDC according to claim 1, characterized in that: The zero temperature drift reference current generating module (100) works in positive voltage domain, For the temperature independent reference current, I ref1 The current mirror input to the dynamic voltage generating and comparing module (200) and output to the resistance R2 connected with the VOUT node to generate the first reference voltage VA on the node A, I ref2 Output to the node B to generate the second reference voltage VB.

3. The dynamic adjustment secondary power supply circuit for negative voltage DCDC of claim 1, wherein: The zero-temperature drift matching current generation module (100) includes diode D1, resistor R0, resistor R1, operational amplifier OP1, NMOS transistor MN1, NMOS transistor MN2 and NMOS transistor MN3; The positive terminal of diode D1 is connected to VIN, and the negative terminal is connected to the positive terminal of resistor R0; the negative terminal of resistor R0 is also connected to I. PTAT And the inverting input terminal of operational amplifier OP1, I PTAT The negative terminal of the transistor is grounded, the positive terminal of resistor R1 is connected to VIN, the positive input terminal of operational amplifier OP1 is connected to the negative terminal of resistor R1 and the drain of transistor MN1, the output terminal of operational amplifier OP1 is connected to the gates of transistors MN1, MN2, and MN3, and the sources of transistors MN1, MN2, and MN3 are all grounded; the drains of transistors MN2 and MN3 output reference current I. ref1 and reference current I ref2 Reference current I ref1 and reference current I ref2 All are output to the dynamic voltage generation and comparison module (200); The operational amplifier OP1, the transistor MN1 and the resistor R1 form a negative feedback loop, which forces the voltage across the resistor R1 to be equal to V bg , thereby generating a reference current .

4. A dynamically adjustable secondary power supply circuit for negative voltage DC-DC converters according to claim 3, characterized in that: MN1, MN2 and MN3 are all identical NMOS transistors.

5. The dynamic adjustment secondary power supply circuit for negative voltage DCDC of claim 1, wherein: When the voltage difference between VIN and VOUT is less than SEL outputs high level, and the level transition controls the pass-through of VIN by the secondary power supply VAUX in the buffer output module (300). When the pressure difference between VIN and VOUT is greater than or equal to When SEL outputs a low level, the level shifting and buffering output module (300) uses the first reference voltage VA as the target voltage; is the breakdown voltage of the low voltage device.

6. The dynamic adjustment secondary power supply circuit for negative voltage DCDC of claim 1, wherein: The dynamic voltage generation and comparison module (200) includes: a current mirror unit, a voltage divider unit, a voltage comparator COMP1, and a clamping protection unit; The current mirror unit will reference current I ref1 The voltage is mirrored to resistor R2 connected to node VOUT. The resistance of R2 is K times the resistance of resistor R1, forming the first reference voltage VA at node A. ； The voltage divider unit divides VIN to form a second reference voltage VB at node B: ； The non-inverting input of voltage comparator COMP1 is connected to node B, the inverting input is connected to node A, and the output terminal outputs the mode selection signal SEL. The clamping protection unit is connected to node A, and when clamps the voltage of node A at 0 V or above.

7. The dynamic adjustment secondary power supply circuit for negative voltage DCDC of claim 6, wherein: The current mirror unit includes PMOS transistors MP1, MP2, and MP3, both with their sources connected to VIN, node A, and resistor R2. The drain and gate of transistor MP1 are both connected to a reference current I. ref1 The gates of transistors MP2 and MP3 are connected. The drain of transistor MP2 is connected to the clamping protection unit. The drain of transistor MP3 is connected to node A and the positive terminal of resistor R2. The negative terminal of resistor R2 is connected to VOUT. The voltage dividing unit comprises a resistor R3 and a node B, and a reference current I ref2 Connect node B and the negative pole of resistor R3 in sequence, and connect the positive pole of resistor R3 with VIN. The clamping protection unit includes NPN transistors Q4 and Q5. The collector and base of transistors Q4 and Q5 are both connected to the drain of transistor MP2. The emitter of transistor Q4 is grounded, and the emitter of Q5 is connected to node A. when When VA > 0V, the current in transistor MP2 flows through the collector and base of transistor Q4, and transistor Q5 is in the off state; when When VA < 0V, transistor Q5 is turned on, injecting current into node A to stabilize node A at 0V.

8. The dynamic adjustment secondary power supply circuit for negative voltage DCDC of claim 1, wherein: The level shifting and buffer output module (300) follows the target voltage through the operational amplifier OP2 and outputs the secondary power supply VAUX through the composite buffer, which is composed of a PNP transistor and a Darlington NPN transistor. The level shift and buffer output module (300) reduces the small signal drive current required to be provided by the operational amplifier OP2 to 1 / (1+β) of the load current 3 where β is the current gain of the transistors in the composite buffer.

9. The dynamic adjustment secondary power supply circuit for negative voltage DCDC of claim 8, wherein: The negative input terminal of operational amplifier OP2 receives the first reference voltage VA, and the positive input terminal outputs VAUX; The composite buffer includes PMOS transistor MP4, PMOS transistor MP5, PNP transistor Q1, NPN transistor Q2 and NPN transistor Q3; The output end of the operational amplifier OP2 is connected with the grid of the tube MP4, the source is connected with VIN, and the drain is connected with the base of Q1 and I b1 the positive electrode of the battery The gate of transistor MP5 is connected to node SEL, and the source is connected to VIN; The emitter of the transistor Q1 is connected to the negative pole of the battery I b2 and the base of the transistor Q2. The emitter of transistor Q2 is connected to I b3 The positive electrode of Q1 and the base of Q2; The emitter of tube Q3, the drain of tube MP5, the positive input of OP2 and the positive pole of I b4 are connected to the node VAUX and are finally outputted; I b1 , I b3 , I b4 negative electrode is grounded, I b2 , Q2 collector, Q3 collector are grounded to VIN; The output of the operational amplifier OP2 is driven by a Darlington buffer consisting of the transistor Ql for a preliminary level shift and the transistors Q2 and Q3 connected in a Darlington pair with a current amplification factor of .

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