Transient response compensation circuit, DC-DC converter, driver chip and electronic equipment

Abstract

This disclosure relates to the field of integrated circuit technology, and more particularly to a transient response compensation circuit, a DC-DC converter, a driver chip, and an electronic device. The transient response compensation circuit is applied in a DC-DC converter and includes a pull-up unit, a pull-down unit, and a control unit. The control unit is used to: pull up the error signal voltage through the pull-up unit when the output voltage is lower than the reference voltage by a preset voltage value; or pull down the error signal voltage through the pull-down unit when the output voltage is higher than the reference voltage by a preset voltage value. The transient response compensation circuit of this disclosure improves the transient response rate of the DC-DC converter by pulling up the error voltage signal when the output voltage is lower than the reference voltage by a preset voltage value, and by pulling down the error voltage signal when the output voltage is higher than the reference voltage by a preset voltage value.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a transient response compensation circuit, a DC-DC converter, a driver chip, and electronic equipment. Background Technology

[0002] As electronic devices evolve towards miniaturization and high performance, DC-DC converters, as core components of power conversion, directly determine the operational stability and reliability of the equipment through their transient response performance. With the continuous expansion of end-user applications, some users are placing higher demands on the transient response speed of DC-DC converters. For example, they require output current to undergo significant jumps within a very short time, with corresponding transient change rates far exceeding traditional design requirements. This poses a severe challenge to the rapid adjustment capabilities of DC-DC converters.

[0003] In the actual operation of DC-DC converters, load transients are a common occurrence. For example, in boost-type DC-DC converters, the inductor current operates in two modes: Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM), and these two modes switch between each other as the load changes. During load transients, when the inductor current switches from discontinuous to continuous conduction mode, the rate of change of the error amplifier's output (EAOUT) slows down significantly, leading to a large undershoot at the converter output and severely affecting the stability of the output voltage.

[0004] The aforementioned issues make rapid transient response of the load a core challenge in the design process of DC-DC converters. How to improve the transient response speed and meet the application requirements of high transient scenarios has become a technical problem that urgently needs to be solved in the current DC-DC converter design field. Summary of the Invention

[0005] In view of this, this disclosure proposes a transient response compensation circuit applied in a DC-DC converter. The DC-DC converter includes a voltage conversion module and a feedback module. The voltage conversion module is used to convert the input voltage to generate an output voltage. The feedback module is used to generate a reset signal based on the error signal of the output voltage and a synthesized slope compensation voltage. The synthesized slope compensation voltage is obtained by adding the inductor current sampling voltage of the inductor in the voltage conversion module and a preset slope compensation voltage.

[0006] The transient response compensation circuit includes a pull-up unit, a pull-down unit, and a control unit. The control unit is used for:

[0007] If the output voltage is lower than the reference voltage by a preset value, the voltage of the error signal is pulled up by the pull-up unit; or

[0008] When the output voltage is higher than the reference voltage by a preset voltage value, the voltage of the error signal is pulled down by the pull-down unit.

[0009] In one possible implementation, the pull-up unit includes a first operational amplifier, a pull-up transistor, a pull-up current source, a pull-up resistor, and a pull-up switch, wherein,

[0010] The non-inverting input of the first operational amplifier is used to receive the synthesized ramp compensation voltage.

[0011] The inverting input terminal of the first operational amplifier is connected to the source of the pull-up transistor and the second terminal of the pull-up resistor.

[0012] The output of the first operational amplifier is connected to the gate of the pull-up transistor, and the drain of the pull-up transistor is grounded.

[0013] The positive terminal of the pull-up current source is connected to the power supply voltage.

[0014] The negative terminal of the pull-up current source is connected to the first terminal of the pull-up switch and the first terminal of the pull-up resistor.

[0015] The second end of the pull-up switch is connected to the feedback module.

[0016] When the output voltage is lower than the reference voltage by a preset value, the pull-up switch is turned on by the control unit; otherwise, the pull-up switch is turned off by the control unit.

[0017] The pull-up transistor is a PMOS transistor.

[0018] In one possible implementation, the pull-down unit includes a second operational amplifier, a pull-down transistor, a pull-down current source, a pull-down resistor, and a pull-down switch, wherein,

[0019] The non-inverting input of the second operational amplifier is used to receive the synthesized ramp compensation voltage.

[0020] The inverting input terminal of the second operational amplifier is connected to the positive terminal of the pull-down current source and the second terminal of the pull-down resistor.

[0021] The output of the second operational amplifier is connected to the gate of the pull-down transistor.

[0022] The drain of the pull-down transistor is connected to the power supply voltage, and the source of the pull-down transistor is connected to the first terminal of the pull-down switch and the first terminal of the pull-down resistor.

[0023] The second terminal of the pull-down switch is connected to the feedback module.

[0024] When the output voltage exceeds the reference voltage by a preset value, the pull-down switch is turned on by the control unit; otherwise, the pull-down switch is turned off by the control unit.

[0025] The pull-down transistor is an NMOS transistor.

[0026] In one possible implementation, the transient response compensation circuit further includes a low-pass filter circuit, which comprises a first filter switch, a second filter switch, a filter resistor, and a filter capacitor.

[0027] Both the first terminal of the first filter switch and the first terminal of the second filter switch are used to receive the synthesized slope compensation voltage.

[0028] The second terminals of both the first and second filter switches are connected to the first terminal of the filter resistor.

[0029] The second terminal of the filter resistor and the first terminal of the filter capacitor are used to output the filtered composite slope compensation voltage.

[0030] The second terminal of the filter capacitor is grounded.

[0031] The first filter switch is controlled by the switch control signal, and the second filter switch is controlled by the reset signal.

[0032] In one possible implementation, the control unit includes a third operational amplifier, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first control resistor, a second control resistor, a first comparator, and a second comparator, wherein...

[0033] The non-inverting input of the third operational amplifier, the non-inverting input of the first comparator, and the inverting input of the second comparator are all used to receive the reference voltage.

[0034] The inverting input terminal of the third operational amplifier is connected to the source of the first transistor and the first terminal of the first control resistor.

[0035] The output of the third operational amplifier is connected to the gate of the first transistor.

[0036] The power supply terminal of the third operational amplifier, the source of the second transistor, and the source of the third transistor are all connected to the power supply voltage.

[0037] The gate and drain of the second transistor, the gate of the third transistor, and the drain of the first transistor are connected.

[0038] The drain of the third transistor, the drain and gate of the fourth transistor, and the gate of the fifth transistor are connected.

[0039] The drain of the fifth transistor, the second terminal of the second control resistor, the non-inverting input of the second comparator, and the inverting input of the first comparator are connected.

[0040] The first terminal of the second control resistor is used to connect to the output voltage.

[0041] The second terminal of the first control resistor, the source of the fourth transistor, and the source of the fifth transistor are all grounded.

[0042] The output terminals of the first comparator and the second comparator are used to output control signals, which are used for:

[0043] If the output voltage is lower than the reference voltage by a preset value, the pull-up unit is controlled to pull up the voltage of the error signal; or

[0044] When the output voltage is higher than the reference voltage by a preset value, the pull-down unit is controlled to pull down the voltage of the error signal.

[0045] In one possible implementation, the first transistor, the fourth transistor, and the fifth transistor are all NMOS transistors, and the second transistor and the third transistor are all PMOS transistors.

[0046] In one possible implementation, the DC-DC converter includes any one of a boost DC-DC converter, a buck DC-DC converter, or a boost-buck DC-DC converter.

[0047] According to one aspect of this disclosure, a DC-DC converter is provided, the DC-DC converter including the transient response compensation circuit described above.

[0048] According to one aspect of this disclosure, a driver chip is provided, the chip including the aforementioned DC-DC converter.

[0049] According to one aspect of this disclosure, an electronic device is provided, the electronic device including the aforementioned driver chip.

[0050] The transient response compensation circuit of this embodiment improves the transient response rate of the DC-DC converter by pulling up the error voltage signal when the output voltage is lower than the reference voltage by a preset voltage value, and pulling down the error voltage signal when the output voltage is higher than the reference voltage by a preset voltage value.

[0051] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0052] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0053] Figure 1 A schematic diagram of a transient response compensation circuit according to an embodiment of the present disclosure is shown.

[0054] Figure 2a A schematic diagram of a boost DC-DC converter according to an embodiment of the present disclosure is shown.

[0055] Figure 2b It shows Figure 2a A schematic diagram of the signal waveform of a boost DC-DC converter.

[0056] Figure 3a , Figure 3b Schematic diagrams of a buck DC-DC converter and a buck-boost DC-DC converter are shown respectively.

[0057] Figure 4a A schematic diagram of a pull-up unit and a pull-down unit according to an embodiment of the present disclosure is shown.

[0058] Figure 4b A schematic diagram of a control unit according to an embodiment of the present disclosure is shown.

[0059] Figure 5 A schematic diagram of a low-pass filter circuit LPF according to an embodiment of the present disclosure is shown.

[0060] Figure 6a and Figure 6b The signal diagrams for PWM and trit are shown in DCM mode and CCM mode, respectively.

[0061] Figure 7 A schematic diagram of the transient response simulation of a boost DC-DC converter is shown.

[0062] Figure 8 A simulation diagram of a boost DC-DC converter is shown. Detailed Implementation

[0063] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0064] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0065] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0066] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0067] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0068] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0069] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant regions.

[0070] Please see Figure 1 , Figure 1 A schematic diagram of a transient response compensation circuit according to an embodiment of the present disclosure is shown.

[0071] like Figure 1 As shown, the transient response compensation circuit 20 is applied in a DC-DC converter 10. The DC-DC converter 10 includes a voltage conversion module 110 and a feedback module 120. The voltage conversion module 110 is used to convert the input voltage Vin to generate an output voltage Vout. The feedback module 120 is used to generate a reset signal based on the error signal of the output voltage Vout and the synthesized slope compensation voltage. The reset signal is used to control the duty cycle of the switching control signal of the voltage conversion module 110. The synthesized slope compensation voltage is obtained by adding the inductor current sampling voltage of the inductor in the voltage conversion module 110 and a preset slope compensation voltage.

[0072] The transient response compensation circuit 20 may include a pull-up unit 210, a pull-down unit 230, and a control unit 220, wherein the control unit 220 is used for:

[0073] When the output voltage Vout is lower than the reference voltage Vref by a preset voltage value, the voltage of the error signal is pulled up by the pull-up unit 210; or

[0074] When the output voltage Vout is higher than the reference voltage Vref by a preset voltage value, the voltage of the error signal is pulled down by the pull-down unit 230.

[0075] The transient response compensation circuit 20 of this embodiment improves the transient response rate of the DC-DC converter 10 by pulling up the error voltage signal when the output voltage Vout is lower than the reference voltage Vref by a preset voltage value, and pulling down the error voltage signal when the output voltage Vout is higher than the reference voltage Vref by a preset voltage value.

[0076] The specific value of the preset voltage is not limited in the embodiments disclosed herein. Those skilled in the art can set it according to actual conditions and needs. It should be noted that in the embodiments of this disclosure, the case where the output voltage Vout is lower than the reference voltage Vref by a value reaching the preset voltage value (the difference between the reference voltage Vref and the output voltage Vout reaches the preset voltage value) includes the case where the output voltage Vout is lower than the reference voltage Vref by a value exceeding the preset voltage value (the difference between the reference voltage Vref and the output voltage Vout is greater than the preset voltage value); correspondingly, the case where the output voltage Vout is higher than the reference voltage Vref by a value reaching the preset voltage value (the difference between the output voltage Vout and the reference voltage Vref reaches the preset voltage value) includes the case where the output voltage Vout is higher than the reference voltage Vref by a value exceeding the preset voltage value (the difference between the output voltage Vout and the reference voltage Vref is greater than the preset voltage value).

[0077] It should be understood that, for other situations where the pull-up or pull-down is not triggered, the operating mode of the DC-DC converter can be implemented by those skilled in the art according to the actual situation and needs, with reference to relevant technologies, and will not be elaborated here.

[0078] For example, in a DC-DC converter, the error signal of the output voltage Vout can be obtained by an error amplifier. For instance, in the feedback module, the feedback voltage Vfb of the output voltage Vout can be acquired by a feedback resistor network and input into the error amplifier together with the reference voltage Vref to generate the error signal of the output voltage Vout.

[0079] This disclosure does not limit the specific type and implementation method of the DC-DC converter. Those skilled in the art can refer to relevant technologies to implement it according to actual conditions and needs. For example, the DC-DC converter may include a boost DC-DC converter, a buck DC-DC converter, a buck-boost DC-DC converter, etc.

[0080] Please see Figure 2a , Figure 2a A schematic diagram of a boost DC-DC converter according to an embodiment of the present disclosure is shown.

[0081] For example, such as Figure 2a As shown, the voltage conversion module 110 of the boost DC-DC converter may include a drive unit, a first voltage conversion transistor Q1, a second voltage conversion transistor Q2, and an energy storage inductor L. The feedback module 120 includes a first feedback resistor R1, a second feedback resistor R2, an error amplifier EA, a feedback comparator Cmpf, an RS flip-flop RS1, a zero-crossing detection circuit, an adder, and several capacitors (Cc, C2) and resistors (Rc, Rout).

[0082] For example, the driving unit may include a pulse width modulation (PWM) signal generator and a gate driver. The PWM signal generator has a built-in RS flip-flop RS1, which can output two PWM logic signals based on the PWM signal (used to determine the duty cycle of the switch control signal) and the trit signal (a high-priority control signal used to turn off both the first voltage conversion transistor Q1 and the second voltage conversion transistor Q2) output by the RS flip-flop. The gate driver amplifies the PWM logic signal to generate corresponding switch control signals S1 and S2 to control the conduction or turn-off of the first voltage conversion transistor Q1 and the second voltage conversion transistor Q2. The specific implementation of the PWM signal generator and the gate driver in this embodiment is not limited. Those skilled in the art can refer to relevant technologies to implement them according to actual conditions and needs.

[0083] For example, such as Figure 2a As shown, the inverting input of the error amplifier EA receives the feedback voltage Vfb between the first feedback resistor R1 and the second feedback resistor R2. The non-inverting input of the error amplifier EA receives the reference voltage Vref (related to the target voltage output by the DC-DC converter). The output of the error amplifier EA outputs the amplified difference signal Vea (the error signal of the output voltage Vout) between the feedback voltage Vfb and the reference voltage Vref to the non-inverting input of the feedback comparator Cmpf. The inverting input of the feedback comparator Cmpf receives the synthesized ramp compensation voltage Vramp (the product of the inductor current IL and the resistance Ri (IL×Ri) generated by current sampling of the energy storage inductor L and the ramp voltage generated by the internal ramp compensation circuit 20). The feedback comparator Cmpf performs a comparison between the synthesized ramp compensation voltage Vramp and the amplified difference signal Vea to generate the reset signal (hcomp) of the PWM signal. As an example, in the RS flip-flop RS1, the set (start) clock signal ck of the PWM signal is triggered by the falling edge, and the reset of the PWM signal is triggered by the rising edge of the reset signal hcomp.

[0084] For example, such as Figure 2a The boost DC-DC converter shown exhibits a situation where, when the output load experiences a positive transient change (i.e., the load current rises from IOUT1 to IOUT2), the output EAOUT of the error amplifier EA needs to rise from the previous operating point EAOUT1 to EAOUT2. Since the op-amp output is the dominant pole after loop compensation, this node has a large capacitive reactance to ground, limiting its rate of change. If the rate of change of the load current IOUT exceeds the maximum rate achievable by EAOUT, the DC-DC converter cannot provide sufficient current to the load in time, causing the output VOUT to jump downwards, resulting in an undershoot. Similarly, when the output load experiences a negative transient change (i.e., the load current drops from IOUT1 to IOUT2), VOUT jumps upwards, resulting in an overshoot.

[0085] For example, such as Figure 2a As shown, since the first voltage conversion transistor Q1 is an NMOS transistor and the second voltage conversion transistor Q2 is a PMOS transistor, when PWM=1, S1=S2=1, the first voltage conversion transistor Q1 is turned on and the first voltage conversion transistor Q2 is turned off; when PWM=0, S1=S2=0, the first voltage conversion transistor Q1 is turned off and the first voltage conversion transistor Q2 is turned on. In this way, the DC-DC converter achieves inductor freewheeling and charges the output capacitor Cout by switching the first voltage conversion transistor Q1 and the second voltage conversion transistor Q2 on and off, thus enabling the output to reach the predetermined target voltage.

[0086] Please see Figure 2b , Figure 2b It shows Figure 2a A schematic diagram of the signal waveform of a boost DC-DC converter.

[0087] For example, such as Figure 2b As shown, when the peak current-mode load transiently changes, the sampling voltage of the inductor current of the energy storage inductor L in the voltage conversion module 110 (denoted as V) is the same as the output of the error amplifier EA. SNS The peak values ​​are compared because the peak inductor current is... ,so Where D represents the duty cycle of the switch control signal. This represents the inductor current of the energy storage inductor L. Ripple current represents the inductor current. Indicates the load current. Indicates the frequency of the switch control signal. This indicates the inductance of the energy storage inductor L. This indicates the current load before the switching action. This represents the load current after the switching action. This represents the peak inductor current before the transition. This indicates the peak value of the inductor current after the switching.

[0088] For example, such as Figure 2b As shown, V SNS =I L ×Ri, so the magnitude of the change in EAOUT when the current load changes. , V represents SNS The change This represents the expected change in load current when a load jump occurs.

[0089] As can be seen, for the traditional peak current model, the change requirement of EAOUT when the load transients is as follows: ×Ri×VOUT / VIN, while the rate of change of EAOUT is dV EAOUT / dt=GM×(Vref-Vfb) / Cc, where GM represents the amplification factor of the error amplifier EA. The values ​​of Ri and GM are determined by the user based on actual conditions and needs. In the loop design, Ri and GM need to change in the same direction; that is, if decreasing Ri reduces ΔEAOUT, then GM must also be reduced accordingly. Otherwise, the loop will become unstable. Taking typical parameters as an example, assuming Ri = 0.5, GM of the main operational amplifier EA = 10µF, compensation capacitor Cc = 50pF, and a transient load change causing a 10mV drop in VFB, then the theoretical rate of change of EAOUT is dV.EAOUT / dt=10u×10mV / 50p=2mV / us.

[0090] Currently, more and more applications require higher load current change rates (e.g., a change of 100mA within 10µs, with a change rate of 10mV / µs, which is 5 times faster than 2mV / µs). Furthermore, it should be understood that during load transient transitions, if the inductor current IL of the energy storage inductor L switches from discontinuous change mode (DCM) to continuous change mode (CCM), the change rate of EAOUT will be slower, resulting in a larger undershoot in the output. This makes the rapid transient response of the load a design challenge for the BOOST converter. The transient response compensation circuit 20 of this embodiment pulls up the error voltage signal when the output voltage Vout is lower than the reference voltage Vref by a preset voltage value, and pulls down the error voltage signal when the output voltage Vout is higher than the reference voltage Vref by a preset voltage value. This allows the error voltage signal to quickly follow the changes in load current, thereby improving the transient response rate of the DC-DC converter 10.

[0091] The embodiments disclosed herein are as follows Figure 2a The present invention provides an example of possible implementations of a boost DC-DC converter, but the embodiments disclosed herein are not limited thereto. Those skilled in the art can modify the implementation of the boost DC-DC converter according to actual conditions and needs, with reference to relevant technologies.

[0092] Please see Figure 3a , Figure 3b , Figure 3a , Figure 3b Schematic diagrams of a buck DC-DC converter and a buck-boost DC-DC converter are shown respectively.

[0093] The compensation circuit 20 of this disclosure embodiment can also be applied to buck DC-DC converters and buck-boost DC-DC converters. It should be understood that... Figure 3a , Figure 3b The buck DC-DC converter and buck-boost DC-DC converter shown are exemplary and should not be considered as limiting the embodiments of this disclosure. In other embodiments, those skilled in the art can apply the compensation circuit 20 to other buck DC-DC converters and buck-boost DC-DC converters according to actual conditions and needs.

[0094] This disclosure does not limit the specific implementation of the pull-up unit 210, pull-down unit 230, and control unit 220 in the compensation circuit 20. Those skilled in the art can implement them according to actual conditions and needs, referring to relevant technologies. The control unit 220 may include, but is not limited to, a separate processor, discrete components, or a combination of a processor and discrete components. The processor may include a controller in an electronic device with instruction execution capabilities. The processor can be implemented in any suitable manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. Within the processor, the executable instructions can be executed through hardware circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0095] Please see Figure 4a , Figure 4a A schematic diagram of a pull-up unit and a pull-down unit according to an embodiment of the present disclosure is shown.

[0096] In one possible implementation, such as Figure 4a As shown, the pull-up unit may include a first operational amplifier Amp1, a pull-up transistor Qp1, a pull-up current source Iref1, a pull-up resistor Rp1, and a pull-up switch S11, wherein,

[0097] The non-inverting input of the first operational amplifier Amp1 is used to receive the synthesized ramp compensation voltage Vramp.

[0098] The inverting input terminal of the first operational amplifier Amp1 is connected to the source of the pull-up transistor Qp1 and the second terminal of the pull-up resistor Rp1.

[0099] The output of the first operational amplifier Amp1 is connected to the gate of the pull-up transistor Qp1, and the drain of the pull-up transistor Qp1 is grounded.

[0100] The positive terminal of the pull-up current source Iref1 is connected to the power supply voltage VCC.

[0101] The negative terminal of the pull-up current source Iref1 is connected to the first terminal of the pull-up switch S11 and the first terminal of the pull-up resistor Rp1.

[0102] The second end of the pull-up switch S11 is connected to the feedback module 120 (e.g., ...). Figure 2a(The output of the intermediate error amplifier EA and the non-inverting input of the comparator Cmpf).

[0103] When the output voltage Vout is lower than the reference voltage Vref by a preset value, the pull-up switch S11 is turned on by the control unit 220; otherwise, the pull-up switch S11 is turned off by the control unit 220.

[0104] The pull-up transistor Qp1 is a PMOS transistor.

[0105] In one possible implementation, such as Figure 4a As shown, the pull-down unit may include a second operational amplifier Amp2, a pull-down transistor Qp2, a pull-down current source Iref2, a pull-down resistor Rp2, and a pull-down switch S12, wherein,

[0106] The non-inverting input of the second operational amplifier Amp2 is used to receive the synthesized ramp compensation voltage Vramp.

[0107] The inverting input of the second operational amplifier Amp2 is connected to the positive terminal of the pull-down current source Iref2 and the second terminal of the pull-down resistor Rp2.

[0108] The output of the second operational amplifier Amp2 is connected to the gate of the pull-down transistor Qp2.

[0109] The drain of the pull-down transistor Qp2 is connected to the power supply voltage VCC, and the source of the pull-down transistor Qp2 is connected to the first terminal of the pull-down switch S12 and the first terminal of the pull-down resistor Rp2.

[0110] The second end of the pull-down switch S12 is connected to the feedback module 120 (e.g., ...). Figure 2a (The output of the intermediate error amplifier EA and the non-inverting input of the comparator Cmpf).

[0111] When the output voltage Vout is higher than the reference voltage Vref by a preset value, the pull-down switch S12 is turned on by the control unit 220; otherwise, the pull-down switch S12 is turned off by the control unit 220.

[0112] The pull-down transistor Qp2 is an NMOS transistor.

[0113] Please see Figure 4b , Figure 4b A schematic diagram of a control unit 220 according to an embodiment of the present disclosure is shown.

[0114] In one possible implementation, such as Figure 4bAs shown, the control unit 220 may include a third operational amplifier Amp3, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a first control resistor R3, a second control resistor R4, a first comparator cmp1, and a second comparator cmp2, ​​wherein...

[0115] The non-inverting input of the third operational amplifier Amp3, the non-inverting input of the first comparator cmp1, and the inverting input of the second comparator cmp2 are all used to receive the reference voltage Vref.

[0116] The inverting input terminal of the third operational amplifier Amp3 is connected to the source of the first transistor M1 and the first terminal of the first control resistor R3.

[0117] The output of the third operational amplifier Amp3 is connected to the gate of the first transistor M1.

[0118] The power supply terminal of the third operational amplifier Amp3, the source of the second transistor M2, and the source of the third transistor M3 are all connected to the power supply voltage.

[0119] The gate and drain of the second transistor M2, the gate of the third transistor M3, and the drain of the first transistor M1 are connected.

[0120] The drain of the third transistor M3, the drain and gate of the fourth transistor M4, and the gate of the fifth transistor M5 are connected.

[0121] The drain of the fifth transistor M5, the second terminal of the second control resistor R4, the non-inverting input of the second comparator cmp2, ​​and the inverting input of the first comparator cmp1 are connected.

[0122] The first terminal of the second control resistor R4 is used to connect the output voltage Vout.

[0123] The second terminal of the first control resistor R3, the source of the fourth transistor M4, and the source of the fifth transistor M5 are all grounded.

[0124] The output terminals of the first comparator cmp1 and the second comparator cmp2 are used to output control signals (uv, ov), which are used for:

[0125] When the output voltage Vout is lower than the reference voltage Vref by a preset voltage value, the pull-up unit 210 is controlled to pull up the voltage of the error signal; or

[0126] When the output voltage is higher than the reference voltage Vref by a preset voltage value, the pull-down unit 230 is controlled to pull down the voltage of the error signal.

[0127] For example, such as Figure 4a and Figure 4b As shown, when the output voltage Vout is lower than the reference voltage Vref by a preset voltage value (ΔV), the control signal uv is high and the control signal ov is low. At this time, the control signal uv controls the pull-up switch S11 to turn on, and the control signal ov controls the pull-down switch S12 to turn off, thereby pulling up the voltage of the error signal through the pull-up unit.

[0128] For example, such as Figure 4a and Figure 4b As shown, when the output voltage Vout is higher than the reference voltage Vref by a preset voltage value (ΔV), the control signal uv is low and the control signal ov is high. At this time, the control signal uv controls the pull-up switch S11 to open and the control signal ov controls the pull-down switch S12 to open, thereby pulling down the voltage of the error signal through the pull-down unit.

[0129] This disclosure does not limit the specific type of each transistor in the control unit 220. Those skilled in the art can set it according to actual conditions and needs. In one possible implementation, the first transistor M1, the fourth transistor M4, and the fifth transistor M5 can all be NMOS transistors, and the second transistor M2 and the third transistor M3 can all be PMOS transistors.

[0130] For example, taking a boost DC-DC converter as an example, such as Figure 2a As shown, Vref=Vfb=Vout / (R1+R2)×R2, let R2 / (R1+R2)=k1, that is, Vref=k1×Vout.

[0131] For example, such as Figure 4b As shown, V1 = (Vout - Vref) / R3 × m1 × m2 × R2. Let (m1 × m2 × R2) / R3 = k2, that is, V1 = Vout - k2 × Vref. In this case, the width-to-length ratio (W / L) of the second transistor M2 and the third transistor M3 is 1:m1, and the width-to-length ratio (W / L) of the fourth transistor M4 and the fifth transistor M5 is 1:m2. The sizes of m1 and m2 can be set according to actual conditions and needs, and this embodiment does not limit them.

[0132] It can be seen that, as Figure 4bAs shown, Vref and V1 serve as the two input terminals of the first comparator cmp1 and the second comparator cmp2. In this embodiment, k1 and k2 can be designed according to actual conditions and needs to generate uv / ov signals when Vout decreases / increases by a preset voltage magnitude ΔV. Therefore, this embodiment can quickly raise / lower EAOUT when the control signal appears, accelerating the loop response and enabling EAOUT to quickly enter the next steady-state value.

[0133] For example, such as Figure 4a As shown, the compensation circuit 20 in this embodiment may further include a low-pass filter circuit LPF. By performing low-pass filtering on the synthesized ramp compensation voltage Vramp through the low-pass filter circuit LPF, a DC voltage signal can be obtained, which facilitates voltage comparison by the comparators of the pull-up unit and the pull-down unit. Of course, this embodiment does not limit the specific implementation of the low-pass filter circuit LPF. Those skilled in the art can implement it by referring to relevant technologies according to actual conditions and needs.

[0134] Please see Figure 5 , Figure 5 A schematic diagram of a low-pass filter circuit LPF according to an embodiment of the present disclosure is shown.

[0135] In one possible implementation, such as Figure 5 As shown, the low-pass filter circuit LPF may include a first filter switch S21, a second filter switch S22, a filter resistor Rf1, and a filter capacitor Cf1.

[0136] The first terminal of the first filter switch S21 and the first terminal of the second filter switch S22 are both used to receive the synthesized slope compensation voltage Vramp.

[0137] The second terminal of the first filter switch S21 and the second terminal of the second filter switch S22 are both connected to the first terminal of the filter resistor Rf1.

[0138] The second terminal of the filter resistor Rf1 and the first terminal of the filter capacitor Cf1 are used to output the filtered synthesized slope compensation voltage Vramp.

[0139] The second terminal of the filter capacitor Cf1 is grounded.

[0140] The first filter switch S21 is controlled by the switch control signal (PWM), and the second filter switch S22 is controlled by the reset signal (trist).

[0141] For example, such as Figure 5As shown, in this embodiment of the present disclosure, the first filter switch S21 and the second filter switch S22 are controlled by the switch control signal and the reset signal, respectively, and a stable DC voltage (red straight line) related to the peak value of the inductor current can be extracted from the periodic synthetic slope compensation voltage Vramp.

[0142] Please see Figure 6a and Figure 6b , Figure 6a and Figure 6b The signal diagrams for PWM and trit are shown in DCM mode and CCM mode, respectively.

[0143] Figure 6a and Figure 6b In the DC-DC converter 10, PWM represents the switching control signal of a voltage conversion transistor in the voltage conversion module 110 (such as the first voltage conversion transistor Q1), and trist represents the switching control signal that turns off both voltage conversion transistors simultaneously when the inductor current crosses zero.

[0144] Specifically, when the PWM signal is high, the first filter switch S21 is turned on, and vice versa; when the trist signal is high, the second filter switch S22 is turned on, and vice versa.

[0145] For example, such as Figure 6a and Figure 6b As shown, in DCM mode, when the inductor current of the energy storage inductor L crosses zero (detected by the zero-crossing detection circuit), trist is high; otherwise, trist is low. This means the second filter switch S22 only conducts when the inductor crosses zero in DCM mode.

[0146] Combination Figure 5 and Figure 6a In DCM mode, when the load current transiently changes, the low-pass filter circuit LPF can filter the input synthetic ramp compensation voltage Vramp to obtain a stable DC voltage (red straight line).

[0147] Combination Figure 5 and Figure 6b In CCM mode, when the load current transiently changes, the low-pass filter circuit LPF can filter the input synthetic slope compensation voltage Vramp to obtain a stable DC voltage (red straight line).

[0148] The embodiments disclosed herein do not limit the bandwidth of the low-pass filter circuit LPF, which can be set by those skilled in the art according to actual conditions and needs.

[0149] Please see Figure 7 , Figure 7A simulation diagram of the transient response of the boost DC-DC converter 10 is shown.

[0150] For example, purple represents the transient response simulation curve of the boost DC-DC converter 10 using the transient response compensation circuit 20 of the present disclosure embodiment, and green represents the transient response simulation curve of the boost DC-DC converter 10 without using the transient response compensation circuit 20 of the present disclosure embodiment.

[0151] For example, such as Figure 7 As shown, when the load current IOUT changes instantaneously from 50mA to 100mA, the approximate range of the purple line is 6.85~7.1V, and the approximate range of the green line is 6.8~7.2V. The former has a range of 205mV, and the latter is 400mV. In practical applications, the process of the output voltage Vout increasing / decreasing and then returning to normal due to rapid load changes can be considered as the transient response process of the circuit. Because the transient response rate is improved, the most intuitive manifestation is that the peak-to-peak value of the output voltage Vout decreases when the load changes rapidly. It can be seen that the boost DC-DC converter using the transient response compensation circuit 20 of this embodiment can significantly improve the response rate of the DC-DC converter 10 compared to conventional technology.

[0152] Please see Figure 8 , Figure 8 A simulation diagram of the boost DC-DC converter 10 is shown.

[0153] Figure 8 In the diagram, blue represents the simulated output voltage Vout curve of the boost DC-DC converter 10 using the transient response compensation circuit 20 of this embodiment, and red represents the simulated output voltage Vout curve of the boost DC-DC converter 10 not using the transient response compensation circuit 20 of this embodiment. Figure 8 As shown, the boost DC-DC converter employing the transient response compensation circuit 20 of this disclosure embodiment has a faster transient response speed compared to related technologies.

[0154] Therefore, the boost DC-DC converter 10 using the transient response compensation circuit 20 of this embodiment can, while maintaining the loop stability, enable the output EAOUT of the error amplifier EA to keep up with the rapid changes in the load current IOUT and reach the steady-state value corresponding to the next load current value earlier, thereby significantly improving the transient response speed.

[0155] In one possible implementation, the DC-DC converter 10 includes any one of a boost DC-DC converter 10, a buck DC-DC converter 10, or a boost-buck DC-DC converter 10.

[0156] According to one aspect of this disclosure, a DC-DC converter 10 is provided, the DC-DC converter 10 including the transient response compensation circuit 20.

[0157] According to one aspect of this disclosure, a driver chip is provided, the chip including the aforementioned DC-DC converter 10.

[0158] According to one aspect of this disclosure, an electronic device is provided, the electronic device including the aforementioned driver chip.

[0159] This disclosure does not limit the specific type of electronic device. Those skilled in the art can configure it according to actual circumstances and needs. For example, the electronic device may include terminal devices and servers. The terminal device may be user equipment (UE), mobile device, user terminal, terminal, handheld device, computing device, or in-vehicle device, etc. Examples of terminals include: mobile phones, tablets, laptops, PDAs, mobile internet devices (MID), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, and wireless terminals in vehicle-to-everything (V2X) networks, etc. For example, the server may be a local server or a cloud server.

[0160] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A transient response compensation circuit, characterized in that, The transient response compensation circuit is applied in a DC-DC converter, which includes a voltage conversion module and a feedback module. The voltage conversion module converts the input voltage to generate an output voltage. The feedback module generates a reset signal based on the error signal of the output voltage and a synthesized slope compensation voltage. The synthesized slope compensation voltage is obtained by adding the inductor current sampling voltage of the inductor in the voltage conversion module and a preset slope compensation voltage. The transient response compensation circuit includes a pull-up unit, a pull-down unit, and a control unit. The control unit is used for: If the output voltage is lower than the reference voltage by a preset value, the voltage of the error signal is pulled up by the pull-up unit; or When the output voltage is higher than the reference voltage by a preset voltage value, the voltage of the error signal is pulled down by the pull-down unit.

2. The transient response compensation circuit according to claim 1, characterized in that, The pull-up unit includes a first operational amplifier, a pull-up transistor, a pull-up current source, a pull-up resistor, and a pull-up switch, wherein, The non-inverting input of the first operational amplifier is used to receive the synthesized ramp compensation voltage. The inverting input terminal of the first operational amplifier is connected to the source of the pull-up transistor and the second terminal of the pull-up resistor. The output of the first operational amplifier is connected to the gate of the pull-up transistor, and the drain of the pull-up transistor is grounded. The positive terminal of the pull-up current source is connected to the power supply voltage. The negative terminal of the pull-up current source is connected to the first terminal of the pull-up switch and the first terminal of the pull-up resistor. The second end of the pull-up switch is connected to the feedback module. When the output voltage is lower than the reference voltage by a preset value, the pull-up switch is turned on by the control unit; otherwise, the pull-up switch is turned off by the control unit. The pull-up transistor is a PMOS transistor.

3. The transient response compensation circuit according to claim 1, characterized in that, The pull-down unit includes a second operational amplifier, a pull-down transistor, a pull-down current source, a pull-down resistor, and a pull-down switch, wherein... The non-inverting input of the second operational amplifier is used to receive the synthesized ramp compensation voltage. The inverting input terminal of the second operational amplifier is connected to the positive terminal of the pull-down current source and the second terminal of the pull-down resistor. The output of the second operational amplifier is connected to the gate of the pull-down transistor. The drain of the pull-down transistor is connected to the power supply voltage, and the source of the pull-down transistor is connected to the first terminal of the pull-down switch and the first terminal of the pull-down resistor. The second terminal of the pull-down switch is connected to the feedback module. When the output voltage exceeds the reference voltage by a preset value, the pull-down switch is turned on by the control unit; otherwise, the pull-down switch is turned off by the control unit. The pull-down transistor is an NMOS transistor.

4. The transient response compensation circuit according to claim 2 or 3, characterized in that, The transient response compensation circuit further includes a low-pass filter circuit, which comprises a first filter switch, a second filter switch, a filter resistor, and a filter capacitor. Both the first terminal of the first filter switch and the first terminal of the second filter switch are used to receive the synthesized slope compensation voltage. The second terminals of both the first and second filter switches are connected to the first terminal of the filter resistor. The second terminal of the filter resistor and the first terminal of the filter capacitor are used to output the filtered composite slope compensation voltage. The second terminal of the filter capacitor is grounded. The first filter switch is controlled by a switch control signal, and the second filter switch is controlled by the reset signal.

5. The transient response compensation circuit according to claim 1, characterized in that, The control unit includes a third operational amplifier, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first control resistor, a second control resistor, a first comparator, and a second comparator, wherein... The non-inverting input of the third operational amplifier, the non-inverting input of the first comparator, and the inverting input of the second comparator are all used to receive the reference voltage. The inverting input terminal of the third operational amplifier is connected to the source of the first transistor and the first terminal of the first control resistor. The output of the third operational amplifier is connected to the gate of the first transistor. The power supply terminal of the third operational amplifier, the source of the second transistor, and the source of the third transistor are all connected to the power supply voltage. The gate and drain of the second transistor, the gate of the third transistor, and the drain of the first transistor are connected. The drain of the third transistor, the drain and gate of the fourth transistor, and the gate of the fifth transistor are connected. The drain of the fifth transistor, the second terminal of the second control resistor, the non-inverting input of the second comparator, and the inverting input of the first comparator are connected. The first terminal of the second control resistor is used to connect to the output voltage. The second terminal of the first control resistor, the source of the fourth transistor, and the source of the fifth transistor are all grounded. The output terminals of the first comparator and the second comparator are used to output control signals, which are used for: If the output voltage is lower than the reference voltage by a preset value, the pull-up unit is controlled to pull up the voltage of the error signal; or When the output voltage is higher than the reference voltage by a preset value, the pull-down unit is controlled to pull down the voltage of the error signal.

6. The transient response compensation circuit according to claim 5, characterized in that, The first transistor, the fourth transistor, and the fifth transistor are all NMOS transistors, and the second transistor and the third transistor are all PMOS transistors.

7. The transient response compensation circuit according to claim 1, characterized in that, The DC-DC converter includes any one of a boost DC-DC converter, a buck DC-DC converter, or a boost-buck DC-DC converter.

8. A DC-DC converter, characterized in that, The DC-DC converter includes a transient response compensation circuit as described in any one of claims 1-7.

9. A driver chip, characterized in that, The chip includes the DC-DC converter as described in claim 8.

10. An electronic device, characterized in that, The electronic device includes the driver chip as described in claim 9.

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