Hybrid Single-Inductor Bipolar Output Converter and Its Control Method

Abstract

This application relates to the field of analog integrated circuits and discloses a hybrid single-inductor bipolar output converter and its control method. The converter includes a flying capacitor, an inductor, seven power transistors, positive and negative output capacitors, and a common-mode-differential-mode control loop. The sixth power transistor connects the input voltage terminal to one end of the inductor, forming an independent discharge path for the negative voltage output terminal in conjunction with the flying capacitor. The control loop simultaneously introduces positive and negative voltage feedback signals into differential-mode and common-mode operations, generating two pulse-width modulation (PWM) signals to regulate the total energy inflow and energy distribution between the positive and negative terminals, respectively. Adaptive switching between three-phase and two-phase operating modes is achieved based on the comparison of the duty cycles of the two signals. This scheme helps reduce device voltage stress and improves output stability under unbalanced dual-terminal loads.

Description

Technical Field

[0001] This application relates to the field of analog integrated circuit technology, and in particular to a single-inductor bipolar output converter and its control technology. Background Technology

[0002] As smart terminals, automotive displays, medical wearables, and portable audio devices evolve towards miniaturization, low power consumption, and multi-functionality, power management integrated circuits (ICs) need to provide stable power supply voltages for different functional modules within limited chip area and peripheral device constraints. In AMOLED display driving scenarios (such as...) Figure 1 As shown, pixel driving circuits typically require both positive and negative voltages for power supply. The gate-source voltage of the driving thin-film transistor is directly affected by the positive output voltage, thus the ripple requirements for the positive output are quite stringent. Simultaneously, as display panel sizes increase, power management chips must also possess sufficient load-carrying capacity. In audio amplifier applications, bipolar power supplies provide symmetrical positive and negative power rails for the amplification stage. The accuracy and transient response speed of the output voltage directly affect the fidelity of the audio signal. In medical wearable devices, space is extremely limited. A single converter providing bipolar output can reduce the number of external components and shrink the circuit board area, but it also requires the converter to maintain stable output under conditions of rapid load changes or single-ended no-load. Due to the limited internal space of terminal devices, power converters using a single inductor to achieve bipolar output have high application value. Such converters are commonly referred to as Single Inductor Bipolar Output (SIBO) converters.

[0003] In existing SIBO converter designs, traditional topologies without flying capacitors, while relatively simple in structure and applicable to a wide range of scenarios, suffer from shortcomings in terms of device voltage stress and load-driving capacity. Hybrid topologies with flying capacitors can improve device stress and load-driving capacity, but are easily limited by output range and independent load operation capability. Under conditions of significant load differences between the positive and negative terminals, sudden load changes at either end, or no load at one end, existing control methods may struggle to simultaneously manage total system energy regulation and positive / negative terminal energy distribution, leading to mutual interference between the two outputs. Therefore, there is an urgent need for a hybrid SIBO converter technology that can achieve low device stress, bipolar output, independent load regulation, and simpler control logic within a single-inductor structure. Summary of the Invention

[0004] The purpose of this application is to provide a hybrid single-inductor bipolar output converter and its control method, so as to improve the device voltage stress, adaptability to unbalanced loads at both ends, and adjustment coupling problem between positive and negative output terminals of the bipolar output converter under the single-inductor structure.

[0005] This application provides a hybrid single-inductor bipolar output converter for converting a positive input voltage into a bipolar positive and negative output voltage. The converter includes: Input voltage terminal, power ground, positive voltage output terminal, and negative voltage output terminal; flying capacitor (CF), inductor (L), positive voltage output capacitor (COP), and negative voltage output capacitor (CON); first power transistor (S1), second power transistor (S2), third power transistor (S3), fourth power transistor (SP1), fifth power transistor (SP2), sixth power transistor (SN1), and seventh power transistor (SN2); each of the first to seventh power transistors includes a first terminal, a second terminal, and a control terminal; The first terminal of the first power transistor (S1) and the first terminal of the sixth power transistor (SN1) are both connected to the input voltage terminal; the second terminal of the first power transistor (S1), the second terminal of the fourth power transistor (SP1), the first terminal of the flying capacitor (CF), and the first terminal of the inductor (L) are connected together to form a first node (VSW1); the first terminal of the second power transistor (S2), the second terminal of the seventh power transistor (SN2), and the second terminal of the flying capacitor (CF) are connected together to form a second node (VSW2); the second terminal of the third power transistor (S3), the second terminal of the fifth power transistor (SP2), the second terminal of the sixth power transistor (SN1), and the second terminal of the inductor (L) are connected together to form a third node (VSW3); The second terminal of the second power transistor (S2), the first terminal of the third power transistor (S3), and the first terminal of the fourth power transistor (SP1) are all connected to the power ground; the first terminal of the fifth power transistor (SP2) is connected to the positive voltage output terminal, and the positive voltage output capacitor (COP) is connected between the positive voltage output terminal and the power ground; the first terminal of the seventh power transistor (SN2) is connected to the negative voltage output terminal, and the negative voltage output capacitor (CON) is connected between the negative voltage output terminal and the power ground. The control terminals of each of the power transistors are used to receive drive signals; the sixth power transistor (SN1) is configured to be turned on during the discharge phase to the negative voltage output terminal to provide an independent discharge path from the input voltage terminal to the third node (VSW3).

[0006] In a preferred embodiment, the first power transistor (S1), the fifth power transistor (SP2), and the sixth power transistor (SN1) are P-type metal-oxide-semiconductor transistors; the second power transistor (S2), the third power transistor (S3), the fourth power transistor (SP1), and the seventh power transistor (SN2) are N-type metal-oxide-semiconductor transistors; wherein the first terminal of each power transistor is the source terminal and the second terminal is the drain terminal.

[0007] In a preferred embodiment, the converter operates in a three-phase mode comprising three stages: Phase 1 (Φ1): The first power transistor (S1), the second power transistor (S2), and the third power transistor (S3) are turned on, while the remaining power transistors are turned off. The input voltage charges the flying capacitor (CF) through the branch of the second power transistor (S2) and simultaneously charges the inductor (L) through the branch of the third power transistor (S3). The potential of the first node (VSW1) is the input voltage, and the potentials of the second node (VSW2) and the third node (VSW3) are both power ground potentials. The inductor current flows at a slope... rise; Second stage (Φ2): The fourth power transistor (SP1) and the fifth power transistor (SP2) are turned on, and the remaining power transistors are turned off; the inductor (L) discharges to the positive output capacitor (COP) through the fifth power transistor (SP2); the potential of the first node (VSW1) is the power ground potential, and the potential of the third node (VSW3) is the positive output voltage. The inductor current has a slope decline; Third stage (Φ3): The sixth power transistor (SN1) and the seventh power transistor (SN2) are turned on, and the remaining power transistors are turned off; the inductor (L) discharges to the negative voltage output capacitor (CON) through the seventh power transistor (SN2); the potential of the second node (VSW2) is the negative voltage output voltage. The potential of the third node (VSW3) is the input voltage. The inductor current has a slope It continues to decline.

[0008] In a preferred embodiment, the flying capacitor (CF) is configured to perform node voltage clamping at different operating stages to reduce voltage stress on each of the power transistors. The clamping process specifically includes: In the second stage (Φ2), the first node (VSW1) is connected to the power ground through the conducting fourth power transistor (SP1), and the flying capacitor (CF) clamps the potential of the second node (VSW2) to the negative input voltage, i.e. ; In the third stage (Φ3), the third node (VSW3) is connected to the input voltage terminal through the conducting sixth power transistor (SN1), and the second node (VSW2) is connected to the negative voltage output terminal through the conducting seventh power transistor (SN2). The flying capacitor (CF) clamps the potential of the first node (VSW1) to the sum of the negative voltage output voltage and the input voltage. ; Due to the clamping effect of the flying capacitor (CF), under the operating conditions that the positive output voltage is not greater than the input voltage and the absolute value of the negative output voltage is not greater than the input voltage, the voltage stress borne by each power transistor in the second stage (Φ2) and the third stage (Φ3) does not exceed the input voltage.

[0009] In a preferred embodiment, the first stage (Φ1) is a necessary stage in each work cycle, while the second stage (Φ2) and the third stage (Φ3) are optional stages; When the difference between the load current at the positive voltage output terminal and the load current at the negative voltage output terminal is within a preset range, the converter operates in a three-phase mode consisting of the first stage (Φ1), the second stage (Φ2), and the third stage (Φ3) in sequence. When the difference between the load at the positive output terminal and the load at the negative output terminal exceeds the preset range or when either terminal is unloaded, the converter switches to a two-phase mode consisting of a combination of the first stage (Φ1) and the second stage (Φ2) or the third stage (Φ3).

[0010] This application provides a control method applied to the above-mentioned hybrid single-inductor bipolar output converter, the control method comprising the following steps: Voltage sampling steps: acquire the positive voltage feedback signal (VFBP) at the positive voltage output terminal and the negative voltage feedback signal (VFBN) at the negative voltage output terminal respectively; Error amplification step: Based on the positive voltage feedback signal (VFBP) and the negative voltage feedback signal (VFBN) output from the voltage sampling step, they are compared with the corresponding reference voltages, and a differential-mode error signal (VEA,DM) for controlling the total energy of the system is generated through differential-mode operation, and a common-mode error signal (VEA,CM) for controlling the energy distribution between the positive and negative terminals is generated through common-mode operation; wherein, the negative voltage feedback signal (VFBN) participates in the common-mode operation to adjust the common-mode error signal (VEA,CM); Current sampling and superposition steps: In the first stage (Φ1) of charging the inductor (L), the charging current flowing through the inductor (L) is sampled to obtain a sampling current signal. The first ramp voltage signal (VRAMP1) is converted into a current signal through a ramp buffer circuit and superimposed with the sampling current signal. Then, it is converted into a superimposed sampling voltage signal (VSUM) through a resistor. Pulse Width Modulation Step: The superimposed sampled voltage signal (VSUM) output from the current sampling and superposition step is compared with the differential mode error signal (VEA,DM) output from the error amplification step. After processing by the first RS flip-flop, a first pulse width modulation signal (VPWM1) with a first duty cycle (D1) is generated. The second ramp voltage signal (VRAMP2) is compared with the common mode error signal (VEA,CM) output from the error amplification step. After processing by the second RS flip-flop, a second pulse width modulation signal (VPWM2) with a second duty cycle (D2) is generated. Driving step: Based on the first pulse width modulation signal (VPWM1) and the second pulse width modulation signal (VPWM2) generated in the pulse width modulation step, the driving circuit module generates driving signals for controlling the turn-on and turn-off of the first to seventh power transistors.

[0011] In a preferred embodiment, during the error amplification step, the positive pressure feedback signal (VFBP) and the negative pressure feedback signal (VFBN) simultaneously participate in the differential-mode operation and the common-mode operation; The differential mode operation processes the error signals of the two sets of reference voltages and feedback voltages to obtain the differential mode error signal (VEA,DM), which is used to control the first duty cycle (D1) to regulate the total energy inflow of the system. The common-mode operation processes the error signals of the two sets of reference voltages and feedback voltages into a common-mode error signal (VEA,CM), which is used to control the second duty cycle (D2) to regulate the energy distribution between the positive voltage output terminal and the negative voltage output terminal. By introducing the negative voltage feedback signal (VFBN) into the control loop of the second duty cycle (D2), the coordinated control of the positive voltage output voltage and the negative voltage output voltage is achieved. The differential mode error signal (VEA,DM) and the common mode error signal (VEA,CM) are processed by a type II compensation network.

[0012] In a preferred embodiment, the step of obtaining the sampled current signal in the current sampling and superposition step specifically includes: in the first stage (Φ1), sampling the current of the conducting third power transistor (S3) to obtain the sampled current signal, thereby eliminating the interference of the flying capacitor (CF) charging current on the inductor current sampling; When the first duty cycle (D1) is greater than a preset threshold, slope compensation is generated by superimposing the first ramp voltage signal (VRAMP1) onto the sampled current signal to suppress subharmonic oscillations.

[0013] In a preferred embodiment, the driving step further includes adaptive switching between three-phase and two-phase operating modes based on the comparison relationship between the first duty cycle (D1) and the second duty cycle (D2). The specific switching logic includes: When the load difference between the two ends is within a preset range, the converter is controlled by the drive signal to operate in a three-phase working mode that sequentially includes the first stage (Φ1), the second stage (Φ2) of discharging to the positive voltage output terminal, and the third stage (Φ3) of discharging to the negative voltage output terminal. When it is determined that the second duty cycle (D2) is less than the first duty cycle (D1), the operating mode of the converter is switched to a two-phase operating mode consisting only of the first stage (Φ1) and the third stage (Φ3); When it is determined that the second pulse width modulation signal (VPWM2) remains at a high level for multiple consecutive switching cycles, the operating mode of the converter is switched to a two-phase operating mode consisting only of the first stage (Φ1) and the second stage (Φ2); The driving step further includes: converting the control signal from the control signal voltage domain to the power module voltage domain through a level shifter; and controlling the switching timing of each power transistor through phase non-overlapping logic to prevent shoot-through between the power transistors, while also facilitating zero-voltage conduction of some of the power transistors.

[0014] This application provides a power management integrated circuit, including: the above-described hybrid single-inductor bipolar output converter; and a control circuit connected to the control terminals of each of the power transistors in the hybrid single-inductor bipolar output converter, the control circuit being configured to execute the above-described control method.

[0015] This application incorporates a flying capacitor in a hybrid single-inductor bipolar output converter. ),inductance( ), the first to seventh power transistors and the positive voltage output capacitor ( ) and negative voltage output capacitor ( This structure forms a bipolar output structure based on a single inductor, capable of releasing energy towards both the positive and negative output terminals. This structure utilizes three floating potential nodes ( ), ( )and( The potential changes at different operating stages allow input energy storage, positive voltage terminal discharge, and negative voltage terminal discharge to be carried out in an orderly manner within the same topology, thereby providing a more compact bipolar power supply basis for miniaturized power management integrated circuits.

[0016] Flying capacitor ( ) connected to the first node ( ) and the second node ( Between the first stage () ) with inductance ( ) and store energy together in the second stage ( ) and the third stage ( Potential clamping of floating nodes in ) — in the second stage, the second node ( Clamp to In the third phase, the first node ( Clamp to Through this node clamping relationship, under the operating conditions where the positive output voltage is no greater than the input voltage and the absolute value of the negative output voltage is no greater than the input voltage, the voltage stress borne by each power transistor does not exceed the input voltage. This provides a structural basis for the selection of low-voltage power transistors and helps reduce the on-resistance and switching losses of the power transistors. It should be noted that the flying capacitor does not isolatedly perform stress reduction; rather, it, together with the inductor, the switching state of the power transistors, and the output terminal connection, defines the equivalent energy transfer path at each stage, thereby balancing the load-carrying capacity and device compatibility of the hybrid topology.

[0017] Sixth power transistor ( The setting of the third node ( In the third stage ( The input voltage terminal is connected to the seventh power transistor ( ). ),inductance( ) and flying capacitors ( This forms an independent discharge path facing the negative voltage output terminal. This path allows the negative voltage output terminal to avoid complete reliance on the shared state of the positive voltage discharge path under load changes or single-ended output requirements, thus improving the applicability of the hybrid topology for independent load operation. This effect is not simply achieved by adding a switching transistor, but rather manifests as a synergistic realization of negative voltage energy release capability and low voltage stress structure—the sixth power transistor (…). The established The potential condition just makes the flying capacitor ( ) can maintain access to the first node ( The clamping of the load independent function does not come at the expense of the stress of the low-voltage components.

[0018] Furthermore, when the first power transistor ( ), fifth power transistor ( ) and the sixth power transistor ( In the implementation method where PMOS transistors are used and NMOS transistors are used for the remaining power transistors, each power transistor can be turned on and off with a lower gate drive voltage within its corresponding operating voltage domain, which helps to simplify the design of the drive circuit and reduce drive losses.

[0019] By the first phase ( ) is set as a necessary stage in each work cycle, and the second stage ( ) and the third stage ( The converter is set as an optional stage, allowing it to switch between three-phase and two-phase operating modes based on the load difference between the positive and negative output terminals. When the loads at both ends are relatively close, the three-phase mode supplies energy to both positive and negative terminals; when the load difference widens or either end is unloaded, the power supply is switched to a different mode. or The two-phase configuration prioritizes meeting the energy demands of the corresponding output terminals. This combination method enables the single-inductor structure to have more flexible energy distribution capabilities in scenarios with unbalanced loads.

[0020] At the control method level, positive pressure feedback signal ( ) and negative pressure feedback signal ( Simultaneously participating in differential-mode and common-mode operations, respectively forming differential-mode error signals ( ) and common-mode error signal ( The differential error signal is used to control the first duty cycle. ), to regulate the first stage ( The total energy inflow into the system; the common-mode error signal is used to control the second duty cycle ( ), to adjust the energy distribution between the positive and negative pressure output terminals. Due to the negative pressure feedback signal ( ) is introduced into the second duty cycle ( The regulation path of the negative voltage end allows the negative voltage end to participate in the energy distribution judgment, thereby helping to reduce the cross-regulation effect between the positive and negative output ends and making the positive voltage output voltage ( ) and negative voltage output voltage ( The control relationship is more coordinated. The introduction of negative voltage feedback signal overcomes the shortcomings of existing control strategies that rely solely on positive voltage feedback information for second duty cycle control while ignoring changes at the negative voltage end, thus facilitating coordinated control of positive and negative voltage output voltages. Differential-mode error signals and common-mode error signals are processed by Type II compensation networks, and by setting the frequency positions of zeros and poles, sufficient phase and gain margins are ensured for each loop within the operating frequency band, ensuring loop stability.

[0021] The current sampling and ramp stacking process is carried out in the first stage ( ) for the third power transistor ( The current of the high-side power transistor (i.e., the first power transistor) is sampled instead of the current of the high-side power transistor, making the sampled signal closer to the inductor charging current itself. In the hybrid architecture, the high-side power transistor (i.e., the first power transistor)... The conduction current in the first stage includes the flying capacitance ( The sum of the charging current and the inductor charging current is used to select the third power transistor. This can eliminate interference from the flying capacitor charging current at the physical circuit level. The first ramp voltage signal ( After being converted by the ramp buffer circuit, it is superimposed on the sampled current signal to form a superimposed sampled voltage signal. This signal is related to the differential error signal ( ) jointly participate in the first pulse width modulation signal ( The generation of ). When the first duty cycle ( When the value is greater than the preset threshold, the slope compensation effect generated by the slope superposition helps to suppress the subharmonic oscillation that may occur in the current loop, which is beneficial to improving the stability of the loop in a wide duty cycle range.

[0022] Regarding adaptive mode switching, based on the first duty cycle ( ) and the second duty cycle ( The comparison relationship between the second pulse width modulation signal and the second pulse width modulation signal. The switching criterion is determined by the specific signal comparison conditions and logical judgment relationships: when the second duty cycle ( () less than the first duty cycle () Switch to The two-phase mode is designed to primarily power the negative voltage output terminal, when the second pulse width modulation signal ( Switching to [the desired level] while maintaining a high level for multiple consecutive switching cycles. The two-phase mode prioritizes power supply to the positive voltage output. This switching utilizes the duty cycle information inherent in the control loop to determine the mode, eliminating the need for additional external detection circuitry and complex control mode switching logic. In the driving process, a level shifter converts the control signal voltage domain to the power module voltage domain, and phase-non-overlapping logic controls the switching sequence of each power transistor to prevent shoot-through. Simultaneously, it facilitates zero-voltage conduction for some power transistors, further reducing switching losses.

[0023] Integrating the aforementioned converter topology and control circuitry onto a single chip constitutes a power management integrated circuit, enabling a highly integrated bipolar power management solution at the chip level. Under operating conditions where the positive output voltage is no greater than the input voltage and the absolute value of the negative output voltage is no greater than the input voltage, the voltage stress on all power transistors does not exceed the input voltage. This allows for low-voltage manufacturing, reducing chip area and manufacturing costs. The common-mode / differential-mode decoupling architecture of the control circuit requires only two sets of comparators and RS flip-flops to achieve dual-terminal coordinated regulation, resulting in low circuit complexity and suitability for on-chip integration. Overall, this application, through the continuous coordination between topology nodes, inductor energy storage, flying capacitor clamping, independent discharge paths, common-mode / differential-mode control, and staged combination switching, enables the hybrid single-inductor bipolar output converter to exhibit better output regulation adaptability under dual-terminal load variation scenarios.

[0024] The specification of this application contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these technical features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which should be considered as described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the AMOLED pixel array driving current structure according to the background technology of this application.

[0026] Figure 2 This is a schematic diagram of the topology of a hybrid single-inductor bipolar output converter according to an embodiment of this application.

[0027] Figure 3 This is a schematic diagram of the power transistor switching timing and inductor current waveform of a hybrid single-inductor bipolar output converter according to an embodiment of this application.

[0028] Figure 4 This is a schematic diagram of the control loop structure of a hybrid single-inductor bipolar output converter according to an embodiment of this application.

[0029] Figure 5 This is a schematic diagram of the control waveform of a hybrid single-inductor bipolar output converter according to an embodiment of this application under load variation conditions. Detailed Implementation

[0030] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0031] Explanation of some concepts: A single-inductor bipolar output converter is a power converter that uses a single inductor to convert a positive input voltage into a positive output voltage and a negative output voltage.

[0032] A hybrid single-inductor bipolar output converter refers to a converter that introduces a flying capacitor into a single-inductor bipolar output topology to participate in node potential clamping and energy transfer.

[0033] Flying capacitor ( ), refers to the connection to the first node ( ) and the second node ( A capacitor used between ( ) to maintain voltage and clamp floating nodes during different operating phases.

[0034] First node ( ), refers to the first power transistor ( The second terminal of the fourth power transistor () The second terminal of the flying capacitor () The first terminal of the inductor and the inductor The first ends of the two nodes are connected together to form a floating potential node.

[0035] Second node ( ), refers to the second power transistor ( The first terminal of ) and the seventh power transistor ( The second terminal of ) and the flying capacitor ( The second end of the two terminals are connected together to form a floating potential node.

[0036] Third node ( ), refers to the third power transistor ( The second terminal of the fifth power transistor () The second terminal of ) and the sixth power transistor ( The second terminal of the inductor and the inductor The second end of the two terminals are connected together to form a floating potential node.

[0037] Positive pressure output terminal ( ), refers to the capacitor used to output positive voltage and connect with the positive voltage output capacitor ( The output terminal is connected to the same terminal.

[0038] Negative pressure output terminal ( ), refers to the capacitor used to output negative polarity voltage and connect with the negative voltage output capacitor ( The output terminal is connected to the same terminal.

[0039] Phase 1 ( ), refers to the first power transistor ( ), second power transistor ( ) and the third power transistor ( ) conduction, to conduct the flying capacitor ( ) and inductance ( The charging phase begins.

[0040] Phase Two ( ), refers to the fourth power transistor ( ) and the fifth power transistor ( ) conducts, so that the inductor ( The working stage that releases energy to the positive pressure output terminal.

[0041] Phase Three ( ), refers to the sixth power transistor ( ) and the seventh power transistor ( ) conducts, so that the inductor ( The working stage that releases energy to the negative pressure output terminal.

[0042] Differential error signal ( ), refers to the error signal obtained by differential mode operation based on positive and negative pressure feedback signals, used to regulate the total energy inflow of the system.

[0043] Common-mode error signal ( ), refers to the error signal obtained by common-mode operation based on positive and negative pressure feedback signals, used to regulate the energy distribution between the positive and negative ends.

[0044] First duty cycle ( ), refers to the first pulse width modulation signal ( The substance carried by ) is used to regulate the first stage ( The duty cycle of the duration.

[0045] Second duty cycle ( ), refers to the second pulse width modulation signal ( The duty cycle carried by the positive pressure output terminal and the negative pressure output terminal is used to regulate the energy distribution between the positive pressure output terminal and the negative pressure output terminal.

[0046] Load independence means that when the loads at the positive and negative output terminals are unbalanced or either terminal is unloaded, the converter can still adjust the phase combination and energy distribution according to the energy demand of the corresponding output terminal.

[0047] Cross regulation refers to the coupling phenomenon in a single-inductor multi-output converter where multiple output terminals share the same inductor. The inductor current fluctuation caused by load changes at one end is transmitted to the other end, causing the output voltage at the other end to deviate.

[0048] Subharmonic oscillation refers to an unstable phenomenon in peak current mode controlled converters where, when the duty cycle exceeds a certain threshold, the inductor current exhibits alternating deviations between adjacent switching cycles, which are continuously amplified, causing the output voltage and inductor current to exhibit periodic oscillations.

[0049] Zero-voltage switching (ZVS) is a switching technology in which a power transistor is turned on only when its drain-source voltage drops to zero or close to zero. It reduces switching losses by eliminating the overlap between the drain-source voltage and the conduction current at the moment of turn-on.

[0050] Type II compensation network refers to an analog frequency domain compensation circuit composed of resistors and capacitors. By setting the frequency positions of zeros and poles, the gain and phase characteristics of the loop are adjusted to ensure that the feedback control loop has sufficient phase margin and gain margin within the operating frequency band.

[0051] The following is a brief summary of some of the innovative aspects of this application: In summary, this application does not only involve flying capacitors ( ), single inductor ( Instead of using a conventional combination with several power transistors, the design of the bipolar output power supply is constrained by the need to simultaneously consider low component stress, unbalanced positive and negative loads, and independent single-ended loads. Figure 2 The first node shown ( ), second node ( ) and the third node ( The phased potential reconstruction relationship of the first power transistor () forms a technical concept of interlocking topology and control loop. Specifically, the first power transistor () ), second power transistor ( ) and the third power transistor ( In the first stage ( In ) make flying capacitor ( ) and inductance ( Synchronous energy storage; fourth power transistor ( ) and the fifth power transistor ( In the second stage ( ) with the help of flying capacitors ( ) for the second node ( The clamping of the positive pressure output terminal () completes the positive pressure output. The energy release of ) in the third stage; and in the third stage ( In ), the sixth power transistor ( It does not simply provide another switching branch—its conduction enables the third node ( The potential of ) is established as the input voltage. The seventh power transistor that is turned on ( ) makes the second node ( The potential of the output voltage changes to a negative voltage. Flying capacitor ( The approximate amount maintained on ) The voltage of the first node is thus determined. The potential clamping to This creates a new independent discharge relationship between the input voltage terminal, the third node, the inductor, the negative voltage output terminal, and the flying capacitor, ensuring that the voltage stress on each power transistor does not exceed the input voltage while meeting low voltage stress conditions. Furthermore, as... Figure 4 and Figure 5 As shown, this application enables a positive pressure feedback signal ( ) and negative pressure feedback signal ( Simultaneously participates in the differential error signal ( ) and common-mode error signal ( The generation of ); wherein, the differential mode loop is achieved by superimposing the sampled voltage signal ( ) and differential error signal ( The comparison control of the first duty cycle () To regulate the total energy inflow of the system, the common-mode loop uses the second ramp voltage signal ( ) and common-mode error signal ( The comparison control of the second duty cycle () ) to regulate the energy distribution between the positive and negative terminals—thus, the topology side is controlled by the sixth power transistor ( ) and flying capacitor ( The independent discharge capability of the negative voltage terminal established by the negative voltage feedback signal can be controlled by the negative voltage feedback signal on the control side. ), common-mode error signal ( ) and second duty cycle ( The negative pressure feedback requirement represented by ) is invoked in a timely manner and through and or The solution responds by combining different operating stages. The technical effect of this solution is not a linear superposition of the functions of each component, but rather a continuous coupling of "node clamping - independent discharge path - differential mode total energy adjustment - common mode energy distribution - stage combination switching", which makes the hybrid single-inductor bipolar output converter more adaptable to application scenarios with different double-ended loads and changing single-ended loads under the condition of limited energy storage components.

[0052] Furthermore, through long-term in-depth research, the inventors of this application discovered that the difficulties faced by single-inductor bipolar output converters in scenarios such as AMOLED display drivers, audio amplifiers, and wearable devices are not merely the conventional power conversion problem of "how to generate a positive voltage and a negative voltage," but rather how to simultaneously handle the contradictions between device voltage stress, positive and negative terminal energy coupling, and single-ended load variations under the constraints of a single inductor, a limited number of switching transistors, and limited space for peripheral devices. After a systematic comparative analysis of the working principles of the two architectures, the inventors realized that the reason why traditional topologies without flying capacitors are difficult to adapt to high-integration applications is that their power transistors are prone to high voltage stress during bipolar conversion, which limits the selection of low-voltage devices and affects efficiency. While existing hybrid topologies with flying capacitors can reduce device stress through node clamping, they lack an independent discharge path at the negative voltage end, making it difficult to escape the problem of mutual constraint between positive and negative energy paths when the negative voltage end is solely loaded or when the load difference between the two ends is large.

[0053] The inventors further realized that simply adding energy storage elements or adjusting the switching timing could not effectively solve the above contradictions; the key lies in making the flying capacitor ( The clamping effect of the third node ( ) and the independent discharge path at the negative voltage end cooperate in the same topology. Based on this understanding, this application connects the third node ( ) at the input voltage end. A sixth power transistor is set between ( ) ), making it in the third stage ( ) and the seventh power transistor ( ),inductance( ) and flying capacitor ( Together, they form an independent energy release relationship at the negative voltage output terminal. As a result, the energy supply at the negative voltage terminal no longer depends solely on the discharge conditions shared with the positive voltage terminal, while the flying capacitor can still maintain the clamping relationship of the corresponding node, thus taking into account both load independence and low device stress at the structural level.

[0054] The inventors also discovered that the independent discharge capability of the topology does not necessarily mean that the system can naturally operate stably under load changes; if the control loop still adjusts the duty cycle based solely on a single output terminal or a single error signal, load changes at the positive and negative terminals will be transmitted to each other through the energy-sharing relationship of the single inductor, causing a mismatch between the regulation of total energy injection and dual-terminal energy distribution. Therefore, this application uses a positive voltage feedback signal ( ) and negative pressure feedback signal ( Simultaneously participates in differential and common mode processing, using the differential error signal ( Adjust the first duty cycle ( The corresponding total energy inflow to the system is expressed in terms of the common-mode error signal ( Adjust the second duty cycle ( This corresponds to the energy distribution at the positive and negative terminals, thereby decoupling the paths at the control and topology levels to achieve matching. Based on the above in-depth research, this application proposes a hybrid single-inductor bipolar output converter with coordinated design of topology and control loop. The implementation process is further explained below with reference to specific embodiments.

[0055] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0056] It should be noted that in the description of this application, the terms "first," "second," and "third," etc., are only used to distinguish different components or steps and do not imply any order or importance. Furthermore, the term "connection" mentioned in this application includes both direct electrical connections and indirect electrical connections achieved through intermediate elements or wires. Unless otherwise stated, the "first terminal," "second terminal," and "control terminal" of each power transistor correspond to the two main current terminals and the drive terminal of the power transistor, respectively. This application does not limit the specific device type of the power transistor. Where there is no conflict, the various embodiments of this application and the features thereof can be combined with each other.

[0057] Example 1: Topology of a Hybrid Single-Inductor Bipolar Output Converter This embodiment provides a hybrid single-inductor bipolar output converter for converting a positive input voltage into bipolar positive and negative output voltages. This converter can be applied to various scenarios requiring bipolar power supply, such as power management in display drivers, audio amplifiers, and medical wearable devices.

[0058] See Figure 2 The converter includes an input voltage terminal. The converter has four external ports: power ground (GND), positive voltage output, and negative voltage output. It further includes a flying capacitor. ,inductance Positive output capacitor and negative voltage output capacitor Four passive energy storage devices and seven power transistors, which are designated as the first power transistors. Second power transistor Third power transistor Fourth power transistor Fifth power transistor Sixth power transistor and the seventh power transistor Each of the power transistors includes a first terminal, a second terminal, and a control terminal, wherein the control terminal is used to receive a drive signal to control the power transistor to turn on or off.

[0059] The connection relationships between the seven power transistors and passive devices are described in detail below.

[0060] The first power transistor The first terminal and the sixth power transistor The first terminal is connected to the input voltage terminal. It should be noted that the sixth power transistor... This is a key new component added to the topology of this application compared to the existing hybrid single-inductor bipolar output converter topology. Its first terminal is directly connected to the input voltage terminal, providing a basic path for the independent discharge of the negative voltage output terminal, which will be described later.

[0061] The converter internally forms three key floating potential nodes. Specifically, the first power transistor... The second end, the fourth power transistor The second end, the flying capacitor The first terminal and the inductor The first ends are connected together to form the first node. The first node It is a floating potential node, whose potential changes with the conduction state of each power transistor during different operating stages. The second power transistor... The first end, the seventh power transistor The second end and the flying capacitor The second ends are connected together to form a second node. The second node It is also a floating potential node. The third power transistor The second end, the fifth power transistor The second end, the sixth power transistor The second terminal and the inductor The second ends are connected together to form a third node. .

[0062] On the ground side, the second power transistor The second end, the third power transistor The first terminal and the fourth power transistor The first terminal of each is connected to the power ground GND. On the output side, the fifth power transistor... The first terminal is connected to the positive voltage output terminal, and the positive voltage output capacitor The seventh power transistor is connected between the positive voltage output terminal and the power ground (GND). The first terminal is connected to the negative voltage output terminal, and the negative voltage output capacitor The two output capacitors are connected between the negative voltage output terminal and the power ground (GND). They are used to filter ripple and maintain stable output voltage at their respective output terminals. The control terminals of each power transistor are used to receive drive signals generated by the drive circuit module.

[0063] In the above topology, the flying capacitor This is one of the key structural features that distinguishes it from traditional non-hybrid single-inductor bipolar output converter topologies. From the perspective of connectivity, the flying capacitor... Bridging at the first node With the second node Between, and inductance Bridging at the first node With the third node Between. Flying capacitor Through the first power transistor Second power transistor Phase 1 Complete charging, and proceed to the subsequent second stage. and the third stage The voltage at the floating node is clamped, thereby limiting the voltage stress on each power transistor to a low level. This clamping mechanism is the core principle for low-voltage power transistor design and will be explained in detail later in conjunction with each working stage.

[0064] More importantly, the sixth power transistor This is a key new component in the topology of this application that enables the "load independence" function. The first terminal of this power transistor is connected to the input voltage terminal. The second end connects to the third node. The third stage is configured to discharge to the negative voltage output terminal. The middle conduction is enabled to provide the input voltage terminal. To the third node The independent discharge path. In existing hybrid single-inductor bipolar output converters with flying capacitors, the discharge stages of the positive and negative output terminals often share the same power transistor path, thus making it impossible to independently power the other terminal under no-load or extreme load conditions. This application adds the sixth power transistor... This provides the negative voltage output terminal with a discharge path independent of the positive voltage output terminal. It should be noted that the sixth power transistor... The introduction of this is not a simple stacking of components, but rather a combination of flying capacitors. Collaborative work, in the third phase A completely new energy transfer path is formed: input voltage via the sixth power transistor Reaching the third node Therefore, the inductor The stored energy can be independently transmitted via the seventh power transistor. Release to the negative voltage output terminal, and simultaneously flyover capacitor With the help of the sixth power transistor The established Potential completion for the first node The clamping mechanism maintains the advantage of low device stress. This structural improvement allows the hybrid topology of this application to not only maintain the low device voltage stress and strong load-carrying capacity brought by the flying capacitor, but also realize the independent load output function of the traditional non-hybrid topology, thus expanding the applicability of the hybrid single-inductor bipolar output converter.

[0065] Furthermore, in an optional implementation, the first power transistor The fifth power transistor and the sixth power transistor It is a P-type metal-oxide-semiconductor (PMOS) transistor, the second power transistor. The third power transistor The fourth power transistor and the seventh power transistor The transistors used are N-type metal-oxide-semiconductor (NMOS) transistors. In this embodiment, the first terminal of each power transistor is the source terminal, the second terminal is the drain terminal, and the control terminal is the gate terminal. PMOS transistors conduct at a low level within their corresponding operating voltage domain, while NMOS transistors conduct at a high level within their corresponding operating voltage domain. It should be noted that the above selection of power transistor type is an exemplary embodiment. Those skilled in the art can select other types of power transistors (e.g., an all-NMOS solution) to achieve similar functions based on specific design requirements and process conditions, as long as the corresponding conduction logic and voltage domain requirements are met.

[0066] Three-phase working mode See Figure 3 The main operating mode of the converter is three-phase mode, that is, it goes through three different power transistor conduction stages in each switching cycle.

[0067] Phase 1 (Inductor and flying capacitor charging stage): In this stage, the first power transistor... The second power transistor and the third power transistor The transistor is on, and all other power transistors are off. Input voltage Through the first power transistor that is turned on Apply to the first node , making The potential is At the same time, because of the second power transistor and the third power transistor Both are on and one end of each is connected to power ground (GND), the second node and the third node The potential of all capacitors is pulled to the power ground potential. Therefore, the flying capacitor... Both ends (i.e.) and The voltage difference between them is Flying capacitor Charged to ;inductance Both ends (i.e.) and The voltage difference between them is also... ,inductance It is also charged. During this stage, the inductor current... It continues to rise with a positive slope, as shown in formula (1): in, For inductor current, Input voltage, Let be the inductance value. Equation (1) shows that in the first stage, the rate of rise of the inductor current is directly proportional to the input voltage and inversely proportional to the inductance value. This stage is a necessary stage in each duty cycle, responsible for storing energy for the system, and its duration is determined by the first duty cycle described later. Decide.

[0068] Phase Two (Positive voltage output discharge stage): In this stage, the fourth power transistor... and the fifth power transistor When the inductor is turned on, the other power transistors are turned off. Through the fifth power transistor that is turned on To the positive voltage output capacitor Discharge provides energy to the positive voltage output terminal. At this time, the fourth power transistor... The first node is turned on. The potential is pulled to the power ground potential, that is... The third node Through the fifth power transistor that is turned on When connected to the positive output terminal, its potential is the positive output voltage. Inductor current It descends with a negative slope, as shown in formula (2): in, This is the positive output voltage. During this stage, the flying capacitor... It played a crucial voltage clamping role: due to the first stage The flying capacitor has been removed Charge to approximately The voltage, and at this time Through the fourth power transistor that is turned on Connected to power ground, therefore flying capacitor The second node The potential is clamped to a negative input voltage, that is... This clamping effect makes the second stage equivalent to the positive buck-boost configuration in a traditional single-inductor bipolar output converter architecture.

[0069] Phase Three (Negative voltage output discharge stage): In this stage, the sixth power transistor... and the seventh power transistor When the inductor is turned on, the other power transistors are turned off. Through the seventh power transistor that is turned on To the negative voltage output capacitor Discharge provides energy to the negative voltage output terminal. At this time, the second node... Through the seventh power transistor that is turned on Connected to the negative voltage output terminal, its potential is the negative voltage output voltage. ( (Negative value). The third node Through the sixth power transistor that is turned on Connect to the input voltage terminal Its potential is .inductance Both ends ( to In the voltage difference of ), The potential is ; and flying capacitor The above still maintains approximately The voltage, due to The potential becomes Therefore, the flying capacitor The first node Potential clamping to Therefore, inductance The voltage difference between the two ends is ,because If the value is negative, the inductor current is... It continues to decrease, and its slope is shown in formula (3): in, negative output voltage ( This stage is equivalent to the negative buck-boost configuration in a traditional single-inductor bipolar output converter architecture.

[0070] Voltage clamping of flying capacitors and stress on low-voltage devices Flying capacitor In the aforementioned second stage and the third stage The voltage clamping effect played by the transistor is the core principle for achieving low-voltage power transistor design in this application. Specifically, in the second stage... In the middle, the first node Through the fourth power transistor that is turned on Connected to power ground, flying capacitor The second node Potential clamping to In the third stage In the middle, the third node Through the sixth power transistor that is turned on Connect to the input voltage terminal Second node Through the seventh power transistor that is turned on Connect to negative pressure output terminal Flying capacitor The first node Potential clamping to .

[0071] Through the above clamping mechanism, the positive output voltage is not greater than the input voltage ( And the absolute value of the negative voltage output voltage is not greater than the input voltage. Under the operating conditions, in each operating stage, the drain-source voltage stress (i.e., the absolute value of the voltage difference between its first and second terminals) borne by each power transistor does not exceed the input voltage. This means that under the above operating conditions, there is no need to use high-voltage power transistors; low-voltage power transistors can be used to achieve bipolar output conversion, thereby reducing the on-resistance and switching losses of the power transistors and achieving better conversion efficiency at the same process node.

[0072] Three-phase / two-phase adaptive working mode switching In the above three-phase working mode, the first stage It is a necessary stage in each work cycle, responsible for the inductor and flying capacitor Charge to accumulate energy. Second stage. and the third stage These are optional stages, each responsible for releasing energy to the positive and negative output terminals respectively. Based on this characteristic, the converter can adaptively switch operating modes according to the load conditions of the positive and negative output terminals.

[0073] Specifically, when the difference between the load current at the positive voltage output terminal and the load current at the negative voltage output terminal is within a preset range, the converter operates in the first stage. Phase Two and the third stage The three-phase mode, composed sequentially, supplies energy to both the positive and negative terminals simultaneously. When the difference between the load at the positive output terminal and the load at the negative output terminal exceeds the preset range, or when either terminal is unloaded, the converter automatically switches to two-phase mode. The two-phase mode includes two combination methods: from the first stage... With the second phase The combined mode focuses on the positive pressure output end. Energy supply, from the first stage Compared with the third stage The combined mode focuses on the negative pressure output end. Supply energy. The preset range can be preset according to output ripple, load capacity, or duty cycle status; in an embodiment without an output current sampling circuit, the load difference can be determined by the first duty cycle. Second duty cycle Second pulse width modulation signal The state is indirectly represented. This adaptive switching mechanism enables the converter to respond quickly to single-ended load changes, helps suppress output voltage fluctuations, and improves the load-independent regulation capability of the hybrid topology.

[0074] Example 2: Control Method This embodiment provides a control method applied to the hybrid single-inductor bipolar output converter described in Embodiment 1. (See also...) Figure 4 and Figure 5 This control method employs a common-mode and differential-mode dual-loop control strategy, which adjusts the first duty cycle. Second duty cycle This control strategy, which achieves overall system energy regulation and energy distribution between the positive and negative terminals, differs from common time-division multiplexing control or single comparison logic in existing technologies. It is specifically designed for the unique coupling relationship between the positive and negative outputs in a hybrid SIBO topology. By simultaneously introducing positive and negative feedback signals into the calculations of two loops, it achieves coordinated regulation of the positive and negative output voltages, helping to reduce cross-regulation effects and suppress output ripple. The control method specifically includes the following steps.

[0075] Step 100: Voltage sampling step.

[0076] In this step, the positive pressure feedback signal of the positive pressure output terminal is acquired respectively. and the negative pressure feedback signal at the negative pressure output terminal Positive pressure feedback signal Reflects the positive voltage output terminal voltage Real-time status, negative pressure feedback signal Reflects the voltage at the negative voltage output terminal The real-time status. In practical implementation, the feedback signal can be obtained by sampling the respective output voltages through a resistor voltage divider network. Positive voltage feedback signal and negative pressure feedback signal It will simultaneously participate in subsequent differential-mode and common-mode operations, forming the signal basis for dual-loop coordinated control.

[0077] Step 200: Error amplification step.

[0078] Based on the positive pressure feedback signal output in step 100 and the negative pressure feedback signal Each of these is compared with its corresponding reference voltage. The core feature of this step is that the positive voltage feedback signal... and negative pressure feedback signal Simultaneously, two parallel processing channels, differential mode operation and common mode operation, are introduced. The system has four error amplifiers, which are paired up to form differential mode group and common mode group respectively.

[0079] Step 210: Differential Calculation The error signals from the two sets of reference voltages and feedback voltages are processed by differential-mode calculation, and then frequency-domain compensation is performed through a Type II compensation network to generate a differential-mode error signal. Differential mode error signal Used to control the first duty cycle Its amplitude reflects the degree to which the total energy of the system deviates from the expected value. When and When both are low, Increase the first duty cycle As it increases, the input terminal becomes more sensitive to the inductor. Inject more energy.

[0080] Specifically, let's assume a positive pressure feedback signal. The corresponding reference voltage is Negative pressure feedback signal The corresponding reference voltage is The positive pressure end error signal is The error signal at the negative pressure end is The differential error signal can then be expressed as: in The equivalent gain for the differential processing channel.

[0081] Formula (4) shows that the differential channel calculates the difference between the two sets of error signals to reflect the total energy deviation of the system: when both outputs are low, the positive pressure feedback signal Lower The increase, coupled with the low absolute value of the negative voltage output, leads to a negative voltage feedback signal. Elevate, make Decrease As it increases, The corresponding increase is to drive more energy injection.

[0082] Step 220: Common Modulus Operation After the two sets of error signals are processed through common-mode operation, they are then subjected to frequency domain compensation through another type II compensation network to generate a common-mode error signal. Common-mode error signal Used to control the second duty cycle Its amplitude reflects the degree to which the energy distribution at the positive and negative ends deviates from the expected proportion.

[0083] Correspondingly, the common-mode error signal can be expressed as: in The equivalent gain of the common-mode processing channel. Equation (5) shows that the common-mode channel sums the two sets of error signals to reflect the energy distribution deviation between the positive and negative output terminals: when the positive voltage terminal needs more energy, Increase The change is small or decreases. As it increases, The corresponding increase drives more energy to be distributed to the positive voltage output terminal. In actual circuits, the above signal processing relationship of differential mode difference and common mode summation can also be achieved through equivalent error amplifier combinations, resistor-capacitor networks, or transconductance amplifier structures.

[0084] It should be particularly noted that in this step, the negative pressure feedback signal Introduced into the common-mode operation to participate in the second duty cycle The adjustment. This design is a key improvement of the control strategy in this application compared to existing technologies. This is achieved by using a negative pressure feedback signal. Introducing a second duty cycle The control loop overcomes the limitations of existing control strategies. The regulation did not take into account the negative voltage output voltage. The insufficient demand enabled positive voltage output. and negative voltage output voltage The coordinated regulation helps reduce cross-modulation effects and suppress dual-end output ripple. This common-mode-differential-mode decomposition is proposed for the special coupling relationship between the positive and negative outputs of the SIBO topology, and the technical problems it solves and the technical effects it achieves differ from the general concept of differential-mode / common-mode signal processing.

[0085] Furthermore, the Type II compensation network consists of resistors and capacitors, and its zero-pole frequencies are set to ensure that the differential-mode loop and the common-mode loop have sufficient phase margin and gain margin in their respective operating frequency bands, thereby ensuring the stability of the loops.

[0086] Step 300: Current sampling and superposition steps.

[0087] In the inductor The first stage of charging During this period, the current flowing through the inductor The charging current is sampled to obtain the sampling current signal. The sampled current signal is then superimposed with the slope compensation signal to generate a superimposed sampled voltage signal. .

[0088] Step 310: Current sampling In the first stage In the middle, the third power transistor that is turned on. The current is sampled to obtain the sampled current signal. Select the third power transistor. Instead of using the high-side power transistor for sampling, which is commonly used in traditional architectures, this application employs a unique design for current sensing. The technical reason for this is that in a hybrid architecture, the high-side power transistor (i.e., the first power transistor)... In the first phase The conduction current includes not only the inductor charging current, but also the flying capacitor current. The charging current and the superposition of the two make it impossible for the high-side sampling to accurately reflect the pure inductor current information. And the third power transistor... One end is connected to power ground (GND), and the other end is connected to the third node. (i.e., inductance) One end), in the first stage Only the inductor charging current flows through it, excluding the flying capacitor. The charging current component. Therefore, the third power transistor is selected. Sampling can eliminate interference from the charging current of the flying capacitor on the inductor current sampling at the physical circuit level, obtain pure inductor current information, and thus provide accurate feedback for the regulation of the total system energy.

[0089] Step 320: Slope Compensation and Overlay The first ramp voltage signal Converted into a current signal by a ramp buffer circuit The current signal The sampled current signal obtained in step 310 The signals are then superimposed. The superimposed current signals are then converted into superimposed sampling voltage signals by a sampling resistor. The first ramp voltage signal The first stage of each switching cycle During this period, a ramp waveform that increases linearly with time is generated. Because the converter designed in this application has a wide output range, the duty cycle may be greater than 0.5, which can easily induce subharmonic oscillations under peak current mode control. When the first duty cycle... When the value is greater than a preset threshold (e.g., 0.5), the slope compensation effect generated by superimposing the slope waveform onto the sampled current signal can effectively suppress the subharmonic oscillation in the current loop and ensure the stable operation of the system within a wide duty cycle range.

[0090] Step 400: Voltage and current limiting steps (optional).

[0091] Optionally, a voltage and current limiting step can be set between the error amplification output in step 200 and the pulse width modulation comparison in step 500. This step uses the voltage and current limiting module to limit the differential mode error signal. and the common-mode error signal The voltage is limited within a preset operating range, and the voltage-limited signal is input to the subsequent pulse width modulation step for comparison. By limiting the maximum voltage value of the error signal, the duty cycle and the maximum value of the inductor current can be indirectly limited. This helps prevent system instability caused by an excessively large duty cycle and also helps avoid excessive power consumption due to excessive inductor current, thereby protecting the safe operating environment of low-voltage devices. At the same time, by limiting the minimum voltage value of the error signal, it can be ensured that the input signal of the comparator is always within the normal operating range.

[0092] Step 500: Pulse width modulation step.

[0093] See Figure 5 This step is performed by a PWM control module consisting of two sets of comparators and RS flip-flops, which is used to generate two pulse width modulation signals.

[0094] Step 510: Generation of the first pulse width modulation signal The superimposed sampling voltage signal output in step 300 The differential mode error signal output in step 200 The input is compared with the first comparator. In the first stage... middle, The signal gradually increases from its initial value as the inductor current rises; when Rise to equal At that time, the first comparator outputs a toggle signal. This toggle signal is processed by the first RS flip-flop to generate a signal with a first duty cycle. First pulse width modulation signal First duty cycle Controlling the first phase (Inductor charging phase) The time percentage within a switching cycle determines the total energy flowing into the system within that cycle. When the load increases, causing a drop in output voltage, the differential mode error signal... Increase achieve The time required has increased. As the load increases, more energy is injected into the system, enabling a rapid response to load fluctuations.

[0095] Step 520: Generation of the second pulse width modulation signal The second ramp voltage signal The common-mode error signal output in step 200 The input is compared using the second comparator. When Rise to equal At that time, the second comparator outputs a toggle signal. This toggle signal is processed by the second RS flip-flop to generate a signal with a second duty cycle. The second pulse width modulation signal Second duty cycle Controlling the second phase Compared with the third stage The time allocation between them is used to regulate the energy distribution ratio between the positive and negative pressure output terminals. When the pressure increases, the positive pressure output terminal Compared to the negative pressure output end They will receive more energy allocation.

[0096] Step 600: Driver steps.

[0097] Based on the first pulse width modulation signal generated in step 500 and the second pulse width modulation signal The drive circuit module generates drive signals to control the on and off states of the first to seventh power transistors.

[0098] Step 610 (Level Conversion Sub-step): Since the voltage domain of the control signal may be different from that of the power module, the drive circuit module is equipped with a level shifter to convert the control signal from the control signal voltage domain to the power module voltage domain, so as to ensure that the gate drive voltage of each power transistor is within the correct range.

[0099] Step 620 (Phase Non-overlapping Sub-step): The driver circuit module further includes a phase non-overlapping logic circuit. This circuit controls the switching timing of each power transistor, inserting an appropriate dead time between the switching moments of adjacent power transistors to prevent shoot-through between power transistors and avoid short-circuit current from the input voltage terminal to power ground. Simultaneously, by reasonably setting the dead time and switching timing, it is beneficial for some power transistors to achieve zero-voltage switching (ZVS), further reducing switching losses and improving the converter's conversion efficiency.

[0100] Step 630 (Adaptive Mode Switching Sub-step): In the driving step, the first duty cycle is also used as a basis. and the second duty cycle The comparison relationship and the second pulse width modulation signal The switching mechanism adaptively switches between three-phase and two-phase operating modes based on the voltage level. This switching mechanism uses a single control mode, automatically determining the mode based on the duty cycle information inherent in the control loop, eliminating the need for additional external detection circuits and complex control mode switching logic.

[0101] The specific switching logic is as follows. When the load difference between the two ends is within a preset range, the drive signal is used to control the converter to sequentially include the first stage. Phase Two and the third stage It operates in a cyclic manner under three-phase working mode. When the second duty cycle is determined... Less than the first duty cycle When this occurs, it indicates that the negative pressure output terminal... More energy supply is required, at which point the converter's operating mode is switched to operate only by the first stage. and the third stage The two-phase operating mode prioritizes power supply to the negative voltage output terminal. When the second pulse width modulation signal is detected... If the voltage remains high for multiple consecutive switching cycles, it indicates a positive voltage output. More energy supply is required, at which point the converter's operating mode is switched to operate only by the first stage. Phase Two The two-phase operating mode prioritizes power supply to the positive voltage output. In the aforementioned adaptive mode switching, The judgment condition can be set to switch only after a preset number of cycles have been continuously reached. The number of consecutive switching cycles mentioned in the determination condition for maintaining a high level is a preset number of cycles. By setting a continuous cycle determination condition, the risk of mode switching repeatedly jumping near the critical state can be reduced.

[0102] Dynamic response analysis of control loop See Figure 5 With positive voltage output terminal load current Taking a relative increase as an example, we can illustrate the dynamic response process of the control loop. When When the voltage increases, the energy carried by the inductor current in the current cycle cannot meet the instantaneous energy demand of the positive voltage output terminal, resulting in a decrease in the positive voltage output voltage. The voltage drops, and the negative voltage output voltage decreases simultaneously. The absolute value of this also decreases. This change causes the positive pressure feedback signal to... Reduce, negative pressure feedback signal The error signal increases. After differential-mode processing, the differential-mode error signal... Rapidly increases; after common-mode operation, the common-mode error signal It also increases rapidly.

[0103] In the differential mode loop, Increase makes achieve The time is longer, the first duty cycle It increases accordingly. Enlargement means the first stage The duration of the (inductor charging phase) increases, and the input voltage continuously supplies the inductor. Longer charging time, inductor current The peak value increases, and the total energy transferred to the system within a single cycle increases, thus enabling a rapid response to load fluctuations. In a common-mode loop, Increasing the second duty cycle It also increases accordingly. Increased pressure means positive pressure output. Compared to the negative pressure output end This will allow for greater energy allocation, thus meeting the increased energy demand at the positive pressure output. The aforementioned dual-loop coordinated response process demonstrates the advantages of the common-mode-differential-mode decoupling control strategy: the two loops can respond independently and synchronously to load changes, reducing the problem of mutual interference between positive and negative control in traditional schemes.

[0104] Example 3: Power Management Integrated Circuit This embodiment provides a power management integrated circuit, which includes a hybrid single-inductor bipolar output converter as described in Embodiment 1, and a control circuit. The control circuit is connected to the control terminals of each power transistor in the hybrid single-inductor bipolar output converter, and is configured to execute the control method described in Embodiment 2. In chip-level implementation, the seven power transistors and modules such as the error amplifier, comparator, RS flip-flop, level shifter, phase non-overlapping logic circuit, drive circuit, and current sampling circuit in the control circuit can be integrated onto the same integrated circuit chip. (Inductor) Positive output capacitor and negative voltage output capacitor As an off-chip component, it is connected to the converter circuit via external pins on the chip. Flying capacitor Depending on capacitance and process requirements, on-chip integration or off-chip interconnection can be selected. By integrating the converter's topology and control circuitry onto the same chip, a highly integrated bipolar power management solution can be achieved, meeting the demands of consumer electronics devices for compact form factors and efficient power management.

[0105] Supplementary Examples: Parameter Examples and Performance Descriptions In one exemplary embodiment, the hybrid single-inductor bipolar output converter described in this application can be used for power supply to an AMOLED display driver. The OLED's driving current... It can be represented as: in, For carrier mobility, The capacitance per unit area of ​​the gate oxide layer. and These represent the channel width and length of the thin-film transistor, respectively. Gate-source voltage, Threshold voltage. Positive output voltage. It will affect the gate-source voltage in the AMOLED pixel driving circuit. Therefore, the ripple control at the positive pressure output end has an impact on the display quality.

[0106] In an example that meets the design objective of low voltage stress, the input voltage Approximately 3.7 V, positive output voltage Approximately 3.3 V, negative output voltage The voltage is approximately -3.3 V, and the positive output voltage is no greater than the input voltage, while the absolute value of the negative output voltage is no greater than the input voltage. The positive output voltage of the converter can be programmed and adjusted within the range of approximately 0 to 4.2 V, and the negative output voltage can be programmed and adjusted within the range of approximately -3 V to -4.9 V. It should be noted that the above-mentioned low-voltage device stress reduction technology works under the operating conditions that the positive output voltage is no greater than the input voltage and the absolute value of the negative output voltage is no greater than the input voltage; when the output voltage exceeds these conditions, the voltage stress on some power transistors may exceed the input voltage. Inductor The inductance value is approximately 2.2 μH, and the flying capacitor... The capacitance value is approximately 4.7 μF, positive voltage output capacitor. and negative voltage output capacitor The capacitance values ​​are each approximately 4.7 μF, and the switching frequency is approximately 1.5 MHz. In V. V. Under typical operating conditions, the converter's peak efficiency is over 90%, the positive voltage output ripple is within 10 mV, and the negative voltage output ripple is within 10 mV.

[0107] Power transistor conduction status table for each operating stage: Summary of node potentials at each stage: The third stage middle The derivation process is as follows: Seventh power transistor Conducting Flying capacitor Maintain in the first stage The voltage obtained (Right now ),therefore .

[0108] Phase Two For example, among the power transistors turned off during this stage, The source potential is Drain potential is ,therefore The voltage across both ends is ; The drain potential is GND and the source potential is ,therefore The voltage across both ends is In the third phase For example, The source potential is Drain potential is ,because It is a negative value. The voltage across both ends is ,exist The voltage should not exceed the input voltage. The voltage stress experienced by each of the other power transistors at each stage can be obtained through similar analysis. and Under the working conditions, the conclusion is that none of them exceed [the specified value]. .

[0109] In an exemplary control implementation, the Type II compensation network may employ a compensation structure comprising a first capacitor, a first resistor, and a second capacitor. For example, the first capacitor... Approximately 15 pF, first resistor Approximately 700 kΩ, second capacitor The transconductance of the error amplifier is approximately 150 fF. Approximately 70 μS. In Under heavy load conditions of mA, the system loop bandwidth is approximately 132.2 kHz, and the phase margin is approximately 44°. These parameters are merely examples to illustrate how the bandwidth and phase margin of the control loop can be adjusted by setting the zeros and poles through a compensation network.

[0110] In one exemplary embodiment, the ramp buffer circuit includes a voltage-to-current conversion stage that receives the ramp voltage signal. It is converted to the form of a transconductance amplifier. Proportional ramp current signal The ramp current signal The sampled current signal generated by the current sampling module The currents are superimposed at the same current node, and the resulting total current flows through a sampling resistor. A superimposed sampling voltage signal is generated across the resistor. ,Right now: During adaptive mode switching, the load difference between the two ends is within a preset range, which can be determined directly by the output current sampling results or by controlling the first duty cycle in the control loop. Second duty cycle Second pulse width modulation signal The state is indirectly determined. In an implementation without additional output current sampling circuitry, when... When the preset number of cycles is reached, it can be determined that the negative pressure output terminal requires more energy supply, and the system will switch to the first stage. and the third stage The two-phase mode is composed of; when If the voltage remains high for multiple consecutive switching cycles, it can be determined that the positive voltage output terminal requires more energy supply, and the system switches to the first stage. Phase Two The two-phase mode can be formed; when neither of the above two conditions is met, it can be maintained or restored to the three-phase mode.

[0111] Under one test condition, without introducing a negative pressure feedback signal Participate in the second duty cycle In the control scheme, the fluctuations of the positive and negative outputs under a 20 mA common load are approximately 17 mV / 50 mV. In this embodiment, under a 200 mA common load, the fluctuations of both the positive and negative outputs are less than 10 mV, and the recovery time is also improved. Since the two sets of data correspond to different load conditions, the above test results are used to illustrate that this application exhibits a trend of smaller output fluctuations and faster recovery under the corresponding test conditions. Three-phase to two-phase adaptive switching helps reduce the output ripple at the other end under single-end no-load conditions. The above improvement effect stems from the fact that common-mode to differential-mode decoupling allows the two loops to respond independently to load changes, reducing the mutual influence between the positive and negative control.

[0112] It should be noted that in the documents of this application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In the documents of this application, if a reference is made to performing an action based on an element, it means performing the action at least based on that element, including two cases: performing the action only based on that element, and performing the action based on that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0113] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0114] All documents mentioned in this application are considered to be incorporated in their entirety into the disclosure of this application so that they can serve as a basis for modifications if necessary. Furthermore, it should be understood that after reading the foregoing disclosure of this application, those skilled in the art can make various alterations or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A hybrid single-inductor bipolar output converter for converting a positive input voltage into a bipolar positive and negative output voltage, characterized in that, The converter includes: Input voltage terminal, power ground, positive voltage output terminal, and negative voltage output terminal; flying capacitor (CF), inductor (L), positive voltage output capacitor (COP), and negative voltage output capacitor (CON); first power transistor (S1), second power transistor (S2), third power transistor (S3), fourth power transistor (SP1), fifth power transistor (SP2), sixth power transistor (SN1), and seventh power transistor (SN2); each of the first to seventh power transistors includes a first terminal, a second terminal, and a control terminal; The first terminal of the first power transistor (S1) and the first terminal of the sixth power transistor (SN1) are both connected to the input voltage terminal; the second terminal of the first power transistor (S1), the second terminal of the fourth power transistor (SP1), the first terminal of the flying capacitor (CF), and the first terminal of the inductor (L) are connected together to form a first node (VSW1); the first terminal of the second power transistor (S2), the second terminal of the seventh power transistor (SN2), and the second terminal of the flying capacitor (CF) are connected together to form a second node (VSW2); the second terminal of the third power transistor (S3), the second terminal of the fifth power transistor (SP2), the second terminal of the sixth power transistor (SN1), and the second terminal of the inductor (L) are connected together to form a third node (VSW3); The second terminal of the second power transistor (S2), the first terminal of the third power transistor (S3), and the first terminal of the fourth power transistor (SP1) are all connected to the power ground; the first terminal of the fifth power transistor (SP2) is connected to the positive voltage output terminal, and the positive voltage output capacitor (COP) is connected between the positive voltage output terminal and the power ground; the first terminal of the seventh power transistor (SN2) is connected to the negative voltage output terminal, and the negative voltage output capacitor (CON) is connected between the negative voltage output terminal and the power ground. The control terminals of each of the power transistors are used to receive drive signals; the sixth power transistor (SN1) is configured to be turned on during the discharge phase to the negative voltage output terminal to provide an independent discharge path from the input voltage terminal to the third node (VSW3).

2. The converter according to claim 1, characterized in that, The first power transistor (S1), the fifth power transistor (SP2), and the sixth power transistor (SN1) are P-type metal-oxide-semiconductor transistors; the second power transistor (S2), the third power transistor (S3), the fourth power transistor (SP1), and the seventh power transistor (SN2) are N-type metal-oxide-semiconductor transistors; wherein the first terminal of each power transistor is the source terminal and the second terminal is the drain terminal.

3. The converter according to claim 1, characterized in that, The converter operates in a three-phase mode comprising three stages: Phase 1 (Φ1): The first power transistor (S1), the second power transistor (S2), and the third power transistor (S3) are turned on, while the remaining power transistors are turned off. The input voltage charges the flying capacitor (CF) through the branch of the second power transistor (S2) and simultaneously charges the inductor (L) through the branch of the third power transistor (S3). The potential of the first node (VSW1) is the input voltage, and the potentials of the second node (VSW2) and the third node (VSW3) are both power ground potentials. The inductor current flows at a slope... rise; Second stage (Φ2): The fourth power transistor (SP1) and the fifth power transistor (SP2) are turned on, and the remaining power transistors are turned off; The inductor (L) discharges to the positive output capacitor (COP) via the fifth power transistor (SP2); the potential of the first node (VSW1) is the power ground potential, and the potential of the third node (VSW3) is the positive output voltage. The inductor current has a slope decline; Third stage (Φ3): The sixth power transistor (SN1) and the seventh power transistor (SN2) are turned on, and the remaining power transistors are turned off; The inductor (L) discharges to the negative output capacitor (CON) via the seventh power transistor (SN2); the potential of the second node (VSW2) is the negative output voltage. The potential of the third node (VSW3) is the input voltage. The inductor current has a slope It continues to decline.

4. The converter according to claim 3, characterized in that, The flying capacitor (CF) is configured to clamp the node voltage at different operating stages to reduce the voltage stress on each power transistor. The clamping process includes: In the second stage (Φ2), the first node (VSW1) is connected to the power ground through the conducting fourth power transistor (SP1), and the flying capacitor (CF) clamps the potential of the second node (VSW2) to the negative input voltage, i.e. ; In the third stage (Φ3), the third node (VSW3) is connected to the input voltage terminal through the conducting sixth power transistor (SN1), and the second node (VSW2) is connected to the negative voltage output terminal through the conducting seventh power transistor (SN2). The flying capacitor (CF) clamps the potential of the first node (VSW1) to the sum of the negative voltage output voltage and the input voltage. ; Due to the clamping effect of the flying capacitor (CF), under the operating conditions that the positive output voltage is not greater than the input voltage and the absolute value of the negative output voltage is not greater than the input voltage, the voltage stress borne by each power transistor in the second stage (Φ2) and the third stage (Φ3) does not exceed the input voltage.

5. The converter according to claim 3, characterized in that, The first stage (Φ1) is a necessary stage in each work cycle, while the second stage (Φ2) and the third stage (Φ3) are optional stages; When the difference between the load current at the positive voltage output terminal and the load current at the negative voltage output terminal is within a preset range, the converter operates in a three-phase mode consisting of the first stage (Φ1), the second stage (Φ2), and the third stage (Φ3) in sequence. When the difference between the load at the positive output terminal and the load at the negative output terminal exceeds the preset range or when either terminal is unloaded, the converter switches to a two-phase mode consisting of a combination of the first stage (Φ1) and the second stage (Φ2) or the third stage (Φ3).

6. A control method applied to a hybrid single-inductor bipolar output converter as described in any one of claims 1 to 5, characterized in that, The control method includes the following steps: Voltage sampling steps: acquire the positive voltage feedback signal (VFBP) at the positive voltage output terminal and the negative voltage feedback signal (VFBN) at the negative voltage output terminal respectively; Error amplification step: Based on the positive voltage feedback signal (VFBP) and the negative voltage feedback signal (VFBN) output from the voltage sampling step, they are compared with the corresponding reference voltages, and a differential-mode error signal (VEA,DM) for controlling the total energy of the system is generated through differential-mode operation, and a common-mode error signal (VEA,CM) for controlling the energy distribution between the positive and negative terminals is generated through common-mode operation; wherein, the negative voltage feedback signal (VFBN) participates in the common-mode operation to adjust the common-mode error signal (VEA,CM); Current sampling and superposition steps: In the first stage (Φ1) of charging the inductor (L), the charging current flowing through the inductor (L) is sampled to obtain a sampling current signal. The first ramp voltage signal (VRAMP1) is converted into a current signal through a ramp buffer circuit and superimposed with the sampling current signal. Then, it is converted into a superimposed sampling voltage signal (VSUM) through a resistor. Pulse Width Modulation Step: The superimposed sampled voltage signal (VSUM) output from the current sampling and superposition step is compared with the differential mode error signal (VEA,DM) output from the error amplification step. After processing by the first RS flip-flop, a first pulse width modulation signal (VPWM1) with a first duty cycle (D1) is generated. The second ramp voltage signal (VRAMP2) is compared with the common mode error signal (VEA,CM) output from the error amplification step. After processing by the second RS flip-flop, a second pulse width modulation signal (VPWM2) with a second duty cycle (D2) is generated. Driving step: Based on the first pulse width modulation signal (VPWM1) and the second pulse width modulation signal (VPWM2) generated in the pulse width modulation step, the driving circuit module generates driving signals for controlling the turn-on and turn-off of the first to seventh power transistors.

7. The control method according to claim 6, characterized in that, In the error amplification step, the positive pressure feedback signal (VFBP) and the negative pressure feedback signal (VFBN) participate simultaneously in the differential mode operation and the common mode operation; The differential mode operation processes the error signals of the two sets of reference voltages and feedback voltages to obtain the differential mode error signal (VEA,DM), which is used to control the first duty cycle (D1) to regulate the total energy inflow of the system. The common-mode operation processes the error signals of the two sets of reference voltages and feedback voltages into a common-mode error signal (VEA,CM), which is used to control the second duty cycle (D2) to regulate the energy distribution between the positive voltage output terminal and the negative voltage output terminal. By introducing the negative voltage feedback signal (VFBN) into the control loop of the second duty cycle (D2), the coordinated control of the positive voltage output voltage and the negative voltage output voltage is achieved. The differential mode error signal (VEA,DM) and the common mode error signal (VEA,CM) are processed by a type II compensation network.

8. The control method according to claim 6, characterized in that, The current sampling and superposition step specifically includes the following steps: in the first stage (Φ1), the current of the conducting third power transistor (S3) is sampled to obtain the sampling current signal, thereby eliminating the interference of the flying capacitor (CF) charging current on the inductor current sampling. When the first duty cycle (D1) is greater than a preset threshold, slope compensation is generated by superimposing the first ramp voltage signal (VRAMP1) onto the sampled current signal to suppress subharmonic oscillations.

9. The control method according to claim 6, characterized in that, In the driving step, the adaptive switching between three-phase or two-phase operating modes is further performed based on the comparison relationship between the first duty cycle (D1) and the second duty cycle (D2). The specific switching logic includes: When the load difference between the two ends is within a preset range, the converter is controlled by the drive signal to operate in a three-phase working mode that sequentially includes the first stage (Φ1), the second stage (Φ2) of discharging to the positive voltage output terminal, and the third stage (Φ3) of discharging to the negative voltage output terminal. When it is determined that the second duty cycle (D2) is less than the first duty cycle (D1), the operating mode of the converter is switched to a two-phase operating mode consisting only of the first stage (Φ1) and the third stage (Φ3); When it is determined that the second pulse width modulation signal (VPWM2) remains at a high level for multiple consecutive switching cycles, the operating mode of the converter is switched to a two-phase operating mode consisting only of the first stage (Φ1) and the second stage (Φ2); The driving step further includes: converting the control signal from the control signal voltage domain to the power module voltage domain through a level shifter; and controlling the switching timing of each power transistor through phase non-overlapping logic to prevent shoot-through between the power transistors, while also facilitating zero-voltage conduction of some of the power transistors.

10. A power management integrated circuit, characterized in that, include: The hybrid single-inductor bipolar output converter as claimed in any one of claims 1 to 5; and a control circuit connected to the control terminals of each of the power transistors in the hybrid single-inductor bipolar output converter, the control circuit being configured to perform the control method as claimed in any one of claims 6 to 9.

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