Power supply adjusting circuit, power supply adjusting system and electronic device

Abstract

This application discloses a power regulation circuit, a power regulation system, and an electronic device, relating to the field of power management technology. The circuit includes: a regulation module and a drive module; the regulation module includes multiple power transistors connected in parallel; the input terminals of the power transistors are connected to a power supply, the output terminals are connected to a load, and the control terminals are connected to the output terminals of the drive module; the input terminal of the drive module is connected to the voltage feedback terminal of the load; the drive module is used to detect the feedback voltage of the load during load power supply and generate a drive signal based on the feedback voltage; the regulation module is used to receive the drive signal and adjust the conduction degree of each power transistor. Compared with existing technologies, this application achieves refined segmented control of the load output voltage by dynamically adjusting the number and timing of multiple parallel power transistors based on the feedback voltage through the drive module. This improves the power supply capacity under heavy load and reduces conduction losses under light load, balancing high efficiency and fast response.

Description

Technical Field

[0001] This application relates to the field of power management technology, and in particular to a power regulation circuit, a power regulation system, and an electronic device. Background Technology

[0002] In modern high-performance computing systems, the current demand of CPUs, GPUs, and ASICs can fluctuate dramatically within nanoseconds, ranging from tens to hundreds of amperes, when switching between different operating modes. To ensure the stable operation of these chips, the power supply regulator (VRM) circuitry supplying them must possess extremely high transient response speed to control output voltage drops or overshoots within a very small tolerance range.

[0003] Existing technologies typically employ multiphase DC-DC converters (such as Buck circuits) as the main power supply. However, limited by the physical characteristics of power inductors and output capacitors, as well as the compensation network of the control loop, the loop bandwidth of traditional DC-DC converters is usually limited to the 100kHz range, with a response time on the order of microseconds (µs). When encountering load transitions on the order of nanoseconds (ns), the feedback loop cannot respond in time, resulting in a significant drop in output voltage. To alleviate this problem, existing solutions are forced to connect a large number of output capacitors in parallel, but this not only increases the system size and cost but also fails to fundamentally eliminate the response delay.

[0004] Therefore, how to achieve nanosecond-level power supply transient response is a problem that urgently needs to be solved in this field. Summary of the Invention

[0005] The main objective of this application is to provide a power conditioning circuit, a power conditioning system, and an electronic device, which aims to solve the technical problem of how to achieve nanosecond-level power transient response.

[0006] To achieve the above objectives, this application proposes a power regulation circuit, the circuit comprising: a regulation module and a drive module; The adjustment module includes multiple power transistors connected in parallel; The input terminal of the power transistor is connected to the power supply, the output terminal of the power transistor is connected to the load, and the control terminal of the power transistor is connected to the output terminal of the drive module. The input terminal of the drive module is connected to the voltage feedback terminal of the load; The drive module is used to detect the feedback voltage of the load during the power supply process of the load, and generate a drive signal based on the feedback voltage; The adjustment module is used to receive the drive signal and adjust the conduction level of each of the power transistors.

[0007] In one embodiment, the driving module includes: a reference unit and a driving unit; The reference terminal of the drive unit is connected to the reference unit, the input terminal of the drive unit is connected to the load, and the output terminal of the drive unit is connected to the control terminal of the power transistor. The reference unit is used to transmit a reference voltage to the drive unit; The drive unit is used to detect the feedback voltage of the load during the power supply process and generate a drive signal based on the feedback voltage.

[0008] In one embodiment, the reference unit includes: a reference chip and a first resistor to a fourth resistor; The output terminal of the reference chip is connected to the driving unit. The first functional terminal of the reference chip is connected to the first end of the first resistor. The second functional terminal of the reference chip is connected to the second end of the second resistor. The third functional terminal of the reference chip is connected to the first end of the third resistor. The fourth functional terminal of the reference chip is connected to the second end of the fourth resistor. The second end of the first resistor is connected to the second end of the third resistor. The second end of the first resistor is also grounded. The first end of the second resistor is connected to the second end of the third resistor and the driving unit, respectively.

[0009] In one embodiment, the driving unit includes: an amplifier, a transistor, a driving power supply, a fifth resistor, a first capacitor, and a second capacitor; The output terminal of the amplifier is connected to the base of the transistor, the ground terminal of the amplifier is grounded, the power supply terminal of the amplifier is connected to the driving power supply and the collector of the transistor, the positive input terminal of the amplifier is connected to the reference unit, the negative terminal of the amplifier is connected to the first terminal of the fifth resistor and the first terminal of the first capacitor, the second terminal of the fifth resistor is connected to the first terminal of the second capacitor, the second terminal of the first capacitor is connected to the second terminal of the second capacitor and the load, and the emitter of the transistor is connected to the control terminal of the power transistor.

[0010] In one embodiment, the circuit further includes: an execution module; The input terminal of the execution module is connected to the drive module, and the output terminal of the execution module is connected to the input terminal of the power transistor. The execution module is used to receive the drive signal output by the drive module and adjust the conduction degree of each power transistor according to the drive signal.

[0011] In one embodiment, the execution module includes: a plurality of resistors, wherein the number of gate resistors is the same as the number of power transistors; The gate resistors are connected in parallel. The first end of the gate resistor is connected to the driving module, and the second end of the gate resistor is connected to the control terminal of the power transistor.

[0012] In one embodiment, the circuit further includes: an energy storage module; The energy storage module is connected between the power supply and the regulating module; The energy storage unit is used to store electrical energy and provide power supply voltage to the regulation module; The energy storage unit is also used to absorb and store energy from the regulation module.

[0013] In one embodiment, the energy storage module includes: a DC-DC converter and an energy storage unit; The energy storage unit is connected to the DC-DC converter and the regulating module respectively, and the DC-DC converter is connected to the power supply. The DC-DC converter unit is used to receive the input voltage and convert the input voltage into a charging voltage to store electrical energy in the energy storage unit; The energy storage unit is used to store electrical energy and provide power supply voltage to the regulation module; The energy storage unit is also used to absorb and store energy from the regulation module.

[0014] In addition, to achieve the above objectives, this application also proposes a power conditioning system, which includes the power conditioning circuit as described above.

[0015] In addition, to achieve the above objectives, this application also proposes an electronic device, which includes the power regulation circuit as described above.

[0016] This application discloses a power regulation circuit, a power regulation system, and an electronic device. The circuit includes: a regulation module and a drive module; the regulation module includes multiple power transistors connected in parallel; the input terminal of each power transistor is connected to a power supply, the output terminal of each power transistor is connected to a load, and the control terminal of each power transistor is connected to the output terminal of the drive module; the input terminal of the drive module is connected to the voltage feedback terminal of the load; the drive module is used to detect the feedback voltage of the load during the power supply process and generate a drive signal based on the feedback voltage; the regulation module is used to receive the drive signal and adjust the conduction degree of each power transistor.

[0017] This application incorporates a power regulation circuit within the electronic device. This circuit includes an regulation module and a drive module. The regulation module includes multiple power transistors connected in parallel. The input terminals of the power transistors are connected to the power supply, the output terminals are connected to the load, and the control terminals are connected to the output terminals of the drive module. The input terminal of the drive module is connected to the voltage feedback terminal of the load. The drive module detects the feedback voltage of the load during power supply and generates a drive signal based on the feedback voltage. The regulation module receives the drive signal and adjusts the conduction level of each power transistor. Compared to existing technologies, this application dynamically adjusts the number and timing of multiple parallel power transistors based on the feedback voltage through the drive module, thereby achieving refined segmented control of the load output voltage. This improves the power supply capacity under heavy loads and reduces conduction losses under light loads, balancing high efficiency and fast response. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the structure of the first embodiment of the power regulation circuit proposed in this application; Figure 2 This is a schematic diagram of the second embodiment of the power regulation circuit proposed in this application. Figure 3 This is a circuit diagram of the reference unit and the drive unit in the second embodiment of the power regulation circuit proposed in this application. Figure 4 This is a schematic diagram of the first structure of the third embodiment of the power regulation circuit proposed in this application. Figure 5 This is a schematic diagram of the second structure of the third embodiment of the power regulation circuit proposed in this application.

[0021] Explanation of icon numbers:

[0022] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0023] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0025] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0026] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0027] It should be noted that in modern high-performance computing systems, the current demand of CPUs, GPUs, and ASICs can fluctuate dramatically within nanoseconds when switching between different operating modes. To ensure the stable operation of these chips, the power supply regulation circuit (VRM) supplying them must have extremely high transient response speed to control output voltage drops or overshoots within a very small tolerance range.

[0028] Existing technologies typically employ multiphase DC-DC converters (such as Buck circuits) as the main power supply. However, limited by the physical characteristics of power inductors and output capacitors, as well as the compensation network of the control loop, the loop bandwidth of traditional DC-DC converters is usually limited to the 100kHz range, with a response time on the order of microseconds (µs). When encountering load transitions on the order of nanoseconds (ns), the feedback loop cannot respond in time, resulting in a significant drop in output voltage. To alleviate this problem, existing solutions are forced to connect a large number of output capacitors in parallel, but this not only increases the system size and cost but also fails to fundamentally eliminate the response delay.

[0029] To address the aforementioned technical problems, this application proposes a power supply regulation circuit. This application includes a power supply regulation circuit within an electronic device, comprising: a regulation module 1 and a drive module 2; the regulation module 1 includes multiple power transistors connected in parallel; the input terminals of the power transistors are connected to a power supply 3, the output terminals of the power transistors are connected to a load 4, and the control terminals of the power transistors are connected to the output terminals of the drive module 2; the input terminal of the drive module 2 is connected to the voltage feedback terminal of the load 4; the drive module 2 is used to detect the feedback voltage of the load 4 during power supply and generate a drive signal based on the feedback voltage; the regulation module 1 is used to receive the drive signal and adjust the conduction degree of each power transistor. Compared to existing methods, this application, through the drive module 2, dynamically adjusts the number and timing of multiple parallel power transistors based on the feedback voltage, thereby achieving refined segmented control of the output voltage of the load 4, improving the power supply capacity under heavy loads and reducing conduction losses under light loads, while balancing high efficiency and fast response.

[0030] For ease of understanding, the following is combined with Figures 1 to 5 The power regulation circuit provided in the embodiments of this application will be described in detail.

[0031] Reference Figure 1 , Figure 1 This is a schematic diagram of the first embodiment of the power regulation circuit proposed in this application.

[0032] like Figure 1 As shown, in this embodiment, the circuit includes: an adjustment module 1 and a drive module 2; The adjustment module 1 includes multiple power transistors connected in parallel; The input terminal of the power transistor is connected to the power supply 3, the output terminal of the power transistor is connected to the load 4, and the control terminal of the power transistor is connected to the output terminal of the drive module 2. The input terminal of the drive module 2 is connected to the voltage feedback terminal of the load 4; The drive module 2 is used to detect the feedback voltage of the load 4 during the power supply process of the load 4, and generate a drive signal based on the feedback voltage; The adjustment module 1 is used to receive the drive signal and adjust the conduction level of each of the power transistors.

[0033] It should be noted that the aforementioned adjustment module 1 may refer to a power stage circuit unit used to adjust the voltage output to the load 4, such as a circuit structure composed of multiple power switching transistors connected in parallel, which can adjust its own conduction degree according to the drive signal, thereby controlling the amount of energy flowing from the power supply 3 to the load 4.

[0034] The aforementioned drive module 2 can refer to a circuit unit used to detect the voltage of the load 4 and generate control signals. For example, it may be a circuit structure containing a high-speed operational amplifier U2 and a reference voltage source, which can compare the difference between the feedback voltage of the load 4 and the reference voltage in real time and output the corresponding drive signal.

[0035] The aforementioned power transistor can refer to a power semiconductor device used to control the switching or regulation of large currents, such as an N-channel enhancement-mode MOSFET (metal-oxide-semiconductor field-effect transistor), which has three electrodes: an input terminal (drain), an output terminal (source), and a control terminal (gate). It can adjust the conduction level between the input and output terminals according to the voltage signal received at the control terminal.

[0036] The aforementioned power supply 3 can refer to the source of raw power for the entire power regulation circuit, such as the 12V power bus of the server motherboard or an external DC power supply.

[0037] The aforementioned load 4 can refer to electronic devices that require a stable voltage power supply, such as CPU (Central Processing Unit), GPU (Graphics Processing Unit), or ASIC (Application-Specific Integrated Circuit).

[0038] The aforementioned feedback voltage can refer to the voltage signal sampled from load 4, reflecting the actual voltage value currently received by load 4.

[0039] The aforementioned drive signal can refer to an electrical signal used to control the conduction level of the power transistor, such as an analog voltage signal output by the high-speed operational amplifier U2, the amplitude of which varies with the difference between the feedback voltage and the reference voltage.

[0040] It should be emphasized that the functions of the above-mentioned functional transistors are the same, therefore in Figure 1 The explanation uses eight functional transistors (first functional transistor Q1 to eighth functional transistor Q8), but does not impose specific limitations on this embodiment.

[0041] In its implementation, the drive module 2 continuously detects the feedback voltage at the load 4's input terminal while supplying power to the load 4. Internally, the drive module 2 compares the detected feedback voltage with a pre-set reference voltage and generates a drive signal based on the difference between the two. When the feedback voltage is lower than the reference voltage, the amplitude of the drive signal output by the drive module 2 increases; when the feedback voltage is higher than the reference voltage, the amplitude of the drive signal output by the drive module 2 decreases. The drive module 2 outputs the generated drive signal to the control terminals of each power transistor in the adjustment module 1. The adjustment module 1 receives the drive signals output by the drive module 2 through the control terminals of each power transistor. Each power transistor adjusts its conduction level according to the received drive signal. When the drive signal indicates a need to increase the output voltage, the conduction level of each power transistor increases (conduction resistance decreases), absorbing more energy from the power supply 3 and transferring the absorbed energy to the load 4, thereby increasing the voltage output to the load 4. When the drive signal indicates a need to reduce the output voltage, the conduction level of each power transistor decreases (conduction resistance increases), absorbing less energy from the power supply 3, thereby reducing the voltage output to the load 4. Multiple power transistors are connected in parallel to share the current flowing from the power supply 3 to the load 4, reducing the equivalent on-resistance and improving current carrying capacity. Through this closed-loop regulation mechanism, the drive module 2 generates a drive signal in real time based on the feedback voltage from the load 4, and the regulation module 1 adjusts the conduction level of each power transistor according to the drive signal, achieving rapid regulation of the output voltage of the load 4.

[0042] To facilitate understanding, the following explanation uses examples, but does not impose specific limitations on this embodiment. For example, in an application scenario that powers a server CPU, assume that power supply 3 is a 1.35V power supply obtained by stepping down the 12V power bus of the server motherboard through a pre-stage DC-DC converter, and the rated operating voltage of load 4 (CPU) is 1.2V. Regulation module 1 includes eight N-channel MOSFETs connected in parallel as power transistors. The drain (input) of each MOSFET is connected to the 1.35V power supply 3, the source (output) of each MOSFET is connected to the CPU's power supply pin, and the gate (control) of each MOSFET is connected to the output of drive module 2. The input of drive module 2 is connected to the voltage sampling point of the CPU's power supply pin. When the CPU instantly switches from sleep mode to full load mode, the CPU's current demand jumps from 1A to 100A, and the voltage at load 4 drops from 1.2V. The drive module 2 detects that the feedback voltage has dropped to 1.15V, which differs from the internally set 1.2V reference voltage by 0.05V. Based on this difference, the drive module 2 generates a drive signal with increased amplitude (e.g., from 1V to 2.5V) and outputs this drive signal to the gates of the eight MOSFETs. Upon receiving the increased drive signal, the conduction level of each MOSFET increases (on-resistance decreases from 10mΩ to 2mΩ), absorbing more energy from the 1.35V power supply 3 and transferring this absorbed energy to the CPU, causing the CPU supply voltage to rise from 1.15V to near 1.2V. When the CPU instantly switches from full load to sleep mode, the CPU's current demand jumps from 100A to 1A. The voltage at the load terminal 4 overshoots due to the sudden decrease in current, rising to 1.25V. The drive module 2 detects that the feedback voltage has risen to 1.25V, which is higher than the 1.2V reference voltage. Based on this difference, the drive module 2 generates a drive signal with a reduced amplitude (e.g., from 1V to 0.3V) and outputs this drive signal to the gates of the eight MOSFETs. After receiving the reduced drive signal, the conduction level of each MOSFET decreases (the on-resistance increases from 10mΩ to 50mΩ), absorbing less energy from the 1.35V power supply 3, causing the CPU supply voltage to drop from 1.25V back to near 1.2V.

[0043] This embodiment includes a power regulation circuit within the electronic device. This circuit comprises a regulation module 1 and a drive module 2. The regulation module 1 includes multiple power transistors connected in parallel. The input terminals of the power transistors are connected to a power supply 3, the output terminals are connected to a load 4, and the control terminals are connected to the output terminals of the drive module 2. The input terminal of the drive module 2 is connected to the voltage feedback terminal of the load 4. The drive module 2 is used to detect the feedback voltage of the load 4 during power supply and generate a drive signal based on the feedback voltage. The regulation module 1 is used to receive the drive signal and adjust the conduction level of each power transistor. Compared to existing methods, this embodiment dynamically adjusts the number and timing of multiple parallel power transistors based on the feedback voltage using the drive module 2, thereby achieving refined segmented control of the output voltage of the load 4. This improves the power supply capacity under heavy loads and reduces conduction losses under light loads, balancing high efficiency and fast response.

[0044] Reference Figure 2 , Figure 2 This is a schematic diagram of the second embodiment of the power regulation circuit proposed in this application.

[0045] Based on the above embodiments, a second embodiment of this application is proposed. To achieve closed-loop control of the adjustment module 1, such as... Figure 2 As shown, in this embodiment, the driving module 2 includes: a reference unit 21 and a driving unit 22; The reference terminal of the drive unit 22 is connected to the reference unit 21, the input terminal of the drive unit 22 is connected to the load 4, and the output terminal of the drive unit 22 is connected to the control terminal of the power transistor. The reference unit 21 is used to transmit a reference voltage to the drive unit 22; The drive unit 22 is used to detect the feedback voltage of the load 4 during the power supply process of the load 4, and generate a drive signal based on the feedback voltage.

[0046] It should be noted that the aforementioned reference unit 21 may refer to a circuit module used to generate or provide a reference voltage, such as a voltage reference source composed of a reference voltage chip and an external resistor network, which can output a stable and accurate reference voltage signal.

[0047] The aforementioned driving unit 22 may refer to a circuit module used to compare the reference voltage and the feedback voltage and generate a driving signal, such as an amplifier circuit including a high-speed operational amplifier U2 and an external compensation network, which can calculate the difference between the input signals in real time and output the corresponding amplified signal.

[0048] In its implementation, reference unit 21 generates a stable and accurate reference voltage and transmits it to the reference terminal of drive unit 22. This reference voltage represents the rated operating voltage that load 4 expects to obtain and serves as the reference standard for voltage comparison by drive unit 22. During the process of supplying power to load 4, drive unit 22 continuously performs the following operations: drive unit 22 detects the feedback voltage at the load 4 terminal through its input terminal to obtain the actual voltage value currently received by load 4. Subsequently, drive unit 22 compares the detected feedback voltage with the reference voltage received from reference unit 21 and calculates the difference between the two. Based on the calculated difference, drive unit 22 generates a corresponding drive signal: when the feedback voltage is lower than the reference voltage, the amplitude of the drive signal output by drive unit 22 increases; when the feedback voltage is higher than the reference voltage, the amplitude of the drive signal output by drive unit 22 decreases. Drive unit 22 outputs the generated drive signal through its output terminal to the control terminals of each power transistor in adjustment module 1, providing each power transistor with a control basis for adjusting its own conduction level. With the above configuration, the reference unit 21 provides a stable voltage reference for the drive unit 22, and the drive unit 22 generates a control signal based on the difference between the actual voltage of the load 4 and the reference voltage, thereby realizing closed-loop control of the adjustment module 1.

[0049] For ease of understanding, the following explanation uses examples, but does not limit the specific implementation of this embodiment. For example, in an application scenario that powers an ASIC chip, assume that the rated operating voltage of load 4 (ASIC chip) is 0.9V. The reference unit 21 is specifically a circuit composed of a reference voltage chip and a resistor divider network. The reference unit 21 outputs a reference voltage of 0.9V and transmits this 0.9V reference voltage to the reference terminal of the drive unit 22. The drive unit 22 is specifically a circuit containing a high-speed operational amplifier U2. The reference terminal of the drive unit 22 is connected to the non-inverting input terminal of the operational amplifier U2 to receive the 0.9V reference voltage; the input terminal of the drive unit 22 is connected to the inverting input terminal of the operational amplifier U2, which is connected to the power supply pin of the ASIC chip to detect the feedback voltage at the load 4 terminal in real time; the output terminal of the drive unit 22 is connected to the output terminal of the operational amplifier U2, which is connected to the gate of the eight parallel MOSFETs in the regulation module 1. When the ASIC chip switches from a light load state to a heavy load state, the voltage at the load 4 terminal drops from 0.9V to 0.86V. The drive unit 22 detects a feedback voltage of 0.86V at its input terminal. The operational amplifier U2 inside the drive unit 22 compares the 0.86V feedback voltage with the 0.9V reference voltage received at the reference terminal, obtaining a difference of 0.04V. Based on this difference, the drive unit 22 generates a drive signal with increased amplitude (e.g., from 1V to 2V) and outputs this drive signal to the gates of the eight MOSFETs at its output terminal, instructing each MOSFET to increase its conduction level to replenish energy. When the ASIC chip switches from a heavy load state to a light load state, the voltage at load terminal 4 overshoots from 0.9V to 0.93V. The drive unit 22 detects a feedback voltage of 0.93V through its input terminal. The operational amplifier U2 inside the drive unit 22 compares the 0.93V feedback voltage with the 0.9V reference voltage and obtains a difference of 0.03V (the feedback voltage is higher than the reference voltage). The drive unit 22 generates a drive signal with a reduced amplitude (e.g., from 1V to 0.5V) based on this difference and outputs the drive signal to the gates of the eight MOSFETs through its output terminal, instructing each MOSFET to reduce its conduction level to lower the output voltage.

[0050] Furthermore, such as Figure 3 As shown, Figure 3 This is a circuit diagram of the reference unit 21 and the drive unit 22 in the second embodiment of the power regulation circuit proposed in this application. In this embodiment, the reference unit 21 includes: a reference chip U1 and first resistors R1 to fourth resistors R4; The output terminal of the reference chip U1 is connected to the driving unit 22. The first functional terminal of the reference chip U1 is connected to the first end of the first resistor R1. The second functional terminal of the reference chip U1 is connected to the second end of the second resistor R2. The third functional terminal of the reference chip U1 is connected to the first end of the third resistor R3. The fourth functional terminal of the reference chip U1 is connected to the second end of the fourth resistor R4. The second end of the first resistor R1 is connected to the second end of the third resistor R3. The second end of the first resistor R1 is also grounded. The first end of the second resistor R2 is connected to the second end of the third resistor R3 and the driving unit 22.

[0051] It should be noted that the aforementioned reference chip U1 can refer to an integrated circuit element used to generate a stable reference voltage, such as a parallel voltage reference chip U1 like TL431 or LM4040, which can output a stable reference voltage over a wide input voltage range.

[0052] The first resistor R1 to the fourth resistor R4 mentioned above can refer to the resistive elements used to set the output voltage of the reference chip U1. By adjusting the proportional relationship between the resistors, the reference voltage value output by the reference chip U1 can be precisely configured. The first functional terminal mentioned above can refer to the cathode terminal of the reference chip U1, the second functional terminal mentioned above can refer to the reference terminal of the reference chip U1, the third functional terminal mentioned above can refer to the anode terminal of the reference chip U1, and the fourth functional terminal mentioned above can refer to another functional terminal of the reference chip U1 (such as the feedback terminal or adjustment terminal of some reference chips U1). Different models of reference chips U1 may have different functional pin definitions. The ground mentioned above can refer to the reference zero potential point connected to the circuit, that is, the common reference point for voltage measurement and signal transmission.

[0053] In this implementation, the output terminal of the reference chip U1 is electrically connected to the drive unit 22 to provide a reference voltage to the drive unit 22. The first functional terminal of the reference chip U1 is connected to the first end of the first resistor R1. The second functional terminal of the reference chip U1 is connected to the second end of the second resistor R2. The third functional terminal of the reference chip U1 is connected to the first end of the third resistor R3. The fourth functional terminal of the reference chip U1 is connected to the second end of the fourth resistor R4. The second ends of the first resistor R1 and the third resistor R3 are interconnected, and the second end of the first resistor R1 is also connected to ground. The first end of the second resistor R2 is connected to both the second end of the third resistor R3 and the drive unit 22. Specifically, the first end of the second resistor R2 and the second end of the third resistor R3 are connected to the same point, which is also connected to the drive unit 22, for transmitting the reference voltage configured through the resistor network to the drive unit 22. Through the above-described resistor network configuration, resistors R1 to R4 together form a resistor voltage divider network. This network, in conjunction with the reference chip U1, proportionally transforms the reference voltage generated internally by the chip, thereby generating a precisely set reference voltage at the connection point between the first terminal of the second resistor R2 and the second terminal of the third resistor R3. The value of this reference voltage is determined by the proportional relationship between the resistance values ​​of resistors R1 and R4. This connection point is connected to the drive unit 22, thereby transmitting the precisely set reference voltage to the drive unit 22 for use as a reference standard for voltage comparison.

[0054] For ease of understanding, the following explanation uses examples, but does not limit the scope of this embodiment. For example, in an application scenario requiring a 0.9V reference voltage for load 4, the reference chip U1 is a TL431 adjustable parallel regulator. The TL431 chip has a cathode terminal as the first functional terminal, a reference terminal as the second functional terminal, and an anode terminal as the third functional terminal. The fourth functional terminal of the TL431 chip can refer to another pin (e.g., the NC terminal or a non-connected terminal in some packages). The specific resistance values ​​of the first resistor R1 to the fourth resistor R4 are configured as follows: the resistance of the first resistor R1 is 10kΩ, the resistance of the second resistor R2 is 5kΩ, the resistance of the third resistor R3 is 1kΩ, and the resistance of the fourth resistor R4 is 2kΩ. In terms of connection, the cathode (first functional terminal) of the TL431 chip is connected to the first terminal of the first resistor R1 (10kΩ), the reference terminal (second functional terminal) of the TL431 chip is connected to the second terminal of the second resistor R2 (5kΩ), and the anode (third functional terminal) of the TL431 chip is connected to the first terminal of the third resistor R3 (1kΩ). The second terminals of the first resistor R1 (10kΩ) and the third resistor R3 (1kΩ) are interconnected, and the second terminal of the first resistor R1 is connected to the ground terminal. The first terminal of the second resistor R2 (5kΩ) is connected to the second terminal of the third resistor R3 (1kΩ) and the drive unit 22. Through the above resistor network configuration, a reference voltage of 0.9V is generated at the connection point of the first terminal of the second resistor R2 and the second terminal of the third resistor R3. This 0.9V reference voltage is transmitted to the drive unit 22, which uses this 0.9V as a target reference value and compares it with the feedback voltage at the load terminal 4 to determine whether the output voltage needs adjustment. If the rated operating voltage of load 4 needs to be adjusted to 1.2V, the reference voltage at the connection point of the resistor network can be changed to 1.2V by adjusting the resistance ratio of the first resistor R1 to the fourth resistor R4 (for example, adjusting the first resistor R1 to 8kΩ and the second resistor R2 to 4kΩ).

[0055] Furthermore, continue as Figure 3 As shown, in this embodiment, the driving unit 22 includes: amplifier U2, transistor Q9, driving power supply A, fifth resistor R5, first capacitor C1 and second capacitor C2; The output terminal of amplifier U2 is connected to the base of transistor Q9. The ground terminal of amplifier U2 is grounded. The power supply terminal of amplifier U2 is connected to the drive power supply A and the collector of transistor Q9. The positive input terminal of amplifier U2 is connected to the reference unit 21. The negative terminal of amplifier U2 is connected to the first terminal of the fifth resistor R5 and the first terminal of the first capacitor C1. The second terminal of the fifth resistor R5 is connected to the first terminal of the second capacitor C2. The second terminal of the first capacitor C1 is connected to the second terminal of the second capacitor C2 and the load 4. The emitter of transistor Q9 is connected to the control terminal of the power transistor.

[0056] It should be noted that the aforementioned amplifier U2 may refer to a high-speed operational amplifier U2 used to compare the difference between input signals and amplify the output signal, such as an operational amplifier U2 chip with a gain-bandwidth product greater than or equal to 100MHz, which can respond to voltage changes at the nanosecond level in real time.

[0057] The aforementioned transistor Q9 can refer to a bipolar transistor used for current amplification, such as an NPN transistor Q9, whose base receives the output signal of amplifier U2, its collector receives the current provided by the drive power supply A, and its emitter outputs the amplified drive signal to the control terminal of the power transistor.

[0058] The aforementioned drive power supply A can refer to the power supply terminal that provides the operating voltage and drive current to the drive unit 22, such as a positive voltage source provided by an external power supply system.

[0059] The aforementioned fifth resistor R5 can refer to a resistor element used in conjunction with the first capacitor C1 and the second capacitor C2 to form a compensation network, used to adjust the frequency response characteristics of amplifier U2.

[0060] The first capacitor C1 mentioned above can refer to a capacitor element used to form a compensation network, which is connected in series with the fifth resistor R5 to form zero-point compensation.

[0061] The aforementioned second capacitor C2 may refer to another capacitor element used to form a compensation network, connected in parallel with the first capacitor C1 to form a high-frequency filtering or compensation path.

[0062] In its implementation, amplifier U2 receives a reference voltage from reference unit 21 through its positive input terminal and a feedback voltage from load 4 (passing through a compensation network consisting of the fifth resistor R5, the first capacitor C1, and the second capacitor C2) through its negative input terminal. Amplifier U2 compares the voltage difference between its positive and negative input terminals and generates an initial drive signal based on this difference. The initial drive signal generated by amplifier U2 is output to the base of transistor Q9 through its output terminal. Transistor Q9 receives the initial drive signal from the output terminal of amplifier U2, and this initial drive signal controls the conduction level of transistor Q9. The collector of transistor Q9 receives current from the drive power supply A. Based on the initial drive signal received at its base, transistor Q9 amplifies the current input to its collector and outputs the amplified drive signal from its emitter. The amplified drive signal has a stronger current driving capability and can drive the gates of multiple parallel power transistors (e.g., multiple parallel MOSFETs) in the regulation module 1. Transistor Q9 outputs the amplified drive signal through its emitter to the control terminals of each power transistor. Drive power supply A provides the operating voltage and drive current to amplifier U2 and transistor Q9. The fifth resistor R5, the first capacitor C1, and the second capacitor C2 together form a compensation network. This compensation network is connected between the negative input terminal of amplifier U2 and the feedback voltage acquisition point, used to adjust the frequency response characteristics of amplifier U2, suppress high-frequency oscillations, and ensure the loop stability of drive unit 22 under high-speed operating conditions.

[0063] For ease of understanding, the following explanation uses examples, but does not impose specific limitations on this embodiment. For example, in a power regulation circuit application scenario for powering a CPU, amplifier U2 is selected as a high-speed operational amplifier U2 with a gain-bandwidth product of 150MHz (e.g., OPA855). Transistor Q9 is selected as an NPN small-signal transistor Q9 (e.g., 2N3904). The drive power supply A provides a 5V DC voltage. In terms of connection, the output terminal (pin 1) of amplifier U2 is connected to the base of transistor Q9. The ground terminal (pin 2) of amplifier U2 is connected to the ground plane of the circuit board. The power supply terminal (pin 3) of amplifier U2 is connected to the 5V drive power supply A, and this power supply terminal is also connected to the collector of transistor Q9, so that the collector of transistor Q9 also receives a 5V voltage. The positive input terminal (pin 4) of amplifier U2 is connected to the output terminal of reference unit 21, receiving a 0.9V reference voltage from reference unit 21. The negative input terminal (pin 5) of amplifier U2 is connected to the first terminal of the fifth resistor R5 and the first terminal of the first capacitor C1. The resistance of the fifth resistor R5 is 100Ω, and the second terminal of the fifth resistor R5 is connected to the first terminal of the second capacitor C2. The capacitance of the first capacitor C1 is 10pF, and the capacitance of the second capacitor C2 is 100pF. The second terminals of the first capacitor C1 and the second terminals of the second capacitor C2 are interconnected and simultaneously connected to the voltage sampling point of load 4. The emitter of transistor Q9 is connected to the common gate of the eight parallel MOSFETs in regulation module 1. When the voltage at load 4 drops from 0.9V to 0.86V, amplifier U2 detects a feedback voltage of 0.86V through its negative input terminal. This feedback voltage is compared with the 0.9V reference voltage at the positive input terminal of amplifier U2 to obtain a difference of 0.04V. Amplifier U2 outputs an initial drive signal with increased amplitude (e.g., from 1V to 2V) based on this difference. The initial drive signal is transmitted to the base of transistor Q9, increasing the conduction level of Q9. This amplifies the 5V current at the collector and outputs an amplified drive signal of approximately 2.5V from the emitter of Q9 to the common gate of the eight parallel MOSFETs, driving each MOSFET to increase its conduction level to replenish energy. The compensation network consisting of the fifth resistor R5, the first capacitor C1, and the second capacitor C2 suppresses any high-frequency oscillations that may occur in amplifier U2 during this process, ensuring a stable output of the drive signal.

[0064] Reference Figure 4 , Figure 4 This is a schematic diagram of the first structure of the third embodiment of the power regulation circuit proposed in this application.

[0065] Based on the above embodiments, a third embodiment of this application is proposed. To ensure that each power transistor can respond stably and synchronously to the drive signal, such as... Figure 4 As shown, in this embodiment, the circuit further includes: an execution module 5; The input terminal of the execution module 5 is connected to the drive module 2, and the output terminal of the execution module 5 is connected to the input terminal of the power transistor. The execution module 5 is used to receive the drive signal output by the drive module 2 and adjust the conduction degree of each power transistor according to the drive signal.

[0066] It should be noted that the aforementioned execution module 5 may refer to an interface circuit used to transmit drive signals to the control terminals of each power transistor, such as a drive resistor network composed of multiple parallel resistors. One end of each resistor receives the drive signal, and the other end is connected to the control terminal of the corresponding power transistor, which is used to distribute the drive signal to each power transistor and play a role in current limiting and damping.

[0067] In its implementation, execution module 5 receives the drive signal output by drive module 2 through its input terminal. The drive signal is an analog voltage signal generated by drive module 2 based on the difference between the reference voltage and the feedback voltage. The amplitude of this drive signal reflects the degree of deviation between the load 4 voltage and the target voltage. Execution module 5 processes the received drive signal and outputs the processed drive signal through its output terminal to the control terminals of each power transistor. Execution module 5 plays a role in signal distribution and conditioning during drive signal processing. Specifically, execution module 5 distributes the single drive signal output by drive module 2 to multiple parallel power transistors, ensuring that the control terminal of each power transistor can receive the drive signal. Simultaneously, execution module 5 performs current limiting and damping processing on the drive signal, limiting the current flowing into the control terminal of each power transistor and suppressing potential high-frequency oscillations at the control terminals. Each power transistor receives the processed drive signal through its respective control terminal and adjusts its conduction level according to the received drive signal. When the drive signal amplitude is large, the conduction degree of each power transistor increases, absorbing more energy from the power supply 3 and transferring it to the load 4; when the drive signal amplitude is small, the conduction degree of each power transistor decreases, absorbing less energy from the power supply 3 and transferring it to the load 4. Through the above configuration, the execution module 5 acts as the interface circuit between the drive module 2 and the power transistors in the adjustment module 1, distributing the drive signal output by the drive module 2 to each power transistor, and playing a role in current limiting and damping, ensuring that each power transistor can respond to the drive signal stably and synchronously.

[0068] For ease of understanding, the following explanation uses examples, but does not limit the scope of this embodiment. For instance, in a power regulation circuit application scenario for a GPU, assume that regulation module 1 includes eight N-channel MOSFETs connected in parallel as power transistors, and execution module 5 includes eight 10Ω resistors. The input terminal of execution module 5 (the common connection point of the first ends of the eight resistors) is connected to the output terminal of drive module 2 (e.g., the emitter of transistor Q9 in drive unit 22). The output terminal of execution module 5 includes eight output nodes, each corresponding to the second end of a resistor, which is connected to the gate of the corresponding MOSFET among the eight MOSFETs. When drive module 2 outputs a drive signal with an amplitude of 2.5V, this drive signal enters execution module 5 through the input terminal of execution module 5. The eight 10Ω resistors in execution module 5 simultaneously distribute the 2.5V drive signal to the eight output nodes, each output node receiving a 2.5V drive signal, which is then transmitted to the gate of the corresponding MOSFET. Each 10Ω resistor limits the charging current flowing into the gate of its corresponding MOSFET (e.g., to the tens of milliamps), preventing excessive gate current from damaging the MOSFET or driver module 2. Simultaneously, each 10Ω resistor, together with the gate input capacitance of its corresponding MOSFET, forms an RC network to absorb high-frequency oscillation energy, ensuring a smooth rise in the gate voltage of each MOSFET and preventing voltage ringing. When one of the eight MOSFETs has a smaller gate input capacitance due to manufacturing variations, the independent 10Ω resistor corresponding to that MOSFET can still independently limit the charging current in that path, ensuring that the switching speed of that MOSFET remains consistent with the other MOSFETs, thereby achieving synchronous turn-on and turn-off of all eight MOSFETs.

[0069] Furthermore, continue as Figure 4 As shown, in this embodiment, the execution module 5 includes: a plurality of gate resistors, the number of which is the same as the number of power transistors; The gate resistors are connected in parallel. The first end of the gate resistor is connected to the driving module 2, and the second end of the gate resistor is connected to the control terminal of the power transistor.

[0070] It should be noted that the aforementioned gate resistor can refer to a passive electronic component used to limit current and distribute voltage, such as a surface-mount resistor or a thin-film resistor. In the execution module 5 of this embodiment, the gate resistor is used as a gate resistor, with each gate resistor corresponding to a power transistor. The first end of the aforementioned gate resistor can refer to one pin of the gate resistor, used to receive the drive signal from the drive module 2; the second end of the aforementioned gate resistor can refer to the other pin of the resistor, used to connect to the control terminal of the corresponding power transistor. The aforementioned parallel connection can mean that one end of multiple gate resistors is connected to the same node (the output terminal of the drive module 2), and the other ends of multiple gate resistors are respectively connected to the control terminal of their respective power transistors, forming multiple independent signal paths, rather than a series connection between the gate resistors.

[0071] It should be emphasized that the gate resistors mentioned above all have the same function, therefore in Figure 4 The example uses eight gate resistors (from the first gate resistor R6 to the second gate resistor) for explanation, but does not impose specific limitations on this embodiment.

[0072] In the specific implementation, the drive signal output by drive module 2 is simultaneously transmitted to the first terminal of each gate resistor. After passing through the resistor, the drive signal is transmitted to the control terminal of each power transistor. Each gate resistor plays a role in current limiting and damping in its corresponding signal path. The drive signal output by drive module 2 reaches the first terminal (common connection point) of all gate resistors. After passing through each resistor, the drive signal is output from the second terminal of the gate resistor to the control terminal of the corresponding power transistor. Each gate resistor limits the drive signal current flowing through it, preventing excessive control terminal charging current from damaging the power transistor or drive module 2. At the same time, each gate resistor and the corresponding power transistor's control terminal input capacitor form an RC network. This RC network can absorb high-frequency oscillation energy, suppress the ringing phenomenon of the power transistor control terminal voltage, and ensure that the control terminal voltage of each power transistor changes smoothly. Since each power transistor has an independent control terminal resistor, the drive paths between each power transistor are independent. Even if there are slight differences in the manufacturing parameters of each power transistor, the independent control terminal gate resistor can balance the switching characteristics of each power transistor, enabling multiple power transistors connected in parallel to turn on and off synchronously, avoiding uneven current or local overheating caused by asynchronous switching. With the above configuration, several resistors form a parallel resistor network, which distributes the single drive signal output by the drive module 2 to the control terminals of multiple power transistors, while providing independent current limiting and damping functions for each power transistor.

[0073] For ease of understanding, the following explanation uses examples, but does not limit the scope of this embodiment. For example, in a CPU power supply application scenario, assume that the regulation module 1 includes eight N-channel MOSFETs connected in parallel as power transistors, and the execution module 5 correspondingly includes eight gate resistors. Each gate resistor has a resistance of 10Ω and is packaged as a 0402 surface mount resistor. The first terminals of the eight gate resistors are connected to the output terminal of the drive module 2 (e.g., the emitter of transistor Q9 in the drive unit 22). The drive signal output by the drive module 2 (e.g., a voltage signal with an amplitude of 2.5V) simultaneously reaches the first terminals of the eight gate resistors. The second terminal of the first gate resistor is connected to the gate of the first MOSFET, the second terminal of the second gate resistor is connected to the gate of the second MOSFET, and so on, with the second terminal of the eighth gate resistor connected to the gate of the eighth MOSFET. When the drive module 2 outputs a 2.5V drive signal, the signal is transmitted to the gates of the eight MOSFETs through the eight 10Ω resistors respectively. Each 10Ω gate resistor limits the gate charging current flowing through it to a reasonable range (e.g., the gate charging current of each MOSFET is limited to the tens of milliamps), preventing overload of drive module 2. Simultaneously, each 10Ω gate resistor, together with the corresponding MOSFET's gate input capacitance (e.g., 1000pF), forms a charging loop with an RC time constant of approximately 10ns. This loop absorbs the high-frequency oscillation energy in the gate drive circuit, ensuring a smooth gate voltage rise and preventing voltage ringing. When one of the eight MOSFETs has a smaller gate input capacitance due to manufacturing variations, the independent 10Ω gate resistor corresponding to that MOSFET can still independently limit the charging current of that path, ensuring that the switching speed of that MOSFET remains consistent with the other MOSFETs, thereby achieving synchronous turn-on and turn-off of all eight MOSFETs. In the PCB layout, the eight 10Ω gate resistors are placed close to their respective MOSFET gates to shorten the physical length of the gate drive circuit, further reducing parasitic inductance and improving switching speed and reliability.

[0074] Furthermore, in order to act as an energy absorption device when there is excess energy at load 4, and to prevent excess energy from causing voltage overshoot, such as Figure 5 As shown, Figure 5 This is a second structural schematic diagram of a third embodiment of the power regulation circuit proposed in this application. In this embodiment, the circuit further includes: an energy storage module 6; The energy storage module 6 is connected between the power supply 3 and the regulating module 1; The energy storage unit 61 is used to store electrical energy and provide power supply voltage to the regulating module 1; The energy storage unit 61 is also used to absorb and store energy from the regulation module 1.

[0075] It should be noted that the aforementioned energy storage module 6 can refer to an energy buffer unit for storing and releasing electrical energy, such as a circuit structure composed of a DC-DC converter and an energy storage capacitor, which can obtain and store electrical energy from the power supply 3, release energy to the regulating module 1 when needed, or absorb and store excess energy from the regulating module 1 when there is excess energy.

[0076] In its implementation, the energy storage module 6 receives input voltage from the power supply 3. The energy storage module 6 stores the received electrical energy in the form of an electric field, forming a stable supply voltage. The energy storage module 6 converts the stored electrical energy into the supply voltage and provides this supply voltage to the regulating module 1, which then uses it as an energy source. The energy storage module 6 also has a reverse energy absorption function. When the regulating module 1 absorbs excess energy from the load 4 and feeds this energy back to the energy storage module 6 (for example, when the load 4 switches from a heavy load state to a light load state, the parasitic reverse diode of the power transistor conducts, forming a discharge path from the load 4 to the energy storage module 6), the energy storage module 6 receives the energy fed back from the regulating module 1, absorbs and stores this fed-back energy. Through this function, the energy storage module 6 acts as an energy absorption device when the load 4 has excess energy, preventing voltage overshoot caused by excess energy. With the above configuration, the energy storage module 6 is responsible for storing electrical energy and providing a stable supply voltage to the regulating module 1, while also possessing bidirectional energy storage capabilities for absorbing fed-back energy, thus playing a role in energy buffering and voltage stabilization.

[0077] To facilitate understanding, the following explanation uses examples, but does not impose specific limitations on this embodiment. For example, in an application scenario powering a server CPU, assume that power supply 3 is a 1.35V power supply obtained by stepping down the 12V power bus of the server motherboard through a pre-stage DC-DC converter, and the rated operating voltage of load 4 (CPU) is 1.2V. Energy storage module 6 specifically consists of six 330μF ceramic capacitors connected in parallel, with a total capacitance of 1980μF. These six capacitors are connected to power supply 3 (1.35V), receiving the 1.35V voltage. The six capacitors are charged to 1.35V, storing electrical energy. Simultaneously, the six capacitors are connected to the drains of eight parallel MOSFETs in regulation module 1, providing a 1.35V supply voltage to regulation module 1. When the CPU switches from a light load state to a heavy load state, the conduction level of the eight MOSFETs in regulation module 1 increases, absorbing energy from energy storage module 6 and transferring the energy to load 4. The six capacitors in energy storage module 6 release stored electrical energy to provide a transient large current (e.g., 100A) to regulation module 1. During the release process, the capacitor terminal voltage briefly drops from 1.35V to 1.30V, but remains within an acceptable range. When the CPU switches from a heavy load state to a light load state, the eight MOSFETs in regulation module 1 turn off, and the parasitic reverse diodes of the MOSFETs turn on, absorbing excess energy from load 4 and releasing this energy back to energy storage module 6. The six capacitors in energy storage module 6 receive the energy fed back from regulation module 1, and the capacitor terminal voltage briefly rises from 1.35V to 1.38V, storing the excess energy. Subsequently, the front-end DC-DC converter detects the increase in capacitor terminal voltage and automatically reduces the output power, allowing the capacitor terminal voltage to gradually recover to the steady-state value of 1.35V. Through the above configuration, the six parallel capacitors in energy storage module 6 can both quickly release stored electrical energy when load 4 needs energy and absorb and store excess energy when load 4 has excess energy, playing a role in energy buffering and voltage regulation.

[0078] Furthermore, continue as Figure 5 As shown, in this embodiment, the energy storage module 6 includes: a DC-DC converter 62 and an energy storage unit 61; The energy storage unit 61 is connected to the DC-DC converter 62 and the regulating module 1 respectively, and the DC-DC converter 62 is connected to the power supply 3; The DC-DC converter 62 is used to receive the input voltage and convert the input voltage into a charging voltage to store electrical energy in the energy storage unit 61. The energy storage unit 61 is used to store electrical energy and provide power supply voltage to the regulating module 1; The energy storage unit 61 is also used to absorb and store energy from the regulation module 1.

[0079] It should be noted that the DC-DC conversion unit 62 mentioned above can refer to a power conversion circuit used to convert the input voltage to different voltage levels, such as a buck DC-DC converter, which can convert a higher input voltage (such as 12V) to a lower charging voltage (such as 1.35V).

[0080] The aforementioned energy storage unit 61 may refer to a component or circuit used to store electrical energy, such as an electrolytic capacitor, a ceramic capacitor, or a supercapacitor, which can store charge in the form of an electric field and release the stored electrical energy when needed, as well as absorb and store excess energy when there is an excess of external energy.

[0081] In its implementation, the DC-DC converter 62 receives input voltage from the power supply 3. Internally, the DC-DC converter 62 uses power switches, inductors, and capacitors to convert the received input voltage into the required charging voltage. The converted charging voltage is typically higher than the rated voltage of the load 4. For example, if the rated voltage of the load 4 is 1.2V, the charging voltage can be set to 1.3V or 1.35V to allow for voltage differential adjustment by the regulating module 1. The DC-DC converter 62 outputs the converted charging voltage to the energy storage unit 61. The energy storage unit 61 receives the charging voltage output from the DC-DC converter 62 and stores electrical energy within itself. The energy storage unit 61 stores the electrical energy in the form of an electric field, forming a stable supply voltage. The energy storage unit 61 converts the stored electrical energy back into the supply voltage and provides this supply voltage to the regulating module 1 as its energy source. The energy storage unit 61 also has a reverse energy absorption function. When the regulating module 1 absorbs excess energy from the load 4 and releases it back to the energy storage module 6, the energy storage unit 61 receives the energy fed back from the regulating module 1, absorbs and stores this fed-back energy. Through this function, the energy storage unit 61 acts as an energy absorption device when the load 4 has excess energy, preventing voltage overshoot caused by excess energy. With the above configuration, the DC-DC converter 62 is responsible for converting the input voltage into a suitable charging voltage for storage, while the energy storage unit 61 is responsible for storing electrical energy and providing a stable supply voltage to the regulating module 1, while also possessing bidirectional energy storage capabilities for absorbing fed-back energy.

[0082] For ease of understanding, the following explanation uses examples, but does not limit the specific implementation of this embodiment. For example, in an application scenario that powers a server CPU, assume that power supply 3 is the 12V power bus of the server motherboard, and the rated operating voltage of load 4 (CPU) is 1.2V. The DC-DC converter unit 62 is specifically a four-phase step-down DC-DC converter, whose input is connected to the 12V power bus. The DC-DC converter converts the 12V input voltage into a charging voltage of 1.35V, which is 0.15V higher than the rated voltage of load 4 (1.2V), providing sufficient voltage difference for regulation module 1. The DC-DC converter outputs the 1.35V charging voltage to the energy storage unit 61. The energy storage unit 61 is specifically composed of six 330μF ceramic capacitors connected in parallel, with a total capacitance of 1980μF. These six capacitors are connected to the output of the DC-DC converter to receive the 1.35V charging voltage. The six capacitors are charged to 1.35V, storing electrical energy. Six capacitors are simultaneously connected to the drains of eight parallel MOSFETs in regulation module 1, providing a 1.35V supply voltage to regulation module 1. When the CPU switches from a light-load state to a heavy-load state, regulation module 1 absorbs energy from energy storage unit 61 and transfers the energy to load 4. The six capacitors in energy storage unit 61 release the stored electrical energy, providing a transient large current (e.g., 100A) to regulation module 1. During the release process, the capacitor terminal voltage briefly drops from 1.35V to 1.30V, but remains within an acceptable range. When the CPU switches from a heavy-load state to a light-load state, regulation module 1 absorbs excess energy from load 4 and releases this energy back to energy storage unit 61. The six capacitors in energy storage unit 61 receive the energy fed back from regulation module 1, and the capacitor terminal voltage briefly rises from 1.35V to 1.38V, storing the excess energy. Subsequently, DC-DC converter unit 62 detects the increase in capacitor terminal voltage and automatically reduces the output power, allowing the capacitor terminal voltage to gradually recover to the steady-state value of 1.35V. With the above configuration, the six parallel capacitors in the energy storage unit 61 can quickly release the stored electrical energy when the load 4 needs energy, and can also absorb and store excess energy when the load 4 has excess energy, thus playing the role of energy buffering and voltage stabilization.

[0083] To achieve the above objectives, this application also proposes a power conditioning system, which includes the power conditioning circuit described above.

[0084] It should be noted that the specific implementation of the power regulation system provided in this embodiment can refer to the above embodiments, and this embodiment will not elaborate on it further. Therefore, the effects achieved by the power regulation system in this embodiment can also refer to the above embodiments, and this embodiment will not elaborate on them further.

[0085] To achieve the above objectives, this application also proposes an electronic device, which includes the power regulation circuit described above.

[0086] It should be noted that the specific implementation of the electronic device provided in this embodiment can refer to the above embodiments, and this embodiment will not elaborate on them. Therefore, the effects achieved by the electronic device in this embodiment can also refer to the above embodiments, and this embodiment will not elaborate on them either.

[0087] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A power supply regulation circuit, characterized in that, The circuit includes: an adjustment module and a drive module; The adjustment module includes multiple power transistors connected in parallel; The input terminal of the power transistor is connected to the power supply, the output terminal of the power transistor is connected to the load, and the control terminal of the power transistor is connected to the output terminal of the drive module. The input terminal of the drive module is connected to the voltage feedback terminal of the load; The drive module is used to detect the feedback voltage of the load during the power supply process of the load, and generate a drive signal based on the feedback voltage; The adjustment module is used to receive the drive signal and adjust the conduction level of each of the power transistors.

2. The circuit as described in claim 1, characterized in that, The driving module includes: a reference unit and a driving unit; The reference terminal of the drive unit is connected to the reference unit, the input terminal of the drive unit is connected to the load, and the output terminal of the drive unit is connected to the control terminal of the power transistor. The reference unit is used to transmit a reference voltage to the drive unit; The drive unit is used to detect the feedback voltage of the load during the power supply process and generate a drive signal based on the feedback voltage.

3. The circuit as described in claim 2, characterized in that, The reference unit includes: a reference chip and a first resistor to a fourth resistor; The output terminal of the reference chip is connected to the driving unit. The first functional terminal of the reference chip is connected to the first end of the first resistor. The second functional terminal of the reference chip is connected to the second end of the second resistor. The third functional terminal of the reference chip is connected to the first end of the third resistor. The fourth functional terminal of the reference chip is connected to the second end of the fourth resistor. The second end of the first resistor is connected to the second end of the third resistor. The second end of the first resistor is also grounded. The first end of the second resistor is connected to the second end of the third resistor and the driving unit, respectively.

4. The circuit as described in claim 2, characterized in that, The driving unit includes: an amplifier, a transistor, a driving power supply, a fifth resistor, a first capacitor, and a second capacitor; The output terminal of the amplifier is connected to the base of the transistor, the ground terminal of the amplifier is grounded, the power supply terminal of the amplifier is connected to the driving power supply and the collector of the transistor, the positive input terminal of the amplifier is connected to the reference unit, the negative terminal of the amplifier is connected to the first terminal of the fifth resistor and the first terminal of the first capacitor, the second terminal of the fifth resistor is connected to the first terminal of the second capacitor, the second terminal of the first capacitor is connected to the second terminal of the second capacitor and the load, and the emitter of the transistor is connected to the control terminal of the power transistor.

5. The circuit as described in claim 1, characterized in that, The circuit further includes: an execution module; The input terminal of the execution module is connected to the drive module, and the output terminal of the execution module is connected to the input terminal of the power transistor. The execution module is used to receive the drive signal output by the drive module and adjust the conduction degree of each power transistor according to the drive signal.

6. The circuit as described in claim 3, characterized in that, The execution module includes: a plurality of gate resistors, the number of which is the same as the number of power transistors; The gate resistors are connected in parallel. The first end of the gate resistor is connected to the driving module, and the second end of the gate resistor is connected to the control terminal of the power transistor.

7. The circuit as described in claim 1, characterized in that, The circuit also includes: an energy storage module; The energy storage module is connected between the power supply and the regulating module; The energy storage unit is used to store electrical energy and provide power supply voltage to the regulation module; The energy storage unit is also used to absorb and store energy from the regulation module.

8. The circuit as described in claim 1, characterized in that, The energy storage module includes: a DC-DC converter and an energy storage unit; The energy storage unit is connected to the DC-DC converter and the regulating module respectively, and the DC-DC converter is connected to the power supply. The DC-DC converter unit is used to receive the input voltage and convert the input voltage into a charging voltage to store electrical energy in the energy storage unit; The energy storage unit is used to store electrical energy and provide power supply voltage to the regulation module; The energy storage unit is also used to absorb and store energy from the regulation module.

9. A power regulation system, characterized in that, The power conditioning system includes the power conditioning circuit according to any one of claims 1 to 8.

10. An electronic device, characterized in that, The electronic device includes the power regulation circuit according to any one of claims 1 to 8.

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