Satellite high-voltage bus power distribution circuit

Abstract

This application relates to a satellite high-voltage busbar power distribution circuit, comprising: a power input terminal, a power output terminal, a control sub-circuit, and a magnetic latching relay. The control sub-circuit includes an NMOS transistor and an isolation power supply. The first terminal of the NMOS transistor is connected to the positive terminal of the power input terminal, and the second terminal of the NMOS transistor is connected to the positive terminal of the power output terminal. The contacts of the magnetic latching relay are connected in series with the isolation power supply between the control terminal and the second terminal of the NMOS transistor. The contacts of the magnetic latching relay are configured to: close in response to a pulse-type turn-on command, applying the output voltage of the isolation power supply to the control terminal of the NMOS transistor; and open in response to a pulse-type turn-off command, disconnecting the isolation power supply from the control terminal of the NMOS transistor. This application simplifies the circuit structure and achieves high- and low-voltage electrical isolation by using a magnetic latching relay and an isolation power supply to drive the high-side NMOS transistor. It is adaptable to pulse-type control commands of satellite electronic systems and suitable for power distribution scenarios of satellite high-voltage buses above 200V.

Description

Technical Field

[0001] This application relates to the field of satellite power supply and distribution technology, and in particular to a satellite high-voltage busbar power distribution circuit. Background Technology

[0002] With the rapid development of new types of spacecraft such as high-capacity communication satellites, radar imaging satellites, and computing satellites, the demand for power supply from satellite platforms continues to increase significantly. Traditional kilowatt-level power supply capabilities are no longer sufficient to meet the ever-growing payload requirements. To reduce the weight of the power supply system and lower transmission losses, increasing the bus voltage of the satellite power system from the traditional 28V, 42V, and 100V levels to high-voltage levels of 200V and above has become an important development trend in this field.

[0003] Satellite power systems typically consist of solar arrays, battery banks, and a power controller. The power controller is responsible for the core functions of regulating the power of the solar arrays, managing the charging and discharging of the battery banks, and uniformly distributing power. Its internal power distribution circuitry is responsible for distributing a stable bus voltage to all payloads and platform equipment throughout the satellite. With the increasing bus voltage level, higher requirements are placed on the voltage withstand capability, drive reliability, and anti-interference performance of the power controller's internal power distribution circuitry. Summary of the Invention

[0004] To address at least some of the aforementioned technical problems, this application provides a satellite high-voltage bus power distribution circuit that enables high-side NMOS transistor drive with a simple structure and high reliability in high-voltage bus scenarios above 200V, adapts to conventional pulse-type control commands of satellite electronic systems, and simultaneously achieves high- and low-voltage electrical isolation.

[0005] This application provides a satellite high-voltage bus power distribution circuit, including: a power input terminal, a power output terminal, a control sub-circuit, and a magnetic latching relay.

[0006] The power input terminal is used to connect to the satellite high-voltage bus, and the power output terminal is used to connect to the electrical load.

[0007] The control sub-circuit includes an NMOS transistor and an isolation power supply. The first terminal of the NMOS transistor is connected to the positive terminal of the power supply input, and the second terminal of the NMOS transistor is connected to the positive terminal of the power supply output.

[0008] The contacts of the magnetic latching relay are connected in series with the isolation power supply between the control electrode and the second electrode of the NMOS transistor.

[0009] The contacts of the magnetic latching relay are configured as follows: In response to a pulsed turn-on command closing, the output voltage of the isolation power supply is applied to the control electrode of the NMOS transistor to drive it to turn on; and, In response to a pulse-type turn-off command, the isolation power supply is disconnected from the control electrode of the NMOS transistor, thereby turning off the NMOS transistor.

[0010] In some embodiments, the magnetic latching relay includes a first coil and a second coil. The first coil is connected to a first control command input terminal. The second coil is connected to a second control command input terminal. The first control command input terminal is used to receive a pulse-type turn-on command, and the second control command input terminal is used to receive a pulse-type turn-off command.

[0011] In some embodiments, the satellite high-voltage busbar power distribution circuit further includes: a first coil protection sub-circuit and a second coil protection sub-circuit. The first coil protection sub-circuit is connected in parallel with the first coil and is used to provide a unidirectional current discharge path when the first coil is de-energized. The second coil protection sub-circuit is connected in parallel with the second coil and is used to provide a unidirectional current discharge path when the second coil is de-energized.

[0012] In some embodiments, the first coil protection sub-circuit includes a first diode and a second diode, wherein the first diode and the second diode are connected in series and then connected in parallel with the first coil.

[0013] In some embodiments, the second coil protection sub-circuit includes a third diode and a fourth diode, wherein the third diode and the fourth diode are connected in series and then connected in parallel with the second coil.

[0014] In some embodiments, the satellite high-voltage bus power distribution circuit further includes: a first resistor and a second resistor. The first resistor is connected in series with the first coil, and the second resistor is connected in series with the second coil.

[0015] In some embodiments, the satellite high-voltage bus power distribution circuit further includes a Zener diode connected in parallel with the isolation power supply to clamp the output voltage of the isolation power supply.

[0016] In some embodiments, the satellite high-voltage bus power distribution circuit further includes a current-limiting resistor, which is connected in series with the control electrode of the NMOS transistor.

[0017] In some embodiments, the satellite high-voltage bus distribution circuit further includes a balancing resistor connected in parallel between the control electrode and the second electrode of the NMOS transistor.

[0018] In some embodiments, the satellite high-voltage bus power distribution circuit includes at least two control sub-circuits, which are connected in parallel.

[0019] In some embodiments, the satellite high-voltage bus power distribution circuit further includes: a first capacitor, and / or at least one power diode. The first capacitor is connected in parallel between the positive and negative terminals of the power output terminal. The cathode of the power diode is connected to the positive terminal of the power output terminal, and the anode of the power diode is connected to the negative terminal of the power output terminal.

[0020] In some embodiments, the voltage of the satellite high-voltage bus is greater than or equal to 200V, and the output voltage of the isolation power supply is 10V to 18V.

[0021] The satellite high-voltage bus power distribution circuit provided in this application embodiment drives the high-side NMOS transistor through a magnetic latching relay and an isolation power supply, so as to achieve a simple and reliable power distribution control in high-voltage bus scenarios above 200V, adapt to the conventional pulse-type control commands of satellite electronic systems, and at the same time achieve high and low voltage electrical isolation. Attached Figure Description

[0022] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0023] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A schematic diagram of the circuit structure of the satellite high-voltage bus power distribution circuit provided in the embodiments of this application; Figure 2 Power-on waveform diagram of the satellite high-voltage bus power distribution circuit provided in the embodiments of this application; Figure 3 The power-down waveform diagram of the satellite high-voltage bus power distribution circuit provided in the embodiments of this application; Figure 4 The common-mode voltage waveform of the satellite high-voltage bus distribution circuit provided in the embodiments of this application is shown. Detailed Implementation

[0025] To better understand the above-mentioned objectives, features, and advantages of this application, the solution of this application will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0026] Many specific details are set forth in the following description in order to provide a full understanding of this application, but this application may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some embodiments of this application, and not all embodiments.

[0027] In existing technologies, satellite high-voltage bus power distribution circuits mostly use power-type magnetic latching relays directly as power distribution switches, or a scheme using PMOS transistors in conjunction with signal-type magnetic latching relays. The former has shortcomings such as poor breaking capacity, difficulty in arc extinguishing, and large size and weight in high-voltage scenarios above 200V; the latter is unsuitable as a high-voltage power distribution switch because the performance of PMOS transistors is limited under high voltage. When using NMOS transistors to replace PMOS transistors, existing high-side NMOS driving schemes mostly rely on dedicated gate drivers, but few of these drivers meet aerospace-grade radiation resistance requirements, and they require separate auxiliary power supplies, resulting in complex circuit structures and poor compatibility with the conventional pulse-type command control methods of satellite electronic systems.

[0028] Based on this, this application provides a satellite high-voltage bus power distribution circuit, which will be described below with reference to specific embodiments.

[0029] like Figure 1 As shown, the satellite high-voltage bus power distribution circuit includes a power input terminal and a power output terminal. The power input terminal is used to connect to the satellite high-voltage bus, and the power output terminal is used to connect to the electrical load.

[0030] like Figure 1 As shown, the power input terminal includes a positive terminal and a negative terminal, and the power output terminal includes a positive terminal and a negative terminal. Figure 1 Vin+ is the positive terminal of the power input. Figure 1 Vin- is the negative terminal of the power input. Figure 1 Vout+ is the positive terminal of the power output. Figure 1 Vout- is the negative terminal of the power supply output.

[0031] In some embodiments, such as Figure 1 As shown, the satellite high-voltage bus power distribution circuit includes a control sub-circuit, which is connected between the power input terminal and the power output terminal. It is used to transmit the power of the satellite high-voltage bus to the electrical load when a pulse-type turn-on command is received, and to cut off the power transmission when a pulse-type turn-off command is received.

[0032] One or more control sub-circuits can be set. When the satellite high-voltage bus distribution circuit includes two or more control sub-circuits, the control sub-circuits are connected in parallel.

[0033] like Figure 1 As shown, each control sub-circuit is connected in parallel between the positive terminal Vin+ of the power input and the positive terminal Vout+ of the power output, jointly undertaking the power transmission task from the high-voltage bus to the load.

[0034] It should be noted that setting up multiple (two or more) control sub-circuits and connecting them in parallel is a redundancy design adopted in this application. In this way, when one control sub-circuit fails, the remaining control sub-circuits can continue to undertake the power transmission task and maintain the normal function of the satellite high-voltage bus power distribution circuit.

[0035] Specifically, each control sub-circuit includes an NMOS transistor (e.g. Figure 1 Q1, Q2 shown) and isolated power supply (e.g. Figure 1 (V1 and V2 are shown). Figure 1 Taking the illustrated embodiment as an example, the satellite high-voltage bus power distribution circuit includes two parallel control sub-circuits, which are referred to as the first control sub-circuit and the second control sub-circuit, respectively.

[0036] In some embodiments, such as Figure 1 As shown, the voltage of the satellite's high-voltage bus is greater than or equal to 200V, and the isolated power supply (e.g.) Figure 1 The output voltages of V1 and V2 shown are 10V to 18V.

[0037] The voltage of the satellite's high-voltage bus is greater than or equal to 200V (e.g., 270V), corresponding to the high-voltage bus level used in current high-power communication satellites, radar satellites, and other new spacecraft. The output voltages of the isolation power supplies V1 and V2 are 10V to 18V (e.g., 13V). This voltage range provides sufficient gate-source drive voltage for the NMOS transistor, enabling it to fully conduct and operate in a low on-resistance state, while not exceeding the safe withstand voltage limit of the NMOS transistor's gate oxide layer, achieving a good balance between drive capability and device safety.

[0038] From the perspective of the high-voltage bus, the voltage of the satellite's high-voltage bus is greater than or equal to 200V, with a typical value of 270V. This voltage level corresponds to the high-voltage bus standard used in current high-capacity communication satellites, radar imaging satellites, computing satellites, and other new types of spacecraft. Compared to the 28V, 42V, or 100V low-voltage buses commonly used in traditional satellites, high-voltage buses of 200V or higher can significantly reduce the bus current at the same transmission power, thereby reducing the cross-sectional area and weight of the power supply cables and reducing the resistance loss of the transmission lines (loss is proportional to the square of the current). This is of great significance for spacecraft that are extremely sensitive to weight and size.

[0039] The satellite high-voltage bus power distribution circuit of this application has been optimized for this voltage level in terms of component selection and parameter design. The withstand voltage of each component (including the NMOS transistor, isolation power supply, power diode, capacitor, etc. mentioned below) meets the usage requirements of high voltage scenarios above 200V, ensuring the safe and reliable operation of the circuit in a high voltage environment.

[0040] From the perspective of the drive voltage, the output voltage of the isolation power supply is 10V to 18V, with a typical value of 13V. As a voltage-controlled device, the conduction level of an NMOS transistor depends on the gate-source voltage (i.e., the voltage between the control electrode and the secondary electrode). To enable the NMOS transistor to conduct fully and operate in the linear region with low on-resistance, the gate-source voltage typically needs to reach 8V to 10V or higher. At the same time, the gate oxide layer of an NMOS transistor is extremely fragile, and its withstand voltage limit is typically around ±20V. Exceeding this limit will cause permanent breakdown and damage to the gate oxide layer.

[0041] This embodiment limits the output voltage of the isolated power supply to the range of 10V to 18V, which falls precisely between the two boundary conditions mentioned above: on the one hand, a voltage above 10V is sufficient to fully turn on the NMOS transistor, achieving a lower on-resistance and thus reducing the conduction loss and heat generation of the power switch; on the other hand, a voltage below 18V provides ample voltage margin, ensuring that even with fluctuations in the output voltage of the isolated power supply or the presence of transient interference, the 20V safety limit of the NMOS transistor's gate oxide layer is unlikely to be exceeded. Taking a typical value of 13V as an example, it provides sufficient driving capability while retaining a voltage margin of approximately 7V, achieving a good balance between driving capability and device safety.

[0042] Furthermore, the input voltage of the isolated power supply is derived from the primary bus voltage of the power controller (e.g., powered by solar arrays and battery banks), and is independent of the satellite's high-voltage bus Vin. This power supply architecture ensures that the output voltage of the isolated power supply is unaffected by voltage fluctuations or abnormalities at the high-voltage bus Vin. Even when transient drops or surges occur at the high-voltage bus, the isolated power supply can maintain a stable output voltage of 10V to 18V, thereby guaranteeing the stability and reliability of the NMOS transistor gate-source drive voltage.

[0043] In summary, by limiting the voltage range of the satellite high-voltage bus and the output voltage range of the isolation power supply, this embodiment enables the satellite high-voltage bus distribution circuit of this application to directly adapt to the bus voltage standards of mainstream high-voltage satellite platforms, and achieves an optimized balance between driving capability and device safety, thus possessing good engineering practicality and versatility.

[0044] Among them, such as Figure 1 As shown, the first control sub-circuit includes a first NMOS transistor Q1, a first isolation power supply V1, a first Zener diode Z1, a first current-limiting resistor R4, and a first balancing resistor R6. The second control sub-circuit includes a second NMOS transistor Q2, a second isolation power supply V2, a second Zener diode Z2, a second current-limiting resistor R3, and a second balancing resistor R5.

[0045] The first control sub-circuit and the second control sub-circuit are electrically connected in parallel. The input terminals of both are connected to the positive terminal Vin+ of the power input terminal, and the output terminals of both are connected to the positive terminal Vout+ of the power output terminal.

[0046] As the main power switching device in each control sub-circuit, the NMOS transistor's first terminal (drain) is connected to the positive terminal Vin+ of the power input, and its second terminal (source) is connected to the positive terminal Vout+ of the power output. The NMOS transistor controls the on / off state of the power transmission from the high-voltage bus to the load by switching its on and off states.

[0047] As a high-side power switch, NMOS transistors have advantages over PMOS transistors with the same on-resistance specifications, such as small size, low cost, and low conduction loss. They can also reliably operate in high-voltage bus environments above 200V, meeting the core requirements of high-power satellites for power distribution switches.

[0048] The isolation power supplies are used to provide the drive voltage required for the NMOS transistors in the corresponding control sub-circuits to turn on. The input of each isolation power supply is converted from the primary bus voltage of the power controller (powered by the solar cell array and battery pack) and is not affected by the high voltage bus Vin voltage fluctuation. Its output provides a stable DC voltage to establish the drive voltage difference between the gate and source when the corresponding NMOS transistor is turned on.

[0049] In some embodiments, such as Figure 1 As shown, the satellite high-voltage busbar power distribution circuit includes a magnetic latching relay K1. The magnetic latching relay K1 has multiple (two or more) contacts, and the contacts of the magnetic latching relay K1 are configured in a one-to-one correspondence with the control sub-circuit. That is, one contact of the magnetic latching relay K1 is configured to correspond to one control sub-circuit.

[0050] like Figure 1 As shown, the magnetic latching relay K1 includes a first contact (A1-B1) and a second contact (A2-B2). The first contact (A1-B1) is connected in series with the first isolation power supply V1 between the control electrode and the second electrode of the first NMOS transistor Q1. The second contact (A2-B2) is connected in series with the second isolation power supply V2 between the control electrode and the second electrode of the second NMOS transistor Q2. Each isolation power supply is connected to its corresponding NMOS transistor in a one-to-one correspondence, forming an independent drive circuit.

[0051] Specifically, the positive terminal of the first isolation power supply V1 is connected to the control terminal of the first NMOS transistor Q1 via contacts A1 and B1 of the magnetic latching relay K1, and the negative terminal of the first isolation power supply V1 is connected to the second terminal of the first NMOS transistor Q1. The positive terminal of the second isolation power supply V2 is connected to the control terminal of the second NMOS transistor Q2 via contacts A2 and B2 of the magnetic latching relay K1, and the negative terminal of the second isolation power supply V2 is connected to the second terminal of the second NMOS transistor Q2.

[0052] The contacts of the magnetic latching relay K1 are configured to: close in response to a pulse-type turn-on command, thereby applying the output voltage of each isolation power supply between the control electrode and the second electrode of the corresponding NMOS transistor to drive each NMOS transistor to turn on synchronously; and open in response to a pulse-type turn-off command, thereby disconnecting each isolation power supply from the control electrode of the corresponding NMOS transistor to turn off synchronously.

[0053] In this embodiment, the high-side NMOS transistor is driven by a magnetic latching relay K1 in conjunction with an isolated power supply, thus eliminating the driving method that relies on a dedicated gate driver in traditional solutions.

[0054] On the one hand, the contacts of the magnetic latching relay K1 are directly connected in series between the isolation power supply and the control electrode of the NMOS transistor, resulting in an extremely simple circuit structure. There is no need to configure an independent auxiliary power supply for the gate driver, which reduces the number of components, lowers system complexity and potential failure points, and thus significantly improves overall reliability.

[0055] On the other hand, the magnetic latching relay K1 only requires a short pulse command to switch the contact state, and maintains the state by relying on the internal permanent magnet or mechanical structure after the command disappears. It is naturally compatible with the pulse command control method commonly used in satellite electronic systems, effectively avoiding the risk of false triggering caused by abnormal bus signals or software failures of level commands, and enhancing anti-interference capabilities.

[0056] Meanwhile, the input of the isolated power supply is independently powered by the primary bus voltage, and its output voltage is not affected by the high-voltage bus Vin, ensuring the stability of the gate-source drive voltage of the NMOS transistor; moreover, the isolated power supply itself has electrical isolation function, which enables complete electrical isolation between the low-voltage control side and the high-voltage power side, fundamentally eliminating the safety hazards of high-voltage crosstalk and backflow to the low-voltage side that exist in non-isolated drive schemes.

[0057] Furthermore, in conjunction with the aforementioned redundancy design, each isolated power supply is connected one-to-one with its corresponding NMOS transistor, and each NMOS transistor is provided with its own independent gate-source drive voltage by its own isolated power supply. This design ensures that when a certain isolated power supply fails, only its corresponding NMOS transistor is affected, while the NMOS transistors in other control sub-circuits can still be driven normally by their corresponding isolated power supplies, achieving full-link redundancy from the drive power supply to the power devices.

[0058] In some embodiments, such as Figure 1 As shown, the magnetic latching relay K1 includes a first coil and a second coil. The first coil is connected to a first control command input terminal Turn_ON. The second coil is connected to a second control command input terminal Turn_OFF. The first control command input terminal Turn_ON is used to receive a pulse-type turn-on command, and the second control command input terminal Turn_OFF is used to receive a pulse-type turn-off command.

[0059] The first coil is dedicated to responding to pulse-type turn-on commands, and the second coil is dedicated to responding to pulse-type turn-off commands. The two coils are electrically and functionally independent. This design completely separates the turn-on control circuit from the turn-off control circuit, avoiding the risk of logic confusion or malfunctions that may occur due to control signal polarity reversal in a single-coil scheme. When one coil receives a pulse command to drive the contact switching, the other coil is in a non-operating state, with no electromagnetic interference between them, further improving the determinism and reliability of command execution.

[0060] From a command adaptability perspective, the dual-coil structure is naturally suited to the conventional pulse-type command control method of satellite electronic systems. Onboard computers or remote control command systems on satellite platforms typically output short-duration pulse signals as control commands for power distribution switches, rather than continuous level signals. The dual-coil structure of the magnetic latching relay K1 can directly respond to such pulse-type commands: the first coil specifically receives pulse-type turn-on commands (Turn_ON), ​​and the second coil specifically receives pulse-type turn-off commands (Turn_OFF). Each coil is energized only momentarily upon receiving the corresponding pulse command, generating electromagnetic force to drive the contact switching; after the command pulse disappears, the contacts maintain the switched state relying on the permanent magnet or mechanical structure inside the relay, without requiring continuous power supply. This operating method is naturally adapted to satellite pulse-type commands, eliminating the need for command conversion or holding circuits in the control link and simplifying system interface design.

[0061] In terms of anti-interference capability, pulse-type commands combined with a dual-coil bistable structure exhibit superior anti-interference performance compared to level-type commands. In traditional level-type command control, the state of the power distribution switch entirely depends on the continuous maintenance of the command level. If an anomaly occurs on the command bus (such as a signal line open circuit, short circuit, or software fault causing level flipping), the power distribution switch may malfunction or become stuck. However, in this embodiment, the magnetic latching relay K1 only responds to the edge triggering of the command pulse. Continuous interference signals or abnormal levels on the command line will not cause changes in the contact state, effectively suppressing the risk of false triggering that may be caused by electromagnetic interference and single-event effects.

[0062] Furthermore, the first and second coils are electrically and functionally independent, with the turn-on control circuit and turn-off control circuit completely separated. This avoids the risk of logical confusion or malfunction that may occur due to the reversal of control signal polarity in a single-coil scheme. When one coil receives a pulse command to drive the contact switching, the other coil is in a non-operating state, with no electromagnetic interference between them, further improving the determinism and reliability of command execution.

[0063] From a power consumption control perspective, the bistable characteristic of magnetic latching relays offers significant energy-saving advantages. The magnetic latching relay K1 consumes energy only during the instant of contact state switching (i.e., during the effective period of the pulse command). During the state retention period after the command disappears, no current flows through the coil, consuming no static power. For energy-intensive satellites operating in orbit for extended periods, this characteristic effectively reduces the static power consumption of the power controller, decreases system heat dissipation, and facilitates the optimization of satellite energy budgets and simplification of thermal control design.

[0064] It should be noted that the coil operating voltage VCC of the magnetic latching relay K1 is converted from the primary bus voltage of the power controller (powered by the solar cell array and battery pack), and is not affected by the voltage fluctuations of the high-voltage bus Vin. Diodes D1 to D4 provide freewheeling discharge paths for the first and second coils respectively (see the following embodiments for details), further protecting the safe and reliable operation of the drive circuit.

[0065] In summary, this embodiment, by employing a dual-coil magnetic latching relay structure, achieves perfect compatibility with satellite pulse-type commands, improves anti-interference capability and command execution determinism, and reduces system static power consumption, providing a reliable and energy-saving control interface solution for high-voltage busbar power distribution circuits.

[0066] In some embodiments, such as Figure 1 As shown, the satellite high-voltage busbar power distribution circuit also includes: a first coil protection sub-circuit and a second coil protection sub-circuit. The first coil protection sub-circuit is connected in parallel with the first coil and is used to provide a unidirectional current discharge path when the first coil is de-energized. The second coil protection sub-circuit is connected in parallel with the second coil and is used to provide a unidirectional current discharge path when the second coil is de-energized.

[0067] For example, such as Figure 1 As shown, the first coil protection sub-circuit includes a first diode D1 and a second diode D2, which are connected in series and then in parallel with the first coil. The second coil protection sub-circuit includes a third diode D3 and a fourth diode D4, which are connected in series and then in parallel with the second coil.

[0068] This embodiment effectively solves the problem of reverse induced electromotive force generated when the relay coil, as an inductive load, ends at the moment the pulse command ends by configuring independent coil protection sub-circuits for the two coils of the magnetic latching relay K1.

[0069] From the basic principle of freewheeling protection, the coil of the magnetic latching relay K1 is an inductive element. When the pulse command at the first control command input terminal Turn_ON or the second control command input terminal Turn_OFF ends, the current path in the corresponding coil is suddenly cut off. According to the law of electromagnetic induction, the inductor will try its best to maintain its internal current from sudden change. Therefore, at the moment of power failure, a reverse induced electromotive force will be generated in the opposite direction to the original power supply direction. The amplitude of this reverse induced electromotive force may be much higher than the rated operating voltage VCC of the coil. If it is not suppressed, it will be directly applied to the transistor or other sensitive components at the drive command output terminal, causing overvoltage breakdown and damage to the device.

[0070] The first and second coil protection sub-circuits are connected in parallel across the corresponding coils. Their unidirectional conductivity ensures that the protection sub-circuits are in reverse cutoff when the coil is normally energized, without affecting the normal operation of the coil. At the instant the coil is de-energized, the polarity of the reverse induced electromotive force makes the protection sub-circuit conduct in the forward direction, providing a low-impedance freewheeling discharge circuit for the induced current. This dissipates the magnetic field energy stored in the inductor on the coil's own resistance and the forward voltage drop of the protection sub-circuit, thereby clamping the reverse voltage across the coil within a safe range and effectively protecting the preceding drive circuit.

[0071] From a reliability perspective of redundancy design, this embodiment uses a structure of two diodes connected in series, rather than a single diode, primarily to prevent single-point failures caused by diode short-circuit failure. In the long-term on-orbit operation of aerospace products, the failure of electronic components is an unavoidable risk. For diodes, short-circuit failure is a relatively common failure mode. If the coil protection sub-circuit uses only a single diode, once that diode short-circuits, the two ends of the coil will be directly short-circuited.

[0072] When the pulse command arrives, the VCC supply current bypasses the coil and flows directly back to the command terminal through the short-circuit diode. No current flows through the coil, and the electromagnetic force required to drive the contact switching cannot be generated, causing the contacts of the magnetic latching relay K1 to permanently fail to close, resulting in a complete loss of function for the entire power distribution circuit. In contrast, this embodiment uses a structure with two diodes connected in series. Only when both diodes experience a short-circuit fault simultaneously will the coil be bypassed, a serious consequence. The probability of two independent devices simultaneously experiencing the same failure mode is the product of the failure probabilities of individual devices—an extremely low probability event. Therefore, the series redundancy structure significantly improves the coil protection sub-circuit's tolerance to short-circuit failure modes. A short-circuit failure of a single diode will not affect the normal operation of the magnetic latching relay K1, effectively ensuring the functional integrity of the power distribution circuit.

[0073] From the perspective of the specific requirements of aerospace applications, the dual-diode series structure also brings additional technical benefits. On the one hand, the two diodes connected in series share the voltage stress of the reverse induced electromotive force, distributing the reverse voltage amplitude, improving the overall withstand voltage capability of the protection sub-circuit, and enhancing the reliability margin under extreme operating conditions. On the other hand, diodes are not ideal open circuits when reverse-biased, exhibiting a small reverse leakage current. This leakage current increases significantly at high temperatures, causing additional power loss. Connecting two diodes in series is equivalent to increasing the "thickness" of the reverse barrier, which can effectively reduce the overall reverse leakage current and reduce unnecessary static power consumption. This is of practical significance for satellite platforms with tight energy budgets.

[0074] In summary, this embodiment, by configuring a coil protection sub-circuit for each coil of the magnetic latching relay K1, not only effectively suppresses the reverse induced electromotive force and protects the safety of the drive circuit, but also eliminates the risk of single-point fault due to diode short circuit through series redundancy design, thus achieving the dual goals of functional protection and reliability improvement, and embodying the typical concept of aerospace high-reliability circuit design.

[0075] In some embodiments, such as Figure 1 As shown, the satellite high-voltage bus power distribution circuit also includes: a first resistor R1 and a second resistor R2. The first resistor R1 is connected in series with the first coil, and the second resistor R2 is connected in series with the second coil.

[0076] This embodiment achieves precise limitation of the operating current of the magnetic latching relay K1 coil and further improves the circuit reliability by connecting a first resistor R1 and a second resistor R2 in series in the power supply circuits of the first coil and the second coil, respectively.

[0077] From the perspective of precise control of the coil drive current, the first resistor R1 and the second resistor R2 act as current-limiting resistors, limiting the current flowing through the corresponding coil within the rated operating range. The coil of the magnetic latching relay K1 has rated operating voltage and operating current parameters. Figure 1 Taking the illustrated embodiment as an example, the rated coil operating voltage of the magnetic latching relay K1 is VCC (converted from the primary bus voltage of the power controller), and the coil itself has a certain DC resistance.

[0078] However, in practical engineering applications, the supply voltage VCC may fluctuate within a certain range, and the coil's own resistance may also drift due to temperature changes. Without current limiting measures, when VCC is too high or the coil resistance is too low, the current flowing through the coil may exceed its rated value, leading to increased coil heating. Long-term operation may cause insulation aging or even coil burnout.

[0079] Conversely, when VCC is too low or the coil resistance is too high, the current flowing through the coil may be insufficient to generate the electromagnetic force required for reliable contact switching, leading to contact switching failure or unreliable contact. The introduction of the first resistor R1 and the second resistor R2, by appropriately selecting their resistance values, matches the supply voltage of the coil circuit with the actual voltage division of the coil. This ensures that even with a certain fluctuation range in VCC, the current flowing through the coil remains stable within the rated operating range, guaranteeing the reliability of contact switching while avoiding the risk of coil overcurrent damage.

[0080] From the perspective of circuit reliability and fault isolation, the current-limiting resistor also has a certain fault protection function. Under extreme operating conditions, if the coil of the magnetic latching relay K1 experiences an inter-turn short circuit or other abnormality causing a sharp drop in equivalent resistance, the first resistor R1 or the second resistor R2 can limit the short-circuit current, preventing excessive fault current from impacting and damaging the upstream power supply (VCC) and the command drive circuit. Simultaneously, the introduction of the current-limiting resistor gives the coil drive circuit a certain impedance matching characteristic, which helps suppress high-frequency ringing and electromagnetic interference that may be generated at the edge of the command pulse, improving the signal integrity of command transmission.

[0081] In summary, this embodiment achieves precise control of the coil operating current and further improves circuit reliability by connecting current-limiting resistors R1 and R2 in series with the two coils of the magnetic latching relay K1, using simple passive components. This enhances the adaptability of the power distribution circuit to power supply voltage fluctuations and its robustness under fault conditions.

[0082] In some embodiments, such as Figure 1 As shown, the satellite high-voltage bus power distribution circuit also includes a Zener diode (e.g., Figure 1 Z1 and Z2 shown in the figure), Zener diodes and isolated power supplies (e.g. Figure 1 The V1 and V2 shown are connected in parallel to clamp the output voltage of the isolation power supply.

[0083] In each control sub-circuit, the Zener diode and its corresponding isolation power supply are connected in parallel. Specifically, as follows: Figure 1As shown, in the first control sub-circuit, the first Zener diode Z1 is connected in parallel with the first isolation power supply V1 to clamp the output voltage of the first isolation power supply V1, so as to prevent overvoltage damage between the control electrode and the second electrode of the first NMOS transistor Q1; in the second control sub-circuit, the second Zener diode Z2 is connected in parallel with the second isolation power supply V2 to clamp the output voltage of the second isolation power supply V2, so as to prevent overvoltage damage between the control electrode and the second electrode of the second NMOS transistor Q2.

[0084] This embodiment provides targeted secondary overvoltage protection for the gate-source drive voltage of each NMOS transistor by independently configuring a parallel Zener diode in each control sub-circuit for each isolated power supply.

[0085] From the perspective of the necessity of protecting the gate oxide layer of NMOS transistors, the introduction of Zener diodes is a key protective measure to cope with the special environment and potential failure modes in aerospace. As a voltage-controlled power device, the gate oxide layer of an NMOS transistor is extremely thin and is highly sensitive to overvoltage. Taking the NMOS transistor used in this application as an example, its gate-source voltage safety limit is typically around ±20V. Once this limit is exceeded, the gate oxide layer will undergo irreversible breakdown damage, leading to permanent failure of the NMOS transistor.

[0086] Although the isolation power supplies V1 and V2 have voltage regulation functions and can provide a stable drive voltage (such as 10V to 18V) under normal operating conditions, in aerospace applications, due to factors such as space radiation environment (such as single-event effect, total dose effect), electromagnetic interference, or potential faults in the isolation power supply module itself, the output voltage may still experience transient overvoltage spikes.

[0087] For example, a single-event event may momentarily disrupt the feedback control loop inside the isolated power supply, causing a brief loss of control over the output voltage; electromagnetic interference may couple from the power input to the output, superimposing high-frequency spikes on the drive voltage. Once these transient overvoltage spikes are applied between the gate and source of the NMOS transistor, they are highly likely to cause gate oxide breakdown.

[0088] Taking the first control sub-circuit as an example, the first Zener diode Z1 is connected in parallel to the output terminal of the first isolation power supply V1. During normal operation, it is in reverse cutoff, consuming no additional power and not affecting the normal regulated output of the first isolation power supply V1. Once the output voltage of the first isolation power supply V1 exceeds the breakdown voltage threshold of the first Zener diode Z1, the first Zener diode Z1 quickly reverse-biased conduction, clamping the output voltage within a preset safe range. This limits the voltage applied between the control electrode and the second electrode of the first NMOS transistor Q1 to within the safe threshold, effectively preventing damage to the first NMOS transistor Q1 due to overvoltage. The protection mechanism of the second Zener diode Z2 for the second NMOS transistor Q2 in the second control sub-circuit is the same.

[0089] From a redundancy design perspective, each control subcircuit includes an independent NMOS transistor, an independent isolation power supply, and an independent Zener diode protection element. The protection functions of each control subcircuit are independent and undependent. When a Zener diode in a control subcircuit fails (such as an open-circuit failure causing loss of clamping function, or a short-circuit failure causing short-circuiting of the isolation power supply output), the fault only affects the control subcircuit it belongs to. The Zener diodes in other control subcircuits can still perform their protection functions normally, and the gate-source overvoltage protection of the corresponding NMOS transistor is unaffected. This "one-to-one" independent protection architecture eliminates the hidden danger of a single point failure of a protection element causing all power switches to lose overvoltage protection, further enhancing the system's redundancy reliability and fault isolation capability.

[0090] From the perspective of the rationality of the protection location selection, connecting the Zener diode in parallel with the output of the isolation power supply, rather than directly in parallel with the gate and source terminals of the NMOS transistor, can achieve the same protection effect, and the circuit implementation is simpler. Combined with... Figure 1 The circuit topology shown, taking the first control sub-circuit as an example, is such that when the contacts (A1 and B1) of the magnetic latching relay K1 are closed, the output voltage of the first isolation power supply V1 is directly applied between the control electrode and the second electrode of the first NMOS transistor Q1 through the first current limiting resistor R4, driving the first NMOS transistor Q1 to conduct.

[0091] In other words, during the conduction of the first NMOS transistor Q1, its gate-source voltage is equal to the output voltage of the first isolation power supply V1. Therefore, clamping the output voltage of the first isolation power supply V1 is equivalent to clamping the gate-source drive voltage of the first NMOS transistor Q1. Connecting the first Zener diode Z1 in parallel across the first isolation power supply V1 can protect the first isolation power supply V1 itself from overvoltage stress and indirectly protect the gate oxide layer of the first NMOS transistor Q1.

[0092] Meanwhile, this connection method ensures that the first Zener diode Z1 remains connected in parallel to the output of the first isolated power supply V1 even when the magnetic latching relay K1 is open and the first NMOS transistor Q1 is off, continuously providing overvoltage protection to the first isolated power supply V1 without being affected by contact state switching, thus guaranteeing the continuity and reliability of protection. The protection relationship between the second Zener diode Z2, the second isolated power supply V2, and the second NMOS transistor Q2 in the second control sub-circuit is the same, and will not be elaborated here.

[0093] In summary, this embodiment achieves targeted secondary overvoltage protection for the gate-source drive voltage of each NMOS transistor by independently configuring parallel Zener diodes in each control sub-circuit, with a simple circuit structure and redundant protection architecture. This effectively addresses the transient overvoltage risk that may occur in aerospace applications and is consistent with the overall redundant design concept of this application, further improving the survivability and reliability of the power distribution circuit in space radiation and complex electromagnetic environments.

[0094] In some embodiments, such as Figure 1 As shown, the satellite high-voltage bus power distribution circuit also includes current-limiting resistors (e.g., Figure 1 R3, R4 shown), current-limiting resistor and NMOS transistor (e.g. Figure 1 The control electrodes of Q1 and Q2 are connected in series as shown in the figure.

[0095] Specifically, in each control sub-circuit, the first control sub-circuit includes a first current-limiting resistor R4, which is connected in series with the control electrode of the first NMOS transistor Q1; the second control sub-circuit includes a second current-limiting resistor R3, which is connected in series with the control electrode of the second NMOS transistor Q2.

[0096] From the basic principle of NMOS transistor turn-on speed regulation, the introduction of the current-limiting resistor effectively controls the gate charging current during the NMOS transistor's transition from the off to the on state. There is an inherent parasitic capacitance (gate-source capacitance Cgs) between the control electrode (gate) and the second electrode (source) of the NMOS transistor, and there is also a parasitic capacitance (gate-drain capacitance Cgd, i.e., Miller capacitance) between the control electrode and the first electrode (drain).

[0097] When the contacts of the magnetic latching relay K1 close and the output voltage of the isolation power supply begins to apply a drive voltage to the control electrode of the NMOS transistor, the drive voltage needs to charge these parasitic capacitances, causing the control electrode potential to gradually rise until it reaches the NMOS transistor's turn-on threshold voltage. The speed of this charging process directly determines the turn-on speed of the NMOS transistor.

[0098] If a current-limiting resistor is not connected in series in the control circuit, the charging current of the parasitic capacitor is only limited by the internal resistance of the isolation power supply and the resistance of the wires. The charging current may be large, causing the NMOS transistor to turn on rapidly in a very short time. Excessive turn-on speed has two adverse effects: First, the surge current amplitude at the moment of turn-on is high, causing a significant impact on the input power supply and the load-side filter capacitors, potentially triggering grid protection or accelerating device aging; second, the rapid voltage and current change rates (dv / dt and di / dt) generate strong electromagnetic interference, affecting the normal operation of surrounding sensitive circuits.

[0099] Taking the first control sub-circuit as an example, the first current-limiting resistor R4 is connected in series with the control electrode of the first NMOS transistor Q1, limiting the current from the first isolation power supply V1 to charge the parasitic capacitance of the control electrode of the first NMOS transistor Q1. This appropriately extends the switching time required for the first NMOS transistor Q1 to go from cutoff to full conduction, thereby effectively suppressing the surge current amplitude at the moment of conduction, reducing the impact on the power supply and load, and lowering the level of electromagnetic interference. The second current-limiting resistor R3 in the second control sub-circuit has the same mechanism for adjusting the conduction speed of the second NMOS transistor Q2.

[0100] From the perspective of the flexibility of independent adjustment of each control sub-circuit, configuring an independent current-limiting resistor for each NMOS transistor allows designers to independently select the resistance value of each current-limiting resistor according to actual needs and the electrical characteristics or power distribution requirements of different control sub-circuits, thereby achieving fine adjustment of the conduction speed of each NMOS transistor.

[0101] For example, in applications where multiple control sub-circuits are connected in parallel and redundantly, the turn-on timing of each NMOS transistor can be finely adjusted by appropriately adjusting the resistance value of the current-limiting resistor in each branch, thus avoiding the generation of excessive combined surge current caused by all NMOS transistors turning on at the same instant.

[0102] Furthermore, through the design of independently configured current-limiting resistors, when a current-limiting resistor in a certain control sub-circuit fails (such as an open circuit failure), it only affects the normal conduction of the NMOS transistor in that branch. The NMOS transistors in the other control sub-circuits can still achieve normal conduction speed control by their respective independent current-limiting resistors in conjunction with the isolation power supply. Each branch is independent of each other and does not interfere with each other, thus improving the fault isolation capability of the system.

[0103] In summary, this embodiment achieves effective control of the NMOS transistor's turn-on speed using simple passive components by connecting independent current-limiting resistors in series with the control electrode of each NMOS transistor. This suppresses inrush current and electromagnetic interference, while providing independent parameter adjustment flexibility for each control sub-circuit, thus balancing circuit performance and system reliability.

[0104] In some embodiments, such as Figure 1 As shown, the satellite high-voltage bus power distribution circuit also includes balancing resistors (e.g., Figure 1 R5 and R6 shown in the figure), the balancing resistor is connected in parallel with the NMOS transistor (e.g. Figure 1 The control electrode (Q1, Q2) shown in the figure is between the second electrode and the second electrode.

[0105] Specifically, in each control sub-circuit, the first control sub-circuit includes a first balancing resistor R6, which is connected in parallel between the control electrode and the second electrode of the first NMOS transistor Q1; the second control sub-circuit includes a second balancing resistor R5, which is connected in parallel between the control electrode and the second electrode of the second NMOS transistor Q2.

[0106] This embodiment ensures reliable cutoff of each NMOS transistor in the off state by connecting a balancing resistor in parallel between the control electrode and the second electrode of each NMOS transistor.

[0107] From the basic principle of NMOS transistor turn-off reliability, the introduction of the balancing resistor provides a reliable discharge path for residual charge at the control electrode, preventing the risk of accidental turn-on due to a floating control electrode. NMOS transistors are voltage-controlled devices, and their turn-on and turn-off states depend entirely on the voltage between the control electrode and the gate-source voltage.

[0108] During normal operation, when the contacts of the magnetic latching relay K1 are closed, the output voltage of the isolation power supply is applied between the control electrode and the secondary electrode, charging the parasitic capacitance of the control electrode, establishing the gate-source voltage, and driving the NMOS transistor to conduct. When the contacts of the magnetic latching relay K1 are open, the connection between the isolation power supply and the control electrode is broken, and the NMOS transistor should theoretically enter the off state. However, if there is no parallel balancing resistor between the control electrode and the secondary electrode, the control electrode will be in a high-resistance floating state.

[0109] At this point, a small amount of charge may remain on the parasitic capacitance of the control electrode, preventing the gate-source voltage from rapidly decreasing to zero. The NMOS transistor may remain in an incompletely off intermediate state (i.e., the subthreshold region) for an extended period, generating continuous leakage current, increasing power consumption, and potentially causing device damage due to heat accumulation. More seriously, in a space environment, a floating control electrode is highly susceptible to electromagnetic interference or space radiation (such as single-event effects), inducing stray voltages. Once the induced voltage exceeds the NMOS transistor's turn-on threshold voltage, the NMOS transistor will turn on unnecessarily, causing the load to be unexpectedly energized when it should not be, potentially leading to serious system failures.

[0110] Taking the first control sub-circuit as an example, the first balancing resistor R6 is connected in parallel between the control electrode and the second electrode of the first NMOS transistor Q1, providing a reliable low-impedance discharge path for the residual charge on the parasitic capacitance of the control electrode. When the contacts of the magnetic latching relay K1 open, the residual charge on the control electrode of the first NMOS transistor Q1 is quickly discharged to the second electrode through the first balancing resistor R6, causing the gate-source voltage to drop rapidly to zero, ensuring that the first NMOS transistor Q1 is completely and reliably turned off.

[0111] Meanwhile, the first balancing resistor R6 stabilizes the DC potential of the control electrode at the second electrode potential (i.e., the source potential), effectively suppressing stray voltages induced on the control electrode by electromagnetic interference and spatial radiation, thus improving the circuit's anti-interference capability. The second balancing resistor R5 in the second control sub-circuit provides the same mechanism for ensuring the turn-off reliability and anti-interference capability of the second NMOS transistor Q2.

[0112] From the perspective of redundant design with independent configuration of each control sub-circuit, each NMOS transistor is configured with an independent balancing resistor. Each control sub-circuit contains an independent NMOS transistor, an independent isolation power supply, an independent Zener diode, an independent current limiting resistor, and an independent balancing resistor. The turn-off reliability guarantee mechanism of each control sub-circuit is independent of each other.

[0113] When a balancing resistor in a control sub-circuit fails (e.g., a circuit failure breaks the discharge path, or resistance drift changes the discharge time constant), the failure only affects the turn-off reliability of the NMOS transistor in that sub-circuit. The balancing resistors in other control sub-circuits can still perform their residual charge discharge and potential stabilization functions normally, and the reliable turn-off of the corresponding NMOS transistors remains unaffected. This "one-to-one" independent configuration eliminates the potential for a single-point fault to cause unreliable turn-off of all power switches, further enhancing the system's redundancy reliability and fault isolation capabilities.

[0114] In summary, this embodiment ensures reliable cutoff and anti-interference capability of each NMOS transistor in the off state by connecting independent balancing resistors in parallel between the control electrode and the second electrode of each NMOS transistor using simple passive components. This is consistent with the overall redundancy design concept of this application and further improves the working reliability of the power distribution circuit in complex electromagnetic and radiation environments.

[0115] In some embodiments, such as Figure 1 As shown, the satellite high-voltage bus power distribution circuit also includes: a first capacitor C1, and / or, at least one power diode (e.g., Figure 1 (D5 and D6 are shown in the diagram). The first capacitor C1 is connected in parallel between the positive terminal Vout+ and the negative terminal of the power supply output. The cathode of the power diode is connected to the positive terminal Vout+ of the power supply output, and the anode of the power diode is connected to the negative terminal Vout- of the power supply output.

[0116] It should be noted that the number of power diodes can be one, two or more, and this application does not impose any specific restrictions on this.

[0117] When only one power diode is used, it is connected in parallel between the positive terminal Vout+ and the negative terminal Vout- of the power output. When the NMOS transistor is turned off and the downstream inductive load generates a reverse induced electromotive force (EMF), this power diode alone undertakes the task of freewheeling and discharging, providing an energy discharge path for the reverse EMF. The scheme using a single power diode has fewer components and the simplest circuit structure, making it suitable for scenarios with low load power and limited reverse induced EMF energy.

[0118] When there are two or more power diodes, each power diode is connected in series between the positive terminal Vout+ and the negative terminal Vout- of the power output. Figure 1 In the illustrated embodiment, two power diodes are used: a first power diode D5 and a second power diode D6. The cathode of the first power diode D5 is connected to the positive terminal Vout+ of the power output, the anode of the first power diode D5 is connected to the cathode of the second power diode D6, and the anode of the second power diode D6 is connected to the negative terminal Vout- of the power output. That is, the first power diode D5 and the second power diode D6 are connected in series and then in parallel between the positive terminal Vout+ and the negative terminal Vout- of the power output.

[0119] When the NMOS transistor is turned off and the downstream inductive load generates a reverse induced electromotive force, the first power diode D5 and the second power diode D6 jointly undertake the task of freewheeling discharge. Using two or more power diodes in series improves the overall withstand voltage of the freewheeling branch. Both diodes share the voltage stress of the reverse induced electromotive force, making it particularly suitable for high-voltage bus scenarios where the withstand voltage of a single diode is insufficient. Furthermore, the series redundancy structure also improves the reliability of the freewheeling protection function. When one power diode fails due to a short circuit, the other power diode can still independently perform the reverse blocking function, preventing the power output from being bypassed by the short-circuited diode during normal power supply. This ensures uninterrupted system protection and eliminates the risk of single-point short-circuit faults.

[0120] By adding a first capacitor C1 and / or a power diode at the power output terminal, the common-mode voltage interference problem and the inductive load adaptation problem unique to satellite high-voltage bus power distribution scenarios are solved respectively.

[0121] The first capacitor C1 is connected in parallel between the positive terminal Vout+ and the negative terminal Vout- of the power supply output terminal, and is used to discharge the high-frequency common-mode voltage coupled to the power supply output terminal by the parasitic capacitance of the NMOS transistor.

[0122] From the perspective of common-mode voltage generation mechanism, in the modular design of satellite power controllers, due to heat dissipation requirements, the internal DC / DC power conversion module usually needs to be installed close to the unit's structural panel. This installation method inevitably results in parasitic capacitance between the positive (Vin+) and return (Vin-) lines of the high-voltage bus and the grounded structural panel. The high-frequency switching action of the power conversion module will generate high-frequency common-mode voltage between the high-voltage bus and the structural panel through these parasitic capacitances.

[0123] When the NMOS transistor in this application is in the off state, although the high-frequency common-mode voltage on the high-voltage bus cannot be transmitted to the output terminal through the conduction channel of the NMOS transistor, it can still be coupled to the power output terminal through the parasitic capacitance of the NMOS transistor itself (mainly the drain-source capacitance Cds and the gate-drain capacitance Cgd), thereby generating a common-mode interference voltage at the load terminal, which adversely affects the normal operation of sensitive loads.

[0124] The first capacitor C1 is connected in parallel between the positive and negative terminals of the power supply output, providing a low-impedance bypass path for the coupled high-frequency common-mode signal. Because the first capacitor C1 exhibits low capacitive reactance to high-frequency signals, the common-mode voltage signal coupled to the output is bypassed to the negative terminal of the output by the first capacitor C1, significantly reducing the actual common-mode voltage amplitude experienced by the load. The first capacitor C1 is preferably a high-voltage ceramic capacitor, and its capacitance value can be reasonably selected based on the frequency range of the common-mode voltage and the expected suppression effect.

[0125] A power diode is connected between the positive and negative terminals of the power supply output to provide an energy discharge path for the reverse induced electromotive force generated by the inductive load when the downstream inductive load is turned off.

[0126] From the perspective of adapting to inductive loads, typical loads in high-voltage, high-power satellite systems, such as SAR radar, electric propulsion systems, magnetic torquers, and high-power drive mechanisms, all exhibit significant inductive characteristics. When the NMOS transistors (Q1, Q2) are turned off, cutting off the supply current to the inductive load, according to the law of electromagnetic induction, the magnetic field energy stored in the load inductance is released instantaneously, generating a very high-amplitude reverse induced electromotive force (EMF). The polarity of this reverse induced EMF is opposite to the original supply voltage; that is, a high voltage appears at the negative terminal Vout- of the power supply output relative to the positive terminal Vout+. If left unchecked, this reverse induced EMF can reach hundreds or even thousands of volts, far exceeding the withstand voltage limit of the NMOS transistor, causing the NMOS transistor to break down and potentially endangering other components in the downstream circuitry.

[0127] When the power diode is under normal power supply, it is in a reverse bias state and exhibits high-impedance cutoff characteristics, which does not affect the normal power distribution operation of the circuit. When the NMOS transistor is turned off and the inductive load generates a reverse induced electromotive force, the potential of the negative terminal Vout- of the power supply output is momentarily higher than the potential of the positive terminal Vout+. This voltage polarity just causes the power diode to be in a forward bias state and conduct.

[0128] The conducting power diode provides a low-impedance loop for the freewheeling of the inductive load. The magnetic field energy stored in the load inductance is consumed by the diode forward voltage drop and the load's own resistance through the freewheeling loop formed by the power diode. This clamps the reverse voltage at the power output terminal to the level of the diode forward voltage drop (usually only about 1V), effectively protecting the NMOS transistor and the downstream circuit from overvoltage damage.

[0129] The power diode is preferably a high-voltage, high-current power diode to meet the voltage withstand and freewheeling current requirements in high-voltage bus scenarios.

[0130] When the number of power diodes is two or more connected in series (e.g.) Figure 1 As shown, D5 and D6 are connected in series. The series structure allows the two diodes to share the reverse voltage stress, which improves the overall withstand voltage capability of the freewheeling branch and is suitable for high-voltage busbar scenarios. The series redundancy structure improves the reliability of the freewheeling protection function. When one of the power diodes fails due to a short circuit, the other power diode can still perform the reverse blocking function normally, preventing the power output terminal from being short-circuited during normal power supply and eliminating the risk of single-point short-circuit faults of the protection element.

[0131] When the first capacitor C1 and the power diode are set individually or simultaneously, their functions complement each other. The first capacitor C1 mainly suppresses high-frequency common-mode voltage signals. Its capacitance value is usually small (e.g., in the nF range), and its response speed is fast, making it suitable for discharging high-frequency interference coupled by parasitic capacitance. The power diode mainly discharges energy from low-frequency, high-energy reverse induced electromotive force. It has a large current carrying capacity and high withstand voltage, making it suitable for protecting circuits from high-voltage surges during the moment of power failure of inductive loads. Together, they comprehensively manage abnormal voltages at the power supply output from different frequency bands and energy levels, ensuring the adaptability of the power distribution circuit to various load types and complex electromagnetic environments.

[0132] In summary, this embodiment effectively suppresses common-mode voltage interference in high-voltage bus scenarios by adding a first capacitor C1 and / or at least one power diode at the power output terminal, and provides a reliable reverse induced electromotive force discharge path for inductive loads. The number of power diodes can be flexibly selected according to the actual load power and reliability requirements, significantly improving the adaptability and reliability of the satellite high-voltage bus power distribution circuit to complex load types and harsh electromagnetic environments.

[0133] In some embodiments, such as Figure 1 As shown, the satellite high-voltage bus power distribution circuit also includes a soft-start circuit, which is connected in series with an NMOS transistor (e.g., Figure 1 The second terminal of Q1 and Q2 shown in the figure is between the positive terminal Vout+ of the power supply output terminal, which is used to suppress the surge current and / or reverse electromotive force caused by the excessively fast conduction speed of the NMOS transistor.

[0134] Specifically, the soft-start circuit is connected in series between the second terminal of the NMOS transistor in each control sub-circuit and the positive terminal Vout+ of the power supply output. Figure 1 Taking the illustrated embodiment as an example, the second terminal of the first NMOS transistor Q1 in the first control sub-circuit is connected to the positive terminal Vout+ of the power output terminal via a soft-start circuit, and the second terminal of the second NMOS transistor Q2 in the second control sub-circuit is also connected to the positive terminal Vout+ of the power output terminal via the same soft-start circuit.

[0135] This embodiment effectively suppresses the surge current generated when the NMOS transistor is turned on and the reverse electromotive force generated when it is turned off by connecting a soft-start circuit in series between the second terminal of the NMOS transistor and the positive terminal of the power supply output.

[0136] From the perspective of suppressing inrush current, the soft-start circuit limits the rate of current rise at the moment the NMOS transistor turns on. When the contacts of the magnetic latching relay K1 close and the NMOS transistor starts to conduct, the high-voltage bus voltage at the power input terminal is instantaneously applied to the load terminal. If there are large-capacity filter capacitors or decoupling capacitors at the load terminal, these capacitors are equivalent to a short circuit at the moment the NMOS transistor turns on, generating a very high-amplitude inrush current.

[0137] Excessive inrush current can lead to the following problems: First, it can impact the input power supply, potentially triggering overcurrent protection in the power system or causing a voltage drop on the bus. Second, it can cause excessive current stress on the NMOS transistor, accelerating its aging or even causing damage. Third, it can impact the downstream load circuit, affecting the normal operation of sensitive components. The soft-start circuit controls the current rise slope during the NMOS transistor's conduction process, allowing the charging current of the load capacitor to increase gradually, thus limiting the peak inrush current to a safe range.

[0138] like Figure 2 In the power-on waveform diagram shown, the purple curve represents the 270V bus voltage, the blue curve represents the power-on surge current, and the yellow curve represents the gate-source voltage of the NMOS transistor. It can be seen that under the action of the soft-start circuit, the surge current waveform is smooth and without obvious spikes, which verifies the effective suppression effect of the soft-start circuit on surge current.

[0139] From the perspective of suppressing reverse electromotive force (EMF), when the NMOS transistor is turned off and the load current is interrupted, if there are parasitic inductance or inductive components in the load circuit, the rapid change in current will also generate a reverse induced EMF at the load terminal. The soft-start circuit, by appropriately controlling the turn-off speed of the NMOS transistor (in coordination with the current-limiting resistors R3 and R4 and the balancing resistors R5 and R6 in the gate drive circuit), slows down the rate of current decrease, thereby reducing the amplitude of the reverse induced EMF and further protecting the NMOS transistor and the downstream circuitry. Combined with the freewheeling discharge function of the aforementioned power diodes D5 and D6, the soft-start circuit and the power diodes together constitute a complete protection scheme for inductive loads.

[0140] The soft-start circuit can be a conventional soft-start circuit module in this field, such as an active soft-start circuit composed of resistors, capacitors, and switching transistors, or a passive soft-start circuit composed of negative temperature coefficient thermistors. In aerospace applications, a dedicated soft-start circuit module that is resistant to high voltage and radiation is preferred to meet the stringent requirements of high-voltage buses and the space environment.

[0141] It should be noted that, in the embodiments of this application, the correspondence between the components in the first control sub-circuit and the second control sub-circuit has been... Figure 1 The diagram clearly shows that, specifically, the first control sub-circuit includes a first NMOS transistor Q1, a first isolation power supply V1, a first Zener diode Z1, a first current-limiting resistor R4, and a first balancing resistor R6; the second control sub-circuit includes a second NMOS transistor Q2, a second isolation power supply V2, a second Zener diode Z2, a second current-limiting resistor R3, and a second balancing resistor R5.

[0142] Contacts A1 and B1 of the magnetic latching relay K1 are used to control the switching between the first isolation power supply V1 and the control electrode of the first NMOS transistor Q1 in the first control sub-circuit. Contacts A2 and B2 are used to control the switching between the second isolation power supply V2 and the control electrode of the second NMOS transistor Q2 in the second control sub-circuit. When the Turn_ON terminal receives a pulse-type turn-on command, contacts A1-B1 and A2-B2 close, and the first NMOS transistor Q1 and the second NMOS transistor Q2 turn on synchronously. When the Turn_OFF terminal receives a pulse-type turn-off command, contacts A1-C1 and A2-C2 close, and the control electrodes of the first NMOS transistor Q1 and the second NMOS transistor Q2 are disconnected from their corresponding isolation power supplies. Residual charges are discharged through their respective balancing resistors, achieving synchronous turn-off.

[0143] The voltages of the isolated power supplies V1 and V2 are both derived from the primary bus voltage of the power controller (powered by the solar array and battery pack), and are unaffected by fluctuations in the high-voltage bus Vin voltage. The coil operating voltage VCC of the magnetic latching relay K1 is also derived from the primary bus voltage. This power supply architecture ensures complete electrical isolation between the low-voltage control side circuit and the high-voltage power side circuit, fundamentally eliminating the safety hazard of high-voltage crosstalk to the low-voltage control side.

[0144] In a specific application example, the circuit parameters and component selection of the satellite high-voltage busbar power distribution circuit provided in this application are as follows: High-voltage bus input voltage Vin = 270V; The coil operating voltage of the magnetic latching relay K1 is VCC=12V; the model of the magnetic latching relay K1 is JMC-160MA-012. The output voltage of both the first isolation power supply V1 and the second isolation power supply V2 is 13V. The resistance values ​​of the first resistor R1 and the second resistor R2 are both 51Ω; The resistance values ​​of the first current-limiting resistor R4 and the second current-limiting resistor R3 are both 10kΩ. The resistance values ​​of the first balancing resistor R6 and the second balancing resistor R5 are both 51kΩ.

[0145] Diodes D1 to D4 are of model 2CK75E; The first Zener diode Z1 and the second Zener diode Z2 are model 1N5246B; The first NMOS transistor Q1 and the second NMOS transistor Q2 are model IPW65R022CFD7AXKSA1; Power diodes D5 and D6 are model STBR3008WY; The first capacitor C1 is a 22nF / 2kV ceramic capacitor; The soft-start circuit uses a dedicated soft-start circuit module that is resistant to high voltage.

[0146] The specific circuit parameters and component models described above are merely a preferred embodiment of this application and do not constitute a limitation on the scope of protection of this application. Those skilled in the art can reasonably adjust the above parameters and models according to actual application requirements (such as different bus voltage levels, power levels, reliability requirements, etc.).

[0147] The relevant test waveforms for this example are as follows: Figures 2 to 4 As shown. Figure 2 and Figure 3 In the diagram, the purple line represents the 270V voltage, the blue line represents the power-on surge current, and the yellow line represents the MOSFET's gate-source voltage.

[0148] Figure 2The power-on waveform diagram shows the waveforms of the bus voltage (purple curve, 270V), inrush current (blue curve), and NMOS gate-source voltage (yellow curve) at the instant the circuit is powered on (the instant the NMOS transistor turns on) under the action of a pulse-type turn-on command. Figure 2 As can be seen, the surge current waveform is smooth and without obvious spikes during power-on, the gate-source voltage of the NMOS transistor is established stably, and the circuit has a good soft-start effect.

[0149] Figure 3 The power-down waveform diagram shows the waveforms of the bus voltage (purple curve, 270V), current (blue curve), and NMOS transistor gate-source voltage (yellow curve) at the instant the circuit powers down (the instant the NMOS transistor turns off) under a pulse-type turn-off command. Figure 3 As can be seen, the current quickly returns to zero during the power-down process, the gate-source voltage of the NMOS transistor is rapidly discharged, and the circuit has good turn-off characteristics.

[0150] Depend on Figure 2 , Figure 3 As can be seen, the satellite high-voltage bus power distribution circuit provided in some embodiments of this application can realize the function of power distribution to the downstream load of the high-voltage bus.

[0151] Figure 4 The common-mode voltage waveform comparison diagram shows the voltage waveform under NMOS transistor (e.g., ...). Figure 1 The diagram shows a comparison of the waveform changes of the common-mode voltage between the positive and negative terminals of the power supply output (Vout+ and Vout-) before and after adding the first capacitor C1, with Q1 and Q2 (Q1 and Q2) off. Figure 4 As can be seen, after adding the first capacitor C1, the amplitude of the common-mode voltage at the output terminal is significantly reduced, which verifies the effective suppression effect of the first capacitor C1 on high-frequency common-mode voltage and can significantly reduce the common-mode voltage generated by similar circuits in subsequent stages.

[0152] The above test waveforms fully verify the effectiveness and superiority of the satellite high-voltage bus power distribution circuit provided in this application in terms of power distribution function, soft-start characteristics, shutdown characteristics and common-mode voltage suppression capability in high-voltage bus scenarios.

[0153] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0154] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A satellite high voltage bus power distribution circuit, characterized by, include: The power input terminal is used to connect to the satellite's high-voltage busbar. The power output terminal is used to connect to the electrical load; Control sub-circuit; The control sub-circuit includes an NMOS transistor and an isolation power supply. The first terminal of the NMOS transistor is connected to the positive terminal of the power supply input, and the second terminal of the NMOS transistor is connected to the positive terminal of the power supply output. A magnetic latching relay, wherein the contacts are connected in series with the isolation power supply between the control electrode and the second electrode of the NMOS transistor; The contacts of the magnetic latching relay are configured as follows: In response to a pulse-type turn-on command, the output voltage of the isolation power supply is applied to the control electrode of the NMOS transistor to drive the NMOS transistor to turn on. as well as, In response to a pulse-type shutdown command, the isolation power supply is disconnected from the control electrode of the NMOS transistor, thereby turning off the NMOS transistor.

2. The satellite high voltage bus power distribution circuit of claim 1, wherein, The magnetic latching relay includes: A first coil is connected to a first control command input terminal; the first control command input terminal is used to receive the pulse-type conduction command. The second coil is connected to the second control command input terminal; the second control command input terminal is used to receive the pulse-type shutdown command. The satellite high-voltage bus power distribution circuit also includes: The first coil protection sub-circuit, connected in parallel with the first coil, is used to provide a unidirectional current discharge path when the first coil is de-energized. The second coil protection sub-circuit, connected in parallel with the second coil, is used to provide a unidirectional current discharge path when the second coil is de-energized.

3. The satellite high-voltage busbar power distribution circuit according to claim 2, characterized in that, The first coil protection sub-circuit includes a first diode and a second diode, wherein the first diode and the second diode are connected in series and then connected in parallel with the first coil; The second coil protection sub-circuit includes a third diode and a fourth diode, wherein the third diode and the fourth diode are connected in series and then connected in parallel with the second coil.

4. The satellite high voltage bus power distribution circuit of claim 2, wherein, The satellite high-voltage bus power distribution circuit also includes: The first resistor is connected in series with the first coil; The second resistor is connected in series with the second coil.

5. The satellite high-voltage busbar power distribution circuit according to claim 1, characterized in that, The satellite high-voltage bus power distribution circuit also includes: A Zener diode, connected in parallel with the isolated power supply, is used to clamp the output voltage of the isolated power supply.

6. The satellite high-voltage busbar power distribution circuit according to claim 1, characterized in that, The satellite high-voltage bus power distribution circuit also includes: A current-limiting resistor is connected in series with the control electrode of the NMOS transistor.

7. The satellite high-voltage busbar power distribution circuit according to claim 1, characterized in that, The satellite high-voltage bus power distribution circuit also includes: A balancing resistor is connected in parallel between the control electrode and the second electrode of the NMOS transistor.

8. The satellite high-voltage busbar power distribution circuit according to any one of claims 1 to 7, characterized in that, The satellite high-voltage bus power distribution circuit includes: At least two of the control sub-circuits are connected in parallel with each other.

9. The satellite high-voltage busbar power distribution circuit according to any one of claims 1 to 7, characterized in that, The satellite high-voltage bus power distribution circuit also includes: a first capacitor, and / or, at least one power diode; The first capacitor is connected in parallel between the positive and negative terminals of the power supply output. The cathode of the power diode is connected to the positive terminal of the power output terminal, and the anode of the power diode is connected to the negative terminal of the power output terminal.

10. The satellite high-voltage busbar power distribution circuit according to any one of claims 1 to 7, characterized in that, The voltage of the satellite high-voltage bus is greater than or equal to 200V, and the output voltage of the isolation power supply is 10V to 18V.

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