Apparatus having signal amplifier integrated in semiconductor chip

Abstract

This invention relates to a device having a signal amplifier integrated in a semiconductor chip, the signal amplifier having an amplifier input for an input signal and an amplifier output for an output signal, wherein the signal amplifier has an amplifier stage and a feedback network, and the device has an error identification circuit for identifying erroneous modulation of the output signal due to an error in the wiring of the integrated circuit, wherein the error identification circuit has a comparator designed to compare a comparator input signal with a predetermined tolerance value or tolerance range, the comparator input signal being applied at the comparator input of the comparator, characterized in that the comparator input of the comparator is connected to a node of the signal amplifier arranged between two amplifier stages, and the signal amplifier is designed to output a signal at the node that is more strongly modulated than the input signal.

Description

Technical Field

[0001] The present invention relates to a device having a signal amplifier integrated in a semiconductor chip, the signal amplifier having an amplifier input for an input signal and an amplifier output for an output signal, wherein the signal amplifier has at least two amplifier stages connected in series between the amplifier input and the amplifier output and a feedback network disposed between the amplifier input and the amplifier output, and has an error identification circuit integrated in the semiconductor chip for identifying erroneous modulation of the output signal caused by errors in the wiring of the integrated circuit, wherein the error identification circuit has a comparator designed to compare a comparator input signal applied at the comparator input of the comparator with a predetermined tolerance value or tolerance range. Background Technology

[0002] Sensor technology is becoming increasingly important in the field of vehicle technology. Especially when sensor technology is applied to safety-oriented applications, there are very high requirements not only for accuracy but also for the reliability of sensor signals. Based on existing technologies, redundancy design (including systematic rationality checks) is used to improve system reliability.

[0003] As an alternative to redundancy, relevant signal paths in the system are monitored or designed to be interference robust in terms of known sources and effects of interference through a compensation architecture.

[0004] In the field of combining electronic circuit architecture with physical sensors, many methods are known that lead to extremely robust systems. A common example of this is temperature compensation for circuits and sensors, which is inherent in modern sensor systems. Other effects, such as electromagnetic compatibility (EMV), have also been partially compensated for with satisfactory results.

[0005] Good and reliable compensation requires a precise understanding of the mechanisms by which interference enters the sensor system.

[0006] Situations attributable to poorly elucidated mechanisms of action include errors caused by the failure or malfunction of components involved in the overall system function. In such cases, interference compensation fails, and reliability is only guaranteed by diagnostic instances that continuously monitor system operation. In this situation, erroneous output signals are no longer prevented, but at least they are identified and can be signaled to higher system instances.

[0007] In the case of monolithic integrated sensor systems or general integrated circuits (ICs), potential system components that could cause failure also include external wiring, including input peripherals of the evaluation unit to which data or sensor signals are transmitted.

[0008] In many applications, the output signal exists as the output voltage of a differential or absolute design. The output amplifier here drives an external load, which consists of ohmic, capacitive, and inductive components and is also partly parasitic.

[0009] If a load change occurs now due to the described fault, this could lead to an overload voltage deviation in the output amplifier.

[0010] While large deviations from the internally specified expected value (e.g., caused by a short circuit) can be detected very easily due to the magnitude of the deviation, smaller deviations of only a few millivolts caused by a moderate increase in load current can only be detected with a significantly increased cost.

[0011] A device of the above type is known in practice, having a first signal amplifier integrated into a semiconductor chip, the first signal amplifier having multiple amplifier stages. The first signal amplifier has an amplifier input for a variable input signal and an amplifier output for an output signal. An error identification circuit is integrated into the semiconductor chip, having a second signal amplifier constructed identically to the first signal amplifier, the amplifier input of the second signal amplifier being connected to the amplifier input of the first signal amplifier. The error identification circuit also has a differential amplifier, which has its non-inverting input connected to the amplifier output of the first signal amplifier and its inverting input connected to the amplifier output of the second signal amplifier. To identify deviations in the output signal of the signal amplifier that are outside a predetermined tolerance range, the output of the differential amplifier is connected to the input of a comparator. If small deviations are to be identified, the error identification circuit must have correspondingly high accuracy. Furthermore, it is disadvantageous that the second signal amplifier requires considerable circuitry. Summary of the Invention

[0012] Therefore, the object of the present invention is to provide a device of the type described above, wherein the error identification circuit of the device allows for a simple and cost-effective construction, but can still detect erroneous wiring conditions of integrated circuits, the erroneous wiring conditions causing only a small deviation of the output signal from the desired output signal.

[0013] This task is solved by the features of claim 1. These features, in relation to devices of the above type, specify that the comparator input of the comparator is connected to the signal amplifier at a node between two amplifier stages, and the signal amplifier is designed such that a signal with stronger modulation than the input signal can be output at this node.

[0014] The advantage of the device according to the invention is that the first amplifier stage of the multi-stage amplifier can typically have a high gain factor greater than 1000, while the final amplifier stage (also called the output stage) is more drive-capable compared to stages with high signal gain or high gain factors. Therefore, in the case of output signal deviation (e.g., in the millivolt range), a deviation signal in the volt range can appear at the nodes between amplifier stages. Thus, deviations in the output signal caused by incorrect wiring of the semiconductor chip can be detected in a simple manner using a simple comparator whose threshold is coordinated with the normal swing of the signal applied at the node. As a result, the comparator threshold specification can also be designed with a loose accuracy in the range of several 10mV, by which the tolerance value or tolerance range of the comparator leading to the identification of the error is defined, which can be achieved with less cost in circuit technology. Errors in the wiring of integrated circuits can specifically include connecting an excessively small load impedance at the amplifier output.

[0015] In a preferred embodiment of the invention, the comparator is configured as a window comparator. Thus, the identification circuit enables two-sided checking of the signal applied to the comparator input. Consequently, the identification circuit can identify errors more reliably in specific applications.

[0016] A further extension of the invention specifies that the comparator includes at least one comparator element having inverting and non-inverting comparator element inputs, such that one of these inputs is connected to a comparator input and the other is connected to a threshold value supplier. The threshold value supplier allows a threshold value signal to be applied to the aforementioned comparator element input, and the supplier has means for dynamically adapting the threshold value signal to the temperature and / or the amplitude of the input signal. Thus, the identification circuit enables even more reliable error identification.

[0017] In an advantageous embodiment of the invention, the error identification circuit includes a low-pass filter. Therefore, when EMV interference occurs and during rapid load switching, the error identification circuit enables more reliable operation.

[0018] In its simplest form, the amplifier is designed as a two-stage amplifier, with the node connected to the comparator input of the window comparator positioned between the first and second amplifier stages. In this configuration, the output of the first amplifier stage is connected to the input of the second amplifier stage and to the input of the identification circuit.

[0019] In a preferred embodiment of the invention, the low-pass filter has a low-pass input connected to the node and a low-pass output connected to the comparator input. Here, the comparator output can form the output of the identification circuit. Using a low-pass filter before the comparator limits the input bandwidth and thus reduces the sensitivity of the identification circuit. Rapid load switching, especially capacitive load switching, temporarily causes strong modulation at the nodes between amplifier stages. The identification circuit may temporarily respond to this. In this case, the low-pass filter prevents the identification circuit from being triggered.

[0020] In a further extension of the invention, the low-pass filter is constructed as a first-order RC filter.

[0021] Advantageously, if the comparator constructed as a window comparator has two comparator elements and a digital gate of type NAND or AND, where the output of the digital gate forms the output of the window comparator. The two comparator elements are used to set the upper and lower limits for identifying the circuit response. The upper and lower thresholds for the window comparator are specified by the corresponding reference inputs of the comparator elements. When the signal applied at the node, filtered by the low-pass filter, exceeds the upper threshold, the corresponding comparator output switches from logic "1" to "0". When the signal applied at the node, filtered by the low-pass filter, is below the lower threshold, the corresponding comparator output switches from logic "1" to "0". The inputs of the digital gate are connected to the outputs of the two comparator elements. Depending on the definition, exceeding or falling below the upper or lower threshold (which corresponds to an error) can then be encoded as a digital output state "1" or "0". NAND or AND gates are particularly suitable for this purpose.

[0022] In an advantageous embodiment of the invention, the signal amplifier has more than two amplifier stages. In this case, the node connected to the comparator input is arranged between the penultimate amplifier stage and the last amplifier stage. Attached Figure Description

[0023] Further details, features, and advantages of the invention will become apparent from the following description of embodiments with reference to the accompanying drawings. Wherein it is shown that:

[0024] Figure 1 A device having a four-stage signal amplifier constructed as a voltage signal amplifier and an error detection circuit integrated into a single semiconductor chip.

[0025] Figure 2 Circuit diagram of error identification circuit and

[0026] Figure 3 An embodiment of a device having a two-stage signal amplifier constructed as a voltage signal amplifier. Detailed Implementation

[0027] Figure 1A block diagram of a first embodiment of a device, generally labeled 1, is shown. This device has a signal amplifier 2 integrated into a single semiconductor chip. The signal amplifier has an amplifier input E for applying a variable input signal, an amplifier output A for outputting an output signal, and an error identification circuit 3 for identifying erroneous modulation of the output signal due to errors in the wiring of the integrated circuit. Between the amplifier input E and the amplifier output A, the signal amplifier 2 has a feedback network having a first feedback impedance 4 and a second feedback impedance 5 connected in series with the first feedback impedance.

[0028] Signal amplifier 2 has four amplifier stages 6, 7, 8, and 9 connected in series, each with inputs and outputs 10, 11, 12, and 13. The amplifier input E is connected to the input of the first amplifier stage 6 via a first feedback impedance 4. The output 10 of the first amplifier stage 6 is connected to the input of the second amplifier stage 7. The output 11 of the second amplifier stage 7 is connected to the input of the third amplifier stage 8, and the output 12 of the third amplifier stage is connected to the input of the fourth amplifier stage 9 via node 14. The output 13 of the fourth amplifier stage 9 is connected to the amplifier output A of signal amplifier 2 and is also connected to the input of the first amplifier stage 6 via a second feedback impedance 5. Node 14 is connected to the signal tap section S of the error identification circuit 3.

[0029] like Figure 2 As can be identified, the error recognition circuit 3 has a low-pass filter 15 and a comparator 16 configured as a window comparator. The low-pass filter 15 includes a resistor R. TP and capacitor C TP The comparator input 17 of comparator 16 is connected to the threshold monitoring resistor R. TP The signal tap section S of the error identification circuit 3 is connected and passes through capacitor C. TP The comparator 16 is connected to a terminal for a reference potential. It includes two comparator elements 18 and 19 configured as operational amplifiers and a NAND gate 20. The first comparator element 18 has a first inverting comparator element input, which is connected to the comparator input 17 of the window comparator 16 and the non-inverting comparator element input of the second comparator element 19. The non-inverting comparator element input O of the first comparator element 18 is connected to a feeder for the upper threshold (not shown in detail), and the inverting comparator element input U of the second operational amplifier 19 is connected to a feeder for the lower threshold (not shown in detail). The upper and lower thresholds define a tolerance range within which the voltage at comparator input 17 is allowed to be within this tolerance range during error-free operation of the signal amplifier 2.

[0030] If the potential at comparator input 17 is higher than the upper threshold, a first voltage corresponding to logic value 0 is applied to the output of the first comparator element 18. If the potential at comparator input 17 is lower than the upper threshold, a second voltage corresponding to logic value 1 is applied to the output of the first comparator element 18.

[0031] In a corresponding manner, when the potential at comparator input 17 is higher than the lower threshold potential, a second voltage (logic 1) is applied to the output of the second comparator element 19. If the potential at comparator input 17 is lower than the lower threshold potential, a first voltage corresponding to the logic value 0 is applied to the output of the second comparator element 19.

[0032] The output of the first comparator element 18 is connected to the first input of the NAND gate 20, and the output of the second operational amplifier 19 is connected to the second input of the NAND gate 20. The output F of the NAND gate 20 forms the output of the error identification circuit 3. During operation of the device 1, a signal is emitted at the output F indicating whether the potential at the comparator input 17 is within the tolerance range defined by the lower threshold and the upper threshold.

[0033] If the potential applied at comparator input 17 exceeds the potential at comparator element input O or falls below the potential at comparator element input U, the signal at output F transitions from logic 0 to 1. If the potential applied at comparator input 17 is within the tolerance range defined by the potentials applied at comparator element inputs O and U, output F is at logic 0.

[0034] Figure 3 A second embodiment of the device 1' according to the invention is shown, the device having a two-stage signal amplifier 2' having an amplifier input E and an amplifier output A. In this embodiment, the amplifier input E is connected to the inverting input of the first amplifier stage 6' via a first feedback impedance 4' and to the output A of the signal amplifier 2' via a second feedback impedance 5'. The non-inverting input of the first amplifier stage 6' is at a reference potential Ref.

[0035] The output 10 of the first amplifier stage 6' is connected to node 14' and to the inverting input of the second amplifier stage 7'. The non-inverting input of the second amplifier stage 7' is at the reference potential Ref.

[0036] The output 11 of the second amplifier stage 7' is connected to the amplifier output A of the signal amplifier 1 and is connected to the inverting input of the first amplifier stage 6' via the second feedback impedance 5'. The feedback network formed by the feedback impedances 4' and 5' generates a feedback coefficient R1 / (R1+R2) and configures the device as an inverting amplifier.

[0037] Node 14' and Figure 2The signal tap S of the error identification circuit 3 shown is connected. This corresponds to... Figure 1 The error identification circuit 3 of the first embodiment is depicted. In this regard, the description of the first embodiment is correspondingly applicable to the second embodiment.

[0038] It should also be noted that the device according to the invention can also be constructed using bipolar or BiCMOS circuit technology. In some cases, the comparator is implemented as a current comparator rather than a voltage comparator.

Claims

1. A device (1, 1') having a signal amplifier (2, 2') integrated in a semiconductor chip, the signal amplifier having an amplifier input (E) for an input signal and an amplifier output (A) for an output signal, wherein the signal amplifier (2, 2') has at least two amplifier stages (6, 6', 7, 7', 8, 9) connected in series between the amplifier input (E) and the amplifier output (A) and a feedback network disposed between the amplifier input (E) and the amplifier output (A), and the device having an error identification circuit (3) integrated in the semiconductor chip for identifying erroneous modulation of the output signal due to an error in the wiring of the integrated circuit, wherein the error identification circuit has a comparator (16) designed to compare a comparator input signal with a predetermined tolerance value or tolerance range, the comparator input signal being applied at a comparator input (17) of the comparator (16), characterized in that, The comparator input (17) of the comparator (16) is connected to the node (14, 14') of the signal amplifier (2, 2') arranged between two amplifier stages (6, 6', 7, 7', 8, 9), and the signal amplifier (2, 2') is designed to output a signal that is more strongly modulated than the input signal at the node (14, 14').

2. The device (1, 1') according to claim 1, characterized in that, The comparator (16) is designed as a window comparator.

3. The device (1, 1') according to claim 1 or 2, characterized in that, The comparator (16) includes at least one comparator element (18, 19) having an inverting comparator element input and a non-inverting comparator element input, one of the comparator element inputs being connected to the comparator input (17) and the other comparator element input being connected to a threshold value supplier, through which a threshold value signal can be applied to the aforementioned comparator element input, and the threshold value supplier having means for dynamically adapting the threshold value signal to the temperature and / or the amplitude of the input signal.

4. The device (1, 1') according to any one of claims 1 to 3, characterized in that, The error identification circuit has a low-pass filter (15).

5. The device (1, 1') according to claim 4, characterized in that, The low-pass filter (15) has a low-pass input connected to the node (14, 14') and a low-pass output connected to the comparator input (17), and the output of the comparator (16) preferably forms the output (F) of the identification circuit.

6. The device (1, 1') according to claim 4 or 5, characterized in that, The low-pass filter (15) is designed as a first-order RC filter.

7. The device (1, 1') according to any one of claims 2 to 6, characterized in that, The comparator (16), designed as a window comparator, has two comparator elements (18, 19) and a digital gate, preferably an AND gate or a NAND gate, and the output of the digital gate forms the output of the window comparator (16).

8. The device (1, 1') according to any one of claims 1 to 7, characterized in that, The signal amplifier (2) has more than two amplifier stages (6, 6', 7, 7', 8, 9), and the node (14, 14') connected to the comparator input (17) is arranged between the penultimate amplifier stage (8) and the last amplifier stage (9).

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