An operational amplifier and current sensing circuit for high speed current sensing

Abstract

The present disclosure provides an operational amplifier and a current detection circuit for high-speed current detection, which comprises a differential input structure, an amplification structure, an output structure, a first compensation capacitor and a second compensation capacitor, a first slew rate enhancement circuit and a second slew rate enhancement circuit, respectively coupled between the output structure and two different compensation capacitors, for injecting a transient enhancement current into the compensation capacitors when a differential input signal occurs a positive jump or a negative jump. By introducing the slew rate enhancement circuit, the present disclosure adopts a Cascade structure compared with a traditional five-tube operational amplifier structure, and uses a rail-to-rail structure at the input end to ensure that the circuit can have full-swing input. When the input common-mode voltage of the operational amplifier is too low or too high, the slew rate enhancement circuit can ensure the normal operation of the circuit to continuously supply power to the compensation capacitor, while maintaining high gain, high common-mode rejection ratio and high power supply rejection ratio, and greatly improving the large signal transient response capability.

Description

Technical Field

[0001] This disclosure relates to the field of current detection technology, and more particularly to an operational amplifier and current detection circuit and electronic device for high-speed current detection. Background Technology

[0002] In current sensing circuits, the sensing resistor can be placed on the high-side or low-side of the load. Therefore, current sensing circuits are correspondingly divided into two methods: high-side current sensing and low-side current sensing. In both high-side and low-side current sensing circuits, the operational amplifier is the core component for achieving accurate and stable current measurement. It extracts the weak voltage signal across the sampling resistor through a differential amplification structure, while suppressing high-voltage common-mode interference in high-side sensing or ground noise in low-side sensing, ensuring that the output signal accurately reflects the actual current. Especially in high-side sensing, the operational amplifier needs to accurately capture millivolt-level differential signals against the power supply voltage background, requiring extremely high common-mode rejection ratio and input stage linearity. Therefore, its performance directly determines the accuracy and reliability of the entire sensing system.

[0003] Existing current sensing systems suffer from problems such as dynamic response lag, large signal distortion, and transient measurement errors in applications such as high-frequency switching power supplies, motor drives, or rapid load changes due to insufficient op-amp slew rate. Although techniques such as self-zeroing and chopping in current sensing technology can effectively suppress DC offset and low-frequency noise and improve static accuracy, if the amplifier slew rate is limited, it is still unable to accurately reproduce the rapid changes of current signals with high dI / dt characteristics, thus severely weakening the overall measurement fidelity and real-time performance of the system. Summary of the Invention

[0004] The purpose of this disclosure is to provide an operational amplifier and current detection circuit and electronic device for high-speed current detection, so as to solve the problems existing in the prior art.

[0005] The embodiments of this disclosure adopt the following technical solution: an operational amplifier for high-speed current detection, characterized in that it includes a differential input structure, an amplification structure, an output structure, a first compensation capacitor, and a second compensation capacitor, and further includes: a first slew rate enhancement circuit and a second slew rate enhancement circuit, respectively coupled between the output structure and the two different compensation capacitors, for injecting transient enhancement current into the compensation capacitors when the differential input signal undergoes a positive or negative transition; wherein, both the first slew rate enhancement circuit and the second slew rate enhancement circuit include: a differential detection unit, configured to generate input currents with different distribution ratios according to the transition of the differential input signal; a compensation bias unit, configured to generate a first control voltage according to the input current when the differential input signal is static, and to generate a second control voltage according to the input current when the differential input signal is dynamic; a controllable switch unit, connected between the compensation capacitor and a fixed potential terminal, configured to remain off according to the first control voltage to cut off the leakage path of the compensation capacitor; and remain on according to the second control voltage to inject transient enhancement current into the compensation capacitor.

[0006] In some embodiments, according to claim 1, the operational amplifier is characterized in that the differential detection unit comprises: a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; wherein the sources of the first PMOS transistor and the second PMOS transistor are both connected to a first wake source, the gate of the first PMOS transistor is connected to the inverting input terminal of the operational amplifier, and the gate of the second PMOS transistor is connected to the non-inverting input terminal of the operational amplifier; the sources of the first NMOS transistor and the second NMOS transistor are both connected to a second wake source, the gate of the first NMOS transistor is connected to the non-inverting input terminal of the operational amplifier, and the gate of the second NMOS transistor is connected to the inverting input terminal of the operational amplifier.

[0007] In some embodiments, the aspect ratio of the first PMOS transistor is smaller than that of the second PMOS transistor, and the aspect ratio of the first NMOS transistor is greater than that of the second NMOS transistor.

[0008] In some embodiments, the compensation bias unit includes: a third PMOS transistor to a sixth PMOS transistor, and a third NMOS transistor to a sixth NMOS transistor; wherein the sources of the third PMOS transistor and the fourth PMOS transistor are both connected to the operating voltage, the drain of the third PMOS transistor is connected to the source of the fifth PMOS transistor and the drain of the second NMOS transistor, the drain of the fourth PMOS transistor is connected to the source of the sixth PMOS transistor and the drain of the first NMOS transistor, the drain of the fifth PMOS transistor is connected to the third NMOS transistor and leads out the output terminal of the control voltage, and the drain of the sixth PMOS transistor is connected to the drain of the fourth NMOS transistor and simultaneously connected to the third PMOS transistor. The gates of the MOS transistor and the fourth PMOS transistor, the gates of the fifth PMOS transistor and the sixth PMOS transistor are all connected to a third bias voltage. The source of the third NMOS transistor is connected to the drain of the fifth NMOS transistor and the drain of the first PMOS transistor. The source of the fourth NMOS transistor is connected to the drain of the sixth NMOS transistor and the drain of the second PMOS transistor. The gates of the third NMOS transistor and the fourth NMOS transistor are all connected to a second bias voltage. The sources of the fifth NMOS transistor and the sixth NMOS transistor are grounded. The gates of the fifth NMOS transistor and the sixth NMOS transistor are all connected to a first bias voltage.

[0009] In some embodiments, the controllable switching unit includes: a seventh NMOS transistor to a tenth NMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor; wherein the sources of the seventh PMOS transistor and the eighth PMOS transistor are connected to the operating voltage, the drain of the seventh PMOS transistor serves as the output terminal of the slew rate enhancement circuit and is connected to one side plate of the compensation capacitor, the drain of the eighth PMOS transistor is shorted to its gate and connected to the gate of the seventh PMOS transistor and the drain of the seventh NMOS transistor, the source of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor, the gate of the eighth NMOS transistor is shorted to its drain and connected to the gate of the tenth NMOS transistor, the sources of the tenth NMOS transistor and the eighth NMOS transistor are both grounded, the drain of the tenth NMOS transistor is connected to the source of the ninth NMOS transistor, and the drain of the ninth NMOS transistor is shorted to its gate and connected to the output terminal of the control voltage and the gate of the seventh NMOS transistor.

[0010] In some embodiments, the differential input signal includes a main input signal and an auxiliary input signal. The first slew rate enhancement circuit is used to inject transient enhancement current into the first compensation capacitor when the main input differential signal undergoes a positive or negative transition. The second slew rate enhancement circuit is used to inject transient enhancement current into the second compensation capacitor when the auxiliary input differential signal undergoes a positive or negative transition.

[0011] In some embodiments, the differential input structure is a folded cascode structure, and the output structure is a Class AB output structure based on a transconducting linear loop.

[0012] In some embodiments, the folded cascode structure includes a primary differential NMOS input pair and an auxiliary differential PMOS input pair, forming a rail-to-rail input structure.

[0013] This disclosure also provides a current detection circuit, which includes at least the operational amplifier described above.

[0014] This disclosure also provides an electronic device, which includes at least the current detection circuit described above.

[0015] The beneficial effects of the embodiments disclosed herein are as follows: by introducing a slew rate enhancement circuit, compared with the traditional five-transistor operational amplifier structure, a Cascade structure is adopted, and a rail-to-rail structure is used at the input end to ensure that the circuit can input with full swing. Therefore, when the input common-mode voltage of the operational amplifier is too low or too high, the slew rate enhancement circuit can ensure the normal operation of the circuit and continuously supply power to the compensation capacitor. While maintaining high gain, high common-mode rejection ratio and high power supply rejection ratio, it significantly improves its large-signal transient response capability, ensuring that it can still track rapidly changing current signals without distortion in noisy environments where the switching frequency reaches hundreds of kilohertz or even megahertz. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in one or more embodiments of this specification or in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a low-side current detection circuit in the existing technology; Figure 2 This is a high-side current detection circuit in the existing technology; Figure 3 This is a type of slewing rate enhancement structure in the prior art; Figure 4 This is another slew rate enhancement structure in the prior art; Figure 5 This is a circuit diagram of the slew rate enhancement circuit in the first embodiment of this disclosure; Figure 6 This is a circuit diagram of the operational amplifier in the first embodiment of this disclosure. Detailed Implementation

[0018] To enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the technical solutions in one or more embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, and not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this document.

[0019] In current sensing circuits, the sensing resistor can be placed on the high side or low side of the load. Therefore, current sensing circuits are divided into two methods: high-side current sensing and low-side current sensing. A typical current sensing circuit mainly consists of a sensing resistor Rsense, a system load (SystemLoad), a power supply VDD, and a current sense amplifier (CSA). Its working principle is as follows: When the system load consumes current, a differential voltage signal is generated across the sensing resistor Rsense; the CSA samples this differential voltage signal, amplifies it by a certain factor, and outputs it to the ADC; the ADC converts the analog voltage signal processed by the CSA into a digital signal and outputs it; finally, the MCU receives this digital signal for subsequent data processing.

[0020] like Figure 1 As shown, the low-side current sensing circuit places the sensing resistor Rsense between the system load and ground. This connection method is simple in structure and low in cost. However, because Rsense is located below the load, the load-to-ground reference fluctuates with the current, affecting system stability. Simultaneously, the sensing resistor is susceptible to coupling noise from ground, reducing current sensing accuracy. Furthermore, if a short circuit occurs in the system load, the current sensing function will fail. Figure 2 As shown, the high-side current sensing circuit places the sensing resistor Rsense between the power supply VDD and the system load, effectively avoiding detection failure caused by load short circuits and is unaffected by ground coupling noise, thus achieving higher detection accuracy. However, when Rsense is placed at the power supply terminal, the common-mode input voltage of the CSA must match the power supply voltage. In high-voltage power supply systems, this requires the CSA to have a wide common-mode input range (ICMR), increasing its design complexity and process requirements.

[0021] In high-side and low-side current detection circuits, operational amplifiers (op-amps) are the core components for achieving accurate and stable current measurement. They extract the weak voltage signal across the sampling resistor through a differential amplification structure, while suppressing high-voltage common-mode interference in high-side detection or ground noise in low-side detection, ensuring the output signal accurately reflects the actual current. Especially in high-side detection, the op-amp needs to accurately capture millivolt-level differential signals against the power supply voltage background, requiring extremely high common-mode rejection ratios and input stage linearity. Therefore, its performance directly determines the accuracy and reliability of the entire detection system. From a speed perspective, the op-amp's bandwidth, slew rate, and settling time are crucial. Modern power systems operate at increasingly higher frequencies, with rapid current changes, requiring op-amps to respond to transient changes in real time. Insufficient op-amp speed can lead to signal delay, distortion, or delayed protection actions, failing to promptly cut off the circuit in case of overcurrent or short circuit, potentially damaging power devices. Therefore, high-speed op-amps not only improve dynamic response capabilities but also ensure efficient coordination with ADC sampling or digital controllers, providing a key guarantee for achieving rapid protection and high-precision closed-loop control.

[0022] Miller compensation is typically added to amplifiers to ensure circuit stability, but the capacitor needs to be continuously charged and discharged during signal conversion. Since charge accumulation across the capacitor takes time, the voltage across the capacitor cannot change abruptly, increasing the signal conversion time and reducing the conversion rate. When the signal output needs to achieve a change higher than the slew rate, the op-amp cannot provide it, causing the output waveform to change from a sine wave to a triangular wave, resulting in signal distortion. Because the op-amp's slew rate is mainly limited by the Miller capacitor in the second stage, the key to solving the slew rate problem in high-speed op-amps lies in the Miller capacitor. Reducing the value of the Miller capacitor can speed up the charging and discharging speed, but this results in a reduced phase margin and system instability. Another way to reduce the charging and discharging time is to increase the charging and discharging current, accelerating the accumulation of charge across the capacitor and increasing the op-amp's conversion rate; however, blindly increasing the current will cause excessive overall power consumption. Using a transient enhancement structure to improve the op-amp's slew rate increases the op-amp's response speed.

[0023] Figure 3 This diagram illustrates a slew rate enhancement structure used in the prior art, where the width-to-length ratio of MP1 to MP2 is 7:1. In steady state, the current shared by MP1 and MP2 is 7:1. When a large signal rises at the positive input, the current in MP1 decreases and flows instead to MP2. After passing through the current mirror of MN1, the current charges the Miller compensation capacitor. However, Figure 3In steady state, the MP1 and MP2 transistors will shunt currents, with current constantly flowing from MP2 to MN2. MN1 will be in the subthreshold region, which will cause capacitor leakage and affect the stability of the op-amp system. Furthermore, when the input voltage changes significantly, it cannot provide enough current for the circuit to quickly complete the signal conversion.

[0024] Figure 4 This diagram illustrates another prior art slew rate enhancement structure, in which a set of tail current sources is connected to MN3 to generate a reference voltage V. GS MN3 and MN2 are connected as a current mirror, and MN3 ensures V GS3 >V th MN2 remains in the saturation region. GS1 =V DS2 When the source-drain voltage of MN2 remains constant, MN1 is in the cutoff region. When V INP <V INN At that time, MP1 receives most of the tail current source current, and the current flowing into MN2 through MP2 decreases, V DS2 As V decreases, MN1 remains in the cutoff state. INP >V INN At that time, most of the tail current source current flows into MP2 and then into MN2, causing MN2 to experience V. DS Rapidly increase, i.e., the V of tube MN1 GS The increase in current causes MN1 to generate a large current to charge the Miller compensation capacitor. However, when... Figure 4 After the negative input voltage rises following the positive input voltage, the drain voltage of MN2 is V. INN +|V GS |+V DS Even with a significant voltage drop between the source and drain of MP2, it's impossible to prevent the drain voltage of MN2 from increasing compared to when the input is 0V, i.e., the V of MN1... GS The voltage rises to near the threshold voltage, causing MN1 to remain in the subthreshold region. When the input negative terminal voltage of MN1 increases, it can cause capacitor leakage, affecting the stability of the op-amp system and leading to circuit oscillations. Furthermore, because the circuit uses a five-transistor op-amp structure, it cannot achieve full-swing slew rate enhancement for the preamplifier; when the input voltage is too low or too high, this slew rate enhancement circuit will not function.

[0025] Although techniques such as self-zeroing and chopping in current sensing technology can effectively suppress DC offset and low-frequency noise, improving static accuracy, if the amplifier's slew rate is limited, it still cannot accurately reproduce the rapid changes of current signals with high dI / dt characteristics, thus severely weakening the overall measurement fidelity and real-time performance of the system. Furthermore, traditional slew rate enhancement circuits use a five-transistor operational amplifier structure, preventing the circuit from achieving full-amplitude slew rate enhancement of the preamplifier. Therefore, to address the problems of dynamic response lag, large-signal distortion, and transient measurement errors caused by insufficient operational amplifier slew rate in existing current sensing systems for applications such as high-frequency switching power supplies, motor drives, or rapid load changes, this embodiment proposes an operational amplifier for high-speed current sensing.

[0026] In this embodiment, the operational amplifier OA structure includes a differential input structure, an amplification structure, an output structure, and two compensation capacitors, namely a first compensation capacitor and a second compensation capacitor. It also includes a first slew rate enhancement circuit and a second slew rate enhancement circuit with the same circuit structure. The two symmetrically arranged slew rate enhancement circuits are coupled between the two different compensation capacitors and the output structure, respectively. That is, the first slew rate enhancement circuit is connected between the first compensation capacitor and the output terminal Vout, and the second slew rate enhancement circuit is connected between the second compensation capacitor and the output terminal Vout, so as to inject transient enhancement current into the compensation capacitor when the differential input signal undergoes a positive or negative transition. To achieve rail-to-rail input of the op-amp, this embodiment divides the differential input signal into a main input signal (VINN and VINP) and an auxiliary input signal (VFN and VFP). This ensures that the op-amp's input common-mode voltage range covers the entire power supply voltage range from the negative power supply rail (usually GND) to the positive power supply rail (usually VDD). Furthermore, to synchronize the response of the transient boost current, this embodiment utilizes a first slew rate enhancement circuit to generate a transient boost current injected into the first compensation capacitor based on the transition of the main input signal. The second slew rate enhancement circuit is used to generate a transient boost current based on the transition of the auxiliary input signal and inject it into the second compensation capacitor.

[0027] Specifically, each slew rate enhancement circuit includes the following structure: a differential detection unit configured to generate input currents with different distribution ratios according to the transition of the differential input signal; a compensation bias unit configured to generate a first control voltage based on the input current when the differential input signal is static, and to generate a second control voltage based on the input current when the differential input signal is dynamic; and a controllable switch unit connected between the compensation capacitor and the fixed potential terminal, configured to remain off according to the first control voltage to cut off the leakage path of the compensation capacitor; and to remain on according to the second control voltage to inject transient enhancement current into the compensation capacitor.

[0028] Specifically, Figure 5 The circuit diagram of the slew rate enhancement circuit in this embodiment is shown. The differential detection unit includes: a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, and a second NMOS transistor MN2. The sources of both the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected to a first wake source I1. The gate of the first PMOS transistor MP1 is connected to the inverting input terminal VINN of the operational amplifier, and the gate of the second PMOS transistor MP2 is connected to the non-inverting input terminal VINP of the operational amplifier. The sources of both the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected to a second wake source I2. The gate of the first NMOS transistor MN1 is connected to the non-inverting input terminal VINP of the operational amplifier, and the gate of the second NMOS transistor MN2 is connected to the inverting input terminal VINN of the operational amplifier.

[0029] The compensation bias unit includes: third PMOS transistors MP3 to MP6, and third NMOS transistors MN3 to MN6; wherein the sources of third PMOS transistors MP3 and fourth PMOS transistors MP4 are both connected to the operating voltage VDD; the drain of third PMOS transistor MP3 is connected to the source of fifth PMOS transistor MP5 and the drain of the second NMOS transistor; the drain of fourth PMOS transistor MP4 is connected to the source of sixth PMOS transistor MP6 and the drain of first NMOS transistor MN1; the drain of fifth PMOS transistor MP5 is connected to third NMOS transistor MN3 and leads out the output terminal of the control voltage; the drain of sixth PMOS transistor MP6 is connected to the drain of fourth NMOS transistor MN4 and simultaneously connected to third PMOS transistor MN6. The gates of P3 and the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6 are all connected to a third bias voltage Vb2. The source of the third NMOS transistor MN3 is connected to the drain of the fifth NMOS transistor MN5 and the drain of the first PMOS transistor MP1. The source of the fourth NMOS transistor MN4 is connected to the drain of the sixth NMOS transistor MN6 and the drain of the second PMOS transistor MP2. The gates of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are all connected to a second bias voltage Vb1. The sources of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are grounded. The gates of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are all connected to a first bias voltage Vb0. In this embodiment, the first, second, and third bias voltages are three sets of independent external constant bias voltages, and their specific magnitudes are determined based on the width-to-length ratio of the corresponding switching transistors.

[0030] The controllable switching unit includes: the seventh NMOS transistor MN7 to the tenth NMOS transistor MN10, the seventh PMOS transistor MP7, and the eighth PMOS transistor MP8; wherein, the sources of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 are connected to the operating voltage, the drain of the seventh PMOS transistor MP7 is connected to one side plate of the compensation capacitor C as the output terminal of the slew rate enhancement circuit, the drain of the eighth PMOS transistor MP8 is shorted to the gate and connected to the gate of the seventh PMOS transistor MP7 and the drain of the seventh NMOS transistor MN7, the source of the seventh NMOS transistor MN7 is connected to the drain of the eighth NMOS transistor MN8, the gate of the eighth NMOS transistor MN8 is shorted to the drain and connected to the gate of the tenth NMOS transistor MN10, the sources of the tenth NMOS transistor MN10 and the eighth NMOS transistor MN8 are both grounded, the drain of the tenth NMOS transistor MN10 is connected to the source of the ninth NMOS transistor MN9, and the drain of the ninth NMOS transistor MN9 is shorted to the gate and connected to the output terminal of the control voltage and the gate of the seventh NMOS transistor MN7.

[0031] In this embodiment, the aspect ratio of MP1 is smaller than that of MP2, and the aspect ratio of MN1 is larger than that of MN2. This allows the current of MP1 to decrease and the current of MP2 to increase in the static state. The currents of MN5 and MN6 are equal and remain unchanged, thus the current of MN4 decreases, the gate-source voltage of MP4 decreases, the current of MP3 decreases, and the current of MN3 increases. However, through the channel length modulation effect, the currents of MP5 and MN3 become equal, therefore the drain voltage of MP5 decreases, causing MN9 to turn off. The turn-off of MN9 ensures that the slew rate high-strength circuit will not cause leakage current in the operational amplifier's compensation capacitor in the static state, affecting circuit stability and preventing circuit oscillation.

[0032] During dynamic detection, based on the practical application of op-amps in current detection, when the VINP voltage is greater than the VINN voltage, the MP1 current increases and the MP2 current decreases. The currents of MN5 and MN6 are equal and unchanged, so the MN4 current increases, the gate-source voltage of MP4 increases, the MP3 current increases, and the drain voltage of MP5 increases, causing MN9 to turn on and the current mirrors of MP7 and MP8 to work, thereby charging the compensation capacitor and enhancing the slew rate of the op-amp. Compared with the traditional five-transistor op-amp structure, the slew rate enhancement circuit in this embodiment adopts a Cascade structure and uses a rail-to-rail structure at the input to ensure that the circuit can input the full swing. Therefore, when the input common-mode voltage of the op-amp is too low or too high, the slew rate enhancement circuit can ensure the normal operation of the circuit and continuously supply power to the compensation capacitor, so as to ensure that the rapidly changing current signal can still be tracked without distortion in a noise environment with a switching frequency of hundreds of kilohertz or even megahertz.

[0033] In actual setup, the width-to-length ratio of MP1 and MP2 can be adjusted according to the accuracy requirements of current detection, and the width-to-length ratio of MN1 and MN2 should be the reciprocal of the width-to-length ratio of MP1 and MP2 to ensure the balance of circuit output. The width-to-length ratio of the remaining transistors in the slew rate enhancement circuit can be determined according to the conventional design requirements of the Cascade structure and current mirror; this embodiment does not impose specific limitations.

[0034] Figure 6 The circuit diagram of the operational amplifier in this embodiment is shown. Operational amplifier OA employs a folded cascode differential structure, offering advantages such as high speed, low noise, and low power consumption, while providing a wider common-mode input range. The main input terminal uses a differential NMOS structure, and the auxiliary input terminal uses a differential PMOS structure, together forming a rail-to-rail input stage. The output terminal adopts a Class AB structure based on a transcontinental linear loop. This structure maintains extremely low quiescent power consumption while providing strong dynamic drive capability, achieving rail-to-rail output, and significantly suppressing the influence of common-mode input voltage on the output. It balances the small quiescent current with the ultra-large dynamic output current, thereby improving the output stage efficiency. Simultaneously, when a transistor is turned off, the minimum bias current can maintain its bias state, helping to shorten the turn-on time and reduce crossover distortion. During the operation of the Class AB output stage, this mechanism is crucial for maintaining a constant voltage difference between the two output transistors.

[0035] Furthermore, the first slew rate enhancement circuit 10 is located in Figure 6 The upper part is where the main input signals (VINN and VINP) are located, and the second slew rate enhancement circuit 20 is located in... Figure 6 The lower part uses auxiliary input signals (VFN and VFP). The above design achieves a rail-to-rail structure to ensure full-swing input. When the op-amp's input common-mode voltage is too low or too high, both slew rate enhancement circuits can ensure normal circuit operation and continuously supply power to the compensation capacitor. It should be noted that... Figure 6 Compared to the first slew rate enhancement circuit 10, the second slew rate enhancement circuit 20 lacks a set of PMOS current mirrors (corresponding to P14 and P15 in the first slew rate enhancement circuit 10). The main function of this current mirror is to replicate the transient enhancement current for injection into the compensation capacitor. The second slew rate enhancement circuit 20 omits this component, directly injecting the transient enhancement current output from the drain of N22 into the second compensation capacitor, thus omitting the current mirror replication operation. Furthermore, Figure 6 The wake source in the circuit is represented by transistors P16, N23, P23, and N32, which actually play a role in the circuit as... Figure 5 The mid-tail current sources I1 and I2 are the same.

[0036] This embodiment introduces a slew rate enhancement circuit, which adopts a Cascade structure compared to the traditional five-transistor operational amplifier structure. A rail-to-rail structure is used at the input to ensure that the circuit can receive inputs with full swing. Therefore, when the input common-mode voltage of the operational amplifier is too low or too high, the slew rate enhancement circuit can ensure the normal operation of the circuit and continuously supply power to the compensation capacitor. While maintaining high gain, high common-mode rejection ratio and high power supply rejection ratio, it significantly improves its large-signal transient response capability, ensuring that it can still track rapidly changing current signals without distortion in noisy environments with switching frequencies reaching hundreds of kilohertz or even megahertz.

[0037] Based on the same inventive concept, the second embodiment of this disclosure provides a current detection circuit, which includes at least the operational amplifier described in the first embodiment of this disclosure to achieve high-speed and accurate current detection. The current detection circuit may also include supporting components such as a detection resistor and a system load, or other functional modules may be provided according to actual current detection requirements; this embodiment does not impose any limitations.

[0038] Based on the same inventive concept, the third embodiment of this disclosure provides an electronic device, which includes at least the current detection circuit of the second embodiment of this disclosure.

[0039] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. An operational amplifier for high speed current sensing, characterized by, The system includes a differential input structure, an amplification structure, an output structure, a first compensation capacitor, and a second compensation capacitor. Its distinguishing feature is that it further includes a first slew rate enhancement circuit and a second slew rate enhancement circuit, respectively coupled between the output structure and the two different compensation capacitors, for injecting transient enhancement current into the compensation capacitors when the differential input signal undergoes a positive or negative transition; wherein both the first slew rate enhancement circuit and the second slew rate enhancement circuit include: The differential detection unit is configured to generate input currents with different distribution ratios based on the transitions of the differential input signal; The compensation bias unit is configured to generate a first control voltage based on the input current when the differential input signal is static, and to generate a second control voltage based on the input current when the differential input signal is dynamic. A controllable switching unit, connected between the compensation capacitor and the fixed potential terminal, is configured to remain off according to the first control voltage to cut off the leakage path of the compensation capacitor; and to remain on according to the second control voltage to inject transient boost current into the compensation capacitor.

2. The operational amplifier of claim 1, wherein, The differential detection unit includes: a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; wherein... The sources of both the first PMOS transistor and the second PMOS transistor are connected to the first wake source. The gate of the first PMOS transistor is connected to the inverting input terminal of the operational amplifier, and the gate of the second PMOS transistor is connected to the non-inverting input terminal of the operational amplifier. The sources of both the first NMOS transistor and the second NMOS transistor are connected to a second wake source. The gate of the first NMOS transistor is connected to the non-inverting input of the operational amplifier, and the gate of the second NMOS transistor is connected to the inverting input of the operational amplifier.

3. The operational amplifier of claim 2, wherein, The width-to-length ratio of the first PMOS transistor is smaller than that of the second PMOS transistor, and the width-to-length ratio of the first NMOS transistor is greater than that of the second NMOS transistor.

4. The operational amplifier of claim 3, wherein, The compensation bias unit includes: a third PMOS transistor to a sixth PMOS transistor, and a third NMOS transistor to a sixth NMOS transistor; wherein... The sources of the third and fourth PMOS transistors are both connected to the operating voltage. The drain of the third PMOS transistor is connected to the source of the fifth PMOS transistor and the drain of the second NMOS transistor. The drain of the fourth PMOS transistor is connected to the source of the sixth PMOS transistor and the drain of the first NMOS transistor. The drain of the fifth PMOS transistor is connected to the third NMOS transistor and leads out the output terminal of the control voltage. The drain of the sixth PMOS transistor is connected to the drain of the fourth NMOS transistor and is simultaneously connected to the gates of the third and fourth PMOS transistors. The gate of the fifth PMOS transistor... The third NMOS transistor and the gate of the sixth PMOS transistor are both connected to a third bias voltage. The source of the third NMOS transistor is connected to the drain of the fifth NMOS transistor and the drain of the first PMOS transistor. The source of the fourth NMOS transistor is connected to the drain of the sixth NMOS transistor and the drain of the second PMOS transistor. The gates of the third NMOS transistor and the fourth NMOS transistor are both connected to a second bias voltage. The sources of the fifth NMOS transistor and the sixth NMOS transistor are grounded. The gates of the fifth NMOS transistor and the sixth NMOS transistor are both connected to a first bias voltage.

5. The operational amplifier of claim 4, wherein, The controllable switching unit includes: the seventh to tenth NMOS transistors, the seventh PMOS transistor, and the eighth PMOS transistor; wherein... The sources of the seventh and eighth PMOS transistors are connected to the operating voltage. The drain of the seventh PMOS transistor serves as the output terminal of the slew rate enhancement circuit and is connected to one side plate of the compensation capacitor. The drain of the eighth PMOS transistor is shorted to its gate and connected to the gate of the seventh PMOS transistor and the drain of the seventh NMOS transistor. The source of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor. The gate of the eighth NMOS transistor is shorted to its drain and connected to the gate of the tenth NMOS transistor. The sources of the tenth NMOS transistor and the eighth NMOS transistor are both grounded. The drain of the tenth NMOS transistor is connected to the source of the ninth NMOS transistor. The drain of the ninth NMOS transistor is shorted to its gate and connected to the output terminal of the control voltage and the gate of the seventh NMOS transistor.

6. The operational amplifier of claim 4, wherein, The differential input signal includes a main input signal and an auxiliary input signal. The first slew rate enhancement circuit is used to inject transient enhancement current into the first compensation capacitor when the main input differential signal undergoes a positive or negative transition. The second slew rate enhancement circuit is used to inject transient enhancement current into the second compensation capacitor when the auxiliary input differential signal undergoes a positive or negative transition.

7. The operational amplifier according to any one of claims 1 to 6, characterized by The differential input structure is a folded common-source cascode structure, and the output structure is a Class AB output structure based on a transconducting linear loop.

8. The operational amplifier of claim 7, wherein, The folded cascode structure includes a main differential NMOS input pair and an auxiliary differential PMOS input pair, forming a rail-to-rail input structure.

9. A current sensing circuit, characterized by, It includes at least the operational amplifier described in any one of claims 1 to 8.

10. An electronic device, comprising: It includes at least the current detection circuit as described in claim 9.

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