Multi-bit state race inhibition circuit, sampling circuit, integrated circuit, and method

Abstract

This application provides a multi-bit state contention suppression circuit, a sampling circuit, an integrated circuit, and a method, relating to the field of integrated circuit technology. The multi-bit state contention suppression circuit includes: multiple bit input terminals, a state sensing unit, a global decision unit, a latch output unit, and multiple bit output terminals. The multiple input terminals of the state sensing unit are respectively connected to the multiple bit input terminals and are used to receive multiple bit input signals. The multiple output terminals of the state sensing unit are respectively connected to the multiple input terminals of the global decision unit. The multiple input terminals of the latch output unit are respectively used to receive multiple bit delay signals. The output terminal of the global decision unit is also connected to the latch enable terminal of the latch output unit. The multiple output terminals of the latch output unit are respectively connected to the multiple bit output terminals. This application improves the reliability and robustness of data transmission without increasing system timing constraints.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more specifically, to a multi-bit state contention suppression circuit, a sampling circuit, an integrated circuit, and a method thereof. Background Technology

[0002] In digital circuit systems, multi-bit parallel signal interfaces are widely used in chip configuration, state synchronization, address transmission, and control command issuance. These interfaces require multiple signal pins to switch levels simultaneously and be accurately identified by subsequent circuits as a complete and valid state. However, in actual hardware implementations, due to factors such as different driving capabilities of each signal path, inconsistent trace lengths, load differences, and environmental changes, the level transition times of each bit are not completely synchronized. This results in intermediate states during state transitions, which are easily missampled by subsequent circuits, leading to problems such as logic misjudgments, state machine anomalies, and decoding errors.

[0003] Currently, there are two main methods for suppressing multi-bit state contention. One method uses Gray code encoding, which converts the natural binary code into Gray code where only one bit changes between adjacent states before signal transmission, ensuring that only one signal flips during state transitions. The other method adds a delay filter network consisting of resistors and capacitors to each signal line, adjusting the rising and falling edge shapes of each signal to make them reach a stable state as simultaneously as possible.

[0004] However, Gray code only guarantees single-bit flips between adjacent states; multiple bit flips still occur during non-continuous transitions, failing to eliminate illegal intermediate states. Furthermore, it requires encoding / decoding circuits at both the transceiver and receiver, increasing hardware overhead and signal delay, and necessitates modifications to encoding rules, making it incompatible with existing binary interfaces. Delay filtering relies on matching delay parameters, making it susceptible to influences from component tolerances and environmental factors such as temperature and humidity, leading to inconsistencies in filtering across different paths and exacerbating timing deviations, making it difficult to simultaneously meet the requirements of high reliability and high-speed applications. Summary of the Invention

[0005] The purpose of this application is to address the shortcomings of the prior art by providing a multi-bit state contention suppression circuit, sampling circuit, integrated circuit, and method to improve the reliability and robustness of data transmission without increasing system timing constraints.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: In a first aspect, one embodiment of this application provides a multi-bit state contention suppression circuit, which includes: multiple bit input terminals, a state sensing unit, a global decision unit, a latch output unit, and multiple bit output terminals; The state sensing unit has multiple input terminals connected to multiple bit input terminals respectively, and is used to receive multiple bit input signals respectively. The state sensing unit has multiple first output terminals connected to multiple input terminals of the latch output unit respectively. The state sensing unit has multiple second output terminals connected to multiple input terminals of the global decision unit respectively. The output terminal of the global decision unit is also connected to the latch enable terminal of the latch output unit. The latch output unit has multiple output terminals connected to multiple bit output terminals respectively. The state sensing unit is used to delay each bit input signal to obtain a corresponding bit delay signal, and to perform single-channel signal state decision based on the bit input signal and the corresponding bit delay signal, output the corresponding single-channel state signal, and output multiple single-channel state signals to the global decision unit. The global decision unit is used to make a joint decision based on multiple single-channel status signals and output a global status signal to the latch output unit to enable latching of the latch output unit. The state sensing unit is also used to output the bit delay signal to the latch output unit to provide an input signal to the latch output unit. The latch output unit is used to perform steady-state output and non-steady-state isolation of multiple bit delay signals based on the level value of the global state signal.

[0007] Optionally, the state sensing unit includes: multiple delay detection branches, the input terminals of the multiple delay detection branches being multiple input terminals of the state sensing unit, respectively used to connect to multiple bit input terminals, the first output terminals of the multiple delay detection branches being multiple first output terminals of the state sensing unit, and the second output terminals of the multiple delay detection branches being multiple second output terminals of the state sensing unit.

[0008] Optionally, the delay detection branch includes: a delay unit and an XNOR gate, wherein the input terminal of the delay unit is the input terminal of the delay detection branch, and the output terminal of the delay unit is the first output terminal of the delay detection branch; the output terminal of the delay unit and the corresponding bit input terminal are connected to the two input pins of the XNOR gate, and the output pin of the XNOR gate is the second output terminal of the delay detection branch.

[0009] Optionally, the global decision unit includes a multi-input AND gate, wherein the multiple input pins of the multi-input AND gate are multiple input terminals of the global decision unit, and the output terminal of the multi-input AND gate is the output terminal of the global decision unit.

[0010] Optionally, the latch output unit includes a D-type latch that is enabled by a low level.

[0011] Optionally, if the latch enable pin of the D-type latch is at a high level, the D-type latch is in transparent transmission mode, and the D-type latch transparently outputs the multiple bit delay signals.

[0012] Optionally, if the latch enable pin of the D-type latch is at a low level, the D-type latch is in latch-and-hold mode, and the D-type latch latches multiple bit delay signals.

[0013] Secondly, another embodiment of this application provides a multi-bit sampling circuit, the multi-bit sampling circuit including: a multi-bit state contention suppression circuit, and a target chip, wherein multiple bit output terminals of the multi-bit state contention suppression circuit are respectively connected to multiple input terminals of the target chip, wherein the multi-bit state contention suppression circuit is any of the multi-bit state contention suppression circuits described in the first aspect above.

[0014] Thirdly, another embodiment of this application provides an integrated circuit, the device comprising: the integrated circuit comprising: a circuit board, and a multi-bit state contention suppression circuit integrated on the circuit board, wherein the multi-bit state contention suppression circuit is any of the multi-bit state contention suppression circuits described in the first aspect above.

[0015] Fourthly, another embodiment of this application provides a multi-bit state contention suppression method, applied to any of the multi-bit state contention suppression circuits described in the first aspect above, the method comprising: Each bit input signal is delayed to obtain the corresponding bit delayed signal; Based on the bit input signal and the corresponding bit delay signal, a single-channel signal state decision is made, and the corresponding single-channel state signal is output. Based on the multiple single-channel status signals, a joint decision is made, and a global status signal is output for latching and enabling. Based on the level value of the global state signal, multiple bit delay signals are latched and output to obtain multiple bit output signals.

[0016] The beneficial effects of this application are: This application provides a multi-bit state contention suppression circuit, a sampling circuit, an integrated circuit, and a method. The multi-bit state contention suppression circuit includes: multiple bit input terminals, a state sensing unit, a global decision unit, a latch output unit, and multiple bit output terminals. The multiple input terminals of the state sensing unit are respectively connected to the multiple bit input terminals and are used to receive multiple bit input signals. The multiple first output terminals of the state sensing unit are respectively connected to the multiple input terminals of the latch output unit. The multiple second output terminals of the state sensing unit are respectively connected to the multiple input terminals of the global decision unit. The output terminal of the global decision unit is also connected to the latch enable terminal of the latch output unit. The multiple output terminals of the latch output unit are respectively connected to the multiple bit output terminals. This circuit, by sensing the dynamic change process of the signal at each input terminal and summarizing the local stability information of each bit input signal into a global judgment criterion, achieves accurate identification and coordinated control of the overall stable state of multi-bit data. This allows for the identification and avoidance of transient contention caused by differences in transmission delay, improving the reliability and robustness of data transmission without increasing system timing constraints. At the same time, its latching action is entirely driven by the stable characteristics of the data itself, requiring no additional calibration or external intervention, and has good adaptability to process voltage and temperature. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of a multi-bit state contention suppression circuit provided in an embodiment of this application; Figure 2 A schematic diagram of the structure of a state sensing unit in a multi-bit state contention suppression circuit provided in this application embodiment; Figure 3 A schematic diagram of the delay detection branch in another multi-bit state contention suppression circuit provided in this application embodiment; Figure 4 A schematic diagram of another multi-bit state contention suppression circuit provided in an embodiment of this application; Figure 5 A flowchart illustrating a multi-bit state contention suppression method provided in this application embodiment; Figure 6 This is a schematic diagram of a multi-bit sampling circuit provided in an embodiment of this application; Figure 7This is a schematic diagram of an integrated circuit structure provided in an embodiment of this application. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the accompanying drawings in this application are for illustrative and descriptive purposes only and are not intended to limit the scope of protection of this application. Furthermore, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of this application. It should be understood that the operations in the flowcharts may not be implemented in sequence, and steps without logical contextual relationships may be reversed or implemented simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more other operations to the flowcharts, or remove one or more operations from the flowcharts.

[0020] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0021] It should be noted that the term "comprising" will be used in the embodiments of this application to indicate the presence of the features declared thereafter, but does not exclude the addition of other features.

[0022] In digital circuit systems, multi-bit parallel signal interfaces are widely used for chip configuration, state synchronization, address transmission, and control command issuance. These interfaces require multiple signal pins to switch levels simultaneously, ensuring that subsequent circuits can recognize them as a complete and valid state. However, in actual hardware implementations, limitations such as differences in the driving capabilities of each signal path, inconsistent trace lengths, varying loads, and environmental changes make it difficult to perfectly synchronize the level transitions of each bit. Therefore, invalid intermediate states may briefly appear during state transitions. If these intermediate states are missampled by subsequent circuits, they can lead to logical errors, state machine anomalies, and decoding errors.

[0023] To address this, this application provides a multi-bit state contention suppression circuit, which consists of multiple bit input terminals, a state sensing unit, a global decision unit, a latch output unit, and multiple bit output terminals. The multi-bit state contention suppression circuit in this application identifies illegal intermediate states during multi-bit level switching through the state sensing unit and the global decision unit, and masks intermediate states through the latch output unit. Thus, without modifying the original natural binary code, adding external control pins, or introducing edge trailing caused by filtering, it senses the actual stable state of each signal. Output updates are only enabled when all bits synchronously enter a stable state, eliminating state contention caused by wiring delay, drive difference, or noise interference.

[0024] To clearly describe the multi-bit state contention suppression circuit in this application, the method is explained below with reference to several accompanying figures. Figure 1 This is a schematic diagram of a multi-bit state contention suppression circuit provided in an embodiment of this application, as shown below. Figure 1 As shown, the multi-bit state contention suppression circuit includes: multiple bit input terminals 100, a state sensing unit 200, a global decision unit 300, a latch output unit 400, and multiple bit output terminals 500. The state sensing unit 200 has multiple input terminals connected to multiple bit input terminals 100, which are used to receive multiple bit input signals. The state sensing unit 200 has multiple first output terminals 1OUT connected to multiple input terminals of the latch output unit 400. The state sensing unit 200 has multiple second output terminals 2OUT connected to multiple input terminals IN of the global decision unit 300. The output terminal OUT of the global decision unit 300 is also connected to the latch enable terminal LE of the latch output unit 300. The multiple output terminals of the latch output unit 400 are connected to multiple bit output terminals 500.

[0025] Multi-bit state contention refers to the phenomenon in a parallel data path where multiple bits fail to reach a stable logic level synchronously within the clock edge or level-sensitive window due to differences in propagation delay, uneven driving capability, or asymmetrical wiring. This results in transient glitches, metastability, or incorrect decisions in the combinational logic output. The multi-bit input terminal 100 consists of multiple parallel input ports IN, each receiving an independent digital signal, forming a data bus. Multiple bit input signals are input through the multi-bit input terminal 100, and these multiple bit input signals constitute the transmitted data.

[0026] Each bit of the input signal is a voltage level (0 or 1) on an independent signal line in the parallel data bus. Each bit corresponds to one binary digit. The voltage levels of all bits together form a multi-bit binary data word. In steady state, the value of this data word is a fixed value preset by the transmitting end, and each bit should be stable at its corresponding target voltage level in this steady state.

[0027] The state sensing unit 200 delays each bit input signal to obtain a corresponding bit delay signal, performs single-channel signal state determination based on the bit input signal and the corresponding bit delay signal, outputs a corresponding single-channel state signal, and outputs multiple single-channel state signals to the global determination unit 300. The state sensing unit 200 consists of multiple structurally identical single-channel state sensing branches. The number of single-channel state sensing branches is the same as the number of bit input signals. The bit delay signal is obtained by delaying the bit input signal using the state sensing unit 200 and is used to determine whether the bit input signal is still changing. The single-channel state signal is obtained by the state sensing unit 200 based on the determination of each bit input signal and bit delay signal. The single-channel state signal consists of a high-level signal and a low-level signal. The high-level signal indicates that the bit input signal and bit delay signal are completely consistent and in a steady state, while the low-level signal indicates that the bit input signal and bit delay signal are inconsistent and in a transition process.

[0028] The global decision unit 300 performs joint decision-making based on multiple single-channel status signals and outputs a global status signal to the enable terminal LE of the latch output unit 400 to enable latching in the latch output unit 400. The global decision unit 300 receives multiple single-channel status signals, performs joint decision-making, and concludes whether the entire parallel interface has stabilized, thus obtaining the global status signal. The global status signal is used to determine whether each bit input signal is in a steady state. The global status signal includes a high-level signal and a low-level signal; a high level indicates that each bit input signal is stable, and a low level indicates that each bit input signal is unstable.

[0029] The state-aware unit 200 is also used to output the bit-delay signal to the latch output unit 400 to provide an input signal for the latch output unit 400. The latch output unit 400, based on the level value of the global state signal, performs steady-state output and non-steady-state isolation on the multiple bit-delay signals input to its multiple input terminals D. The latch output unit 400 holds the output at the previous stable value, and only transparently outputs the current input value to the subsequent stage when the global decision unit 300 indicates that all bits are stable. Steady-state output means that after all bits are stable, the multiple bit-delay signals are transmitted to the multiple output pins OUT of the multiple bit output terminals 500. Non-steady-state isolation means that when any bit is still changing, the output maintains its previous stable value and does not follow the input changes.

[0030] Optionally, multiple input terminals of the state sensing unit 200 are respectively connected to multiple input pins IN of multiple bit input terminals 100 to receive multiple bit input signals. The state sensing unit 200 delays each bit input signal to obtain a corresponding bit delay signal. Based on the bit input signal and the corresponding bit delay signal, a single-channel signal state decision is performed, and a corresponding single-channel state signal is output. The second output terminal 2OUT1 of the state sensing unit 200 inputs multiple single-channel state signals to the global decision unit 300, enabling the global decision unit 300 to perform a joint decision based on the multiple single-channel state signals to obtain a global state signal. The global decision unit 300 outputs the global state signal to the enable terminal LE of the latch output unit 400, thereby enabling latching in the latch output unit 400. The input terminal D of the latch output unit 400 is used to connect to the first output terminal IOUT of the state sensing unit 200 to receive the bit delay signal. When the level of the global state signal is high, the latch output unit 400 performs steady-state output, and when the level of the global state signal is low, the latch output unit performs non-steady-state output.

[0031] In this embodiment, the multi-bit state contention suppression circuit includes: multiple bit input terminals, a state sensing unit, a global decision unit, a latch output unit, and multiple bit output terminals; the multiple input terminals of the state sensing unit are respectively connected to the multiple bit input terminals and are respectively used to receive multiple bit input signals; the multiple first output terminals of the state sensing unit are respectively connected to the multiple input terminals of the latch output unit; the multiple second output terminals of the state sensing unit are respectively connected to the multiple input terminals of the global decision unit; the output terminal of the global decision unit is also connected to the latch enable terminal of the latch output unit; and the multiple output terminals of the latch output unit are respectively connected to the multiple bit output terminals. The circuit in this application ensures that the enable terminal of the latch output unit changes before the data terminal, enabling the identification and controllable delay of the transition process of each input signal. Then, the global decision unit coordinates the stable state of all bits and generates a precise latch enable signal, thereby ensuring that the latch output unit only updates the output after all bits have completed the transition and entered a stable state. This avoids the risks of illegal intermediate states and cross-bit competition caused by the difference in propagation delay when multiple bits are asynchronously input. At the same time, it does not rely on an external clock, does not change the original encoding rules, requires no additional calibration or external intervention, and has good process voltage and temperature adaptability.

[0032] Based on the above embodiments, this application also provides a schematic diagram of the structure of a state sensing unit in a multi-bit state contention suppression circuit. Figure 2 This application provides a schematic diagram of the structure of a state sensing unit in a multi-bit state contention suppression circuit, as shown in the embodiment of the present application. Figure 2 As shown, the state sensing unit 200 includes: multiple delay detection branches 201, the input terminals of the multiple delay detection branches 201 are multiple input terminals of the state sensing unit 200, respectively used to connect to multiple bit input terminals 100, the first output terminal 1OUT of the multiple delay detection branches 201 is multiple first output terminal of the state sensing unit 200, and the second output terminal 2OUT of the multiple delay detection branches 201 is multiple second output terminal of the state sensing unit 200.

[0033] The delay detection branch 201 is a basic repeating unit constituting the state sensing unit, with the number of branches matching the number of bits. For example, if it's 8 bits, there are 8 delay detection branches 201. Each branch is completely independent, parameter-matched, physically symmetrical, and the decision conditions for each channel are consistent. The delay detection branch 201 receives the bit input signal, determines the delay based on its structure, and obtains the bit delay signal. This bit delay signal is then sent to the latch output unit 400 through the first output terminal 1OUT. The bit input signal and the bit delay signal are compared to obtain a single-channel state signal. This single-channel state signal indicates whether the signal level has changed within the current window. The single-channel state signal is then sent to the global decision unit 300 through the second output terminal 2OUT.

[0034] In this embodiment, by adopting a fully parallel, channel-isolated delay detection architecture, each bit has an independent stability discrimination path, avoiding deviations introduced by mutual interference of multiple signals or shared resources; each delay detection branch can be highly matched in physical implementation, ensuring that the sensing sensitivity, response window and decision threshold for all bits remain uniform, thereby ensuring the accuracy of global state judgment.

[0035] Based on the above embodiments, this application also provides a schematic diagram of the delay detection branch in another multi-bit state contention suppression circuit. Figure 3 A schematic diagram of the delay detection branch in another multi-bit state contention suppression circuit provided in this application embodiment is shown below. Figure 3 As shown, the delay detection branch 201 includes a delay unit 2011 and an XOR gate 2012. The input terminal of the delay unit 2011 is the input terminal of the delay detection branch 201, and the output terminal of the delay unit 2011 is the first output terminal 1OUT of the delay detection branch 201. The output terminal of the delay unit 2011 and the corresponding bit input terminal are connected to the two input pins of the XOR gate 2012, and the output pin of the XOR gate 2012 is the second output terminal 2OUT of the delay detection branch 201.

[0036] The delay unit 2011 is used to shift the bit input signal on the time axis to delay the bit input signal and generate a bit-delayed signal. The delay unit 2011 can be a capacitor-resistor delay circuit, and the corresponding delay duration is determined based on the resistance value and the stored charge of the capacitor. The resistance value and the stored charge of the capacitor are determined based on the model of the printed circuit board where the multi-bit state contention suppression circuit is located and the corresponding data transmission chip; this embodiment does not impose any limitations on these. The delay unit 2011 can also be an odd-stage inverter chain, a current-controlled delay unit, a buffer chain with a loaded capacitor, etc., where the delay value remains relatively stable and the delay deviation between branches is minimal. The XOR gate 2012 is a dual-input logic gate; it outputs a high level when the bit input signal and the bit-delay signal have the same logic level, and outputs a low level when there is a difference between the two input logic levels. When the input signal is in the steady-state holding phase, the levels of the bit input signal and the bit delay signal are completely consistent, and the output of the XOR gate 2012 is high. Therefore, the single-channel signal state is determined to be single-channel steady state. When the input signal is in the transition phase of level transition, there are timing and level differences between the bit input signal and the bit delay signal. The output of the XOR gate 2012 is low. Therefore, the single-channel signal state is determined to be single-channel transition.

[0037] Optionally, the input terminal IN of the delay unit 2011 is used to receive the bit input signal and delay the bit input signal to obtain the bit delay signal. The first output terminal OUT1 of the delay unit 2011 is used to send the bit delay signal to the latch output unit. The second output terminal OUT2 of the delay unit 2011 is used to send the bit delay signal to one pin IN1 of the XOR gate 2012. The other pin IN2 of the XOR gate 2012 is used to receive the bit input signal and perform detection based on the bit input signal and the bit delay signal. When the input signal is in the steady-state holding stage, the levels of the bit input signal and the bit delay signal are completely consistent, and the output terminal OUT of the XOR gate 2012 outputs a high level. Then the single-channel signal state is determined to be single-channel steady state. When the input signal is in the transition stage of level transition, there is a timing and level difference between the bit input signal and the bit delay signal. The output terminal OUT of the XOR gate 2012 outputs a low level. Then the single-channel signal state is determined to be single-channel transition.

[0038] In this embodiment, the original signal is directly compared with its own delayed signal without the need for an external reference source or clock synchronization. This achieves fully self-contained stability perception. The high level output of the XOR gate indicates that the signal has not changed, making the stable state and the effective logic high completely consistent in terms of level semantics. This simplifies the identification and processing logic of subsequent circuits and avoids the risks of delay, power consumption and noise caused by additional inversion.

[0039] Based on the above embodiments, this application also provides a schematic diagram of another multi-bit state contention suppression circuit. Figure 4 A schematic diagram of another multi-bit state contention suppression circuit provided in this application embodiment is shown below. Figure 4 As shown, the global decision unit 300 includes a multi-input AND gate 301, the multiple input pins of the multi-input AND gate 301 are the multiple input terminals of the global decision unit 300, and the output terminal of the multi-input AND gate 301 is the output terminal of the global decision unit 300.

[0040] The number of IN inputs of the multi-input AND gate 301 is equal to the number of system bits; for example, n bits equals n inputs. Each input is connected to a single-channel state signal from the state sensing unit 200, and its output is the global state signal. The multi-input AND gate 301 outputs a high level only when all inputs are high; otherwise, it outputs a low level. The inputs of the multi-input AND gate 301 refer to the multiple electrical nodes to which it is connected, each receiving a single-channel state signal from the state sensing unit. The signal carried by each input represents whether the corresponding bit is in a stable state at the current moment. Optionally, when multiple single-channel status signals output by the state sensing unit 200 or multiple single-channel status signals output by the multi-channel state sensing unit 200 are in a transitional state of level transition, the XOR gate of the corresponding branch outputs a low-level transition flag signal, and the multi-input AND gate 301 immediately outputs a low-level latch inhibit signal, shielding the non-steady-state timing window during the signal transition process. Only when all multiple input signals have completed level transition and entered a stable holding state, the state sensing unit 200 outputs multiple high-level steady-state flag signals, and the multi-input AND gate 301 outputs a high-level steady-state flag signal, completing the global steady-state valid confirmation of the multi-bit signal.

[0041] In this embodiment, the system is only allowed to enter the non-latch state and output stably when all bits are confirmed to be stable, thus eliminating the risk of false latching caused by delays in individual channels and ensuring that the output data has strict integrity and consistency in the time dimension.

[0042] One possible implementation is that the latch output unit includes a low-level enabled D-type latch. The D-type latch is a multi-input and multi-output D-type latch, having multiple data inputs, one enable input, and multiple outputs.

[0043] Among them, the D-type latch enabled by low level latches the input and output in isolation when the level is low; and disables latching when the level is high, allowing transparent transmission of input and output.

[0044] If the latch enable pin of the D-type latch is high, the D-type latch is in transparent transmission mode, and the D-type latch transparently outputs multiple bit input signals. If the global decision unit outputs a global status signal high, and the latch enable pin of the D-type latch is also high, the D-type latch transparently outputs multiple bit delayed signals, using these multiple bit delayed signals as output signals.

[0045] When the latch enable pin of the D-type latch is low, the D-type latch is in latch-and-hold mode, latching multiple bits of the input signal. If the global decision unit outputs a global status signal low, and the latch enable pin of the D-type latch is also low, then the D-type latch is in latch-and-hold mode, latching multiple bits of the delayed signal and outputting the previous round's multiple bits of the delayed signal as the output signal.

[0046] For example, when the input of multiple bit input signals is 0, the corresponding bit delay signal is also 0, and the state judgment of multiple single-channel signals is high, then the global state signal is high, the enable terminal LE is 1, then the D-type latch transparently outputs multiple bit input signals, and the latch output unit 400 performs steady-state output. The input terminal D is 0, and the output terminal is 0.

[0047] For example, when the input of multiple bit input signals changes from 0 to 1, the bit delay signal remains 0, and the status judgment of multiple single-channel signals is low, then the global status signal is low, the enable terminal LE is pulled low to 0, the D-type latch is in latch-hold mode, and the output terminal of the latch output unit 400 outputs the signal 0 from the previous moment.

[0048] For example, when the delay unit in the state sensing unit 200 starts charging and discharging to delay the input signal, the input terminal D of the latch output unit 400 gradually transitions from 0 to 1. When multiple single-channel signal states are determined to be low, the global state signal is low, the enable terminal LE remains at 0, and the output terminal of the latch output unit 400 outputs the signal 0 from the previous moment, completely ignoring any level changes and illegal intermediate states of the input terminal D of the latch output unit 400.

[0049] For example, when the delay unit in the state sensing unit 200 completes charging and discharging, the bit delay signal stabilizes at 1, and multiple single-channel signal state decisions are high, the global state signal is high, the enable terminal LE is pulled high, the latch output unit 400 re-enters the transparent mode, the input terminal D of the latch output unit 400 has stabilized at 1, and the output of the latch output unit 400 is updated to 1.

[0050] In this embodiment, when all bits are determined to be stable globally, the system automatically enters transparent mode, achieving data follow-up and real-time updates without delay. This avoids the inherent setup and hold time constraints and clock skew issues of edge-triggered devices. When the global state signal becomes invalid, the output can be frozen immediately and the last valid data can be reliably maintained, ensuring that the downstream circuit always receives the complete steady-state value. This reduces the risk of output glitches caused by channel deviation and the complexity and power consumption of system integration. The delay unit is only used to stagger the timing windows of the enable and input terminals and does not affect the edge characteristics of the output signal. The rise / fall time of the output signal is determined by the driving capability of the latch output unit, which is steep and distortion-free, and has strong anti-interference capability.

[0051] Based on the same inventive concept, this application also provides a multi-bit state contention suppression method corresponding to the multi-bit state contention suppression circuit. Figure 5 This is a flowchart illustrating a multi-bit state contention suppression method provided in an embodiment of this application, as shown below. Figure 5 As shown, the method includes: Step 501: Delay each bit of the input signal to obtain the corresponding bit-delayed signal.

[0052] Optionally, the delay unit in the state sensing unit is used to delay each bit of the input signal to obtain the corresponding bit delay signal.

[0053] Step 502: Perform single-channel signal state determination based on the bit input signal and the corresponding bit delay signal, and output the corresponding single-channel state signal.

[0054] Optionally, the XOR gate in the state sensing unit is used to perform single-channel signal state determination based on the bit input signal and the corresponding bit delay signal, and output the corresponding single-channel state signal.

[0055] Step 503: Perform a joint decision based on the multiple single-channel status signals and output a global status signal for latching and enabling.

[0056] Optionally, a global decision unit is used to make joint decisions based on multiple single-channel status signals and output a global status signal for latching enable.

[0057] Step 504: Based on the level value of the global state signal, latch the multiple bit delay signals to obtain multiple bit output signals.

[0058] Optionally, the global decision unit is used to make a joint decision based on multiple single-channel status signals and output a global status signal to the latch output unit to enable latching of the latch output unit. The latch output unit is used to receive multiple bit delay signals and, based on the level value of the global status signal, perform steady-state output and non-steady-state isolation on the multiple bit delay signals.

[0059] In this embodiment, the application achieves proactive perception and adaptive response to the evolution of multi-bit data through delay, comparison, aggregation, enabling, and latching closed loop. This ensures the sensitivity and consistency of single-bit channel decision-making, eliminates the impact of local misjudgments through global joint decision-making, and ensures that the final latching action only occurs when all bits truly achieve time consistency, without introducing additional timing constraints. The output result is a stable data frame, which improves the functional correctness and system reliability of the high-speed parallel interface in complex electromagnetic environments.

[0060] This application also provides a multi-bit sampling circuit. Figure 6 This is a schematic diagram of a multi-bit sampling circuit provided in an embodiment of this application, as shown below. Figure 6As shown, the multi-bit sampling circuit includes a multi-bit state contention suppression circuit 601 and a target chip 602. The multiple bit output terminals of the multi-bit state contention suppression circuit 601 are respectively connected to the multiple input terminals of the target chip 602. The multi-bit state contention suppression circuit 601 is any of the above-mentioned multi-bit state contention suppression circuits.

[0061] This application also provides an integrated circuit. Figure 7 A schematic diagram of an integrated circuit structure provided in an embodiment of this application is shown below. Figure 7 As shown, the integrated circuit includes: a circuit board 700, and a multi-bit state contention suppression circuit 601 integrated on the circuit board, wherein the multi-bit state contention suppression circuit 601 is any of the aforementioned multi-bit state contention suppression circuits.

[0062] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems and devices described above can be referred to the corresponding processes in the method embodiments, and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection can be through some communication interfaces; the indirect coupling or communication connection of devices or modules can be electrical, mechanical, or other forms.

[0063] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. If the functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes: USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, optical disks, and other media capable of storing program code.

[0064] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A multi-bit state contention suppression circuit, characterized in that, The multi-bit state contention suppression circuit includes: multiple bit input terminals, a state sensing unit, a global decision unit, a latch output unit, and multiple bit output terminals; The state sensing unit has multiple input terminals connected to multiple bit input terminals respectively, and is used to receive multiple bit input signals respectively. The state sensing unit has multiple first output terminals connected to multiple input terminals of the latch output unit respectively. The state sensing unit has multiple second output terminals connected to multiple input terminals of the global decision unit respectively. The output terminal of the global decision unit is also connected to the latch enable terminal of the latch output unit. The latch output unit has multiple output terminals connected to multiple bit output terminals respectively. The state sensing unit is used to delay each bit input signal to obtain a corresponding bit delay signal, and to make a single-channel signal state decision based on the bit input signal and the corresponding bit delay signal, output the corresponding single-channel state signal, and output multiple single-channel state signals to the global decision unit. The global decision unit is used to make a joint decision based on multiple single-channel status signals and output a global status signal to the latch output unit to enable latching of the latch output unit. The state sensing unit is also used to output the bit delay signal to the latch output unit to provide an input signal to the latch output unit. The latch output unit is used to perform steady-state output and non-steady-state isolation of multiple bit delay signals based on the level value of the global state signal.

2. The circuit according to claim 1, characterized in that, The state sensing unit includes: multiple delay detection branches, the input terminals of the multiple delay detection branches are multiple input terminals of the state sensing unit, respectively used to connect to multiple bit input terminals, the first output terminals of the multiple delay detection branches are multiple first output terminals of the state sensing unit, and the second output terminals of the multiple delay detection branches are multiple second output terminals of the state sensing unit.

3. The circuit according to claim 2, characterized in that, The delay detection branch includes a delay unit and an XNOR gate. The input terminal of the delay unit is the input terminal of the delay detection branch, and the output terminal of the delay unit is the first output terminal of the delay detection branch. The output terminal of the delay unit and the corresponding bit input terminal are connected to the two input pins of the XNOR gate, and the output pin of the XNOR gate is the second output terminal of the delay detection branch.

4. The circuit according to claim 1, characterized in that, The global decision unit includes a multi-input AND gate, wherein the multiple input pins of the multi-input AND gate are the multiple input terminals of the global decision unit, and the output terminal of the multi-input AND gate is the output terminal of the global decision unit.

5. The circuit according to claim 1, characterized in that, The latch output unit includes a D-type latch that is enabled by a low level.

6. The circuit according to claim 5, characterized in that, If the latch enable pin of the D-type latch is at a high level, the D-type latch is in transparent transmission mode, and the D-type latch transparently outputs multiple bit delay signals.

7. The circuit according to claim 5, characterized in that, When the latch enable pin of the D-type latch is at a low level, the D-type latch is in latch-and-hold mode, and the D-type latch latches multiple bit delay signals.

8. A multi-bit sampling circuit, characterized in that, The multi-bit sampling circuit includes a multi-bit state contention suppression circuit and a target chip. The multiple bit output terminals of the multi-bit state contention suppression circuit are respectively connected to the multiple input terminals of the target chip. The multi-bit state contention suppression circuit is any of the multi-bit state contention suppression circuits described in claims 1-7.

9. An integrated circuit, characterized in that, The integrated circuit includes: a circuit board, and a multi-bit state contention suppression circuit integrated on the circuit board, wherein the multi-bit state contention suppression circuit is any one of the multi-bit state contention suppression circuits described in claims 1-7.

10. A method for suppressing multi-bit state contention, characterized in that, The method, applied to the multi-bit state contention suppression circuit of any one of claims 1-7, comprises: Each bit input signal is delayed to obtain the corresponding bit delayed signal; Based on the bit input signal and the corresponding bit delay signal, a single-channel signal state decision is made, and the corresponding single-channel state signal is output. Based on the multiple single-channel status signals, a joint decision is made, and a global status signal is output for latching and enabling. Based on the level value of the global state signal, multiple bit delay signals are latched and output to obtain multiple bit output signals.

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