Apparatus comprising a differential output stage

Abstract

The invention relates to an apparatus comprising a differential output stage with a first and a second complementary half-bridge, in which two transistors are connected in series, respectively. The sections between the transistors of each half-bridge, respectively, are connected to a signal output for a partial signal of a differential voltage signal, respectively. For recognizing a fault on a load connected to the signal output, the apparatus has a fault recognition circuit. The transistors of each half-bridge are part of a current mirror, respectively, which is designed and coupled to a driver assigned to the transistor such that, when an output current is flowing in the associated half-bridge, a test current proportional to the output current is flowing in a current path assigned to the half-bridge. The current paths are connected to a summing node for adding the test currents. The summing node is connected to a comparison device for comparing the total current of the test currents with a reference value or a reference value range.

Description

Technical Field

[0001] This invention relates to a device including a differential output stage, the differential output stage having a first half-bridge and a second half-bridge, wherein a first transistor and a second transistor are connected in series in the first half-bridge and the second half-bridge, respectively, wherein each transistor has a control input terminal, the control input terminal being connected to a driver respectively provided for the control input terminal.

[0002] -The section between the transistors in the first half-bridge is connected to the first signal output terminal of the first portion of the differential voltage signal, and

[0003] -The section between the transistors in the second half-bridge is connected to the second signal output terminal for the second portion of the differential voltage signal.

[0004] It also includes a fault identification circuit for identifying faults in the load, which is connected to or may be connected to the signal output terminal. Background Technology

[0005] The importance of sensing mechanisms in vehicle technology is becoming increasingly prominent. Especially when used in safety-related applications, there are very high requirements not only for the accuracy of sensor signals but also for their reliability. According to existing technologies, system reliability is improved through redundant design and system reliability testing.

[0006] As an alternative to redundancy, the system monitors or designs relevant signal paths in an interference-resistant manner with the aid of a compensated architecture to monitor or address known sources and effects of interference.

[0007] It is within the realm of electronic circuit architecture, combined with physical sensors, that many measures leading to robust systems are known. A common example of this is temperature compensation for circuits and sensors, which is inherent in modern sensor systems. Other effects, such as electromagnetic uniformity (EMV) effects, have also been partially compensated for with satisfactory results.

[0008] A prerequisite for good and reliable compensation is an accurate understanding of the mechanism by which the interference enters the sensor system. This is especially true when the fault involves an incompletely defined mechanism, resulting from the failure or malfunction of components involved in the overall system function. In this case, interference compensation fails, and reliability is only ensured by a diagnostic entity that continuously monitors the system's operation. Faulty output signals are no longer blocked in this situation, but are at least identified and can be signaled to higher system entities.

[0009] In the case of monolithic integrated sensor systems or integrated circuits (ICs), external wiring, including input external devices to the evaluation unit, is also a potential system component that can cause failure, as data or sensor signals are transmitted to the evaluation unit.

[0010] In various applications, the output signal of the output stage exists as an output voltage designed differentially or absolutely. The output amplifier here drives an external load, which consists of resistive, capacitive, and inductive components and is also partly parasitic.

[0011] The differential signal output comprises two separate signal outputs, which are differentially measured by the evaluation unit. In the literature, this method is also referred to as symmetrical signal transmission. The advantage here lies in the significantly higher robustness of the transmission via the wire connection. In particular, interference of the aforementioned types, such as EMV, is almost completely suppressed by differential or symmetrical transmission. This requires, as far as possible, a symmetrical load ratio between the two separate signal outputs, which form a pair to create the differential outputs. For the system as a whole, this requires that the source impedance, wire impedance, and load impedance be identical.

[0012] The impairment of this symmetry may not directly lead to faulty signal transmission, but rather to a significant reduction in the robustness of signal transmission, such as signals describing measurements in practice.

[0013] EP3018830A1 discloses a detection device for monitoring the quality of a differential wired communication connection. On the receiver side of the communication connection, a fault identification circuit monitors different parameters during signal transmission in the two wires of the differential communication connection. Furthermore, the signal level is measured and evaluated not only absolutely but also differentially. Additionally, other parameters such as short-circuit detection or edge slope detection are implemented in separate modules. Summary of the Invention

[0014] The objective of this invention is to provide an apparatus of the type described at the beginning, which, in terms of its output stage, can detect faults in an external load and / or in a conductor, the external load being connected to or potentially connected to a signal output terminal, the conductor connecting the load to the signal output terminal.

[0015] The task is accomplished by a device having the features of claim 1. Advantageous designs of the invention are the subject of the dependent claims.

[0016] According to the present invention, a device of the type described at the beginning is provided.

[0017] The transistor in the first half-bridge is part of a first current mirror, which has a first current path designed and coupled to a driver provided for the transistor such that when an output current flows in the first half-bridge, a first test current proportional to that output current flows in the first current path.

[0018] The transistor in the second half-bridge is part of a second current mirror, which has a second current path designed and coupled to a driver provided for the transistor such that when an output current flows in the second half-bridge, a second test current proportional to that output current flows in the second current path.

[0019] The first and second current paths are connected to a summing node to add the first and second test currents, and the fault identification circuit has a comparator connected to the summing node to compare the total current formed by the first and second test currents with a reference value or a range of reference values. The device is advantageously capable of detecting asymmetry in the load connected between the signal outputs. Asymmetry here indicates a fault.

[0020] Importantly, as long as the load connected to the signal output terminal of the output stage is symmetrical, the sum of the input currents flowing through the transistors arranged in the half-bridge remains substantially constant. The total current, consisting of the currents in the first and second current paths, is compared with a reference value or a reference range, which preferably coincides with the expected value of the total current. Because asymmetry, or in other words, a fault in the symmetry of the load, will cause a deviation from the expected value of the total current, fault detection can also be performed by comparing the reference value or reference range with the total current.

[0021] The output stage, including the current mirror and comparator, and the fault identification circuitry, are preferably integrated as an integrated circuit into the semiconductor chip. This device then enables the identification of faults within the IC of loads connected to the signal output terminal. This allows for high diagnostic coverage of the output amplifier and housing used in the integrated circuit.

[0022] Because fault detection is implemented at the signal source side or the output stage side (which corresponds to the receiver at the transmitting end in the wired transmission of the differential voltage signal at the output stage), the cost of circuitry is reduced, which contributes to improved reliability. This results in improvements in feature codes such as SPFM (single point fault metric) or PMFH (Probabilistic Metric for Random Hardware Failures) within the scope of functional safety according to ISO 26262 (“Road vehicles - Functional safety”), for example, in use in motor vehicles.

[0023] Preferably, the first transistor and the second transistor of the first half-bridge are designed to complement each other, and / or the first transistor and the second transistor of the second half-bridge are designed to complement each other.

[0024] Preferably, a first transistor element is disposed in the first current path, and the control input terminal of the first transistor element is connected to the control input terminal of the first transistor of the first half-bridge; and / or a second transistor element is disposed in the second current path, and the control input terminal of the second transistor element is connected to the control input terminal of the first transistor of the second half-bridge. This enables precise mapping of the current flowing through the relevant half-bridge to the first or second current path.

[0025] In an advantageous embodiment of the invention, the first transistor of the first half-bridge and the first transistor of the second half-bridge are each designed as PMOS transistors. Here, the first transistor element and the second transistor element can also be designed as PMOS transistor elements. Preferably, the control input terminal (gate) of the first transistor element is connected to the control input terminal (gate) of the first transistor of the first half-bridge, and preferably, the control input terminal (gate) of the second transistor element is connected to the control input terminal (gate) of the first transistor of the second half-bridge. The device can thus be easily integrated into a semiconductor chip.

[0026] In an alternative embodiment of the invention, the first transistor of the first half-bridge and the first transistor of the second half-bridge are both NMOS transistors. In this design, the control input terminal (gate) of the first transistor element is preferably connected to the control input terminal (gate) of the first transistor of the first half-bridge, and the control input terminal (gate) of the second transistor element is preferably connected to the control input terminal (gate) of the first transistor of the second half-bridge; however, the transistor element is designed as an NMOS transistor.

[0027] In a further embodiment of the invention, the comparator, in order to map the total current from the first and second current paths to a third current path, has a third current mirror comprising a third transistor and a third transistor element, wherein the third transistor element is connected in series with a reference power supply in the third current path, wherein the third transistor is disposed in a fourth current path connecting the summing node to a supply voltage terminal, and wherein the control input terminal of the third transistor and the control input terminal of the third transistor element are respectively connected to the summing node. The comparison result between the reference current of the reference power supply and the total current from the first and second current paths is then sampled as a voltage at the node between the third transistor element and the reference power supply and at the summing node in the third current path.

[0028] In a preferred design of the invention, when the transistors and transistor elements of the first and second current mirrors are PMOS transistors, the transistor of the third current mirror is an NMOS transistor. The reference power supply may here have a PMOS transistor.

[0029] In an alternative embodiment of the invention, the transistors and transistor elements of the first and second current mirrors are NMOS transistors and the transistor of the third current mirror is a PMOS transistor. Attached Figure Description

[0030] Further details, features, and advantages of the invention will become apparent from the following description of the embodiments with reference to the accompanying drawings.

[0031] in:

[0032] Figure 1 A schematic diagram of a device including a differential signal output terminal is shown, with a load connected to the signal output terminal;

[0033] Figure 2 A first embodiment of the device is shown and

[0034] Figure 3 A second embodiment of the device is shown. Detailed Implementation

[0035] Figure 1 The diagram shows a schematic of a device 10 designed as an integrated circuit, the device having a microchip 20, a differential output stage, and a fault identification circuit 30 for identifying faults in a load connected to the microchip, the load being connected to the differential signal output terminals A1, A2 of the output stage.

[0036] The first signal output terminal A1 of the device 10 is connected to the first terminal of the evaluation unit 50 via the first wire 40. The second signal output terminal A2 of the device 10 is connected to the second terminal of the evaluation unit 50 via the second wire 60.

[0037] The first signal output terminal A1 on the microchip 20 is connected to the first wire 40 via the first key connection 70, and the second output terminal A2 on the microchip 20 is connected to the second wire 60 via the second key connection 80.

[0038] The first key connection 70 is electrically connected to the output terminal of the first amplifier 90 of the differential output stage. The second key connection 80 is electrically connected to the output terminal of the second amplifier 100 of the differential output stage.

[0039] The input terminals of the first amplifier 90 and the second amplifier 100 are connected to the input signal terminal E. The first amplifier 90 and the second amplifier 100 generate symmetrical differential output signals from the input signal E. The evaluation unit 50 detects the output signal of the device 10 using two symmetrical differential input terminals, which are formed by the first wire 40 and the second wire 60.

[0040] The first conductor 40 has a first conductor impedance 110, and the second conductor 40 has a second conductor impedance 120. The evaluation unit 50 has a first load impedance 130 at its first input terminal, through which the first input terminal is connected to a first supply voltage potential V. DD Connection. The evaluation unit 50 has a second load impedance 140 at its second input terminal, through which the second input terminal is connected to a second supply potential VSS. Additionally, the evaluation unit 50 has a differential load impedance 150 acting between the first conductor 40 and the second conductor 60.

[0041] The conductor impedances 110 and 120 are the same as the load impedances 130 and 140, respectively. Through this perfectly symmetrical arrangement and its differential reading via evaluation unit 50, interference 160 is completely suppressed due to its symmetrical effect. The asymmetry in the listed impedances 110, 120, 130, 140, and 150 also asymmetrically modulates interference 160 in conductors 40 and 60. As a result, the incoming interference 160 is no longer completely suppressed.

[0042] exist Figure 2 and 3In the embodiment shown, the first amplifier 90 has a complementary first half-bridge 200 or a complementary first line driver, and the second amplifier 100 has a complementary second half-bridge 210 or a complementary second line driver. Each half-bridge 200, 201 has a first transistor 201, 211 and a second transistor 202, 212, which is complementary to the first transistor 201, 211 and connected in series therewith. In the embodiment shown in the figures, the series circuits of PMOS and NMOS transistors are shown complementaryly.

[0043] In the first half-bridge 200, the source of the first transistor 201, designed as a PMOS transistor, is connected to the first supply potential V. DD The first transistor 201 is connected to the signal output terminal A1 and the drain of the second transistor 202, which is designed as an NMOS transistor. The source of the second transistor 202 is connected to the second supply potential VSS.

[0044] In a corresponding manner, in the complementary second half-bridge 210, the source of the first transistor 211, designed as a PMOS transistor, is connected to the first supply potential V. DD The PMOS transistor 211 is connected to the signal output terminal A2 and the drain of the second transistor 212, which is designed as an NMOS transistor. The source of the second transistor 212 is connected to the second supply potential VSS.

[0045] Not only the first transistors 201 and 211, but also the second transistors 202 and 212 in the two half-bridges 200 and 210 can be implemented as groups of multiple identical single transistors connected in parallel with each other.

[0046] The first transistor 201 of the first half-bridge 200 is part of the first current mirror 231, which has a first current path 241. A first transistor element 221, designed as a PMOS transistor, is disposed in the first current path 241, and the control input or gate of the first transistor is connected to the control input or gate of the first transistor 201 of the first half-bridge 200. Figure 2 In the embodiment shown, the source of the first transistor element 221 is connected to the first supply voltage potential V. DD The first transistor element 221 is connected to the summing node 251, and the drain of the first transistor element 221 is connected to the summing node 251.

[0047] To map the input current flowing through the source-drain path of the first transistor 201 in the first half-bridge 200 into the first current path 241, the first signal output terminal A1 internally provides feedback, thereby adjusting the first current mirror 231. This is because the control input terminal or gate of the first transistor element 221 and the first transistor 201 in the first half-bridge 200 have the same source potential V. DDThey are controlled in the same way, so the source-drain current through the first transistor element 221 is proportional to the source-drain current through the first transistor 201 of the first half-bridge 200 (assuming the same operating conditions). That is, the current through the first transistor 201 acts on the potential at the first signal output terminal A1, which acts on the regulation circuit, which regulates the gate potential at the first transistor element 221.

[0048] The first transistor 211 of the second half-bridge 210 is part of the second current mirror 232, which has a second current path 242. A second transistor element 222 is disposed in the second current path 242, and its control input or gate is connected to the control input or gate of the first transistor 211 of the second current mirror 232. The source of the second transistor element 222 is connected to the first supply potential V. DD The second transistor element 222 is connected to the summing node 251.

[0049] To map the input current flowing through the source-drain path of the first transistor 211 in the second half-bridge 210 into the second current path 242, the second signal output terminal A2 internally provides feedback, thereby adjusting the second current mirror 232. This is because the control input terminals or gates of the first transistor element 221 and the first transistor 211 in the second half-bridge 210 have the same source potential V. DD They are controlled in the same way, so the current through the second transistor element 222 is proportional to the current through the first transistor 211 of the second half-bridge 210 (assuming the same operating conditions). That is, the current through the first transistor 211 acts on the potential at the second signal output terminal A2, which acts on the regulation circuit, which regulates the gate potential at the second transistor element 222.

[0050] The currents, also referred to as test currents, mapped from the first or second transistor elements 221 and 222 into the first or second current paths 241 and 251, are connected in parallel at the summing node 251. The summing node 251 is connected to the input of the third current mirror 233. The third current mirror 233, which maps the total current from the first and second current paths 241 and 242 into the third current path 243, has a third transistor 223 and a third transistor element 224. The third transistor 223 and the third transistor element 224 are both designed as NMOS transistors.

[0051] The third transistor element 224 is connected in series with the reference power supply 225 in the third current path 243, the reference power supply having its first terminal connected to the first supply voltage potential V. DD It is connected to node 252 via its second terminal, which is connected to the drain of the third transistor element 224. Reference current IRef It flows between the first and second terminals of the reference power supply 225.

[0052] The third transistor 223 is disposed in the fourth current path, which connects the summing node 251 to the second supply voltage terminal VSS. The control input terminals of the third transistor 223 and the third transistor element 224 are connected to the drain of the summing node 251 and the third transistor 223, respectively. The source of the third transistor 223 is at the second supply voltage VSS.

[0053] An ohmic load could also be set instead of the third transistor 223, and the absolute voltage across the load could be evaluated.

[0054] Reference current I of reference power supply 225 Ref The difference between the sum of the test currents in the first current path 241 and the second current path 242 and the voltage tap U is manifested in the voltage tap U. F The voltage fluctuates. Voltage tap U F It has a first contact connected to the summing node 251 and a second contact connected to node 252. If the sum of currents equals the reference current I... Ref If they are the same, then at voltage tap U F The voltage swing is 0 volts under ideal conditions (no noise).

[0055] It should also be noted that it is not necessary to measure the voltage at node 252 to summing node 251, but the voltage can also be measured to the second supply voltage potential VSS or another reference.

[0056] exist Figure 3 In the embodiment shown, the half-bridges 200 and 210 correspond to... Figure 2 The half-bridges 200 and 210. Figure 3 The drivers 206, 216, 207, and 217 also correspond to Figure 2 The driver, therefore Figure 2 The explanation here is for Figure 3 Applicable accordingly.

[0057] However, in this embodiment, the second transistor 202 of the first half-bridge 200 is part of the first current mirror 331, which has a first current path 341. A first transistor element 321 (NMOS) is disposed in the first current path 341, and the control input or gate of the first transistor element is used to map the current flowing through the first half-bridge 200 to the control input or gate of the second transistor 202 of the first half-bridge 200. The source of the first transistor element 321 is connected to the second supply potential VSS, and the drain of the first transistor element 321 is connected to the summing node 351.

[0058] The second transistor 212 of the second half-bridge 210 is part of the second current mirror 332, which has a second current path 342. A second transistor element 322 (NMOS) is disposed in the second current path 342. The control input or gate of the second transistor element is used to map the current flowing through the second half-bridge 210 to the gate of the second transistor 212. The source of the second transistor element 322 is connected to the second supply potential VSS, and the drain of the second transistor element 322 is connected to the summing node 351. That is, the currents mapped by transistor elements 321 and 322 are connected in parallel at the summing node 351.

[0059] The summation node 351 is connected to the input of the third current mirror 333. It is used to map the total current from the first and second current paths 341 and 342 into the third current path 343. The third current mirror 333 has a third transistor 323 and a third transistor element 324. The third transistor 323 and the third transistor element 324 are both designed as PMOS transistors.

[0060] The third transistor element 324 is connected in series with a reference power supply 325 in the third current path 343. The reference power supply is connected to ground potential via its first terminal and to node 352 via its second terminal. The node is connected to the drain of the third transistor element 324. Reference current I Ref It flows between the first and second terminals of the reference power supply 325.

[0061] The third transistor 223 is disposed in the fourth current path, which connects the summing node 351 to the first supply voltage terminal V. DD Connections are made. The control input terminals of the third transistor 323 and the third transistor element 324 are connected to the summing node 351 and the drain of the third transistor 323. The source of the third transistor 323 is at the first supply potential V. DD superior.

[0062] Reference current I of reference power supply 325 Ref The difference between the sum of the test currents in the first current path 341 and the second current path 342 and the voltage tap U is manifested in the voltage tap U. F The voltage fluctuates. Voltage tap U F It has a first contact connected to the summing node 351 and a second contact connected to node 352. If the sum of currents equals the reference current I... Ref If they are the same, then at voltage tap U F The voltage swing is 0 volts under ideal conditions (no noise).

Claims

1. A device (10) including a differential output stage, the differential output stage having a first half-bridge and a second half-bridge (200, 210), wherein a first transistor (201, 211) and a second transistor (202, 212) are connected in series in the first half-bridge and the second half-bridge, respectively, wherein each transistor (201, 211, 202, 212) has a control input terminal, and the control input terminal is connected to a driver (206, 216, 207, 217) respectively assigned to the control input terminal. - The section of the first half-bridge (200) between the transistors (201, 202) of the first half-bridge (200) is connected to the first signal output terminal (A1) of the first part of the differential voltage signal, and - The section of the second half-bridge (210) between the transistors (211, 212) of the second half-bridge (210) is connected to the second signal output terminal (A2) for the second part of the differential voltage signal. Furthermore, the device includes a fault identification circuit (30) for identifying faults, characterized in that, - The transistor (201) of the first half-bridge (200) is part of a first current mirror (231, 331) having a first current path (241, 341) designed and coupled to a driver (206) assigned to the transistor (201) such that when an output current flows in the first transistor (201) of the first half-bridge (200), a first test current proportional to the output current flows in the first current path (241, 341). - The transistor (211) of the second half-bridge (210) is part of a second current mirror (232, 332) having a second current path (242, 342) designed and coupled to a driver (216) assigned to the transistor (211) such that when an output current flows in the first transistor (211) of the second half-bridge (210), a second test current proportional to the output current flows in the second current path (242, 342). The first current path (241, 341) and the second current path (242, 342) are connected to the summing node (251, 351) to add the first test current and the second test current, and the fault identification circuit (30) has a comparator connected to the summing node (251, 351) to compare the total current formed by the first and second first test currents and the second test current with a reference value or a reference value range.

2. The apparatus (10) according to claim 1, characterized in that The first transistor and the second transistor (201, 202) of the first half-bridge (200) are designed to complement each other, and / or the first transistor and the second transistor (211, 212) of the second half-bridge (210) are designed to complement each other.

3. The apparatus (10) according to claim 1 or 2, characterized in that A first transistor element (221, 321) is provided in the first current path (241, 341), and the control input terminal of the first transistor element is connected to the control input terminal of the first transistor (201) of the first half-bridge (200). And / or a second transistor element (222, 322) is provided in the second current path (242, 342), and the control input terminal of the second transistor element is connected to the control input terminal of the first transistor (211) of the second half-bridge (210).

4. The apparatus (10) according to one of claims 1 to 3, characterized in that The first transistor (201) of the first half-bridge (200) and the first transistor (211) of the second half-bridge (210) are designed as PMOS transistors.

5. The apparatus (10) according to claim 4, characterized in that The first transistor element (221, 321) and the second transistor element (222, 322) are designed as PMOS transistor elements.

6. The apparatus (10) according to one of claims 1 to 3, characterized in that The first transistor (201) of the first half-bridge (200) and the first transistor (211) of the second half-bridge (210) are designed as NMOS transistors.

7. The apparatus (10) according to claim 6, characterized in that The first transistor element (221, 321) and the second transistor element (222, 322) are designed as NMOS transistor elements.

8. The apparatus (10) according to one of the claims 1 to 7, characterized in that The comparison device has a third current mirror (233, 333) comprising a third transistor (223, 323) and a third transistor element (224, 324) for mapping the total current from the first and second current paths (241, 341; 242, 342) into the third current path (243, 343), the third transistor element (224, 324) being connected in series with a reference supply (225, 325) in the third current path (243, 343), the third transistor (223, 323) being arranged in a fourth current path connecting the summing node (251, 351) with a supply voltage terminal (V SS , V DD ) and the control input of the third transistor (223, 323) and the control input of the third transistor element (224, 324) being connected with the summing node (251, 351), respectively.

9. The apparatus (10) according to claim 8, characterized in that The third transistors (223, 323) and the third transistor elements (224, 324) are designed as NMOS transistors.

10. The apparatus (10) according to claim 8, characterized in that The third transistors (223, 323) and the third transistor elements (224, 324) are designed as PMOS transistors.

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