Intermediate frequency dynamic compression circuit for a chirp system sounding device

Abstract

An intermediate frequency (IF) dynamic compression circuit for a linear frequency modulation (LFM) detection device belongs to the field of signal processing technology. It employs a single-channel circuit design, consisting of an input impedance matching unit, a first-stage amplification unit, an inter-stage coupling and biasing unit, a second-stage amplification unit, and an output filtering and matching unit, all electrically connected in sequence. The operational amplifier used is a THS4031 high-speed operational amplifier. The circuit frequency response meets the requirements of the relatively low-frequency cutoff frequency, with out-of-band rejection increasing by 12dB for every doubling of the frequency. In use, the IF dynamic compression circuit is connected in series between the video amplifier and the ADC chip, which can compress the dynamic range of the receiving channel by at least 40dB, resulting in an output dynamic range of approximately 60dB. It is compatible with 12-bit ADC chips, simplifying circuit design, reducing system hardware costs, and significantly reducing the false alarm probability of the detection device.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology, and in particular to an intermediate frequency dynamic compression circuit for a linear frequency modulation detection device. Background Technology

[0002] The detection device is mainly used to detect information such as target distance and speed. It requires high ranging accuracy, fast response time and large dynamic range. It mainly consists of an antenna, transceiver components, video amplifier and digital signal processor.

[0003] For detection devices, the detection distance variation range is generally not less than 60 times, so the required dynamic range is 40*log10(60)=71dB. Considering the 30dB change in the RCS of the near-field target, the required dynamic range is at least 101dB. It is difficult for any ADC chip to directly meet this dynamic range requirement. Therefore, the dynamic range must be compressed on the receiving channel. A common dynamic compression method is to divide the detection channel into a far-target channel and a near-target channel, such as... Figure 5 As shown.

[0004] The scheme for setting up distant target channels and near target channels is as follows: Figure 6 As shown, the transceiver components amplify, filter, and mix the echo signal before outputting it to a video amplifier. The video amplifier first splits the echo signal into two via a power divider circuit. One path enters the far-target channel, where the echo signal is first filtered by a bandpass filter. The lower cutoff frequency of the bandpass filter is set to the frequency corresponding to the near-range (typically 1m to 2m) echo signal, and the upper cutoff frequency is set to the frequency corresponding to the maximum reliable operating distance. After the bandpass filter, the echo signal is amplified. The other path enters the near-target channel, where the echo signal is first filtered by a low-pass filter. The cutoff frequency of the low-pass filter is set to the frequency corresponding to the near-range (typically 1m to 2m) echo signal. After the low-pass filter, the echo signal is amplified. Although this scheme divides the echo signal into far-target and near-target channels, greatly improving the dynamic range of the detection device, it also adds a receiving channel, increasing the complexity of the hardware circuitry and software signal processing, significantly increasing the system hardware cost. Furthermore, the increased circuit complexity also increases the false alarm probability of the detection device. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of existing dual-channel dynamic compression schemes, such as high hardware and software complexity, high system cost, and high false alarm probability. This invention provides an intermediate frequency dynamic compression circuit for linear frequency modulation (LFM) detection devices. Based on the echo characteristics of LFM signals, the dynamic range compression of the echo signals is achieved through a single-channel intermediate frequency filtering and amplification circuit. Under the premise of meeting the target detection performance requirements, this invention simplifies circuit design, reduces system cost, and lowers the probability of false alarms.

[0006] The technical solution of this invention: To achieve the above objectives, the present invention adopts the following technical solution: An intermediate frequency dynamic compression circuit for a linear frequency modulation system detection device includes an input impedance matching unit, a first-stage amplification unit, an inter-stage coupling and biasing unit, a second-stage amplification unit, and an output filtering and matching unit connected in sequence. The input impedance matching unit includes a signal source VG1, a resistor R7, a resistor R11, and a capacitor C3; one end of the signal source VG1 is grounded, and the other end is electrically connected to one end of the resistor R7 and one end of the resistor R11 respectively; the other end of the resistor R7 is grounded; the other end of the resistor R11 is electrically connected to one end of the capacitor C3; the other end of the capacitor C3 is the output terminal of the input impedance matching unit. The first-stage amplification unit includes an operational amplifier U1, resistors R3 and R2, capacitor C9, power supply V1, capacitor C10, and power supply V2. The inverting input terminal of operational amplifier U1 is electrically connected to the other end of capacitor C3. The non-inverting input terminal of operational amplifier U1 is electrically connected to one end of resistor R2, and the other end of resistor R2 is grounded. The two ends of resistor R3 are electrically connected to the inverting input terminal and the output terminal of operational amplifier U1, respectively. The positive terminal of power supply V1 is electrically connected to the positive power supply terminal of operational amplifier U1 and one end of capacitor C9, the negative terminal of power supply V1 is grounded, and the other end of capacitor C9 is grounded. The negative terminal of power supply V2 is electrically connected to the negative power supply terminal of operational amplifier U1 and one end of capacitor C10, the positive terminal of power supply V2 is grounded, and the other end of capacitor C10 is grounded. The interstage coupling and biasing unit includes capacitor C4, resistors R4 and R5, power supply V6, resistors R14 and R12; one end of capacitor C4 is electrically connected to the output terminal of operational amplifier U1; the other end of capacitor C4 is electrically connected to one end of resistor R4 and one end of resistor R5 respectively; the other end of resistor R4 is grounded; the positive terminal of power supply V6 is electrically connected to one end of resistor R14, and the negative terminal of power supply V6 is grounded; the other end of resistor R14 is electrically connected to one end of resistor R12 and the non-inverting input terminal of operational amplifier U3 respectively; the other end of resistor R12 is grounded; the other end of resistor R5 is electrically connected to the inverting input terminal of operational amplifier U3. The second-stage amplification unit includes operational amplifier U3, resistor R9, capacitor C12, power supply V4, capacitor C11, and power supply V3. The two ends of resistor R9 are electrically connected to the inverting input and output terminals of operational amplifier U3, respectively. The positive terminal of power supply V4 is electrically connected to the positive power supply terminal of operational amplifier U3 and one end of capacitor C12, while the negative terminal of power supply V4 is grounded, and the other end of capacitor C12 is grounded. The negative terminal of power supply V3 is electrically connected to the negative power supply terminal of operational amplifier U3 and one end of capacitor C11, while the positive terminal of power supply V3 is grounded, and the other end of capacitor C11 is grounded. Both operational amplifiers U1 and U3 are THS4031 high-speed operational amplifiers. The output filtering and matching unit includes resistor R6, inductor L1, capacitor C6, inductor L2, capacitor C7, resistor R10, resistor R13, and output terminal VT1. One end of resistor R6 is electrically connected to the output terminal of operational amplifier U3; the other end of resistor R6 is electrically connected to one end of inductor L1; the other end of inductor L1 is electrically connected to one end of capacitor C6 and one end of inductor L2 respectively; the other end of capacitor C6 is grounded; the other end of inductor L2 is electrically connected to one end of capacitor C7 and one end of resistor R10 respectively; the other end of capacitor C7 is grounded; the other end of resistor R10 is electrically connected to one end of resistor R13 and output terminal VT1 respectively; the other end of resistor R13 is grounded.

[0007] Furthermore, the resistance of resistor R7 is 51Ω, the resistance of resistor R11 is 0Ω, and the capacitance of capacitor C3 is 3.9nF.

[0008] Furthermore, the resistance of resistor R3 is 200Ω, the resistance of resistor R2 is 51Ω, and the capacitance of capacitors C9 and C10 is 1μF.

[0009] Furthermore, the capacitance of capacitor C4 is 3.9nF, the resistance of resistors R4 and R5 is 51Ω, the resistance of resistor R14 is 2kΩ, and the resistance of resistor R12 is 200Ω.

[0010] Furthermore, the resistance of resistor R9 is 300Ω, and the capacitance of capacitors C12 and C11 is 1μF.

[0011] Furthermore, the resistance of resistor R6 is 47Ω, the inductance of inductor L1 is 820nH, the capacitance of capacitor C6 is 430pF, the inductance of inductor L2 is 1.2μH, the capacitance of capacitor C7 is 220pF, the resistance of resistor R10 is 0Ω, and the resistance of resistor R13 is 51Ω.

[0012] Furthermore, the power supply voltages of power supplies V1, V4, and V6 are all +5V, while the power supply voltages of power supplies V2 and V3 are all -5V.

[0013] Furthermore, the frequency response characteristics of the intermediate frequency dynamic compression circuit satisfy the following: relative to the low frequency cutoff frequency, for every halving of the frequency, the out-of-band rejection increases by 12dB.

[0014] Furthermore, the operational amplifier is a THS4031 high-speed operational amplifier.

[0015] Meanwhile, the present invention also provides a linear frequency modulation system detection device, comprising an antenna, a transceiver assembly, a video amplifier, an intermediate frequency dynamic compression circuit as described above, an ADC chip, and a digital signal processor connected in sequence.

[0016] The beneficial effects of this invention are: The present invention provides a mid-frequency dynamic range compression circuit for a detection device, which can not only meet the requirements of target detection, but also greatly compress the dynamic range of the receiving channel, thereby simplifying circuit design, reducing system hardware costs, and greatly reducing the false alarm probability of the detection device. Attached Figure Description

[0017] Figure 1 This is a circuit diagram of the intermediate frequency dynamic compression circuit described in this invention; Figure 2 This is a block diagram illustrating the principle of the detection device with a mid-frequency dynamic compression circuit according to the present invention. Figure 3 This is a frequency response diagram of the filter circuit of the present invention; Figure 4 This is a frequency response characteristic diagram of the intermediate frequency compression circuit described in this invention.

[0018] Figure 5 This is a schematic block diagram of the detection device described in the background art; Figure 6 The principle block diagram of the far / near target channel described in the background technology; Detailed Implementation

[0019] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0020] This invention is based on the echo characteristics of linear frequency modulated (LFM) signals. When detecting near-range targets, the delay is short and the echo is strong, resulting in a low output intermediate frequency (IF) and high amplitude. When detecting far-range targets, the delay is long and the echo is weak, resulting in a high output IF and low amplitude. Therefore, only one filter circuit needs to be designed in the IF path to ensure low gain at low frequencies and high gain at high frequencies. This satisfies the target detection requirements while significantly compressing the dynamic range of the receiver's output IF signal. Figure 2 As shown.

[0021] The design principles of the intermediate frequency filter circuit are: the low-frequency cutoff frequency must ensure that the AD converter is not saturated, and the out-of-band suppression of the rising edge must ensure that the signal-to-noise ratio of the echo signal remains basically consistent within the effective distance range.

[0022] The low-frequency cutoff frequency of the intermediate frequency filter circuit is calculated as follows: S M +G TR +G S AD ... (1) S M AD -G TR -G S in: S M The echo power corresponding to the corner frequency; S AD This represents the maximum input power of the AD chip. G TR For the gain of the transceiver components; G S This is the gain of the video amplifier.

[0023] The maximum input signal power of the AD chip is: S AD =10+20*log10(0.5*V p-p )............ (2) in: V P-P This represents the maximum peak-to-peak value of the input signal to the AD chip.

[0024] The echo power S corresponding to the corner frequency can be calculated according to formula (1). M (P in formula (3)) r The distance R can be calculated from the echo power using formula (3): ……………………(3) in: : Indicates the transmission power; , : Indicates the gain of the transmitting and receiving antennas; : indicates RCS; : Indicates wavelength; L: represents system loss; : This refers to the detection distance.

[0025] ​​The echo distance R corresponding to the maximum input signal power of the AD chip can be calculated using Formula 3. That is, the echo distance corresponding to the low-frequency cutoff frequency of the intermediate frequency filter circuit is the echo frequency corresponding to R.

[0026] The design principle for out-of-band rejection of the rising edge of the intermediate frequency filter circuit is as follows: relative to the low-frequency corner frequency of the filter circuit, for every doubling of the frequency, the out-of-band rejection should increase by 12dB according to the radar equation (40*log10(2f / f)=12dB). Figure 3 As shown.

[0027] This design not only greatly compresses the dynamic range, but also ensures that the signal-to-noise ratio of the echo signal remains basically consistent across the detection range, increasing the reliability of target detection.

[0028] The intermediate frequency (IF) dynamic compression circuit is an active high-pass filter circuit used to compress the dynamic range and ensure near-range dead zones. The subsequent stage is an LC low-pass filter used to further suppress ground clutter. The complete schematic diagram of the IF dynamic compression circuit of this invention is shown below. Figure 1 As shown, the specific circuit structure is as follows: The intermediate frequency dynamic compression circuit includes an input impedance matching unit, a first-stage amplification unit, an inter-stage coupling and biasing unit, a second-stage amplification unit, and an output filtering and matching unit that are connected in sequence.

[0029] The input impedance matching unit includes a signal source VG1, resistors R7 and R11, and capacitor C3. Signal source VG1 is the output signal of the preamplifier video amplifier; one end is grounded, and the other end is electrically connected to one end of resistor R7 and one end of resistor R11. The other end of resistor R7 is grounded and has a resistance of 51Ω. The other end of resistor R11 is electrically connected to one end of capacitor C3 and has a resistance of 0Ω. The other end of capacitor C3 is the output terminal of the input impedance matching unit and has a capacitance of 3.9nF. This unit achieves precise matching with the 50Ω output impedance of the preamplifier video amplifier, reducing signal reflection and transmission loss. Simultaneously, capacitor C3, in conjunction with the input impedance, forms the first stage of a high-pass filter, achieving initial attenuation of low-frequency signals.

[0030] The first-stage amplification unit includes operational amplifier U1, resistors R3 and R2, capacitor C9, power supply V1, capacitor C10, and power supply V2. Operational amplifier U1 is a THS4031 high-speed operational amplifier, with its inverting input terminal electrically connected to the other end of capacitor C3. The non-inverting input terminal of operational amplifier U1 is electrically connected to one end of resistor R2, with the other end of resistor R2 grounded; the resistance is 51Ω. The two ends of resistor R3 are electrically connected to the inverting input and output terminals of operational amplifier U1, respectively, with a resistance of 200Ω, forming an inverting proportional amplifier circuit with a gain of 0. dB; The positive terminal of power supply V1 is electrically connected to the positive power supply terminal of operational amplifier U1 and one end of capacitor C9, respectively. The negative terminal of power supply V1 is grounded and the voltage is +5V. The other end of capacitor C9 is grounded and the capacitance is 1μF. The negative terminal of power supply V2 is electrically connected to the negative power supply terminal of operational amplifier U1 and one end of capacitor C10, respectively. The positive terminal of power supply V2 is grounded and the voltage is -5V. The other end of capacitor C10 is grounded and the capacitance is 1μF. Capacitors C9 and C10 are power supply decoupling capacitors, which are installed near the power supply pins of the op-amp to filter out power supply noise and ensure stable operation of the op-amp.

[0031] The interstage coupling and biasing unit includes capacitor C4, resistor R4, resistor R5, power supply V6, resistor R14, and resistor R12. One end of capacitor C4 is electrically connected to the output of operational amplifier U1, with a capacitance of 3.9nF. It is a DC blocking capacitor, isolating the DC component of the preceding stage and transmitting only the AC intermediate frequency signal. The other end of capacitor C4 is electrically connected to one end of resistor R4 and one end of resistor R5. The other end of resistor R4 is grounded, with a resistance of 51Ω. The other end of resistor R5 is electrically connected to the inverting input of operational amplifier U3. The resistance is 51Ω; the positive terminal of power supply V6 is electrically connected to one end of resistor R14, and the negative terminal of power supply V6 is grounded, with a voltage of +5V; the other end of resistor R14 is electrically connected to one end of resistor R12 and the non-inverting input terminal of operational amplifier U3, with a resistance of 2kΩ; the other end of resistor R12 is grounded, with a resistance of 200Ω; resistors R14 and R12 form a voltage divider circuit to provide a stable DC bias of 1.65V to the non-inverting input terminal of operational amplifier U3, ensuring that the op-amp operates in the linear region and avoiding signal clipping distortion.

[0032] The second-stage amplification unit includes operational amplifier U3, resistor R9, capacitor C12, power supply V4, capacitor C11, and power supply V3. Operational amplifier U3 also uses the THS4031 high-speed operational amplifier. Its inverting input is electrically connected to the other end of resistor R5, and its non-inverting input is electrically connected to the common connection terminal of resistors R14 and R12. The two ends of resistor R9 are electrically connected to the inverting input and output terminals of operational amplifier U3, respectively. The resistance is 300Ω, forming an inverting proportional amplifier circuit with a gain of 0dB, which is matched with the first-stage amplification unit. The circuit is designed to ensure high uniformity of gain within the passband. The positive terminal of power supply V4 is electrically connected to the positive power supply terminal of operational amplifier U3 and one end of capacitor C12. The negative terminal of power supply V4 is grounded, with a voltage of +5V. The other end of capacitor C12 is grounded, with a capacitance of 1μF. The negative terminal of power supply V3 is electrically connected to the negative power supply terminal of operational amplifier U3 and one end of capacitor C11. The positive terminal of power supply V3 is grounded, with a voltage of -5V. The other end of capacitor C11 is grounded, with a capacitance of 1μF. Capacitors C12 and C11 are power supply decoupling capacitors to filter out power supply noise.

[0033] The output filtering and matching unit includes resistor R6, inductor L1, capacitor C6, inductor L2, capacitor C7, resistor R10, resistor R13, and output terminal VT1. One end of resistor R6 is electrically connected to the output terminal of operational amplifier U3, with a resistance of 47Ω, serving as a current-limiting matching resistor. The other end of inductor L1 is electrically connected to one end of capacitor C6 and one end of inductor L2, with an inductance of 820nH. The other end of capacitor C6 is grounded, with a capacitance of 430pF. The other end of inductor L2 is electrically connected to one end of capacitor C7 and one end of resistor R10, with an inductance of 1.2μH. The other end of capacitor C7 is grounded, with a capacitance of 220pF. Inductor L1, capacitor C6, inductor L2, and capacitor C7 form a second-order Butterworth LC low-pass filter, achieving a high-frequency cutoff frequency of 150kHz and out-of-band rejection of 40dB@300kHz, effectively filtering out ground clutter and out-of-band high-frequency interference signals. The other end of resistor R10 is electrically connected to one end of resistor R13 and the output terminal VT1, with a resistance of 0Ω. The other end of resistor R13 is grounded, with a resistance of 51Ω. Resistors R10 and R13 form an output impedance matching network, which is precisely matched with the 50Ω input impedance of the subsequent ADC chip to ensure sampling accuracy. The output terminal VT1 is directly connected to the analog signal input terminal of the ADC chip.

[0034] The frequency response curve of the intermediate frequency compression circuit of the present invention is as follows: Figure 4 As shown, by Figure 4 The results show that after high-pass filtering, the receiver's dynamic range is compressed by at least 40dB, so the intermediate frequency output range is at most about 60dB. For this dynamic range, a 12-bit ADC is sufficient to meet the requirements.

[0035] This invention provides an intermediate frequency dynamic compression circuit for a linear frequency modulated (LFM) detection device. The LFM continuous wave radar detection device has the following core parameters: carrier frequency 10 GHz, frequency modulation bandwidth 150 MHz, maximum reliable operating distance 150 m, near-range blind zone 1.5 m, transceiver gain GTR=40 dB, video amplifier gain GS=20 dB, and a 12-bit ADC chip with a maximum peak-to-peak input Vp-p=2 V.

Claims

1. A medium-frequency dynamic compression circuit for a linear frequency modulation detection device, characterized in that: It includes an input impedance matching unit, a first-stage amplification unit, an inter-stage coupling and biasing unit, a second-stage amplification unit, and an output filtering and matching unit that are connected in sequence. The input impedance matching unit includes a signal source VG1, a resistor R7, a resistor R11, and a capacitor C3; one end of the signal source VG1 is grounded, and the other end is electrically connected to one end of the resistor R7 and one end of the resistor R11 respectively; the other end of the resistor R7 is grounded; the other end of the resistor R11 is electrically connected to one end of the capacitor C3; the other end of the capacitor C3 is the output terminal of the input impedance matching unit. The first-stage amplification unit includes an operational amplifier U1, resistors R3 and R2, capacitor C9, power supply V1, capacitor C10, and power supply V2. The inverting input terminal of operational amplifier U1 is electrically connected to the other end of capacitor C3. The non-inverting input terminal of operational amplifier U1 is electrically connected to one end of resistor R2, and the other end of resistor R2 is grounded. The two ends of resistor R3 are electrically connected to the inverting input terminal and the output terminal of operational amplifier U1, respectively. The positive terminal of power supply V1 is electrically connected to the positive power supply terminal of operational amplifier U1 and one end of capacitor C9, the negative terminal of power supply V1 is grounded, and the other end of capacitor C9 is grounded. The negative terminal of power supply V2 is electrically connected to the negative power supply terminal of operational amplifier U1 and one end of capacitor C10, the positive terminal of power supply V2 is grounded, and the other end of capacitor C10 is grounded. The interstage coupling and biasing unit includes capacitor C4, resistors R4 and R5, power supply V6, resistors R14 and R12; one end of capacitor C4 is electrically connected to the output terminal of operational amplifier U1; the other end of capacitor C4 is electrically connected to one end of resistor R4 and one end of resistor R5 respectively; the other end of resistor R4 is grounded; the positive terminal of power supply V6 is electrically connected to one end of resistor R14, and the negative terminal of power supply V6 is grounded; the other end of resistor R14 is electrically connected to one end of resistor R12 and the non-inverting input terminal of operational amplifier U3 respectively; the other end of resistor R12 is grounded; the other end of resistor R5 is electrically connected to the inverting input terminal of operational amplifier U3. The second-stage amplification unit includes operational amplifier U3, resistor R9, capacitor C12, power supply V4, capacitor C11, and power supply V3. The two ends of resistor R9 are electrically connected to the inverting input and output terminals of operational amplifier U3, respectively. The positive terminal of power supply V4 is electrically connected to the positive power supply terminal of operational amplifier U3 and one end of capacitor C12, while the negative terminal of power supply V4 is grounded, and the other end of capacitor C12 is grounded. The negative terminal of power supply V3 is electrically connected to the negative power supply terminal of operational amplifier U3 and one end of capacitor C11, while the positive terminal of power supply V3 is grounded, and the other end of capacitor C11 is grounded. Both operational amplifiers U1 and U3 are THS4031 high-speed operational amplifiers. The output filtering and matching unit includes resistor R6, inductor L1, capacitor C6, inductor L2, capacitor C7, resistor R10, resistor R13, and output terminal VT1. One end of resistor R6 is electrically connected to the output terminal of operational amplifier U3; the other end of resistor R6 is electrically connected to one end of inductor L1; the other end of inductor L1 is electrically connected to one end of capacitor C6 and one end of inductor L2 respectively; the other end of capacitor C6 is grounded; the other end of inductor L2 is electrically connected to one end of capacitor C7 and one end of resistor R10 respectively; the other end of capacitor C7 is grounded; the other end of resistor R10 is electrically connected to one end of resistor R13 and output terminal VT1 respectively; the other end of resistor R13 is grounded.

2. The intermediate frequency dynamic compression circuit according to claim 1, characterized in that, The resistance of resistor R7 is 51Ω, the resistance of resistor R11 is 0Ω, and the capacitance of capacitor C3 is 3.9nF.

3. The intermediate frequency dynamic compression circuit according to claim 1, characterized in that, The resistance of resistor R3 is 200Ω, the resistance of resistor R2 is 51Ω, and the capacitance of capacitors C9 and C10 is 1μF.

4. The intermediate frequency dynamic compression circuit according to claim 1, characterized in that, The capacitor C4 has a capacitance of 3.9nF, resistors R4 and R5 both have a resistance of 51Ω, resistor R14 has a resistance of 2kΩ, and resistor R12 has a resistance of 200Ω.

5. The intermediate frequency dynamic compression circuit according to claim 1, characterized in that, The resistance of resistor R9 is 300Ω, and the capacitance of capacitors C12 and C11 is 1μF.

6. The intermediate frequency dynamic compression circuit according to claim 1, characterized in that, The resistor R6 has a resistance of 47Ω, the inductor L1 has an inductance of 820nH, the capacitor C6 has a capacitance of 430pF, the inductor L2 has an inductance of 1.2μH, the capacitor C7 has a capacitance of 220pF, the resistor R10 has a resistance of 0Ω, and the resistor R13 has a resistance of 51Ω.

7. The intermediate frequency dynamic compression circuit according to claim 1, characterized in that, The power supply voltages of power supplies V1, V4, and V6 are all +5V, while the power supply voltages of power supplies V2 and V3 are all -5V.

8. The intermediate frequency dynamic compression circuit according to claim 1, characterized in that, The frequency response characteristics of the intermediate frequency dynamic compression circuit satisfy the following: for every halving of the frequency relative to the low frequency cutoff frequency, the out-of-band rejection increases by 12dB.

Images