A duty cycle control circuit for a radio frequency power amplifier

Abstract

The application discloses a duty cycle control circuit for a radio frequency power amplifier and belongs to the field of radio frequency front-end integrated circuits. The duty cycle control circuit internally comprises six parts of a shaping amplifier, a clock buffer, a feedback resistor, a charging and discharging capacitor, a resistor array and a comparison amplifier. The shaping amplifier converts a differential sinusoidal signal from a phase-locked loop into a single-ended square wave signal, and the clock buffer controls the duty cycle of an input signal under the control of a feedback voltage. Four digital signals access the voltage of the circuit through four parallel resistors, and in combination with the feedback resistor, the capacitor voltage can be dynamically balanced, and then through the comparison amplifier, a pair of clamping voltages are output to act on the clock buffer to control the duty cycle of the output signal. The output signal is charged and discharged to the capacitor through the feedback resistor, so that the whole control loop is stable, and the accurate control and adjustment of the duty cycle of the output signal are realized.

Description

Technical Field

[0001] This invention relates to the field of radio frequency front-end integrated circuit technology, and in particular to a duty cycle control circuit for a radio frequency power amplifier. Background Technology

[0002] The duty cycle of a signal refers to the ratio of the time a high level is present to the total time of the signal cycle, and it is a crucial parameter that requires special attention in signal processing. In the design of power amplifiers, the output power is often controlled by adjusting the output current or voltage. The power amplifier achieves its highest power efficiency at maximum output power; however, power amplifiers typically operate in low-power mode, requiring voltage or current reduction for power back-off, which leads to a sharp decrease in power efficiency.

[0003] Traditionally, improving power amplifier back-off efficiency involves a Doherty architecture, using a main amplifier and a peak amplifier. In high-power scenarios, both the peak amplifier and main amplifier are activated to provide maximum output power; in low-power scenarios, the peak amplifier is deactivated while the main amplifier is activated for power back-off, achieving high back-off efficiency. This method offers good performance but suffers from complex circuitry. However, adjusting the signal duty cycle to achieve power back-off offers higher efficiency than reducing voltage or current. Compared to the Doherty architecture, the duty cycle control circuit is simpler, providing a better solution to address the efficiency reduction during power amplifier back-off. Introducing a duty cycle control circuit into the power amplifier is crucial for transmitter output power regulation, average power control, and energy-saving management, and is key to improving power amplifier power efficiency.

[0004] Traditional duty cycle control circuits often employ a fixed feedback structure. By detecting the difference between the current signal's duty cycle and a preset value, a feedback voltage is generated for the duty cycle control circuit. This is typically used to stabilize the signal's duty cycle to a fixed value. However, it cannot perform gradient adjustment or precise control of the duty cycle and is not suitable for power control and efficiency improvement in power amplifiers. Summary of the Invention

[0005] The purpose of this invention is to provide a duty cycle control circuit for an RF power amplifier to solve the problem of significant efficiency reduction in RF power amplifiers during power back-off.

[0006] To address the aforementioned technical problems, this invention provides a duty cycle control circuit for an RF power amplifier, comprising: The shaping amplifier adopts a differential folded cascode structure with dual-ended input and single-ended output. It converts the input sinusoidal differential signals INP and INN into single-ended signals, and outputs a square wave signal IN after passing through an inverter. The clock buffer consists of a six-stage inverter chain. The middle four inverters are connected to voltage-controlled NMOS transistors as voltage-controlled adjustable resistors. Under the control of clamping voltages Vb1 and Vb2, they affect the rise and fall times of the input signal IN in the inverter chain, thereby controlling the duty cycle. Based on the magnitude of clamping voltages Vb1 and Vb2, a square wave signal Y with a specific duty cycle is output. The feedback resistor R feeds the signal Y output by the clock buffer back to the capacitor C, causing the capacitor C to charge and discharge continuously, so that the voltage of node X fluctuates within a certain range to achieve dynamic balance and stabilize the control loop. Capacitor C charges and discharges at node X to form a balanced feedback voltage. After differential amplification with the comparison voltage of the comparator amplifier, it forms a pair of relatively stable clamping voltages Vb1 and Vb2, which are used to control the duty cycle of the signal in the clock buffer. The resistor array consists of four resistors connected in parallel between nodes X of the RC circuit. Four control signals D<3:0> control the voltage connected to the four resistors respectively, initially determining the voltage of node X after capacitor C is charged, and realizing 16-level stepped voltage adjustment. The output signal Y of the clock buffer charges and discharges capacitor C through the feedback resistor R, so that the voltage of node X reaches dynamic balance. It is used as a feedback signal to compare with the preset voltage Vref of the comparator amplifier, and outputs a pair of stable clamping voltages Vb1 and Vb2. The comparator amplifier employs a differential folded cascode structure with dual-input and dual-output. One input terminal is connected to a preset voltage Vref, and the other terminal is connected to the node voltage X for the charging and discharging of capacitor C. An NMOS transistor with diode connection is used as the load, connected in parallel with a large capacitor, so that the output voltage is pulled up from 0 V and the charging time of the output node is lengthened. The settling time of the op-amp is different under different node voltages X, and the output clamping voltages Vb1 and Vb2 are also different, thereby controlling the duty cycle of the output signal of the clock buffer.

[0007] In one embodiment, the shaping amplifier includes a current source I1, NMOS transistors M1, M2, M7, and M8, and PMOS transistors M3, M4, M5, and M6. The gate terminals of NMOS transistors M1 and M2 are connected to the sinusoidal differential signals INN and INP, respectively. The source terminals of both are connected to the input terminal of current source I1, and the output terminal of current source I1 is grounded. The drain terminal of NMOS transistor M1 is connected to the drain terminal of PMOS transistor M3 and the source terminal of PMOS transistor M5, and the drain terminal of NMOS transistor M2 is connected to the drain terminal of PMOS transistor M4 and the source terminal of PMOS transistor M6. The source terminals of PMOS transistors M3 and M4 are both connected to VDD, and the gate terminals of PMOS transistors M3 and M4 are connected to voltage Vb. The gate terminals of PMOS transistors M5 and M6 are connected to voltage Vb, and the drain terminal of PMOS transistor M5 is connected to the drain terminal of NMOS transistor M7. The drain terminals of PMOS transistors M6 and M8 together output a square wave signal IN through an inverter. The drain terminal of NMOS transistor M7 is connected to both its own gate terminal and the gate terminal of NMOS transistor M8, and the source terminals of NMOS transistors M7 and M8 are both grounded.

[0008] In one embodiment, the clock buffer includes PMOS transistors M12, M14, M16, M18, M20, M22, and NMOS transistors M11, M13, M15, M17, M19, M21, M23~M26. The sources of PMOS transistors M12, M14, M16, M18, M20, and M22 are all connected to VDD. The gate of PMOS transistor M12 and the gate of NMOS transistor M11 are both connected to the square wave signal IN. The drain of PMOS transistor M12 and the drain of NMOS transistor M11 are connected to the gate of PMOS transistor M14 and the gate of NMOS transistor M13. The drain of PMOS transistor M14 and the drain of NMOS transistor M13 are connected to the gate of PMOS transistor M16 and the gate of NMOS transistor M15. The drain of PMOS transistor M16 and NMOS transistor M22 are connected to the gate of NMOS transistor M15. The drain of MOSFET M15 is connected to the gate of PMOS transistor M18 and the gate of NMOS transistor M17. The drain of PMOS transistor M18 and the drain of NMOS transistor M17 are connected to the gate of PMOS transistor M20 and the gate of NMOS transistor M19. The drain of PMOS transistor M20 and the drain of NMOS transistor M19 are connected to the gate of PMOS transistor M22 and the gate of NMOS transistor M21. The drain of PMOS transistor M22 and the drain of NMOS transistor M21 are used as the output terminals to output a square wave signal Y with a specific duty cycle. The source terminals of NMOS transistors M11 and M21 are both grounded. The source terminal of NMOS transistor M13 is connected to the drain terminal of NMOS transistor M23, and the gate terminal of NMOS transistor M23 is connected to the clamping voltage Vb1. The source terminal of NMOS transistor M15 is connected to the drain terminal of NMOS transistor M24, and the gate terminal of NMOS transistor M24 is connected to the clamping voltage Vb2. The source terminal of NMOS transistor M17 is connected to the drain terminal of NMOS transistor M25, and the gate terminal of NMOS transistor M25 is connected to the clamping voltage Vb1. The source terminal of NMOS transistor M19 is connected to the drain terminal of NMOS transistor M26, and the gate terminal of NMOS transistor M26 is connected to the clamping voltage Vb2. The sources of NMOS transistors M23 through M26 are all grounded.

[0009] In one embodiment, the comparator amplifier includes NMOS transistors M31, M32, M37, M38, and M39, PMOS transistors M33, M34, M35, and M36, a current source I2, resistors R31 and R32, and capacitors C31 and C32. The gate of NMOS transistor M31 is connected to ground X, the gate of NMOS transistor M32 is connected to the preset voltage Vref, the drain of NMOS transistor M31 is connected to the drain of NMOS transistor M33 and the source of NMOS transistor M35, the drain of NMOS transistor M32 is connected to the drain of NMOS transistor M34 and the source of NMOS transistor M36, the source of NMOS transistor M31 and the source of NMOS transistor M32 are connected to the input of current source I2, and the output of current source I2 is grounded. The source terminals of NMOS transistors M33 and M34 are both connected to voltage VDD, and the gate terminals of NMOS transistors M33 and M34 are both connected to voltage Vb; the gate terminals of NMOS transistors M35 and M36 are both connected to bias voltage Vb, and the drain terminals of NMOS transistors M35 and M36 are connected to clamping voltages Vb1 and Vb2, respectively. The first terminal of resistor R31, the first terminal of capacitor C31, and the drain terminal of NMOS transistor M37 are connected to the clamping voltage Vb1. The second terminal of resistor R32, the second terminal of capacitor C32, and the drain terminal of NMOS transistor M38 are connected to the clamping voltage Vb2. The second terminal of resistor R31, the first terminal of resistor R32, the second terminal of capacitor C31, the first terminal of capacitor C32, the gate terminal of NMOS transistor M37, and the gate terminal of NMOS transistor M38 are connected to the drain terminal of NMOS transistor M39. The source terminals of NMOS transistors M37, M38, and M39 are grounded.

[0010] The present invention provides a duty cycle control circuit for an RF power amplifier, which can be applied to the power control and efficiency improvement of the RF power amplifier. By reducing the signal duty cycle, power back-off is performed, thereby improving the back-off efficiency of the power amplifier. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of the duty cycle control circuit for an RF power amplifier provided by the present invention. Figure 2 This is a schematic diagram of the structure of the shaping amplifier provided by the present invention; Figure 3 This is a schematic diagram of the clock buffer provided by the present invention; Figure 4 This is a schematic diagram of the resistor array provided by the present invention; Figure 5 This is a schematic diagram of the comparator amplifier provided by the present invention; Figure 6This is a waveform diagram illustrating the change in the duty cycle of the input and output signals under two control signals according to the present invention. Detailed Implementation

[0012] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the duty cycle control circuit for an RF power amplifier proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0013] This invention provides a duty cycle control circuit for power control and efficiency improvement of an RF power amplifier, the circuit structure of which is as follows: Figure 1 As shown, it internally includes a shaping amplifier, a clock buffer, a feedback resistor R, a capacitor C, a resistor array, and a comparator amplifier.

[0014] The shaping amplifier adopts a differential folded cascode structure with dual-ended input and single-ended output. It converts the input sinusoidal differential signals INP and INN into single-ended signals, and outputs a square wave signal IN after passing through an inverter. The clock buffer consists of a six-stage inverter chain. The middle four inverters are connected to voltage-controlled NMOS transistors as voltage-controlled adjustable resistors. Under the control of clamping voltages Vb1 and Vb2, they affect the rise and fall times of the input signal IN in the inverter chain, thereby controlling the duty cycle. Based on the magnitude of clamping voltages Vb1 and Vb2, a square wave signal Y with a specific duty cycle is output. The feedback resistor R feeds the signal Y output by the clock buffer back to the capacitor C, causing the capacitor C to charge and discharge continuously, so that the voltage of node X fluctuates within a certain range to achieve dynamic balance and stabilize the control loop. Capacitor C charges and discharges at node X to form a balanced feedback voltage. After differential amplification with the comparison voltage of the comparator amplifier, it forms a pair of relatively stable clamping voltages Vb1 and Vb2, which are used to control the duty cycle of the signal in the clock buffer. The resistor array consists of four resistors connected in parallel between nodes X of the RC circuit. Four control signals D<3:0> control the voltage connected to the four resistors respectively, initially determining the voltage of node X after capacitor C is charged, and realizing 16-level stepped voltage adjustment. The output signal Y of the clock buffer charges and discharges capacitor C through the feedback resistor R, so that the voltage of node X reaches dynamic balance. It is used as a feedback signal to compare with the preset voltage Vref of the comparator amplifier, and outputs a pair of stable clamping voltages Vb1 and Vb2. The comparator amplifier employs a differential folded cascode structure with dual-input and dual-output. One input terminal is connected to the set comparator voltage Vref, and the other terminal is connected to the node voltage X for the charging and discharging of capacitor C. An NMOS transistor with diode connection is used as the load, connected in parallel with a large capacitor, so that the output voltage is pulled up from 0 V and the charging time of the output node is lengthened. The settling time of the op-amp is different under different node voltages X, and the output clamping voltages Vb1 and Vb2 are also different, thereby controlling the duty cycle of the output signal of the clock buffer.

[0015] like Figure 2 The diagram shows the structure of a shaping amplifier, including a current source I1, NMOS transistors M1, M2, M7, and M8, and PMOS transistors M3, M4, M5, and M6. The gate terminals of NMOS transistors M1 and M2 are connected to the sinusoidal differential signals INN and INP, respectively, and their source terminals are connected to the input terminal of current source I1. The output terminal of current source I1 is grounded. The drain terminal of NMOS transistor M1 is simultaneously connected to the drain terminal of PMOS transistor M3 and the source terminal of PMOS transistor M5, and the drain terminal of NMOS transistor M2 is simultaneously connected to the drain terminal of PMOS transistor M4 and the source terminal of PMOS transistor M6. The source terminals of S-MOSFET M3 and PMOS MOSFET M4 are both connected to VDD. The gate terminals of PMOS MOSFET M3 and PMOS MOSFET M4 are connected to voltage Vb. The gate terminals of PMOS MOSFET M5 and PMOS MOSFET M6 are connected to bias voltage Vb. The drain terminal of PMOS MOSFET M5 is connected to the drain terminal of NMOS MOSFET M7. The drain terminals of PMOS MOSFET M6 and NMOS MOSFET M8 together output a square wave signal IN through an inverter. The drain terminal of NMOS MOSFET M7 is connected to both its own gate terminal and the gate terminal of NMOS MOSFET M8. The source terminals of NMOS MOSFET M7 and NMOS MOSFET M8 are both grounded.

[0016] The differential sinusoidal signals INP and INN from the phase-locked loop first enter the shaping amplifier with a differential folded cascode structure. The input signal is applied to the common-source input terminal formed by NMOS transistors M1 and M2, and PMOS transistors M5 and M6 serve as common gates with single-ended output. The amplified single-ended signal is shaped by an inverter, converting the input sinusoidal differential signals INN and INP into square wave signals IN for output, which then enters the clock buffer for duty cycle control.

[0017] The clock buffer uses a six-stage cascaded inverter structure to form an inverter chain, such as... Figure 3As shown, the transistors include PMOS transistors M12, M14, M16, M18, M20, M22, and NMOS transistors M11, M13, M15, M17, M19, M21, and M23~M26. The sources of PMOS transistors M12, M14, M16, M18, M20, and M22 are all connected to VDD. The gates of PMOS transistor M12 and NMOS transistor M11 are both connected to a square wave signal IN. The drains of PMOS transistor M12 and NMOS transistor M11 are connected together. The gates of PMOS transistor M14 and NMOS transistor M13 are connected together. The drains of PMOS transistor M14 and NMOS transistor M13 are connected together to the gates of PMOS transistor M16 and NMOS transistor M15. The drains of PMOS transistor M16 and NMOS transistor M15 are connected together to the gates of PMOS transistor M18 and NMOS transistor M17. The drains of PMOS transistor M18 and NMOS transistor M17 are connected together to the gates of PMOS transistor M20 and NMOS transistor M15. The gate of S-MOSFET M19, the drain of PMOS transistor M20, and the drain of NMOS transistor M19 are all connected to the gates of PMOS transistor M22 and NMOS transistor M21. The drains of PMOS transistor M22 and NMOS transistor M21 together serve as the output terminals, outputting a square wave signal Y with a specific duty cycle. The sources of NMOS transistors M11 and M21 are both grounded. The source of NMOS transistor M13 is connected to the drain of NMOS transistor M23. The gate of NMOS transistor M23... The source of NMOS transistor M15 is connected to the drain of NMOS transistor M24, the gate of NMOS transistor M24 is connected to the clamping voltage Vb2, the source of NMOS transistor M17 is connected to the drain of NMOS transistor M25, the gate of NMOS transistor M25 is connected to the clamping voltage Vb1, the source of NMOS transistor M19 is connected to the drain of NMOS transistor M26, the gate of NMOS transistor M26 is connected to the clamping voltage Vb2, and the sources of NMOS transistors M23 to M26 are all grounded.

[0018] Each of the four intermediate inverter stages is connected to an NMOS transistor with an adjustable bias voltage. These NMOS transistors act as voltage-controlled variable resistors, their resistance values ​​controlled by clamping voltages Vb1 and Vb2. Different resistor values ​​affect the fall time of the output waveform. The square wave signal IN, input to the clock buffer from the shaping amplifier, is inverted and then undergoes waveform conversion through this four-stage structure. After passing through the inverters, a signal Y with a specific duty cycle is output. This duty cycle is determined by the voltage-controlled resistor value of the NMOS transistor, i.e., controlled by the bias voltages Vb1 and Vb2 (i.e., clamping voltages Vb1 and Vb2). This clock buffer allows for precise adjustment of the signal duty cycle under voltage control.

[0019] like Figure 4As shown, the resistor array consists of four resistors R3, R2, R1, and R0 connected in parallel at node X between RC circuits. Four control signals D<3:0> control the voltage connected to each of the four resistors, thus initially determining the voltage X of capacitor C after charging and enabling 16-level stepped voltage adjustment. Furthermore, the output node Y of the clock buffer charges and discharges capacitor C through the feedback resistor R, causing voltage fluctuations at point X to maintain dynamic balance. The four control signals D<3:0> can control the voltage at node X within a set range.

[0020] like Figure 5 As shown, the comparator amplifier adopts a differential folded cascode structure with dual-input and dual-output, including NMOS transistors M31, M32, M37, M38, and M39, PMOS transistors M33, M34, M35, and M36, current source I2, resistors R31 and R32, and capacitors C31 and C32. The gate of NMOS transistor M31 is connected to ground X, the gate of NMOS transistor M32 is connected to a preset voltage Vref, the drain of NMOS transistor M31 is connected to both the drain of NMOS transistor M33 and the source of NMOS transistor M35, the drain of NMOS transistor M32 is connected to both the drain of NMOS transistor M34 and the source of NMOS transistor M36, the source of NMOS transistors M31 and M32 are connected to the input of current source I2, and the output of current source I2 is grounded; the source of NMOS transistor M33 and the source of NMOS transistor M34 are connected to the input of current source I2. All terminals are connected to voltage VDD. The gate terminals of NMOS transistors M33 and M34 are connected to voltage Vb. The gate terminals of NMOS transistors M35 and M36 are connected to voltage Vb. The drain terminals of NMOS transistors M35 and M36 are connected to clamping voltages Vb1 and Vb2, respectively. The first terminal of resistor R31, the first terminal of capacitor C31, and the drain terminal of NMOS transistor M37 are connected to clamping voltage Vb1. The second terminal of resistor R32, the second terminal of capacitor C32, and the drain terminal of NMOS transistor M38 are connected to clamping voltage Vb2. The second terminal of resistor R31, the first terminal of resistor R32, the second terminal of capacitor C31, the first terminal of capacitor C32, the gate terminals of NMOS transistors M37 and M38 are connected to the drain terminal of NMOS transistor M39. The source terminals of NMOS transistors M37, M38, and M39 are grounded.

[0021] NMOS transistors M37 and M38, connected in diode configuration, are used as loads and connected in parallel with large capacitors C31 and C32. This allows the output voltages Vb1 and Vb2 to be pulled up from 0 V and extends the charging time of the output node. The stabilization time of the op-amp varies under different feedback voltages X, and the output clamping voltages Vb1 and Vb2 also vary, thereby controlling the duty cycle of the clock buffer's output signal.

[0022] When the control signals D<3:0> are <0;0;0;1> and <1;0;0;0> respectively, the waveforms of the square wave signal IN and the output signal Y changing their duty cycles are as follows: Figure 6 As shown.

[0023] In summary, the duty cycle control circuit proposed in this invention first converts the sinusoidal differential signal from the phase-locked loop into a single-ended square wave signal via a shaping amplifier, which then enters the clock buffer for subsequent duty cycle processing. The resistor array independently controls the input voltage of the four parallel resistors using a four-bit digital signal, achieving precise control of the target voltage of capacitor C. Combined with the feedback resistor R, the output voltage of the clock buffer is introduced into the capacitor node, causing capacitor C to continuously charge and discharge, ultimately achieving dynamic voltage equilibrium. The comparator amplifier compares the preset voltage Vref with the capacitor voltage, outputting clamping voltages Vb1 and Vb2 of different magnitudes as feedback voltages. These voltages control the NMOS transistors connected to the four inverters in the middle of the clock buffer, allowing the NMOS transistors to act as voltage-controlled adjustable resistors, influencing the fall time of the inverter output signal. The square wave signal input to the clock buffer from the shaping amplifier is inverted and then undergoes waveform conversion through a four-stage structure. After passing through an inverter, a signal with a specific duty cycle is output. The duty cycle is determined by the voltage-controlled resistor value of the NMOS transistor connected below, i.e., controlled by voltages Vb1 and Vb2, which are controlled by the capacitor voltage. Through feedback resistors and resistor arrays, the capacitor voltage can be kept balanced at a specific value, maintaining the stability of the control loop, thereby achieving precise adjustment of the signal duty cycle under the control of a four-bit digital signal.

[0024] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.

[0025] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A duty cycle control circuit for a radio frequency power amplifier, characterized by, include: The shaping amplifier adopts a differential folded cascode structure with dual-ended input and single-ended output. It converts the input sinusoidal differential signals INP and INN into single-ended signals, and outputs a square wave signal IN after passing through an inverter. The clock buffer consists of a six-stage inverter chain. The middle four inverters are connected to voltage-controlled NMOS transistors as voltage-controlled adjustable resistors. Under the control of clamping voltages Vb1 and Vb2, they affect the rise and fall times of the input signal IN in the inverter chain, thereby controlling the duty cycle. Based on the magnitude of clamping voltages Vb1 and Vb2, a square wave signal Y with a specific duty cycle is output. The feedback resistor R feeds the signal Y output by the clock buffer back to the capacitor C, causing the capacitor C to charge and discharge continuously, so that the voltage of node X fluctuates within a certain range to achieve dynamic balance and stabilize the control loop. Capacitor C charges and discharges at node X to form a balanced feedback voltage. After differential amplification with the comparison voltage of the comparator amplifier, it forms a pair of relatively stable clamping voltages Vb1 and Vb2, which are used to control the duty cycle of the signal in the clock buffer. The resistor array consists of four resistors connected in parallel between nodes X of the RC circuit. Four control signals D<3:0> control the voltage connected to the four resistors respectively, initially determining the voltage of node X after capacitor C is charged, and realizing 16-level stepped voltage adjustment. The output signal Y of the clock buffer charges and discharges capacitor C through the feedback resistor R, so that the voltage of node X reaches dynamic balance. It is used as a feedback signal to compare with the preset voltage Vref of the comparator amplifier, and outputs a pair of stable clamping voltages Vb1 and Vb2. The comparator amplifier employs a differential folded cascode structure with dual-input and dual-output. One input terminal is connected to a preset voltage Vref, and the other terminal is connected to the node voltage X for the charging and discharging of capacitor C. An NMOS transistor with diode connection is used as the load, connected in parallel with a large capacitor, so that the output voltage is pulled up from 0 V and the charging time of the output node is lengthened. The settling time of the op-amp is different under different node voltages X, and the output clamping voltages Vb1 and Vb2 are also different, thereby controlling the duty cycle of the output signal of the clock buffer.

2. The duty cycle control circuit for a radio frequency power amplifier of claim 1, wherein, The shaping amplifier includes a current source I1, NMOS transistors M1, M2, M7, and M8, and PMOS transistors M3, M4, M5, and M6; The gate terminals of NMOS transistors M1 and M2 are connected to the sinusoidal differential signals INN and INP, respectively. The source terminals of both are connected to the input terminal of current source I1, and the output terminal of current source I1 is grounded. The drain terminal of NMOS transistor M1 is connected to the drain terminal of PMOS transistor M3 and the source terminal of PMOS transistor M5, and the drain terminal of NMOS transistor M2 is connected to the drain terminal of PMOS transistor M4 and the source terminal of PMOS transistor M6. The source terminals of PMOS transistors M3 and M4 are both connected to VDD, and the gate terminals of PMOS transistors M3 and M4 are connected to voltage Vb. The gate terminals of PMOS transistors M5 and M6 are connected to bias voltage Vb. The drain terminal of PMOS transistor M5 is connected to the drain terminal of NMOS transistor M7. The drain terminals of PMOS transistors M6 and M8 together output a square wave signal IN through an inverter. The drain terminal of NMOS transistor M7 is connected to both its own gate terminal and the gate terminal of NMOS transistor M8. The source terminals of NMOS transistors M7 and M8 are both grounded.

3. The duty cycle control circuit for a radio frequency power amplifier of claim 1, wherein, The clock buffer includes PMOS transistors M12, M14, M16, M18, M20, M22, and NMOS transistors M11, M13, M15, M17, M19, M21, M23~M26; The sources of PMOS transistors M12, M14, M16, M18, M20, and M22 are all connected to VDD. The gate of PMOS transistor M12 and the gate of NMOS transistor M11 are both connected to the square wave signal IN. The drain of PMOS transistor M12 and the drain of NMOS transistor M11 are connected to the gate of PMOS transistor M14 and the gate of NMOS transistor M13. The drain of PMOS transistor M14 and the drain of NMOS transistor M13 are connected to the gate of PMOS transistor M16 and the gate of NMOS transistor M15. The drain of PMOS transistor M16 and NMOS transistor M22 are connected to the gate of NMOS transistor M15. The drain of MOSFET M15 is connected to the gate of PMOS transistor M18 and the gate of NMOS transistor M17. The drain of PMOS transistor M18 and the drain of NMOS transistor M17 are connected to the gate of PMOS transistor M20 and the gate of NMOS transistor M19. The drain of PMOS transistor M20 and the drain of NMOS transistor M19 are connected to the gate of PMOS transistor M22 and the gate of NMOS transistor M21. The drain of PMOS transistor M22 and the drain of NMOS transistor M21 are used as the output terminals to output a square wave signal Y with a specific duty cycle. The source terminals of NMOS transistors M11 and M21 are both grounded. The source terminal of NMOS transistor M13 is connected to the drain terminal of NMOS transistor M23, and the gate terminal of NMOS transistor M23 is connected to the clamping voltage Vb1. The source terminal of NMOS transistor M15 is connected to the drain terminal of NMOS transistor M24, and the gate terminal of NMOS transistor M24 is connected to the clamping voltage Vb2. The source terminal of NMOS transistor M17 is connected to the drain terminal of NMOS transistor M25, and the gate terminal of NMOS transistor M25 is connected to the clamping voltage Vb1. The source terminal of NMOS transistor M19 is connected to the drain terminal of NMOS transistor M26, and the gate terminal of NMOS transistor M26 is connected to the clamping voltage Vb2. The sources of NMOS transistors M23 through M26 are all grounded.

4. The duty cycle control circuit for a radio frequency power amplifier of claim 1, wherein, The comparator amplifier includes NMOS transistors M31, M32, M37, M38, and M39, PMOS transistors M33, M34, M35, and M36, a current source I2, resistors R31 and R32, and capacitors C31 and C32. The gate of NMOS transistor M31 is connected to ground X, the gate of NMOS transistor M32 is connected to the preset voltage Vref, the drain of NMOS transistor M31 is connected to the drain of NMOS transistor M33 and the source of NMOS transistor M35, the drain of NMOS transistor M32 is connected to the drain of NMOS transistor M34 and the source of NMOS transistor M36, the source of NMOS transistor M31 and the source of NMOS transistor M32 are connected to the input of current source I2, and the output of current source I2 is grounded. The source terminals of NMOS transistors M33 and M34 are both connected to voltage VDD, and the gate terminals of NMOS transistors M33 and M34 are both connected to voltage Vb; the gate terminals of NMOS transistors M35 and M36 are both connected to voltage Vb, and the drain terminals of NMOS transistors M35 and M36 are connected to clamping voltages Vb1 and Vb2, respectively. The first terminal of resistor R31, the first terminal of capacitor C31, and the drain terminal of NMOS transistor M37 are connected to the clamping voltage Vb1. The second terminal of resistor R32, the second terminal of capacitor C32, and the drain terminal of NMOS transistor M38 are connected to the clamping voltage Vb2. The second terminal of resistor R31, the first terminal of resistor R32, the second terminal of capacitor C31, the first terminal of capacitor C32, the gate terminal of NMOS transistor M37, and the gate terminal of NMOS transistor M38 are connected to the drain terminal of NMOS transistor M39. The source terminals of NMOS transistors M37, M38, and M39 are grounded.

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