A high-speed tracking and holding circuit

Abstract

The application discloses a high-speed track-keeping circuit. The high-speed track-keeping circuit comprises an input buffer circuit, a sampling switch circuit, a capacitor element and an output driving circuit. The Darlington structure circuit is used as a core amplifier tube in the input buffer circuit, differential input signals are received through the Darlington structure circuit, impedance matching is performed on the differential input signals, and an input voltage signal is obtained. The output end of the input buffer circuit is connected to the input end of the capacitor element through the sampling switch circuit, so that the input voltage signal is sent to the input end of the capacitor element. The sampling switch circuit is used for controlling the output end of the input buffer circuit and the input end of the capacitor element to be in a conduction state or a disconnected state. The signal collection end of the output driving circuit is connected to the input end of the capacitor element, so as to collect the voltage signal at the input end of the capacitor element as a sampling signal. The technical scheme of the application can significantly enhance the working frequency of the high-speed track-keeping circuit.

Description

Technical Field

[0001] This invention relates to the field of high-frequency circuit technology, and in particular to a high-speed tracking and holding circuit. Background Technology

[0002] With the advent of the 6G era, the demand for ultra-high-speed, ultra-wide bandwidth, and ultra-high frequency circuits in various systems is gradually increasing. The speed and bandwidth of circuits greatly affect the performance of various high-end systems. At the same time, there is a wide demand for high-speed track-and-hold amplifiers (THAs) in fields such as next-generation high-end instruments, electronic countermeasures, and large scientific facilities. These THAs are used to acquire analog signals to obtain sampled signals, thereby improving the performance of analog-to-digital converters.

[0003] In the prior art, the input buffer circuit in the high-speed tracking and holding circuit mainly uses a single-transistor double heterojunction bipolar transistor (DHBT) as the core current switch. However, the current amplification capability and cutoff frequency of the single-transistor DHBT are relatively low, resulting in a low operating frequency of the high-speed tracking and holding circuit using the single-transistor DHBT as the core current switch, which in turn cannot meet the high-speed signal acquisition requirements of the high analog-to-digital conversion circuit. Summary of the Invention

[0004] In view of this, this application provides a high-speed tracking and holding circuit, the main purpose of which is to solve the technical problem of the low operating frequency of current high-speed tracking and holding circuits.

[0005] According to a first aspect of the present invention, a high-speed tracking and holding circuit is provided, the high-speed tracking and holding circuit including an input buffer circuit, a sampling switch circuit, a capacitor element, and an output drive circuit;

[0006] The input buffer circuit uses a Darlington structure circuit as the core amplifier tube, which is used to receive differential input signals through the Darlington structure circuit and perform impedance matching on the differential input signals to obtain input voltage signals.

[0007] The output of the input buffer circuit is connected to the input of the capacitor element via the sampling switch circuit, so as to send the input voltage signal to the input of the capacitor element.

[0008] The sampling switch circuit is used to control whether the output terminal of the input buffer circuit and the input terminal of the capacitor element are in a conducting or disconnected state.

[0009] The signal acquisition terminal of the output drive circuit is connected to the input terminal of the capacitor element to acquire the voltage signal at the input terminal of the capacitor element as a sampling signal.

[0010] The present invention provides a high-speed tracking and holding circuit, which uses a Darlington structure circuit as the core amplifying transistor in the input buffer circuit. The current amplification capability and circuit cutoff frequency of the Darlington structure circuit are twice that of a conventional single-transistor DHBT, which greatly increases the signal frequency that the high-speed tracking and holding circuit can acquire, thereby significantly enhancing the operating frequency of the high-speed tracking and holding circuit.

[0011] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0012] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0013] Figure 1 This figure shows one of the structural schematic diagrams of a high-speed tracking and holding circuit provided in an embodiment of the present invention;

[0014] Figure 2 This is a second schematic diagram of a high-speed tracking and holding circuit provided in an embodiment of the present invention;

[0015] Figure 3 This is shown as a third schematic diagram of a high-speed tracking and holding circuit according to an embodiment of the present invention;

[0016] Figure 4 A schematic diagram of a capacitor circuit provided in an embodiment of the present invention is shown;

[0017] Figure 5 A schematic diagram of an output driving circuit provided in an embodiment of the present invention is shown;

[0018] Figure 6 This diagram illustrates the structure of a common DHBT single tube according to an embodiment of the present invention.

[0019] Figure 7 A schematic diagram of a Darlington structure provided in an embodiment of the present invention is shown;

[0020] Figure 8 A schematic diagram of a Darlington structure with emitter degeneration provided in an embodiment of the present invention is shown;

[0021] Figure 9 This diagram illustrates the cutoff frequency performance of a DHBT single tube and Darlington structure according to an embodiment of the present invention.

[0022] Figure 10 This diagram illustrates the structure of an active inductor provided in an embodiment of the present invention.

[0023] Figure 11 A schematic diagram of the equivalent circuit of an active inductor provided in an embodiment of the present invention is shown;

[0024] Figure 12 This diagram illustrates the frequency response of an active inductor according to an embodiment of the present invention.

[0025] Figure 13 A schematic diagram of a clock buffer circuit provided in an embodiment of the present invention is shown;

[0026] Figure 14 (a) illustrates an embodiment of the present invention. T - A structural diagram of Doubler;

[0027] Figure 14 (b) illustrates an embodiment of the present invention. T -Doubler's small-signal equivalent circuit diagram;

[0028] Figure 15 The diagram shows a layout design schematic of a high-speed track-and-hold circuit according to an embodiment of the present invention;

[0029] Figure 16 This diagram illustrates the simulation results of the differential small-signal SDD21 of a high-speed tracking and holding circuit in tracking state according to an embodiment of the present invention.

[0030] Figure 17 A schematic diagram of transient simulation results for a high-speed tracking and holding circuit provided in an embodiment of the present invention is shown.

[0031] Figure 18 This diagram illustrates a simulation of the total harmonic distortion and spurious-free dynamic range of a high-speed tracking and holding circuit according to an embodiment of the present invention.

[0032] Figure 19 The diagram shows a simulation schematic of the 1dB compression point P1dB and the third-order intermodulation distortion IIP3 of a high-speed tracking and holding circuit provided in an embodiment of the present invention. Detailed Implementation

[0033] The present invention will be described in detail below with reference to the accompanying drawings and embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in the present application can be combined with each other.

[0034] In one embodiment, such as Figure 1 As shown, a high-speed tracking and holding circuit is provided. Taking the application of this high-speed tracking and holding circuit in a high-speed analog-to-digital converter as an example, the high-speed tracking and holding circuit includes an input buffer circuit 100, a sampling switch circuit 200, a capacitor element 300, and an output drive circuit 400.

[0035] Specifically, the input buffer circuit 100 uses a Darlington structure circuit as the core amplifier tube, which is used to receive differential input signals through the Darlington structure circuit, and is responsible for impedance matching with the external input, thereby achieving impedance matching of the differential input signals. At the same time, it converts the differential input signals into low-impedance voltage signals to obtain input voltage signals.

[0036] Furthermore, the output terminal of the input buffer circuit 100 is connected to the input terminal of the capacitor element 300 via the sampling switch circuit 200 to send the input voltage signal to the input terminal of the capacitor element 300. Here, the capacitor element 300 can be a capacitor used to receive the input voltage signal and hold the input voltage signal so as to maintain the voltage value of the input voltage signal when the high-speed tracking and holding circuit enters the holding state.

[0037] Furthermore, the sampling switch circuit 200 is used to control whether the output terminal of the input buffer circuit 100 and the input terminal of the capacitor element 300 are in a conducting or disconnected state. Here, the sampling switch circuit 200 can be connected to a host computer (not shown in the figure) to receive a clock signal from the host computer so as to be controlled to be in a conducting or disconnected state. When the sampling switch circuit 200 is in a conducting state, the output terminal of the input buffer circuit 100 and the input terminal of the capacitor element 300 are in a conducting state. Conversely, when the sampling switch circuit 200 is in a disconnected state, the output terminal of the input buffer circuit 100 and the input terminal of the capacitor element 300 are in a disconnected state.

[0038] Furthermore, the signal acquisition terminal of the output driving circuit 400 is connected to the input terminal of the capacitor element 300 to acquire the voltage signal at the input terminal of the capacitor element 300 as a sampling signal. Furthermore, the output driving circuit 400 can output the sampling signal to external signal acquisition devices such as analog-to-digital converters (not shown in the figure); here, the output driving circuit 400 is mainly responsible for converting the tracked and held voltage signal into a signal output with a 50-ohm output impedance. Its core structure can adopt a Darlington structure to improve the circuit bandwidth of the high-speed track-and-hold circuit.

[0039] The high-speed tracking and holding circuit provided by this invention uses a Darlington structure circuit as the core amplifying transistor in the input buffer circuit. The current amplification capability and circuit cutoff frequency of the Darlington structure circuit are twice that of a conventional single-transistor DHBT, which greatly increases the signal frequency that the high-speed tracking and holding circuit can acquire, thereby significantly enhancing the operating frequency of the high-speed tracking and holding circuit.

[0040] In an optional embodiment, such as Figure 2 As shown, the sampling switch circuit 200 includes a first sampling switch circuit 210 and a second sampling switch circuit 220; the input buffer circuit 100 includes a first Darlington structure circuit 110, a second Darlington structure circuit 120, a power input circuit 130, a first signal input circuit 140, and a second signal input circuit 150; the differential input signal includes a first differential input signal Vin and a second differential input signal Vip; wherein the first differential input signal Vin and the second differential input signal Vip are differential signals to each other; the input voltage signal includes a first input voltage signal and a second input voltage signal; the capacitor element includes a first storage capacitor 310 and a second storage capacitor 320.

[0041] Specifically, the input terminal of the first signal input circuit 140 receives the first differential input signal Vin, and the output terminal of the first signal input circuit 140 is connected to the signal input terminal of the first Darlington structure circuit 110, for receiving the first differential input signal Vin and outputting the first differential input signal Vin to the first Darlington structure circuit 110.

[0042] Furthermore, the output terminal of the first Darlington structure circuit 110 is connected to the first terminal of the first storage capacitor 310 via the first sampling switch circuit 210, for impedance matching of the first differential input signal Vin to obtain the first input voltage signal, and outputting the first input voltage signal to the first storage capacitor 310.

[0043] Furthermore, the input terminal of the second signal input circuit 150 receives the second differential input signal Vip, and the output terminal of the second signal input circuit 150 is connected to the signal input terminal of the second Darlington structure circuit 120 for receiving the second differential input signal Vip and outputting the second differential input signal Vip to the second Darlington structure circuit 120.

[0044] Furthermore, the output terminal of the second Darlington structure circuit 120 is connected to the first terminal of the second storage capacitor 320 via the second sampling switch circuit 220, for receiving the second differential input signal Vip, performing impedance matching on the second differential input signal Vip to obtain the second input voltage signal, and outputting the second input voltage signal to the second storage capacitor 320, wherein the second terminal of the first storage capacitor 310 and the second terminal of the second storage capacitor 320 are respectively grounded.

[0045] Furthermore, the first sampling switch circuit 210 is used to control the output terminal of the first Darlington structure circuit 110 to be in a conducting or disconnected state with the first terminal of the first storage capacitor 310, and the second sampling switch circuit 220 is used to control the output terminal of the second Darlington structure circuit 120 to be in a conducting or disconnected state with the first terminal of the second storage capacitor 320; when the first sampling switch circuit 210 and the second sampling switch circuit 220 are conducting, the high-speed tracking and holding circuit is in a tracking state, and when the first sampling switch circuit 210 and the second sampling switch circuit 220 are disconnected, the high-speed tracking and holding circuit is in a holding state.

[0046] Furthermore, the power input circuit 130 is used to receive a negative voltage and output the negative voltage to each power input terminal of the first Darlington structure circuit 110 and each power input terminal of the second Darlington structure circuit 120; here, the power input circuit 130 can output a -6V voltage to each power input terminal of the first Darlington structure circuit 110 and the second Darlington structure circuit 120.

[0047] Furthermore, the first input terminal and the second input terminal of the output driving circuit 400 are respectively connected to the first terminal of the first storage capacitor 310 and the first terminal of the second storage capacitor 320 to acquire the first voltage signal at the first terminal of the first storage capacitor 310 and the second voltage signal at the first terminal of the second storage capacitor 320, and use the first voltage signal and the second voltage signal as the sampling signal, and can send the sampling signal to a signal acquisition device such as an analog-to-digital converter (not shown in the figure).

[0048] Here, the principle of the first input terminal of the output driving circuit 400 acquiring the first voltage signal is as follows: When the first sampling switch circuit 210 is turned on, the output driving circuit 400 acquires the first input voltage signal from the first terminal of the first storage capacitor 310 as the first voltage signal, and the high-speed tracking and holding circuit is in tracking state; when the first sampling switch circuit 210 is turned off, the first storage capacitor 310 releases electrical energy, so that the voltage value of the first terminal of the first storage capacitor 310 is maintained at the voltage value of the first input voltage signal before the first sampling switch circuit 210 is turned off, thereby enabling the output driving circuit 400 to acquire this voltage value as the first voltage signal, and enabling the high-speed tracking and holding circuit to be in holding state. The principle of the second input terminal of the output driving circuit 400 acquiring the second voltage signal is the same as the principle of the first input terminal of the output driving circuit 400 acquiring the first voltage signal, and will not be described in detail here.

[0049] The technical solution provided in this application offers an improved switched-emitter-follower (SEF) diode switching THA circuit, which can acquire differential input signals at high speed, thereby improving the signal acquisition capability of the high-speed tracking and holding circuit.

[0050] In an optional embodiment, such as Figure 3 As shown, the first Darlington structure circuit includes a first transistor S1, a first resistor R1, a first active inductor L1, a first Darlington structure sub-circuit 111, and a second Darlington structure sub-circuit 112. The first Darlington structure sub-circuit 111 includes a third transistor S3, a fourth transistor S4, a seventh resistor R7, an eighth resistor R8, and a first diode D1; the second Darlington structure sub-circuit 112 includes a fifth transistor S5, a sixth transistor S6, a ninth resistor R9, a tenth resistor R10, and a second diode D2; the first Darlington structure sub-circuit 111 and the second Darlington structure sub-circuit 112 respectively constitute an emitter-degraded Darlington structure circuit; the first active inductor L1 includes an eleventh transistor S11 and a fifteenth resistor R15.

[0051] Furthermore, the second Darlington structure circuit includes a second transistor S2, a second resistor R2, a second active inductor L2, a third Darlington structure sub-circuit, and a fourth Darlington structure sub-circuit; wherein, the third Darlington structure sub-circuit 121 includes a seventh transistor S7, an eighth transistor S8, a thirteenth resistor R13, a fourteenth resistor R14, and a third diode D3; the fourth Darlington structure sub-circuit includes a ninth transistor S9, a thirteenth transistor S10, an eleventh resistor R11, a twelfth resistor R12, and a fourth diode D4; the third and fourth Darlington structure sub-circuits respectively constitute emitter-degraded Darlington structure circuits; the second active inductor L2 includes a twelfth transistor S12 and a sixteenth resistor R16. Here, setting the first active inductor L1 and the second active inductor L2 in the input buffer circuit can improve the bandwidth of the input buffer circuit.

[0052] Furthermore, the first signal input circuit includes a fifteenth resistor R15, a thirteenth transistor S13, and a fifth diode D5; the second signal input circuit includes a fourteenth transistor S14, an eighth diode D8, and a thirty-ninth resistor R39. Specifically, the input terminals of the first Darlington sub-circuit 111 and the second Darlington sub-circuit 112 are respectively connected to the output terminal of the first signal input circuit to receive the first differential input signal Vin. The first terminal of the fifteenth resistor R15, connected to the base of the thirteenth transistor S13, is used to receive the first differential input signal Vin. The second terminal of the fifteenth resistor R15, connected to the collector of the thirteenth transistor S13, is grounded. The emitter of the thirteenth transistor S13 is connected to the base of the fifth transistor S5 via the fifth diode D5. The cathode of the fifth diode D5 is connected to the anode of the sixth diode D6, and the cathode of the sixth diode D6 is connected to the base of the third transistor S3. Thus, the first differential input signal Vin can be output to the first Darlington sub-circuit 111 and the second Darlington sub-circuit 112.

[0053] Furthermore, the output terminal of the first Darlington structure sub-circuit 111 is connected to the emitter terminal of the first transistor S1, and the output terminal of the second Darlington structure sub-circuit 112 is connected to the base terminal of the first transistor S1, wherein the emitter terminal of the first transistor S1 serves as the output terminal of the first Darlington structure circuit. Specifically, the collector terminal of the third transistor S3 is connected to both the anode terminal of the first diode D1 and the emitter terminal of the first transistor S1, the cathode terminal of the first diode D1 is connected to the collector terminal of the fourth transistor S4, the emitter terminal of the third transistor S3 is connected to the first terminal of the seventh resistor R7, and the emitter terminal of the fourth transistor S4 is connected to the first terminal of the eighth resistor R8.

[0054] Furthermore, the collector of the fifth transistor S5 is connected to the anode of the second diode D2 and the base of the first transistor S1, respectively. The cathode of the second diode D2 is connected to the collector of the sixth transistor S6. The emitter of the fifth transistor S5 is connected to the first terminal of the ninth resistor R9, and the emitter of the sixth transistor S6 is connected to the first terminal of the tenth resistor R10. Thus, the first Darlington sub-circuit 111 and the second Darlington sub-circuit 112 can perform impedance matching on the first differential input signal Vin, convert the input signal into a low-impedance first input voltage signal, and send the first input voltage signal to the base of the first transistor S1. Here, the first Darlington sub-circuit 111 is used to eliminate nonlinear signals in the first input voltage signal, and the second Darlington sub-circuit 112 is used to send the first input voltage signal to the first transistor S1.

[0055] Furthermore, the base of the first transistor S1 is connected to the first end of the first resistor R1, the second end of the first resistor R1 is connected to the first end of the first active inductor L1, and the second end of the first active inductor L1 is connected to the collector of the first transistor S1 and grounded. Specifically, the second end of the first resistor R1 is connected to the emitter of the eleventh transistor S11, the base of the eleventh transistor S11 is connected to the first end of the fifteenth resistor R15, and the connection between the collector of the eleventh transistor S11 and the second end of the fifteenth resistor R15 is connected to the collector of the first transistor S1.

[0056] Furthermore, the first power input terminal and the second power input terminal of the first Darlington structure sub-circuit 111 are respectively connected to the power input circuit to receive the negative voltage, and the first power input terminal and the second power input terminal of the second Darlington structure sub-circuit 112 are respectively connected to the power input circuit to receive the negative voltage; specifically, the power input circuit is used to connect a -6V voltage, and the power input circuit includes a seventeenth resistor R17, an eighteenth resistor R18, a seventh diode D7, and a tenth diode D10. Specifically, the second terminals of the seventh resistor R7 and the eighth resistor R8 serve as the first and second power input terminals of the first Darlington structure sub-circuit 111, respectively; the second terminals of the ninth resistor R9 and the tenth resistor R10 serve as the first and second power input terminals of the second Darlington structure sub-circuit 112, respectively; furthermore, the power input circuit is connected to the second terminals of the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, and the tenth resistor R10, respectively, to output negative voltages for the first Darlington structure sub-circuit 111 and the second Darlington structure sub-circuit 112.

[0057] Furthermore, the input terminals of the third Darlington sub-circuit 121 and the fourth Darlington sub-circuit 122 are respectively connected to the output terminals of the second signal input circuit to receive the second differential input signal Vip. Specifically, the connection terminal of the first end of the thirty-ninth resistor R39, after being connected to the base of the fourteenth transistor S14, is used to receive the second differential input signal Vip. The connection terminal of the second end of the thirty-ninth resistor R39, after being connected to the collector of the fourteenth transistor S14, is grounded. The emitter of the fourteenth transistor S14 is connected to the base of the ninth transistor S9 via the eighth diode D8. The cathode of the eighth diode D8 is connected to the anode of the ninth diode D9, and the cathode of the ninth diode D9 is connected to the base of the seventh transistor S7. Thus, the second differential input signal Vip can be output to the third Darlington sub-circuit 121 and the fourth Darlington sub-circuit 122.

[0058] Furthermore, the output terminal of the third Darlington structure sub-circuit 121 is connected to the emitter terminal of the second transistor S2, and the output terminal of the fourth Darlington structure sub-circuit 122 is connected to the base terminal of the second transistor S2, wherein the emitter terminal of the second transistor S2 serves as the output terminal of the second Darlington structure circuit.

[0059] Specifically, the collector of the seventh transistor S7 is connected to the anode of the third diode D3 and the emitter of the second transistor S2, the cathode of the third diode D3 is connected to the collector of the eighth transistor S8, the emitter of the seventh transistor S7 is connected to the first end of the fourteenth resistor R14, and the emitter of the eighth transistor S8 is connected to the first end of the thirteenth resistor R13.

[0060] Furthermore, the collector of the ninth transistor S9 is connected to the anode of the fourth diode D4 and the base of the second transistor S2, respectively. The cathode of the fourth diode D4 is connected to the collector of the thirteenth transistor S10. The emitter of the ninth transistor S9 is connected to the first terminal of the twelfth resistor R12, and the emitter of the thirteenth transistor S10 is connected to the first terminal of the eleventh resistor R11. Thus, the third Darlington sub-circuit 121 and the fourth Darlington sub-circuit 122 can perform impedance matching on the second differential input signal Vip, convert the input signal into a low-impedance second input voltage signal, and send the second input voltage signal to the base of the second transistor S2. Here, the third Darlington sub-circuit 121 is used to eliminate nonlinear signals in the second input voltage signal, and the fourth Darlington sub-circuit 122 is used to send the second input voltage signal to the second transistor S2.

[0061] Furthermore, the base of the second transistor S2 is connected to the first end of the second resistor R2, the second end of the second resistor R2 is connected to the first end of the second active inductor L2, and the second end of the second active inductor L2 is connected to the collector of the second transistor S2 and grounded. Specifically, the second end of the second resistor R2 is connected to the emitter of the twelfth transistor S12, the base of the twelfth transistor S12 is connected to the first end of the sixteenth resistor R16, and the connection point between the collector of the twelfth transistor S12 and the second end of the sixteenth resistor R16 is connected to the collector of the second transistor S2.

[0062] Furthermore, the first and second power input terminals of the third Darlington structure sub-circuit 121 are respectively connected to the power input circuit to receive the negative voltage, and the first and second power input terminals of the fourth Darlington structure sub-circuit 122 are respectively connected to the power input circuit to receive the negative voltage. Specifically, the second terminals of the thirteenth resistor R13 and the fourteenth resistor R14 serve as the first and second power input terminals of the third Darlington structure sub-circuit 121, respectively; and the second terminals of the eleventh resistor R11 and the twelfth resistor R12 serve as the first and second power input terminals of the fourth Darlington structure sub-circuit 122, respectively. Specifically, the power input circuit is used to connect a -6V voltage, and is connected to the second terminals of the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13, and the fourteenth resistor R14, respectively, to output negative voltages to the third and fourth Darlington structure sub-circuit 121 and the fourth Darlington structure sub-circuit 122.

[0063] Furthermore, the emitter of the third transistor S3 is connected to the emitter of the seventh transistor S7 via the third resistor R3; the emitter of the fourth transistor S4 is connected to the emitter of the eighth transistor S8 via the fourth resistor R4; the emitter of the fifth transistor S5 is connected to the emitter of the ninth transistor S9 via the fifth resistor R5; and the emitter of the sixth transistor S6 is connected to the emitter of the thirteenth transistor S10 via the sixth resistor R6.

[0064] The embodiments provided in this application can receive a first differential input signal based on a first Darlington structure sub-circuit and a second Darlington structure sub-circuit, perform impedance matching on the first differential input signal, and simultaneously perform nonlinear signal cancellation processing, thereby outputting a low-impedance first input voltage signal to the first terminal of the first storage capacitor via a first sampling switch circuit. Simultaneously, based on a third Darlington structure sub-circuit and a fourth Darlington structure sub-circuit, a second differential input signal can be received, perform impedance matching on the second differential input signal, and simultaneously perform nonlinear signal cancellation processing, thereby outputting a low-impedance second input voltage signal to the first terminal of the second storage capacitor via a second sampling switch circuit. This allows for an increase in the operating frequency of the input buffer circuit based on the Darlington structure circuit. Furthermore, the operating bandwidth of the input buffer circuit can be increased through the first and second active inductors, thereby improving the high-speed signal acquisition capability of the high-speed tracking and holding circuit.

[0065] In an optional embodiment, the as... Figure 2 As shown, the high-speed tracking and holding circuit also includes a clock buffer circuit 500.

[0066] Specifically, the first input terminal and the second input terminal of the clock buffer circuit 500 are used to receive the positive phase clock signal and the negative phase clock signal, respectively, and to amplify the positive phase clock signal and the negative phase clock signal to obtain the tracking signal T and the holding signal H.

[0067] Furthermore, the tracking signal input terminals of the first sampling switch circuit 210 and the second sampling switch circuit 220 are used to receive the tracking signal T, and the hold signal input terminals of the first sampling switch circuit 210 and the second sampling switch circuit 220 are used to receive the hold signal H. Here, when the signal level of the tracking signal T received by the first sampling switch circuit 210 and the second sampling switch circuit 220 is higher than the signal level of the hold signal H, the first sampling switch circuit 210 and the second sampling switch circuit 220 are in the on state; conversely, when the signal level of the tracking signal T received by the first sampling switch circuit 210 and the second sampling switch circuit 220 is lower than the signal level of the hold signal H, the first sampling switch circuit 210 and the second sampling switch circuit 220 are in the off state.

[0068] Furthermore, such as Figure 3As shown, the first sampling switch circuit includes a first switching diode Ds1 and a first Darlington structure control circuit. The cathode of the first switching diode Ds1 is connected to the first terminal of the first storage capacitor CH1, and the anode of the first switching diode Ds1 is connected to the output terminal of the first Darlington structure circuit, i.e., the anode of the first switching diode Ds1 is connected to the emitter terminal of the first transistor S1.

[0069] Furthermore, the first current terminal of the first Darlington structure control circuit is connected to the first terminal of the first storage capacitor CH1, and the second current terminal of the first Darlington structure control circuit is connected to the base terminal of the first transistor S1; here, the first Darlington structure control circuit includes the fifteenth transistor S15, the sixteenth transistor S16, the seventeenth transistor S17, the eighteenth transistor S18, the nineteenth transistor S19, the twenty-third transistor S20, the twenty-first transistor S21, the twenty-second transistor S22, the eleventh diode D11, the twelfth diode D12, and the tenth... Diodes D13, D14, D15, D16, D17, D18, D19, D20, D21, D22, R19, R20, R21, R22, R22, R23, R24, R25, R26, R27, and R28 are used. The collector terminal of the sixteenth transistor S16 serves as the first current terminal of the first Darlington structure control circuit, and the anode terminal of the eleventh diode D11 serves as the second current terminal of the first Darlington structure control circuit.

[0070] Furthermore, the tracking signal input terminal of the first Darlington structure control circuit is used to receive the tracking signal T, and the hold signal input terminal of the first Darlington structure control circuit is used to receive the hold signal H. The first Darlington structure control circuit is used to draw current from the first terminal of the first storage capacitor CH1 when the tracking signal T is greater than the hold signal H, so as to control the first switching diode Ds1 to turn on; conversely, the first Darlington structure control circuit is also used to draw current from the base terminal of the first transistor S1 when the tracking signal T is less than the hold signal H, so as to control the first switching diode Ds1 to turn off.

[0071] Specifically, the connection between the first terminal of the twenty-third resistor R23 and the base terminal of the twenty-third transistor S20 serves as the tracking signal input terminal of the first Darlington structure control circuit. The second terminal of the twenty-third resistor R23 is connected to the emitter terminal of the nineteenth transistor S19. The base terminal of the nineteenth transistor S19 is connected to the first terminal of the twenty-fourth resistor R24. The connection between the second terminal of the twenty-fourth resistor R24 ​​and the collector terminal of the nineteenth transistor S19 is grounded. The twenty-fourth resistor R24 ​​and the nineteenth transistor S19 together constitute an active inductor.

[0072] Furthermore, the collector of the 23rd transistor S20 is connected to the cathode of the 15th diode D15, and the connection between the anode of the 15th diode D15 and the anode of the 18th diode D18 is grounded. Furthermore, the emitter of the 23rd transistor S20 is connected to the base of the 15th transistor S15 via the 16th diode D16 and the 17th diode D17. Furthermore, the emitter of the 15th transistor S15 is connected to the first terminal of the 19th resistor R19 via the 12th diode D12, and the base of the 15th transistor S15 is also connected to the first terminal of the 27th resistor R27; the emitter of the 15th transistor S15 is also connected to the base of the 16th transistor S16, and the emitter of the 16th transistor S16 is connected to the first terminal of the 20th resistor R20. Furthermore, the second terminals of the 19th resistor R19, the 20th resistor R20, and the 27th resistor R27 are used to connect to a -6V voltage.

[0073] Furthermore, the connection terminal of the 25th resistor R25, after being connected to the base terminal of the 22nd transistor S22, serves as the hold signal input terminal of the first Darlington structure control circuit. The second terminal of the 25th resistor R25 is connected to the emitter terminal of the 21st transistor S21, and the base terminal of the 21st transistor S21 is connected to the first terminal of the 26th resistor R26. The connection terminal of the 26th resistor R26 and the collector terminal of the 21st transistor S21 is grounded. The 26th resistor R24 ​​and the 21st transistor S21 together constitute an active inductor.

[0074] Furthermore, the collector terminal of the 22nd transistor S22 is connected to the cathode terminal of the 21st diode D21, and the anode terminal of the 21st diode D21 is grounded; furthermore, the emitter terminal of the 22nd transistor S22 is connected to the base terminal of the 17th transistor S17 via the 22nd diode D22 and the 14th diode D14.

[0075] Furthermore, the emitter of the seventeenth transistor S17 is connected to the first terminal of the twenty-second resistor R22 via the thirteenth diode D13, and the base of the seventeenth transistor S17 is also connected to the first terminal of the twenty-eighth resistor R28; the emitter of the seventeenth transistor S17 is also connected to the base of the eighteenth transistor D18, and the emitter of the eighteenth transistor S18 is connected to the first terminal of the twenty-first resistor R21; furthermore, the second terminals of the twenty-first resistor R21, the twenty-second resistor R22, and the twenty-eighth resistor R28 are used to connect a -6V voltage.

[0076] Furthermore, the emitter terminal of the fifteenth transistor S15 is also connected to the emitter terminal of the seventeenth transistor S17, and the emitter terminal of the sixteenth transistor S16 is also connected to the emitter terminal of the eighteenth transistor S18. Here, the fifteenth transistor S15, the sixteenth transistor S16, the seventeenth transistor S17, and the eighteenth transistor S18 constitute the Darlington structure of the first sampling switch circuit to improve the switching speed of the first sampling switch circuit.

[0077] Furthermore, the second sampling switch circuit includes a second switching diode Ds2 and a second Darlington structure control circuit; wherein, the cathode of the second switching diode Ds2 is connected to the first terminal of the second storage capacitor CH2, and the anode of the second switching diode Ds2 is connected to the output terminal of the second Darlington structure circuit, that is, the anode of the second switching diode Ds2 is connected to the emitter terminal of the second transistor S2.

[0078] Furthermore, the first current terminal of the second Darlington structure control circuit is connected to the first terminal of the second storage capacitor CH2, and the second current terminal of the second Darlington structure control circuit is connected to the base terminal of the second transistor S2; here, the second Darlington structure control circuit includes transistors S23 (23rd), S24 (24th), S25 (25th), S26 (26th), S27 (27th), S28 (28th), S29 (29th), S30 (33rd), diode D23 (23rd), diode D24 (24th), and diode D25 (25th). Diodes D25, D26 (26th), D27 (27th), D28 (28th), D29 (29th), D20 (30th), D31 (31st), D32 (32nd), D33 (33rd), D34 (34th), D35 (35th), R29 (29th), R30 (30th), R31 (31st), R32 (31st), R33 (31st), R34 (31st), R35 (31st), R36 (31st), R37 (31st), and R38 (31st). The connection method for these components is as follows: Figure 3 As shown; wherein, the anode of the twenty-eighth diode D28 serves as the first current terminal of the second Darlington structure control circuit, and the anode of the twenty-seventh diode D27 serves as the second current terminal of the second Darlington structure control circuit.

[0079] Furthermore, the tracking signal input terminal of the second Darlington structure control circuit is used to receive the tracking signal T, and the hold signal input terminal of the second Darlington structure control circuit is used to receive the hold signal H. When the tracking signal T is greater than the hold signal H, the second Darlington structure control circuit draws current from the first terminal of the second storage capacitor CH2 to control the second switching diode Ds2 to conduct. The second Darlington structure control circuit is also used to draw current from the base terminal of the second transistor S2 when the tracking signal T is less than the hold signal H to control the second switching diode Ds2 to disconnect. Here, the connection terminal between the first terminal of the thirtieth resistor R30 and the base terminal of the twenty-fourth transistor S24 serves as the hold signal input terminal of the second Darlington structure control circuit, and the connection terminal between the first terminal of the thirty-seventh resistor R37 and the base terminal of the twenty-ninth transistor S29 serves as the tracking signal input terminal of the second Darlington structure control circuit.

[0080] In addition, such as Figure 3As shown, the second sampling switch circuit is composed of transistors S25 (25th), S26 (26th), S27 (27th), and S28 (28th) to improve the switching speed of the second sampling switch circuit; the active inductor of the second Darlington structure control circuit is composed of resistor R29 (29th) and transistor S23 (23rd); and the other active inductor of the second Darlington structure control circuit is composed of resistor R38 (38th) and transistor S30 (33rd).

[0081] Furthermore, the principle of the high-speed tracking and holding circuit in tracking and holding the input voltage is as follows: For the first sampling switch circuit, the first sampling switch circuit draws current from the base terminal of the first transistor S1, causing the voltage at the base terminal of the first transistor S1 to decrease, thereby reducing the voltage at the emitter terminal of the first transistor S1. At this time, the difference between the voltage at the emitter terminal of the first transistor S1 and the voltage at the cathode terminal of the first switching diode Ds1 is less than the forward voltage Vbe of the first switching diode Ds1, so the first switching diode Ds1 is turned off, and the high-speed tracking and holding circuit is in the holding state. Conversely, when the first sampling switch circuit draws current from the emitter terminal of the first transistor S1 to the cathode terminal of the first switching diode Ds1, the first switching diode Ds1 is turned on, and the high-speed tracking and holding circuit is in the tracking state.

[0082] Furthermore, regarding the second sampling switch circuit, the second sampling switch circuit draws current from the base terminal of the second transistor S2, causing the voltage at the base terminal of the second transistor S2 to decrease, thereby reducing the emitter voltage of the second transistor S2. At this time, the difference between the emitter voltage of the second transistor S2 and the cathode voltage of the second switching diode Ds2 is less than the forward voltage Vbe of the second switching diode Ds2, so the second switching diode Ds2 is turned off, and the high-speed tracking and holding circuit is in the holding state. Conversely, when the second sampling switch circuit draws current from the emitter terminal of the second transistor S2 to the cathode terminal of the second switching diode Ds2, the second switching diode Ds2 is turned on, and the high-speed tracking and holding circuit is in the tracking state.

[0083] Furthermore, the first sampling switch circuit also includes a first capacitor C1, with its first terminal connected to the first terminal of the first storage capacitor CH1, and its second terminal connected to the emitter terminal of the second transistor S2. Furthermore, the second sampling switch circuit also includes a second capacitor C2, with its first terminal connected to the first terminal of the second storage capacitor CH2, and its second terminal connected to the emitter terminal of the first transistor S1. Here, the first capacitor C1 and the second capacitor C2 can serve as undercurrent capacitors in the high-speed track-and-hold circuit, used to offset the capacitance when the first switching diode Ds1 and the second switching diode Ds2 are disconnected. Furthermore, Figure 3 Each diode shown can be composed of a transistor, with the emitter of the transistor serving as the cathode of the diode, and the junction of the collector and base of the transistor serving as the cathode of the diode.

[0084] Furthermore, the first capacitor C1 and the second capacitor C2 can be in the form of a capacitor circuit, such as... Figure 4 As shown, the capacitor circuit includes a first circuit transistor S001, a second circuit transistor S002, a third circuit transistor S003, and a fourth circuit transistor S004. The connection point formed by connecting the base and collector terminals of the first circuit transistor S001, the base and collector terminals of the second circuit transistor S002, serves as the first terminal of either the first capacitor C1 or the second capacitor C2. The connection point formed by connecting the base and collector terminals of the third circuit transistor S003, the base and collector terminals of the fourth circuit transistor S004, serves as the second terminal of both the first capacitor C1 and the second capacitor C2.

[0085] Furthermore, such as Figure 5 As shown, the output driving circuit includes a first output transistor S01, a second output transistor S02, a third output transistor S03, a fourth output transistor S04, a fifth output transistor S05, a sixth output transistor S06, a seventh output transistor S07, an eighth output transistor S08, a first output resistor R01, a second output resistor R02, a third output resistor R03, a fourth output resistor R04, a fifth output resistor R05, a sixth output resistor R06, a seventh output resistor R06, an eighth output resistor R07, a first wire La, a second wire Lb, a third wire Lc, and a fourth wire Ld; wherein, the first wire La, the second wire Lb, the third wire Lc, and the fourth wire Ld are used to achieve impedance matching of the output driving circuit.

[0086] Specifically, the base of the first output transistor S01 is connected to the first end of the first storage capacitor CH1, the emitter of the first output transistor S01 is connected to the base of the second output transistor S02 and the first end of the first output resistor R01, the emitter of the second output transistor S02 is connected to the first end of the second output resistor R02, and the collector of the first output transistor S01 is connected to the first end of the first wire La.

[0087] Furthermore, the second end of the first wire La is connected to the base terminal of the fifth output transistor S05 and the emitter terminal of the sixth output transistor S06, respectively. The connection terminal after the fifth output transistor S05 and the sixth output transistor S06 are connected is connected to the first end of the seventh output resistor R07. The second end of the seventh output resistor R07 is grounded. The emitter terminal of the fifth output transistor S05 is connected to the first end of the second wire Lb. The second end of the second wire Lb is connected to the collector terminal of the second output transistor S02. The first end of the seventh output resistor R07 extends to a first signal output port for outputting the first voltage signal Von.

[0088] Furthermore, the base terminal of the third output transistor S03 is connected to the first terminal of the second storage capacitor CH2, the emitter terminal of the third output transistor S03 is connected to the base terminal of the fourth output transistor S04 and the first terminal of the third output resistor R03, the emitter terminal of the fourth output transistor S04 is connected to the first terminal of the fourth output resistor R04, and the collector terminal of the third output transistor S03 is connected to the first terminal of the third wire Lc.

[0089] Furthermore, the second end of the third wire Lc is connected to the base of the seventh output transistor S07 and the emitter of the eighth output transistor S08, respectively. The connection end of the seventh output transistor S07 and the collector of the eighth output transistor S08 is connected to the first end of the eighth output resistor R08. The second end of the eighth output resistor R08 is grounded. The emitter of the seventh output transistor S07 is connected to the first end of the fourth wire Ld. The second end of the fourth wire Ld is connected to the collector of the fourth output transistor S04. The first end of the eighth output resistor R08 extends to a second signal output port for outputting the second voltage signal Vop.

[0090] Furthermore, the base terminals of the sixth output transistor S06 and the eighth output transistor S08 are connected to an external voltage source VCom to receive the supply voltage. The emitter terminal of the first output transistor S01 is also connected to the emitter terminal of the third output transistor S03 through the fifth output resistor R05, and the emitter terminal of the second output transistor S02 is also connected to the emitter terminal of the fourth output transistor S04 through the sixth output resistor R06.

[0091] Furthermore, the connection terminal formed by linking the second ends of the first output resistor R01, the second output resistor R02, the third output resistor R03, and the fourth output resistor R04 is used to receive negative voltage. Here, the first output transistor S01, the second output transistor S02, the first output resistor R01, and the second output resistor R02 constitute one emitter-degraded Darlington structure of the output drive circuit, and the third output transistor S03, the fourth output transistor S04, the third output resistor R03, and the fourth output resistor R04 constitute another emitter-degraded Darlington structure of the output drive circuit, thereby improving the signal bandwidth that the output drive circuit can process.

[0092] The technical solution provided in this application incorporates a Darlington structure in the input buffer circuit, the first sampling switch circuit, the second sampling switch circuit, and the output drive circuit. Figures 6 to 8 This illustrates the difference between the Darlington structure used in high-speed track-and-hold circuits and ordinary DHBT single transistors. Figure 6 It is a standard DHBT single tube 10. Figure 7 This is a Darlington structure, consisting of two transistors (20). The current amplification capability β of this structure is twice that of a typical single transistor, according to f... T Given β, the cutoff frequency f of the Darlington structure is... T It is approximately twice that of a typical DHBT single tube. Figure 8 The Darlington structure with emitter degradation is presented. The emitter terminal of transistor 20 is connected to resistor 30. The Darlington structure with emitter degradation can introduce negative feedback during common-emitter amplification, thereby improving the linearity of the circuit.

[0093] Furthermore, the performance comparison between a single DHBT tube and a Darlington structure is as follows: Figure 9 As shown, the cutoff frequency of a single-tube DHBT is 175 GHz, while that of a Darlington transistor is 246 GHz. The Darlington structure can significantly improve the cutoff frequency of the device, and the simulation results are consistent with the theoretical results. Furthermore, Figure 8 The emitter-degenerate Darlington structure in the common-emitter amplifier introduces negative feedback, improving the linearity of the circuit. The core transistors in the sample-and-hold amplifier circuit, input buffer circuit, and output driver circuit all utilize the emitter-degenerate Darlington structure to improve the small-signal bandwidth of the circuit; furthermore, the sampling switch circuit also uses the Darlington structure to improve the switching speed of the sampling switch circuit.

[0094] Furthermore, the technical solution of this application uses active inductors in the input buffer circuit, the first sampling switch circuit, the second sampling switch circuit, and the output drive circuit. Furthermore, Figures 10 to 12 This demonstrates the active inductor used in a high-speed track-and-hold circuit and its equivalent analysis, in which Figure 10This is the circuit structure of an active inductor, mainly composed of a DHBT transistor (10) and a resistor (30). Furthermore, the equivalent circuit of an active inductor is as follows: Figure 11 As shown, the active inductor can be viewed as a first equivalent circuit resistor 31 connected in parallel with an inductor L0, and then connected in series with a second equivalent circuit resistor 32. Small-signal analysis of this active inductor yields its impedance. Among them, R e1 R is the resistance value of resistor 31 in the first equivalent circuit. e2 32 is the resistance value of the second equivalent circuit resistor, and L is the inductance of inductor L0.

[0095] Furthermore, the circuit frequency response of an active inductor is as follows: Figure 12 As shown, the area between the zero w1 and the pole p1 can be considered as having an inductive characteristic. This structure is used in an input buffer circuit to amplify the load resistance of the circuit. It forms a zero at the load location, pushing the dominant pole of the system outward, thereby expanding the bandwidth of the input buffer circuit.

[0096] Furthermore, such as Figure 13 As shown, the clock buffer circuit includes a ninth output resistor R09, a tenth output resistor R010, an eleventh output resistor R011, a twelfth output resistor R012, a thirteenth output resistor R013, a fourteenth output resistor R014, a first output diode D01, a second output diode D02, a ninth output transistor S09, a tenth output transistor S010, an eleventh output transistor S011, a twelfth output transistor S012, a thirteenth output transistor S013, and a fourteenth output transistor S014.

[0097] Specifically, the connection between the first terminal of the ninth output resistor R09 and the base terminal of the ninth output transistor S09 serves as the first input terminal of the clock buffer circuit, used to receive the positive phase clock signal CLKN. The connection between the second terminal of the ninth output resistor R09 and the collector terminal of the ninth output transistor S09 is grounded. The emitter terminal of the ninth output transistor S09 is connected to the anode terminal of the first output diode D01. The cathode terminal of the first output diode D01 is connected to the first terminal of the eleventh output resistor R011 and the base terminal of the eleventh output transistor S011.

[0098] Furthermore, the connection terminal of the tenth output resistor R10 and the base terminal of the tenth output transistor S010 serves as the second input terminal of the clock buffer circuit, used to receive the negative phase clock signal CLKP. The connection terminal of the tenth output resistor R010 and the collector terminal of the tenth output transistor S010 is grounded. The emitter terminal of the tenth output transistor S010 is connected to the anode terminal of the second output diode D02. The cathode terminal of the second output diode D02 is connected to the first terminal of the twelfth output resistor R012 and the base terminal of the fourteenth output transistor S014, respectively.

[0099] Furthermore, the connection terminal of the eleventh output transistor S011 connected to the emitter terminal of the twelfth output transistor S012 is connected to the first terminal of the thirteenth output resistor R013. The connection terminal of the twelfth output transistor S012 connected to the base terminal of the thirteenth output transistor S013 is used to receive the external power supply voltage Vb. The connection terminal of the thirteenth output transistor S013 connected to the emitter terminal of the fourteenth output transistor S014 is connected to the first terminal of the fourteenth output resistor R014.

[0100] Furthermore, the connection terminal of the eleventh output resistor R011, the twelfth output resistor R012, the thirteenth output resistor R013, and the fourteenth output resistor R014 is connected to a negative voltage.

[0101] Furthermore, the connection terminal of the collector of the eleventh output transistor S011 and the collector of the thirteenth output transistor S013 is used to output the tracking signal T, and the connection terminal of the collector of the twelfth output transistor S012 and the collector of the fourteenth output transistor S014 is used to output the holding signal H.

[0102] Here, the clock buffer circuit amplifies the externally input clock and transmits it to the first sampling switch circuit and the second sampling switch circuit. Its eleventh output transistor S011, thirteenth output transistor S013, twelfth output transistor S012, and fourteenth output transistor S014 constitute the clock f. T -doubler structure to improve clock operating frequency and conversion rate.

[0103] Furthermore, Figure 14 The circuit shown is the clock f. T -doubler structure, Figure 14 (a) is the clock f TThe -doubler circuit consists of two differential amplifiers, and its small-signal equivalent circuit diagram is shown in 14(b). Their common input terminal can be considered as a differential ground, and their input equivalent capacitance can be reduced to half of the original. This structure is used in the amplification section of a clock buffer circuit to improve the operating frequency and slew rate of the clock buffer circuit.

[0104] The high-speed track-and-hold circuit provided in this application employs a Darlington structure, an active inductor, and a clock signal f. T The -doubler structure enables the high-speed track-and-hold circuit to have an extremely wide sampling bandwidth and an extremely high clock sampling rate. This greatly improves the utilization of the device's cutoff frequency, thereby significantly increasing the operating frequency and analog bandwidth of the high-speed track-and-hold circuit.

[0105] Figure 15 This presentation showcases the layout design of an improved SEF diode switch high-speed track-and-hold circuit. The track-and-hold input signal is differentially input from the left, the output signal is differentially output from the bottom, the power signal is supplied from the top, and the clock signal is differentially input from the right. All long traces are matched using coplanar waveguide with ground (CPWG) transmission lines to ensure flat signal transmission and improve in-band flatness.

[0106] Figure 16 This presentation showcases simulation results of the improved SEF diode switch high-speed track-and-hold circuit layout in tracking mode using the differential small-signal SDD21. It can be seen that the -3dB bandwidth of the differential small-signal SDD21 in tracking mode is 67.4GHz. This is significant because the cutoff frequency f of a single transistor in this process is... T At 175 GHz, its effect on device f T Utilization rate BW / f T The efficiency is 39.6%, which is significantly higher than that of similar high-speed track-and-hold circuits currently known.

[0107] Figure 17 This presentation shows the transient simulation results of a high-speed track-and-hold circuit layout with an improved SEF diode switch, sampling an 8.7GHz differential input signal at a 50GHz clock input. It is evident that it exhibits a significant tracking and holding effect on the sampled voltage Vout, and the sampling rate has a significant impact on the device's cutoff frequency f. T Utilization rate Sample / f T The efficiency is 29.4%, which is significantly higher than that of similar high-speed track-and-hold circuits currently known.

[0108] Figure 18The simulations show the total harmonic distortion (THD) and spurious-free dynamic range (SFDR) of the high-speed track-and-hold circuit layout of the improved SEF diode switch. The THD of the high-speed track-and-hold circuit is -37 at the worst within 15 GHz, and the SFDR is 38 at the worst within 15 GHz, which is a good harmonic distortion.

[0109] Figure 19 The simulations show the 1dB compression point P1dB and third-order intermodulation distortion IIP3 of the high-speed track-and-hold circuit layout of the improved SEF diode switch. The lowest P1dB is -1.4dBm, and the worst IIP3 is 4.9dBm within 16GHz, showing good linearity.

[0110] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0111] The serial numbers in this application are for descriptive purposes only and do not represent the superiority or inferiority of any particular implementation scenario. The above disclosures are merely a few specific implementation scenarios of this application; however, this application is not limited thereto, and any variations conceived by those skilled in the art should fall within the protection scope of this application.

Claims

1. A high-speed track-and-hold circuit, characterized by comprising: The high-speed tracking and holding circuit includes an input buffer circuit, a sampling switch circuit, a capacitor element, and an output drive circuit. The input buffer circuit uses a Darlington structure circuit as the core amplifier tube, which is used to receive differential input signals through the Darlington structure circuit and perform impedance matching on the differential input signals to obtain input voltage signals. The output of the input buffer circuit is connected to the input of the capacitor element via the sampling switch circuit, so as to send the input voltage signal to the input of the capacitor element. The sampling switch circuit is used to control whether the output terminal of the input buffer circuit and the input terminal of the capacitor element are in a conducting or disconnected state. The signal acquisition terminal of the output drive circuit is connected to the input terminal of the capacitor element to acquire the voltage signal at the input terminal of the capacitor element as a sampling signal.

2. The high-speed track-and-hold circuit of claim 1, wherein The sampling switch circuit includes a first sampling switch circuit and a second sampling switch circuit; the input buffer circuit includes a Darlington structure circuit, a power input circuit, a first signal input circuit, and a second signal input circuit; the Darlington structure circuit includes a first Darlington structure circuit and a second Darlington structure circuit; the differential input signal includes a first differential input signal and a second differential input signal; the input voltage signal includes a first input voltage signal and a second input voltage signal; the capacitor element includes a first storage capacitor and a second storage capacitor. The output terminal of the first signal input circuit is connected to the signal input terminal of the first Darlington structure circuit, and is used to receive the first differential input signal and output the first differential input signal to the first Darlington structure circuit. The output terminal of the first Darlington structure circuit is connected to the first terminal of the first storage capacitor via the first sampling switch circuit, which is used to perform impedance matching on the first differential input signal to obtain the first input voltage signal, and output the first input voltage signal to the first storage capacitor. The output terminal of the second signal input circuit is connected to the signal input terminal of the second Darlington structure circuit, and is used to receive the second differential input signal and output the second differential input signal to the second Darlington structure circuit. The output terminal of the second Darlington structure circuit is connected to the first terminal of the second storage capacitor via the second sampling switch circuit. It is used to receive the second differential input signal, perform impedance matching on the second differential input signal to obtain the second input voltage signal, and output the second input voltage signal to the second storage capacitor. The second terminal of the first storage capacitor and the second terminal of the second storage capacitor are respectively grounded. The first sampling switch circuit is used to control the output terminal of the first Darlington structure circuit and the first terminal of the first storage capacitor to be in a conducting or disconnected state, and the second sampling switch circuit is used to control the output terminal of the second Darlington structure circuit and the first terminal of the second storage capacitor to be in a conducting or disconnected state. The power input circuit is used to receive negative voltage and output the negative voltage to each power input terminal of the first Darlington structure circuit and each power input terminal of the second Darlington structure circuit. The first input terminal and the second input terminal of the output driving circuit are respectively connected to the first terminal of the first storage capacitor and the first terminal of the second storage capacitor to collect a first voltage signal at the first terminal of the first storage capacitor and a second voltage signal at the first terminal of the second storage capacitor, and the first voltage signal and the second voltage signal are used as the sampling signal.

3. The high-speed track-and-hold circuit of claim 2, wherein The first Darlington structure circuit includes a first transistor, a first resistor, a first active inductor, a first Darlington structure sub-circuit, and a second Darlington structure sub-circuit; The input terminals of the first Darlington structure sub-circuit and the second Darlington structure sub-circuit are respectively connected to the output terminal of the first signal input circuit to receive the first differential input signal. The output terminal of the first Darlington structure sub-circuit is connected to the emitter terminal of the first transistor, and the output terminal of the second Darlington structure sub-circuit is connected to the base terminal of the first transistor, wherein the emitter terminal of the first transistor serves as the output terminal of the first Darlington structure circuit. The base of the first transistor is connected to the first end of the first resistor, the second end of the first resistor is connected to the first end of the first active inductor, and the second end of the first active inductor is connected to the collector of the first transistor and grounded. The first power input terminal and the second power input terminal of the first Darlington structure sub-circuit are respectively connected to the power input circuit to receive the negative voltage; the first power input terminal and the second power input terminal of the second Darlington structure sub-circuit are respectively connected to the power input circuit to receive the negative voltage. The second Darlington structure circuit includes a second transistor, a second resistor, a second active inductor, a third Darlington structure sub-circuit, and a fourth Darlington structure sub-circuit; The input terminals of the third Darlington structure sub-circuit and the fourth Darlington structure sub-circuit are respectively connected to the output terminal of the second signal input circuit to receive the second differential input signal. The output terminal of the third Darlington structure sub-circuit is connected to the emitter terminal of the second transistor, and the output terminal of the fourth Darlington structure sub-circuit is connected to the base terminal of the second transistor, wherein the emitter terminal of the second transistor serves as the output terminal of the second Darlington structure circuit. The base of the second transistor is connected to the first end of the second resistor, the second end of the second resistor is connected to the first end of the second active inductor, and the second end of the second active inductor is connected to the collector of the second transistor and grounded. The first and second power input terminals of the third Darlington structure sub-circuit are respectively connected to the power input circuit to receive the negative voltage, and the first and second power input terminals of the fourth Darlington structure sub-circuit are respectively connected to the power input circuit to receive the negative voltage.

4. The high-speed track-and-hold circuit of claim 3, wherein The input buffer circuit further includes a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor; the first Darlington structure sub-circuit includes a third transistor, a fourth transistor, a first diode, a seventh resistor, and an eighth resistor; the second Darlington structure sub-circuit includes a fifth transistor, a sixth transistor, a second diode, a ninth resistor, and a tenth resistor; the third Darlington structure sub-circuit includes a seventh transistor, an eighth transistor, a third diode, a thirteenth resistor, and a fourteenth resistor; the fourth Darlington structure sub-circuit includes a ninth transistor, a thirteenth transistor, a fourth diode, an eleventh resistor, and a twelfth resistor; The base of the third transistor is connected to the output of the first signal input circuit, and the emitter of the third transistor is connected to the power input circuit via the seventh resistor to receive the negative voltage. The collector of the third transistor is connected to the anode of the first diode and the emitter of the first transistor. The cathode of the first diode is connected to the collector of the fourth transistor, and the emitter of the fourth transistor is connected to the power input circuit via the eighth resistor to receive the negative voltage. The base of the fifth transistor is connected to the output of the first signal input circuit, and the emitter of the fifth transistor is connected to the power input circuit via the ninth resistor to receive the negative voltage. The collector of the fifth transistor is connected to the anode of the second diode and the base of the first transistor. The cathode of the second diode is connected to the collector of the sixth transistor, and the emitter of the sixth transistor is connected to the power input circuit via the tenth resistor to receive the negative voltage. The base of the seventh transistor is connected to the output of the second signal input circuit. The emitter of the seventh transistor is connected to the power input circuit via the fourteenth resistor to receive the negative voltage. The collector of the seventh transistor is connected to the anode of the third diode and the emitter of the second transistor. The cathode of the third diode is connected to the collector of the eighth transistor. The emitter of the eighth transistor is connected to the power input circuit via the thirteenth resistor to receive the negative voltage. The base of the ninth transistor is connected to the output of the second signal input circuit, and the emitter of the ninth transistor is connected to the power input circuit via the twelfth resistor to receive the negative voltage. The collector of the ninth transistor is connected to the anode of the fourth diode and the base of the second transistor. The cathode of the fourth diode is connected to the collector of the thirteenth transistor, and the emitter of the thirteenth transistor is connected to the power input circuit via the eleventh resistor to receive the negative voltage. The emitter of the third transistor is connected to the emitter of the seventh transistor via the third resistor, and the emitter of the fourth transistor is connected to the emitter of the eighth transistor via the fourth resistor. The emitter terminal of the fifth transistor is connected to the emitter terminal of the ninth transistor via the fifth resistor, and the emitter terminal of the sixth transistor is connected to the emitter terminal of the thirteenth transistor via the sixth resistor.

5. The high-speed track-and-hold circuit of claim 3, wherein The high-speed tracking and holding circuit also includes a clock buffer circuit; The first input terminal and the second input terminal of the clock buffer circuit are used to receive the positive phase clock signal and the negative phase clock signal, respectively, and to amplify the positive phase clock signal and the negative phase clock signal to obtain the tracking signal and the holding signal. The tracking signal input terminal of the first sampling switch circuit and the tracking signal input terminal of the second sampling switch circuit are used to receive the tracking signal, and the hold signal input terminal of the first sampling switch circuit and the hold signal input terminal of the second sampling switch circuit are used to receive the hold signal. When the signal level of the tracking signal received by the first sampling switch circuit and the second sampling switch circuit is higher than the signal level of the holding signal, the first sampling switch circuit and the second sampling switch circuit are in the on state. When the signal level of the tracking signal received by the first sampling switch circuit and the second sampling switch circuit is lower than the signal level of the hold signal, the first sampling switch circuit and the second sampling switch circuit are in an off state.

6. The high-speed track-and-hold circuit of claim 5, wherein, The first sampling switch circuit includes a first switching diode and a first Darlington structure control circuit; The cathode of the first switching diode is connected to the first terminal of the first storage capacitor, and the anode of the first switching diode is connected to the output terminal of the first Darlington structure circuit. The first current terminal of the first Darlington structure control circuit is connected to the first terminal of the first storage capacitor, and the second current terminal of the first Darlington structure control circuit is connected to the base terminal of the first transistor. The tracking signal input terminal of the first Darlington structure control circuit is used to receive the tracking signal, and the hold signal input terminal of the first Darlington structure control circuit is used to receive the hold signal. The first Darlington structure control circuit is used to draw current from the first terminal of the first storage capacitor when the tracking signal is greater than the hold signal, so as to control the first switching diode to turn on. The first Darlington structure control circuit is also used to draw current from the base terminal of the first transistor when the tracking signal is less than the holding signal, so as to control the first switching diode to turn off.

7. The high-speed track-and-hold circuit of claim 5, wherein The second sampling switch circuit includes a second switching diode and a second Darlington structure control circuit; The cathode of the second switching diode is connected to the first terminal of the second storage capacitor, and the anode of the second switching diode is connected to the output terminal of the second Darlington structure circuit. The first current terminal of the second Darlington structure control circuit is connected to the first terminal of the second storage capacitor, and the second current terminal of the second Darlington structure control circuit is connected to the base terminal of the second transistor. The tracking signal input terminal of the second Darlington structure control circuit is used to receive the tracking signal, the hold signal input terminal of the second Darlington structure control circuit is used to receive the hold signal, and the second Darlington structure control circuit is used to draw current from the first terminal of the second storage capacitor when the tracking signal is greater than the hold signal, so as to control the second switching diode to conduct. The second Darlington structure control circuit is also used to draw current from the base terminal of the second transistor when the tracking signal is less than the holding signal, so as to control the second switching diode to turn off.

8. The high-speed track-and-hold circuit of claim 7, wherein, The first sampling switch circuit further includes a first capacitor, the first end of which is connected to the first end of the first storage capacitor, and the second end of which is connected to the emitter terminal of the second transistor. The second sampling switch circuit also includes a second capacitor, the first end of which is connected to the first end of the second storage capacitor, and the second end of which is connected to the emitter terminal of the first transistor.

9. The high-speed track-and-hold circuit of claim 7, wherein, The output drive circuit includes a first output transistor, a second output transistor, a third output transistor, a fourth output transistor, a fifth output transistor, a sixth output transistor, a seventh output transistor, an eighth output transistor, a first output resistor, a second output resistor, a third output resistor, a fourth output resistor, a fifth output resistor, a sixth output resistor, a seventh output resistor, an eighth output resistor, a first wire, a second wire, a third wire, and a fourth wire; The base of the first output transistor is connected to the first end of the first storage capacitor. The emitter of the first output transistor is connected to the base of the second output transistor and the first end of the first output resistor, respectively. The emitter of the second output transistor is connected to the first end of the second output resistor. The collector of the first output transistor is connected to the first end of the first wire. The second end of the first wire is connected to the base terminal of the fifth output transistor and the emitter terminal of the sixth output transistor, respectively. The connection terminal after the collector terminals of the fifth and sixth output transistors are connected is connected to the first end of the seventh output resistor. The second end of the seventh output resistor is grounded. The emitter terminal of the fifth output transistor is connected to the first end of the second wire. The second end of the second wire is connected to the collector terminal of the second output transistor. The first end of the seventh output resistor extends to a first signal output port for outputting the first voltage signal. The base of the third output transistor is connected to the first end of the second storage capacitor. The emitter of the third output transistor is connected to the base of the fourth output transistor and the first end of the third output resistor. The emitter of the fourth output transistor is connected to the first end of the fourth output resistor. The collector of the third output transistor is connected to the first end of the third wire. The second end of the third wire is connected to the base terminal of the seventh output transistor and the emitter terminal of the eighth output transistor, respectively. The connection terminal after the collector terminals of the seventh and eighth output transistors are connected is connected to the first end of the eighth output resistor. The second end of the eighth output resistor is grounded. The emitter terminal of the seventh output transistor is connected to the first end of the fourth wire. The second end of the fourth wire is connected to the collector terminal of the fourth output transistor. The first end of the eighth output resistor extends to a second signal output port for outputting the second voltage signal. The base terminals of the sixth output transistor and the eighth output transistor are connected to an external voltage source to receive the power supply voltage. The emitter terminal of the first output transistor is also connected to the emitter terminal of the third output transistor through the fifth output resistor. The emitter terminal of the second output transistor is also connected to the emitter terminal of the fourth output transistor through the sixth output resistor. The connection point formed by linking the second end of the first output resistor, the second end of the second output resistor, the second end of the third output resistor, and the second end of the fourth output resistor is used to receive negative voltage.

10. The high-speed track-and-hold circuit of claim 5, wherein, The clock buffer circuit includes a ninth output resistor, a tenth output resistor, an eleventh output resistor, a twelfth output resistor, a thirteenth output resistor, a fourteenth output resistor, a first output diode, a second output diode, a ninth output transistor, a tenth output transistor, an eleventh output transistor, a twelfth output transistor, a thirteenth output transistor, and a fourteenth output transistor; The connection between the first end of the ninth output resistor and the base of the ninth output transistor serves as the first input of the clock buffer circuit, used to receive the positive clock signal. The connection between the second end of the ninth output resistor and the collector of the ninth output transistor is grounded. The emitter of the ninth output transistor is connected to the anode of the first output diode. The cathode of the first output diode is connected to the first end of the eleventh output resistor and the base of the eleventh output transistor. The connection between the first end of the tenth output resistor and the base of the tenth output transistor serves as the second input of the clock buffer circuit, used to receive the negative phase clock signal. The connection between the second end of the tenth output resistor and the collector of the tenth output transistor is grounded. The emitter of the tenth output transistor is connected to the anode of the second output diode. The cathode of the second output diode is connected to the first end of the twelfth output resistor and the base of the fourteenth output transistor, respectively. The connection terminal of the eleventh output transistor connected to the emitter terminal of the twelfth output transistor is connected to the first terminal of the thirteenth output resistor. The connection terminal of the twelfth output transistor connected to the base terminal of the thirteenth output transistor is used to receive external power supply voltage. The connection terminal of the thirteenth output transistor connected to the emitter terminal of the fourteenth output transistor is connected to the first terminal of the fourteenth output resistor. The connection point formed by connecting the second terminals of the eleventh output resistor, the twelfth output resistor, the thirteenth output resistor, and the fourteenth output resistor is connected to a negative voltage. The connection between the collector terminals of the eleventh and thirteenth output transistors is used to output the tracking signal, and the connection between the collector terminals of the twelfth and fourteenth output transistors is used to output the hold signal.

Images