A reliable power-on reset circuit and method

Abstract

This invention discloses a reliable power-on reset circuit and method. By setting an LDO module and a power-on reset circuit in the power supply system, the power-on reset circuit includes a VCC voltage detection module, a VDDD voltage detection module, and a digital logic function detection module. The VCC voltage detection module receives the VCC power supply and outputs a first release signal to the VDDD voltage detection module. The VDDD voltage detection module outputs a second release signal to the first inverter unit and a clock enable signal to the LSI unit based on the first release signal and the VCC voltage. The second release signal is then output to the flip-flop unit. The flip-flop unit receives the clock output signal and the second release signal and outputs a reset release signal in the third D flip-flop. This dual detection of VCC and VDDD provides a more stable power-on for the entire system, ensures the accuracy of the power-on control signals and timing of the power supply system, and improves the working stability and reliability of the power supply system.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and particularly relates to a reliable power-on reset circuit and method. Background Technology

[0002] Power-on reset circuits are a key technology in electronic systems to ensure reliable startup of devices upon power-up. Their core function is to force microcontrollers (MCUs), processors, and other digital systems into a known and stable initial state during power supply voltage establishment, preventing logic errors and program crashes caused by voltage instability or clock malfunctions. Traditional power-on reset methods detect the system's VCC power supply, charge capacitors using a current related to the power supply voltage, and determine the charging voltage. When the power supply voltage reaches a designed threshold, the circuit generates a logic high level, causing the digital logic to transition the system from a reset state to a released state. For example... Figure 1 .

[0003] The power-on detection only monitors and detects the system's power supply voltage VCC. When the VCC voltage rises to a preset value, a reset release signal is issued, and the power-on reset transitions from 0 to high. However, due to the presence of an LDO in the system, the output voltage of VDDD is uncontrollable when VCC reaches the design threshold. Furthermore, the settling time of VDDD varies depending on the power supply system's power-on speed, and its settling time also varies depending on the load and operating conditions. Therefore, it is difficult to guarantee that VDDD will be stable simultaneously with VCC reaching the design threshold.

[0004] For example Figure 2 When the VDDD setup time is uncontrollable, the power-on signal has already been released, and the digital and analog circuits cannot operate under a normal VDDD voltage. In this case, the reset is invalid, meaning the entire digital and analog section operating under the VDDD power domain lacks a reliable reset process, leading to the loss of some important initial states. This severely affects the normal operation of the chip. Therefore, there is an urgent need to provide a reliable power-on reset circuit to solve the aforementioned technical problems. Summary of the Invention

[0005] In view of this, the present invention provides a reliable power-on reset circuit and method, which performs dual detection of VCC and VDDD during power-on reset, thereby improving the working stability and reliability of the power supply system and ensuring the accuracy of the power-on control signals and timing of the power supply system. The specific technical solution adopted is as follows.

[0006] In a first aspect, the present invention provides a reliable power-on reset circuit applied to a power supply system. The power supply system includes an LDO module and a power-on reset circuit. The power-on reset circuit includes a VCC voltage detection module, a VDDD voltage detection module, and a digital logic function detection module. The LDO module is used to convert the VCC power supply in the power supply system into a VDDD power supply. The input terminal of the VCC voltage detection module is connected to the VCC power supply, and the output terminal of the VCC voltage detection module and the VDDD power supply are connected to the input terminal of the VDDD voltage detection module. The digital logic function detection module includes a first inverter unit, an LSI unit, and a flip-flop unit. The input terminals of the first inverter unit and the LSI unit are both connected to the output terminal of the VDDD voltage detection module. The output terminal of the first inverter unit is connected to the reset signal input terminal of the flip-flop unit. The flip-flop unit includes a first D flip-flop, a second D flip-flop, and a third D flip-flop. The output terminal of the LSI unit is connected to the clock input terminal of the first D flip-flop. The data input terminal of the first D flip-flop is connected to the inverted state output terminal of the first D flip-flop. The state output terminal of the first D flip-flop is connected to the clock input terminal of the second D flip-flop. The data input terminal of the second D flip-flop is connected to the inverted state output terminal of the second D flip-flop and the clock input terminal of the third D flip-flop. The data input terminal of the third D flip-flop is connected to the VDDD power supply. The VCC voltage detection module receives the VCC power supply and outputs a first release signal to the VDDD voltage detection module. The VDDD voltage detection module outputs a second release signal to the first inverter unit and a clock enable signal to the LSI unit based on the first release signal and the VCC voltage of the VCC power supply. The first inverter unit outputs the second release signal to the reset signal input terminal of the flip-flop unit. The flip-flop unit receives the clock output signal corresponding to the clock enable signal from the LSI unit and the second release signal from the first inverter unit, and outputs a corresponding reset release signal at the data output terminal of the third D flip-flop.

[0007] As a preferred embodiment of the above technical solution, the VCC voltage detection module includes a charging unit and a second inverter unit. Both the charging unit and the second inverter unit are connected to the VCC power supply. The charging unit is connected to the input terminal of the second inverter unit, and the output terminal of the second inverter unit is connected to the VDDD voltage detection module. The charging unit is used to receive the VCC voltage of the VCC power supply and output a first voltage signal to the second inverter unit. The second inverter unit outputs a first release signal corresponding to the first voltage signal to the VDDD voltage detection module according to the first voltage signal.

[0008] As a preferred embodiment of the above technical solution, the charging unit includes a resistor R2 and a capacitor C2, and the second inverter unit includes a Schmitt inverter I0, an inverter I1, and an inverter I2. One end of the resistor R2 is connected to the VCC terminal of the Schmitt inverter I0, the VCC terminal of the inverter I1, and the VCC terminal of the inverter I2. The other end of the resistor R2 is connected to one end of the capacitor C2 and the input terminal of the Schmitt inverter I0. The output terminal of the Schmitt inverter I0 is connected to the input terminal of the inverter I1, and the output terminal of the inverter I1 is connected to the input terminal of the inverter I2. The other end of the capacitor C2 is connected to the VSS terminal of the Schmitt inverter I0, the VSS terminal of the inverter I1, and the VSS terminal of the inverter I2. Resistor R2 charges capacitor C2, generating a first voltage signal VA. When the first voltage signal VA increases with the VCC voltage of the VCC power supply, the first voltage signal VA reaches a first preset voltage threshold. The output of Schmitt inverter I0 changes from high level to low level, the output of inverter I1 changes from low level to high level, and the output of inverter I2 changes from high level to low level.

[0009] As a preferred embodiment of the above technical solution, the VDDD voltage detection module includes a switching unit and a third inverter unit. Both the switching unit and the third inverter unit are connected to the VDDD power supply. The switching unit is connected to the input terminal of the third inverter unit, and the output terminal of the third inverter unit is connected to the second inverter unit and the LSI unit. The switching unit outputs a second voltage signal to the third inverter unit according to the first release signal, the third inverter unit outputs a second release signal to the first inverter unit according to the second voltage signal, and the LSI unit outputs a clock enable signal.

[0010] As a preferred embodiment of the above technical solution, the switching unit includes MOSFET Q0, MOSFET Q1, resistor R3, and resistor R4; the third inverter unit includes Schmitt inverter I3 and inverter I4; the gate of MOSFET Q0 is connected to the output terminal of inverter I2; the drain of MOSFET Q0 is connected to one end of resistor R4, the input terminal of Schmitt inverter I3, and one end of resistor R3; the source of MOSFET Q0 is connected to the drain of MOSFET Q1 and the VSS terminal of inverter I4; the other end of resistor R4 is connected to the source of MOSFET Q1; the gate of MOSFET Q1 is connected to the output terminal of Schmitt inverter I3 and the input terminal of inverter I4; and the other end of resistor R3 is connected to the VDDD terminal of inverter I4. When the VCC voltage is low and the first release signal output by the inverter I2 is high, the MOS transistor Q1 is turned on and pulls the second voltage signal VB low, making both the second release signal and the clock enable signal low, thus disabling the digital logic function detection module and resetting the flip-flop unit.

[0011] As a preferred embodiment of the above technical solution, when the VCC voltage rises to the first preset voltage threshold, the first release signal becomes low level, and the MOS transistor Q1 is turned off. When the VDDD voltage rises and the second voltage signal VB voltage rises and reaches the second preset voltage threshold, the output of Schmitt inverter I3 changes from high level to low level, and the clock enable signal output of inverter I4 and the second release signal output of inverter I6 change from low level to high level.

[0012] As a preferred embodiment of the above technical solution, when the clock enable signal is high, the LSI unit starts and outputs a clock output signal, wherein the second release signal is the reset signal of the digital logic function detection module; When the second release signal changes from low level to high level, the second release signal ends the reset state of the trigger unit, and the trigger unit operates normally.

[0013] As a preferred embodiment of the above technical solution, the first inverter unit includes inverter I5 and inverter I6. The input terminal of inverter I5 is connected to the output terminal of inverter I4 and the input terminal of the LSI unit. The output terminal of inverter I5 is connected to the input terminal of inverter I6. The output terminal of inverter I6 is connected to the reset signal input terminal of the trigger unit. When the second release signal is low, the data output terminal of the third D flip-flop is set to 0, and the power supply system does not work.

[0014] As a preferred embodiment of the above technical solution, when the second release signal is high, the digital logic function detection module performs logic operation according to the clock output signal, and the third D flip-flop transmits the high-level VDDD voltage to the data output terminal of the third D flip-flop to complete the output of the high-level por_rst signal. The por_rst signal is output from the low level of the flip-flop unit in the reset state to the high level after normal operation, and the power supply system obtains a reliable reset release signal. When inverter I2 outputs a high level when VCC voltage is low, the second voltage signal is pulled low by MOSFET Q1, inverters I4 and I6 both output a low level, the trigger unit is in the set state, the por_rst signal is low, and the power supply system is in the reset state.

[0015] Secondly, the present invention also provides a reliable power-on reset method, which is used to execute the above-mentioned reliable power-on reset circuit, and includes the following steps: The VCC voltage detection module receives the VCC power supply and outputs a first release signal to the VDDD voltage detection module, wherein the LDO module controls the output of VDDD voltage to the VDDD voltage detection module according to the VCC voltage of the VCC power supply. The VDDD voltage detection module is controlled to output a second release signal to the first inverter unit based on the first release signal and the VCC voltage, and the LSI unit outputs a clock enable signal. The first inverter unit outputs the second release signal to the reset signal input terminal of the trigger unit; The flip-flop unit receives the clock output signal corresponding to the clock enable signal output by the LSI unit and the second release signal output by the first inverter unit, and outputs the corresponding reset release signal at the data output terminal of the third D flip-flop.

[0016] This invention provides a reliable power-on reset circuit and method. By incorporating an LDO module and a power-on reset circuit into the power supply system, the power-on reset circuit includes a VCC voltage detection module, a VDDD voltage detection module, and a digital logic function detection module. The VCC voltage detection module receives the VCC power supply and outputs a first release signal to the VDDD voltage detection module. Based on the first release signal and the VCC voltage of the VCC power supply, the VDDD voltage detection module outputs a second release signal to a first inverter unit and a clock enable signal to an LSI unit. The first inverter unit outputs the second release signal to the reset signal input of a flip-flop unit. The flip-flop unit receives the clock output signal corresponding to the clock enable signal from the LSI unit and the second release signal from the first inverter unit, and outputs the corresponding reset release signal at the data output terminal of a third D flip-flop. This dual detection of VCC and VDD by the VCC and VDD voltage detection modules provides a more stable power-on for the entire system, ensuring the accuracy of the power-on control signals and timing, and improving the operational stability and reliability of the power supply system. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a circuit diagram of a traditional power-on reset circuit. Figure 2 The power-on reset waveform diagram for a traditional power supply system; Figure 3 The structural block diagram of the reliable power-on reset circuit provided by the present invention; Figure 4 A circuit diagram of the reliable power-on reset circuit provided by the present invention; Figure 5 A flowchart of a reliable power-on reset method provided by the present invention; Figure 6 The power-on reset flowchart provided for this invention.

[0019] The symbols for the main components are explained below: 10 - LDO module; 20 - Power-on reset circuit; 30 - VCC voltage detection module; 40 - VDDD voltage detection module; 50 - Digital logic function detection module; 51 - First inverter unit; 52 - LSI unit; 53 - Flip-flop unit; 54 - Charging unit; 55 - Second inverter unit; 56 - Switching unit; 57 - Third inverter unit. Detailed Implementation

[0020] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0021] Electronic products operate in diverse environments and power supply schemes, ranging from rapid power-on to extremely slow power-on. Once operational, these power supplies generate significant fluctuations and interference. Typically, chip systems are designed using multi-power supply systems. This involves internally employing an LDO (Low Dropout Linear Regulator) to convert the power supply voltage VCC to a low-voltage VDDD (Digital Power Supply Voltage), typically 1.5V or 1.2V. Most analog circuitry and all digital circuitry are then designed on the VDDD power domain, using low-voltage devices. This approach further reduces interference on the VCC power supply and, more importantly, allows for smaller device sizes, significantly reducing chip area and cost.

[0022] However, since an LDO power supply is used to generate the VDDD voltage, modules operating in this voltage domain need to be able to operate only after the VDDD voltage reaches a suitable value and stabilizes. Traditional detection methods typically only monitor the VCC power supply. Because the generation times of the VCC and VDDD voltages are different, the stabilization and establishment times of the two voltages are inconsistent and differ significantly, leading to the generation of false reset signals when detecting VCC. Therefore, the reliable power-on reset circuit and method provided in this invention are used to solve the above-mentioned technical problems. The specific implementation process is as follows: See Figure 3 and Figure 4This invention provides a reliable power-on reset circuit for use in a power supply system. The power supply system includes an LDO module 10 and a power-on reset circuit 20. The power-on reset circuit 20 includes a VCC voltage detection module 30, a VDDD voltage detection module 40, and a digital logic function detection module 40. The LDO module 10 is used to convert the VCC power supply in the power supply system into a VDDD power supply. The input terminal of the VCC voltage detection module 30 is connected to the VCC power supply, and the output terminal of the VCC voltage detection module 30, the VDDD power supply, and the input terminal of the VDDD voltage detection module 40 are connected. The digital logic function detection module 50 includes a first inverter unit 51, an LSI unit 52, and a flip-flop unit 53. The input terminals of the first inverter unit 51 and the LSI unit 52 (LSI) are both connected to the output terminal of the VDDD voltage detection module 40. The output terminal of the first inverter unit 51 is connected to the reset signal input terminal (RN) of the flip-flop unit 53. The flip-flop unit 53 includes a first D flip-flop (I8), a second D flip-flop (I9), and a third D flip-flop (I10). The output terminal of the LSI unit 52 is connected to the clock input terminal (CK) of the first D flip-flop. The data input terminal (D) of the first D flip-flop is connected to the inverted state output terminal (QN) of the first D flip-flop. The state output terminal (Q) of the first D flip-flop is connected to the clock input terminal of the second D flip-flop. The data input terminal of the second D flip-flop is connected to the inverted state output terminal of the second D flip-flop and the clock input terminal of the third D flip-flop. The data input terminal of the third D flip-flop is connected to the VDDD power supply. The VCC voltage detection module 30 receives the VCC power supply and outputs a first release signal to the VDDD voltage detection module 40. The VDDD voltage detection module 40 outputs a second release signal to the first inverter unit 51 and a clock enable signal to the LSI unit 52 based on the first release signal and the VCC voltage of the VCC power supply. The first inverter unit 51 outputs the second release signal to the reset signal input terminal of the flip-flop unit 53. The flip-flop unit 53 receives the clock output signal corresponding to the clock enable signal output by the LSI unit 52 and the second release signal output by the first inverter unit 51, and outputs a corresponding reset release signal at the data output terminal of the third D flip-flop.

[0023] In this embodiment, the VCC voltage detection module 30 includes a charging unit 54 and a second inverter unit 55. Both the charging unit 54 and the second inverter unit 55 are connected to the VCC power supply. The charging unit 54 is connected to the input terminal of the second inverter unit 55, and the output terminal of the second inverter unit 55 is connected to the VDDD voltage detection module 40. The charging unit 54 is used to receive the VCC voltage from the VCC power supply and output a first voltage signal to the second inverter unit 55. The second inverter unit 55 outputs a first release signal corresponding to the first voltage signal to the VDDD voltage detection module 40 according to the first voltage signal. The charging unit 54 includes a resistor R2 and a capacitor C2. The second inverter unit 55 includes a Schmitt inverter I0, an inverter I1, and an inverter I2. One end of the resistor R2 is connected to the VCC terminals of the Schmitt inverter I0, I1, and I2. The other end of the resistor R2 is connected to one end of the capacitor C2 and the input terminal of the Schmitt inverter I0. The output terminal of the Schmitt inverter I0 is connected to the input terminal of the inverter I1, and the output terminal of the inverter I1 is connected to the input terminal of the inverter I2. The other end of capacitor C2 is connected to the VSS terminals of Schmitt inverter I0, inverter I1, and inverter I2. Resistor R2 charges capacitor C2 to generate a first voltage signal VA. When the first voltage signal VA increases with the VCC voltage of the VCC power supply, the first voltage signal VA reaches a first preset voltage threshold. The output of Schmitt inverter I0 changes from high level to low level, the output of inverter I1 changes from low level to high level, and the output of inverter I2 changes from high level to low level.

[0024] It should be noted that the VDDD voltage detection module 40 includes a switching unit 56 and a third inverter unit 57. Both the switching unit 56 and the third inverter unit 57 are connected to the VDDD power supply. The switching unit 56 is connected to the input terminal of the third inverter unit 57, and the output terminal of the third inverter unit 57 is connected to the second inverter unit 55 and the LSI unit 52. The switching unit 56 outputs a second voltage signal to the third inverter unit 57 according to the first release signal. The third inverter unit 57 outputs a second release signal (VO_B) to the first inverter unit 51 according to the second voltage signal, and the LSI unit 52 (LSI) outputs a clock enable signal (Clk_en). The switching unit 56 includes MOSFETs Q0 and Q1, resistors R3 and R4, and the third inverter unit 57 includes a Schmitt inverter I3 and an inverter I4. The gate of MOSFET Q0 is connected to the output terminal of inverter I2. The drain of MOSFET Q0 is connected to one end of resistor R4, the input terminal of Schmitt inverter I3, and one end of resistor R3. The source of MOSFET Q0 is connected to the drain of MOSFET Q1 and the VSS terminal of inverter I4. The other end of resistor R4 is connected to MOSFET Q1. The source of the MOSFET Q1 is connected to the output of the Schmitt inverter I3 and the input of the inverter I4. The other end of the resistor R3 is connected to the VDDD terminal of the inverter I4. When the VCC voltage is low and the first release signal output by the inverter I2 is high, the MOSFET Q1 is turned on and pulls the second voltage signal VB low, making both the second release signal and the clock enable signal low, and disabling the operation of the digital logic function detection module 50. The trigger unit 53 performs a reset.

[0025] Specifically, the processes executed by the VCC voltage detection module 30, the VDDD voltage detection module 40, and the digital logic function detection module 50 are denoted as three stages (steps): A, B, and C. The first voltage signal (VA) is related to the VCC voltage. The VA voltage increases as the VCC (voltage) increases. When the VCC reaches a sufficiently high level, the VA voltage reaches the first preset voltage threshold (design threshold). The Schmitt inverter sensor I0 detects the increase in VA, and its output changes from high (level) to 0 (low level). The output of inverter I1 changes from 0 to high, and the output of inverter I2, VO_A, changes from high to 0. The LDO is a module that converts the VCC power supply to the VDDD power supply. In general, digital power supplies in power systems are provided by LDOs using the VDDD voltage as the digital power supply.

[0026] It should be understood that by setting up an LDO module 10 and a power-on reset circuit 20 in the power supply system, the power-on reset circuit 20 includes a VCC voltage detection module 30, a VDDD voltage detection module 40, and a digital logic function detection module 50. The VCC voltage detection module 30 receives the VCC power supply and outputs a first release signal to the VDDD voltage detection module 40. The VDDD voltage detection module 40 outputs a second release signal to the first inverter unit 51 and a clock enable signal to the LSI unit 52 based on the first release signal and the VCC voltage of the VCC power supply. The first inverter unit 51 then outputs the second release signal. The discharge signal is output to the reset signal input terminal of the flip-flop unit 53. The flip-flop unit 53 receives the clock output signal corresponding to the clock enable signal output by the LSI unit 52 and the second release signal output by the first inverter unit 51, and outputs the corresponding reset release signal at the data output terminal of the third D flip-flop. The power-on reset with dual detection of VCC and VDDD by the VCC voltage detection module 30 and the VDDD voltage detection module 40 provides a more stable power-on for the entire system, ensures the accuracy of the power-on control signals and timing of the power supply system, and improves the working stability and reliability of the power supply system. Optionally, when the VCC voltage rises to a first preset voltage threshold, the first release signal becomes low, and the MOSFET Q1 is turned off. When the VDDD voltage rises and the second voltage signal VB voltage rises and reaches the second preset voltage threshold, the output of Schmitt inverter I3 changes from high level to low level, and the clock enable signal output of inverter I4 and the second release signal output of inverter I6 change from low level to high level.

[0027] In this embodiment, as Figure 4 As shown, when the clock enable signal is high, the LSI unit starts and outputs a clock output signal (Clk_out). The second release signal is the reset signal for the digital logic function detection module. When the second release signal changes from low to high, the second release signal ends the reset state of the flip-flop unit, and the flip-flop unit operates normally. When VCC voltage is low, the inverter I2 outputs VO_A high, the MOS transistor Q1 (NMOS) turns on (conducts), and pulls the VB voltage (second voltage signal) low. A low VB voltage causes VO_B to be 0 and Clk_en (Lsi_en) to be 0, thus preventing the subsequent module C (digital logic function detection module) from working and resetting I8~I10 (first D flip-flop, second D flip-flop, and third D flip-flop). That is, when VCC is low, the entire system is always in a reset state, and the digital system will not work. The LSI unit is an integrated circuit that integrates a large number of transistors, resistors, capacitors, and inductors onto a single chip.

[0028] When the initial VCC rises to the expected level, VO_A becomes 0, at which point transistor Q1 (MOSFET Q1) is turned off (disconnected). The VB voltage (second voltage signal) changes with the VDDD voltage. When VDDD (voltage) rises, the VB voltage also rises. When it reaches the design threshold (second preset voltage threshold), the output of Schmitt inverter I3 changes from high to 0, and the outputs of inverter I4 (Clk_en) and inverter I6 (VO_B) both change from 0 to high, thus completing the function of the VDDD voltage detection section.

[0029] When Clk_en is high, the LSI unit is enabled, and the clock output signal Clk_out is output. Since the VO_B signal is the reset signal of module C, when the VO_B signal changes from 0 to high, the reset state of the three flip-flops I8~I10 ends, and the three flip-flops can work normally, thus completing the release of the third stage (the execution process of module C).

[0030] Optionally, the first inverter unit includes inverter I5 and inverter I6. The input terminal of inverter I5 is connected to the output terminal of inverter I4 and the input terminal of LSI unit. The output terminal of inverter I5 is connected to the input terminal of inverter I6. The output terminal of inverter I6 is connected to the reset signal input terminal of trigger unit. When the second release signal is low, the data output terminal of the third D flip-flop is set to 0, and the power supply system does not work.

[0031] In this embodiment, when the second release signal is high, the digital logic function detection module performs logic operation according to the clock output signal. The third D flip-flop transmits the high-level VDDD voltage to the data output terminal of the third D flip-flop to complete the output of the high-level por_rst signal. The por_rst signal is output from the low level of the flip-flop unit in the reset state to the high level after normal operation, and the power supply system obtains a reliable reset release signal. When the inverter I2 outputs a high level when the VCC voltage is low, the second voltage signal is pulled low by the MOS transistor Q1, and both inverters I4 and I6 output a low level. The flip-flop unit is in the set state, the por_rst signal is low, and the power supply system is in the reset state.

[0032] It should be noted that section C (module C) is responsible for digital logic function testing. The flip-flops are the basic logic modules; if flip-flops I8 to I10 function correctly, the entire digital system will operate normally. When the VDDD voltage is too low to support the entire digital system, the VO_B signal from module B (VDDD voltage detection module) is 0. The VO_B signal is also the reset terminal for the logic modules (flip-flops) in module C. When the VO_B signal is 0, the output is forcibly set to 0, thus preventing the entire digital system from operating. When the VO_B signal is high, the reset bit is released, and normal function operation begins. Module C uses the clock signal Clk_out provided by module B for logic operation. Flip-flop I10 (the third D flip-flop) transmits the high potential VDDD to por_rst. When normal operation is achieved, the output por_rst signal becomes high. The por_rst signal changes from 0 (reset state) to high (normal operation state) after flip-flops I8 to I10, providing a reliable reset release signal for the digital system. Since inverter I2 outputs high when VCC is low, VB is pulled to 0V by MOSFET Q1. Inverters I4 and I6 both output 0V, and the three DFFs (D-type flip-flops) I8-I10 are all in the set state. por_rst outputs 0, and the entire system is in the reset phase (state). Flip-flops can be replaced with other digital units, and the clock can be replaced with other low-voltage analog ports; there are no restrictions here, and the settings can be adjusted according to the specific circumstances.

[0033] See Figure 5 and Figure 6 The present invention also provides a reliable power-on reset method, which is used to execute the above-mentioned reliable power-on reset circuit, and includes the following steps: S1: Obtain the first release signal from the VCC voltage detection module to the VDDD voltage detection module, wherein the LDO module controls the output of VDDD voltage to the VDDD voltage detection module according to the VCC voltage of the VCC power supply. S2: Control the VDDD voltage detection module to output a second release signal to the first inverter unit and the LSI unit to output a clock enable signal according to the first release signal and the VCC voltage; S3: The first inverter unit outputs the second release signal to the reset signal input terminal of the trigger unit; S4: The flip-flop unit receives the clock output signal corresponding to the clock enable signal output by the LSI unit and the second release signal output by the first inverter unit, and outputs the corresponding reset release signal at the data output terminal of the third D flip-flop.

[0034] In this embodiment, the power-on reset process mainly includes the following steps: (1) Start detection; (2) After detecting that the VCC voltage rises, the LDO (module) can output VDDD normally, and then release downwards, otherwise wait; (3) After detecting that the VDDD voltage can make the low-voltage LSI unit work, release downwards to make the clock work, otherwise wait; (4) The LSI unit receives the enable signal (clock enable signal) and starts working, and provides the clock (output) signal to the digital logic (function detection) module, otherwise wait; (5) Determine whether the digital logic module under VDDD can work normally. If it cannot work normally, wait without releasing.

[0035] In all examples shown and described herein, any specific values ​​should be interpreted as merely exemplary and not as limitations; therefore, other examples of exemplary embodiments may have different values.

[0036] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0037] The above-described embodiments are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

Claims

1. A reliable power-on reset circuit, characterized in that, This invention is applied to a power supply system, which includes an LDO module and a power-on reset circuit. The power-on reset circuit includes a VCC voltage detection module, a VDDD voltage detection module, and a digital logic function detection module. The LDO module is used to convert the VCC power supply in the power supply system into a VDDD power supply. The input terminal of the VCC voltage detection module is connected to the VCC power supply, and the output terminal of the VCC voltage detection module and the VDDD power supply are connected to the input terminal of the VDDD voltage detection module. The digital logic function detection module includes a first inverter unit, an LSI unit, and a flip-flop unit. The input terminals of the first inverter unit and the LSI unit are both connected to the output terminal of the VDDD voltage detection module. The output terminal of the first inverter unit is connected to the reset signal input terminal of the flip-flop unit. The flip-flop unit includes a first D flip-flop, a second D flip-flop, and a third D flip-flop. The output terminal of the LSI unit is connected to the clock input terminal of the first D flip-flop. The data input terminal of the first D flip-flop is connected to the inverted state output terminal of the first D flip-flop. The state output terminal of the first D flip-flop is connected to the clock input terminal of the second D flip-flop. The data input terminal of the second D flip-flop is connected to the inverted state output terminal of the second D flip-flop and the clock input terminal of the third D flip-flop. The data input terminal of the third D flip-flop is connected to the VDDD power supply. The VCC voltage detection module receives the VCC power supply and outputs a first release signal to the VDDD voltage detection module. The VDDD voltage detection module outputs a second release signal to the first inverter unit and a clock enable signal to the LSI unit based on the first release signal and the VCC voltage of the VCC power supply. The first inverter unit outputs the second release signal to the reset signal input terminal of the flip-flop unit. The flip-flop unit receives the clock output signal corresponding to the clock enable signal from the LSI unit and the second release signal from the first inverter unit, and outputs a corresponding reset release signal at the data output terminal of the third D flip-flop.

2. The reliable power-on reset circuit according to claim 1, characterized in that, The VCC voltage detection module includes a charging unit and a second inverter unit. Both the charging unit and the second inverter unit are connected to the VCC power supply. The charging unit is connected to the input terminal of the second inverter unit, and the output terminal of the second inverter unit is connected to the VDDD voltage detection module. The charging unit is used to receive the VCC voltage of the VCC power supply and output a first voltage signal to the second inverter unit. The second inverter unit outputs a first release signal corresponding to the first voltage signal to the VDDD voltage detection module according to the first voltage signal.

3. The reliable power-on reset circuit according to claim 2, characterized in that, The charging unit includes a resistor R2 and a capacitor C2. The second inverter unit includes a Schmitt inverter I0, an inverter I1, and an inverter I2. One end of the resistor R2 is connected to the VCC terminals of the Schmitt inverter I0, I1, and I2. The other end of the resistor R2 is connected to one end of the capacitor C2 and the input terminal of the Schmitt inverter I0. The output terminal of the Schmitt inverter I0 is connected to the input terminal of the inverter I1. The output terminal of the inverter I1 is connected to the input terminal of the inverter I2. The other end of the capacitor C2 is connected to the VSS terminals of the Schmitt inverter I0, I1, and I2. Resistor R2 charges capacitor C2, generating a first voltage signal VA. When the first voltage signal VA increases with the VCC voltage of the VCC power supply, the first voltage signal VA reaches a first preset voltage threshold. The output of Schmitt inverter I0 changes from high level to low level, the output of inverter I1 changes from low level to high level, and the output of inverter I2 changes from high level to low level.

4. The reliable power-on reset circuit according to claim 2, characterized in that, The VDDD voltage detection module includes a switching unit and a third inverter unit. Both the switching unit and the third inverter unit are connected to the VDDD power supply. The switching unit is connected to the input terminal of the third inverter unit, and the output terminal of the third inverter is connected to the second inverter unit and the LSI unit. The switching unit outputs a second voltage signal to the third inverter unit according to the first release signal, the third inverter unit outputs a second release signal to the first inverter unit according to the second voltage signal, and the LSI unit outputs a clock enable signal.

5. The reliable power-on reset circuit according to claim 4, characterized in that, The switching unit includes MOSFET Q0, MOSFET Q1, resistor R3, and resistor R4. The third inverter unit includes Schmitt inverter I3 and inverter I4. The gate of MOSFET Q0 is connected to the output terminal of inverter I2. The drain of MOSFET Q0 is connected to one end of resistor R4, the input terminal of Schmitt inverter I3, and one end of resistor R3. The source of MOSFET Q0 is connected to the drain of MOSFET Q1 and the VSS terminal of inverter I4. The other end of resistor R4 is connected to the source of MOSFET Q1. The gate of MOSFET Q1 is connected to the output terminal of Schmitt inverter I3 and the input terminal of inverter I4. The other end of resistor R3 is connected to the VDDD terminal of inverter I4. When the VCC voltage is low and the first release signal output by the inverter I2 is high, the MOS transistor Q1 is turned on and pulls the second voltage signal VB low, making both the second release signal and the clock enable signal low, thus disabling the digital logic function detection module and resetting the flip-flop unit.

6. The reliable power-on reset circuit according to claim 5, characterized in that, When the VCC voltage rises to the first preset voltage threshold, the first release signal becomes low, and the MOSFET Q1 is turned off. When the VDDD voltage rises and the second voltage signal VB voltage rises and reaches the second preset voltage threshold, the output of Schmitt inverter I3 changes from high level to low level, and the clock enable signal output of inverter I4 and the second release signal output of inverter I6 change from low level to high level.

7. The reliable power-on reset circuit according to claim 6, characterized in that, When the clock enable signal is high, the LSI unit starts and outputs a clock output signal, wherein the second release signal is the reset signal of the digital logic function detection module; When the second release signal changes from low level to high level, the second release signal ends the reset state of the trigger unit, and the trigger unit works normally.

8. The reliable power-on reset circuit according to claim 6, characterized in that, The first inverter unit includes inverter I5 and inverter I6. The input terminal of inverter I5 is connected to the output terminal of inverter I4 and the input terminal of LSI unit. The output terminal of inverter I5 is connected to the input terminal of inverter I6. The output terminal of inverter I6 is connected to the reset signal input terminal of trigger unit. When the second release signal is low, the data output terminal of the third D flip-flop is set to 0, and the power supply system does not work.

9. The reliable power-on reset circuit according to claim 8, characterized in that, When the second release signal is high, the digital logic function detection module performs logic operation according to the clock output signal. The third D flip-flop transmits the high-level VDDD voltage to the data output terminal of the third D flip-flop to complete the output of the high-level por_rst signal. The por_rst signal is output from the low level of the flip-flop unit in the reset state to the high level after normal operation. The power supply system obtains a reliable reset release signal. When inverter I2 outputs a high level when VCC voltage is low, the second voltage signal is pulled low by MOSFET Q1, inverters I4 and I6 both output a low level, the trigger unit is in the set state, the por_rst signal is low, and the power supply system is in the reset state.

10. A reliable power-on reset method, characterized in that, The reliable power-on reset method is used to execute the reliable power-on reset circuit as described in any one of claims 1-9, and includes the following steps: The VCC voltage detection module receives the VCC power supply and outputs a first release signal to the VDDD voltage detection module, wherein the LDO module controls the output of VDDD voltage to the VDDD voltage detection module according to the VCC voltage of the VCC power supply. The VDDD voltage detection module is controlled to output a second release signal to the first inverter unit based on the first release signal and the VCC voltage, and the LSI unit outputs a clock enable signal. The first inverter unit outputs the second release signal to the reset signal input terminal of the trigger unit; The flip-flop unit receives the clock output signal corresponding to the clock enable signal output by the LSI unit and the second release signal output by the first inverter unit, and outputs the corresponding reset release signal at the data output terminal of the third D flip-flop.

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