Edge timing arbitration and lane selection circuit, chip and electronic device

Abstract

This invention provides an edge timing arbitration and channel selection circuit, chip, and electronic device. The edge timing arbitration and channel selection circuit includes a channel reset module and one or more cascaded channel selection execution modules; each channel selection execution module includes a first channel selection output unit that receives a first input signal, a second channel selection output unit that receives a second input signal, and a channel arbitration output unit. The channel arbitration output unit outputs one of the first and second input signals whose rising edges arrive first, based on a first intermediate signal output by the first channel selection output unit, a second intermediate signal output by the second channel selection output unit, and a reset signal generated by the channel reset module. This invention not only supports cycle-by-cycle edge timing detection and real-time arbitration and gating of multiple channels with strong anti-interference capabilities, but also has a simple structure and is easy to implement.

Description

Technical Field

[0001] This invention relates to the field of circuit design technology, and in particular to an edge timing arbitration and channel selection circuit, chip, and electronic device. Background Technology

[0002] Please see Figure 1 , Figure 2 and Figure 3 ,in, Figure 1 This is a block diagram of an edge timing arbitration and channel selection circuit in the prior art. Figure 2 for Figure 1 The diagram shows a topology of the edge timing arbitration and channel selection circuit in one specific example. Figure 3 For input to Figure 2 The diagram shows the waveforms of the two signals in the edge timing arbitration and channel selection circuit. From... Figure 1 and Figure 2 It can be seen that the edge timing arbitration and channel selection circuits in the existing technology usually use logic gates and flip-flops to determine the order of arrival of the rising edges of two voltage signals A and B: if the rising edge of signal A arrives before signal B, then QA is pulled high and QB is pulled low; otherwise, QB is pulled high and QA is pulled low. However, research has found that the edge timing arbitration and channel selection circuits in the existing technology have the following defects in integrated circuit design, since they usually use logic gates or FPGA logic devices to detect the rising / falling edge of the voltage signal and generate trigger signals: (1) Limited timing arbitration accuracy: If the edge timing of two voltage signals is very close, timing arbitration and channel selection cannot be performed; (2) Does not support cycle-by-cycle detection: It cannot perform cycle-by-cycle detection and can only realize single timing arbitration, and cannot continuously detect; if cycle detection is to be supported, additional peripheral circuits are required; (3) Does not support multi-channel: It can only detect the edge timing between two channels and cannot support multi-channel real-time arbitration and gating; (4) If multi-channel output is supported, additional peripheral circuits are required, resulting in a complex structure and weak anti-noise interference capability.

[0003] However, the existing technology's requirements for cycle-by-cycle detection of edge timing signals and multi-channel arbitration and channel selection cover, but are not limited to, reliability monitoring and protection throughout the entire chip lifecycle. Application scenarios include functional safety monitoring systems for ASIL-D-level automotive-grade MCUs / SoCs and multi-core power management and DVFS systems for high-end server CPUs. Therefore, how to provide a circuit that supports cycle-by-cycle, multi-channel edge timing arbitration and channel selection has increasingly become one of the technical problems that urgently needs to be solved by those skilled in the art.

[0004] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to address the problem that existing edge timing arbitration and channel selection circuits do not support cycle-by-cycle, multi-channel detection, and to provide an edge timing arbitration and channel selection circuit, chip, and electronic device. This invention not only supports cycle-by-cycle edge timing detection and real-time arbitration and gating of multiple channels with strong anti-interference capabilities, but also has a simple structure and is easy to implement.

[0006] To achieve the above objectives, the present invention provides the following technical solution: an edge-timing arbitration and channel selection circuit, comprising a channel reset module and one or more cascaded channel selection execution modules; each of the channel selection execution modules includes a first channel selection output unit for receiving a first input signal, a second channel selection output unit for receiving a second input signal, and a channel arbitration output unit; the first input signal and the second input signal are pulse signals with rising edges of different timings;

[0007] The channel reset module is configured to output a reset signal when the rising edge of any input signal received by all the channel selection execution modules arrives, so that the first channel selection output unit outputs a first intermediate signal and the second channel selection output unit outputs a second intermediate signal; and when the rising edge of the first input signal precedes the rising edge of the second input signal, the first intermediate signal is high and the second intermediate signal is low; when the rising edge of the second input signal precedes the rising edge of the first input signal, the first intermediate signal is low and the second intermediate signal is high.

[0008] The channel arbitration output unit is coupled to the first channel selection output unit and the second channel selection output unit to the first node and the second node, respectively, and is configured to output one of the first input signal and the second input signal whose rising edge arrives first, based on the first input signal, the second input signal, the first intermediate signal, the second intermediate signal and the reset signal.

[0009] Optionally, the edge timing arbitration and channel selection circuit includes multiple channel selection execution modules, and the number of channel selection execution modules near the input side is twice that of adjacent channel selection execution modules near the output side; the first channel selection output unit and the second channel selection output unit of the channel selection execution module closest to the input side are used to receive the input signal, the first channel selection output unit and the second channel selection output unit of the channel selection execution module located in the middle stage are respectively used to receive the output signals of the channel arbitration output units of the two corresponding channel selection execution modules of the adjacent previous stage, and the channel arbitration output unit of the channel selection execution module closest to the output side is used to output one of the input signals whose rising edge arrives first.

[0010] Optionally, the channel reset module includes a first OR gate, the input of which is used to receive all the input signals, and its output is respectively connected to the reset terminals of the first channel selection output units, the second channel selection output units, and the first input terminal of the channel arbitration output unit of all the channel selection execution modules.

[0011] Optionally, the first channel selection output unit includes a first delay sub-circuit, a first flip-flop, a first transmission gate, a first inverter, and a first resistor; the second channel selection output unit includes a second delay sub-circuit, a second flip-flop, a second transmission gate, a second inverter, and a second resistor.

[0012] The input terminal of the first delay sub-circuit receives the first input signal, and its output terminal is connected to the clock terminal of the first flip-flop. The reset terminal of the first flip-flop is connected to the output terminal of the channel reset module, its data input terminal is connected to its inverting output terminal, and its output terminal is connected to the input terminal of the first transmission gate. The output terminal of the first transmission gate is connected to the first terminal of the first resistor, the second input terminal of the channel arbitration output unit is connected to the first node, its control terminal is connected to the output terminal of the first inverter, its inverting control terminal is connected to the input terminal of the first inverter, the third input terminal of the channel arbitration output unit is connected to the second node, and the second terminal of the first resistor is connected to reference ground.

[0013] The input terminal of the second delay sub-circuit receives the second input signal, and its output terminal is connected to the clock terminal of the second flip-flop. The reset terminal of the second flip-flop is connected to the output terminal of the channel reset module, its data input terminal is connected to its inverting output terminal, and its output terminal is connected to the input terminal of the second transmission gate. The output terminal of the second transmission gate is connected to the first terminal of the second resistor, the third input terminal of the channel arbitration output unit is connected to the second node, its control terminal is connected to the output terminal of the second inverter, its inverting control terminal is connected to the input terminal of the second inverter, the second input terminal of the channel arbitration output unit is connected to the first node, and the second terminal of the second resistor is connected to reference ground.

[0014] Optionally, the first delay sub-circuit includes a third inverter, a first delay sub-module, and a fourth inverter. The input terminal of the third inverter receives the first input signal, and its output terminal is connected to the input terminal of the first delay sub-module. The output terminal of the first delay sub-module is connected to the input terminal of the fourth inverter, and the output terminal of the fourth inverter is connected to the clock terminal of the first flip-flop.

[0015] and / or

[0016] The second delay sub-circuit includes a fifth inverter, a second delay sub-module, and a sixth inverter. The input terminal of the fifth inverter receives the second input signal, and its output terminal is connected to the input terminal of the second delay sub-module. The output terminal of the second delay sub-module is connected to the input terminal of the sixth inverter, and the output terminal of the sixth inverter is connected to the clock terminal of the second flip-flop.

[0017] Optionally, the channel arbitration output unit includes a timing arbitration sub-circuit and a channel selection sub-circuit; the first input terminal of the timing arbitration sub-circuit is connected to the first node, its second input terminal is connected to the second node, its third input terminal is connected to the output terminal of the channel reset module, and its output terminal is connected to the fifth input terminal of the channel selection sub-circuit, and is used to output a pulse signal when the rising edge of either the first input signal or the second input signal arrives; the first input terminal of the channel selection sub-circuit receives the first input signal, its second input terminal receives the second input signal, its third input terminal is connected to the first node, its fourth input terminal is connected to the second node, and its output terminal is used to output the first of the rising edges of the first input signal and the second input signal.

[0018] Optionally, the timing arbitration sub-circuit includes a seventh inverter, a first AND gate, an eighth inverter, a second AND gate, and a third AND gate. The input of the seventh inverter is connected to the first node, and its output is connected to the first input of the first AND gate. The second input of the first AND gate receives the reset signal, and its output is connected to the first input of the third AND gate. The input of the eighth inverter is connected to the second node, and its output is connected to the first input of the second AND gate. The second input of the second AND gate receives the reset signal, and its output is connected to the second input of the third AND gate. The output of the third AND gate is connected to the fifth input of the channel selection sub-circuit and is used to output a pulse signal when the rising edge of either the first input signal or the second input signal arrives.

[0019] Optionally, the channel selection sub-circuit includes a fourth AND gate, a fifth AND gate, and a second OR gate. The first input of the fourth AND gate receives the first input signal, its second input is connected to the first node, and its output is connected to the first input of the second OR gate. The first input of the fifth AND gate is connected to the second node, its second input receives the second input signal, and its output is connected to the second input of the second OR gate. The third input of the second OR gate is connected to the output of the timing arbitration sub-circuit, and its output outputs the first of the rising edges of the first input signal and the second input signal.

[0020] To achieve the above objectives, the present invention also provides a chip, wherein the chip integrates the edge timing arbitration and channel selection circuit described in any of the above claims.

[0021] To achieve the above objectives, the present invention also provides an electronic device comprising the edge timing arbitration and channel selection circuit described in any of the preceding claims or the aforementioned chip.

[0022] Compared with the prior art, the edge timing arbitration and channel selection circuit, chip, and electronic device provided by the present invention have the following beneficial effects: The edge timing arbitration and channel selection circuit provided by the present invention allows the channel reset module to output a reset signal when the rising edge of any input signal received by all the channel selection execution modules arrives, thereby enabling the edge timing arbitration and channel selection circuit provided by the present invention to support cycle-by-cycle detection; furthermore, each of the channel selection execution modules can support real-time arbitration and selection of two channels of input signals, thus allowing the number of channel selection execution modules to be reasonably set according to the number of input signals to achieve real-time arbitration and selection of multi-channel input signals; and further still, the channel arbitration output unit can, according to the first input... The system selects the input signal, the second input signal, the first intermediate signal and the second intermediate signal output by the first channel selection output unit and the second channel selection output unit respectively, and the input signal of the channel selection execution module where the reset signal is output, and the rising edge of these signals arrives first. This effectively achieves real-time arbitration and selection of multi-channel input signals. Furthermore, the edge-timing arbitration and channel selection circuit provided by this invention adopts a design that includes a channel reset module, a channel selection execution module comprising a first channel selection output unit, a second channel selection output unit, and a channel arbitration output unit. This design is simple, easy to implement, and has strong anti-interference capabilities. Moreover, by using logic gates, flip-flops, and resistors to implement this invention, the timing arbitration accuracy of this invention can be significantly improved.

[0023] Since the chip and electronic device provided by this invention belong to the same inventive concept as the edge timing arbitration and channel selection circuit provided by this invention, the chip and electronic device provided by this invention have at least all the above-mentioned advantages of the edge timing arbitration and channel selection circuit provided by this invention. To avoid redundancy, they will not be described in detail here. Attached Figure Description

[0024] Figure 1 This is a block diagram of an edge timing arbitration and channel selection circuit in the prior art.

[0025] Figure 2 for Figure 1 The diagram shows a topology of the edge timing arbitration and channel selection circuit in one specific example.

[0026] Figure 3 For input to Figure 2 The waveform diagram of the two signals of the edge timing arbitration and channel selection circuit is shown.

[0027] Figure 4 This is a block diagram of an edge timing arbitration and channel selection circuit provided in one embodiment of the present invention.

[0028] Figure 5 This is a block diagram of the channel selection execution module of the edge timing arbitration and channel selection circuit provided by the present invention in one specific example.

[0029] Figure 6 for Figure 5 A schematic diagram of the circuit topology of the middle channel selection execution module in a specific example.

[0030] Figure 7 This is a block diagram illustrating the edge timing arbitration and channel selection circuit provided by the present invention for arbitration and channel selection of four-channel input signals.

[0031] Figure 8 To adopt Figure 7 The timing diagram of the timing arbitration and channel selection signals in one specific example of the edge timing arbitration and channel selection circuit is shown.

[0032] The reference numerals in the attached figures are explained as follows:

[0033] Channel reset module-100, first OR gate-110; Channel selection execution module-200, first channel selection output unit-210, first delay sub-circuit-211, third inverter-2111, first delay sub-module-2112, fourth inverter-2113, first flip-flop-212, first transmission gate-SW1, first inverter-213, first resistor-R1; Second channel selection output unit-220, second delay sub-circuit-221, fifth inverter-2211, second delay sub-module-2212, sixth inverter-2213, second flip-flop-222, second transmission gate-SW2; Second inverter-223, second resistor-R2, channel arbitration output unit-230, timing arbitration sub-circuit-231, seventh inverter-2311, first AND gate-2312, eighth inverter-2313, second AND gate-2314, third AND gate-2315; channel selection sub-circuit-232, fourth AND gate-2321, fifth AND gate-2322, second OR gate-2323; first input signal-IN1, second input signal-IN2, reset signal-RST; first node-N1, second node-N2, third node-N3, fourth node-N4, fifth node-N5, sixth node-N6. Detailed Implementation

[0034] To make the objectives, advantages, and features of the present invention clearer, the edge timing arbitration and channel selection circuit, chip, and electronic device proposed by the present invention will be further described in detail below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise scales, used only to facilitate and clearly illustrate the objectives of the embodiments of the present invention. It should be understood that the drawings do not necessarily show the specific structure of the invention to scale, and the illustrative features used to illustrate certain principles of the invention in the drawings are also drawn in a slightly simplified manner. Specific design features of the invention disclosed herein, including, for example, specific dimensions, orientations, positions, and shapes, will be determined in part by the specific application and environment in which they are used. Furthermore, in the embodiments described below, the same reference numerals are sometimes used across different drawings to denote the same parts or parts having the same function, omitting repeated descriptions. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings. Where appropriate, these terms used thus can be replaced.

[0035] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0036] It should be understood that when a component is referred to as "connected," "connected to," or "coupled to" other components, it may be directly connected to other components, or there may be intermediary components. Conversely, when a component is referred to as "directly connected" or "directly connected to" other components, there are no intermediary components.

[0037] The core idea of ​​this invention is to provide an edge timing arbitration and channel selection circuit, chip, and electronic device. This invention not only supports cycle-by-cycle edge timing detection and real-time arbitration and gating of multiple channels with strong anti-interference capability, but also has a simple structure and is easy to implement.

[0038] To achieve the above-mentioned goals, one embodiment of the present invention provides an edge timing arbitration and channel selection circuit. For an example, please refer to... Figure 4 and Figure 5 ,in, Figure 4 A block diagram of an edge timing arbitration and channel selection circuit provided in one embodiment of the present invention; Figure 5 This is a block diagram illustrating the channel selection execution module of the edge timing arbitration and channel selection circuit provided by the present invention in one specific example. Figure 4As can be seen, the edge timing arbitration and channel selection circuit provided by the present invention includes a channel reset module 100 and one or more cascaded channel selection execution modules 200. Figure 4 (This is achieved through multiple cascaded channel selection execution modules: 1, 2, 3, 4, ..., 2n-1, 2n, ...). Further, from... Figure 5 Yes, each of the aforementioned channel selection execution modules 200 ( Figure 5 Example of a channel selection execution module 1 (from China and Israel) includes a first channel selection output unit 210 for receiving a first input signal IN1, a second channel selection output unit 220 for receiving a second input signal IN2, and a channel arbitration output unit 230; the first input signal IN1 and the second input signal IN2 are pulse signals with rising edges at different timings (see [reference]). Figure 8 (Adaptive understanding). Furthermore, the channel reset module 100 is configured to output a reset signal RST when the rising edge of any input signal received by all the channel selection execution modules 200 arrives, so that the first channel selection output unit 210 outputs a first intermediate signal and the second channel selection output unit 220 outputs a second intermediate signal; and when the rising edge of the first input signal IN1 precedes the rising edge of the second input signal IN2, the first intermediate signal is high and the second intermediate signal is low; when the rising edge of the second input signal IN2 precedes the rising edge of the first input signal IN1, the first intermediate signal is low and the second intermediate signal is high; the channel arbitration output unit 230, coupled to the first channel selection output unit 210 and the second channel selection output unit 220 respectively at the first node N1 and the second node N2, is configured to output one of the first input signal IN1 and the second input signal IN2 whose rising edge arrives first, based on the first input signal IN1, the second input signal IN2, the first intermediate signal, the second intermediate signal, and the reset signal RST.

[0039] The edge timing arbitration and channel selection circuit provided by this invention allows the channel reset module 100 to output a reset signal RST when the rising edge of any input signal received by all the channel selection execution modules 200 arrives, thereby enabling the edge timing arbitration and channel selection circuit provided by this invention to support cycle-by-cycle detection. Furthermore, each of the channel selection execution modules 200 can support real-time arbitration and selection of two channels of input signals. Therefore, the number of channel selection execution modules 200 can be reasonably set according to the number of input signals to achieve real-time arbitration and selection of multi-channel input signals. Further still, the channel arbitration output unit 230 can output a reset signal RST based on the first input signal IN1, the second input signal IN2, and the first channel selection output unit... The rising edge of the first intermediate signal, the second intermediate signal, and the reset signal RST output from the first channel selection output unit 210 and the second channel selection output unit 220, respectively, is the first to arrive in the input signal of the channel selection execution module 200. This effectively achieves real-time arbitration and selection of multi-channel input signals. Furthermore, the edge-timing arbitration and channel selection circuit provided by this invention adopts a design of channel reset module 100, channel selection execution module 200 including first channel selection output unit 210, second channel selection output unit 220, and channel arbitration output unit 230. This design is simple, easy to implement, and has strong anti-interference capabilities. Moreover, by using logic gates, flip-flops, and resistors to implement this invention, the timing arbitration accuracy of this invention can be significantly improved.

[0040] It should be noted that those skilled in the art should understand that the present invention does not limit the number of the channel selection execution modules 200, and the number should be reasonably set according to actual needs when implementing the present invention. For example, when only arbitration of the input signals of two channels is required, only one channel selection execution module 200 can be used to implement the edge timing arbitration and channel selection circuit provided by the present invention; when arbitration of the input signals of more than two channels is required, multiple cascaded channel selection execution modules 200 can be used to implement the edge timing arbitration and channel selection circuit provided by the present invention.

[0041] It should be noted that the edge timing arbitration and channel selection circuit provided by this invention does not limit its application scenarios or uses in any way. The core idea of ​​this invention is to accurately capture the instantaneous transitions of multiple input signals from low to high within the clock domain of the system (such as inside the chip) and output a narrow pulse of a single clock cycle, thoroughly distinguishing between "level continuity" and "transition events". For example, the edge timing arbitration and channel selection circuit provided by this invention can be applied to the reliability monitoring and protection of the entire life cycle of a chip, including but not limited to automotive-grade, industrial-grade, and high-reliability server chips. These chips typically integrate multiple temperature, voltage, and current sensors. By employing the edge timing arbitration and channel selection circuit provided in this invention, the rising edge triggered by the sensor threshold can be detected cycle by cycle. When abnormal states such as over-temperature, over-voltage, under-voltage, or clock loss are detected, protective actions such as clock frequency reduction, core shutdown, and power reset are immediately triggered. This effectively protects the related devices from damage and ensures safe operation. By using the edge timing arbitration and channel selection circuit provided in this invention, a cycle-by-cycle detection mechanism can be achieved to ensure nanosecond-level response, completely avoiding chip damage under harsh operating conditions and meeting the mandatory requirements of ISO 26262 ASIL-D level automotive-grade chips. For example, in some exemplary embodiments, the edge timing arbitration and channel selection circuit provided by this invention can be applied to the functional safety monitoring system of ASIL-D level automotive-grade MCUs / SoCs. By adopting this invention, not only can the rising edge of the clock, voltage, and temperature signals of each safety monitoring channel be detected cycle by cycle, ensuring that a full-state detection is completed in each cycle; but also, through multi-channel gating logic, hundreds of safety monitoring channels can be monitored in parallel. Once an anomaly occurs in a channel, the channel number is immediately locked, triggering the safety state machine to enter the fail-safe mode, which can well meet the highest level requirements of automotive-grade functional safety. In other exemplary embodiments, the edge timing arbitration and channel selection circuit provided by this invention can be applied to the multi-core power management and DVFS system of high-end server CPUs. By adopting this invention, not only can the rising edge of the clock of each CPU core be detected cycle by cycle, synchronously triggering the performance counter sampling, and calculating the core load cycle by cycle; but also, through multi-channel gating logic, the rising edge of the load signal of dozens of cores can be monitored in parallel, centrally scheduling the voltage and frequency of each core, realizing the coordinated DVFS management of the entire chip, and balancing peak performance and power consumption.

[0042] For example, please continue to see 4 and Figure 5 ,like Figure 4 As shown, in some exemplary embodiments, the edge timing arbitration and channel selection circuit includes a plurality of the channel selection execution modules 200. Figure 4The channel selection execution modules 200 are numbered 1, 2, 3, 4, ..., 2n-1, 2n, 12, 34, 1234, 3n, ..., and the number of channel selection execution modules 200 closer to the input side is twice that of the adjacent channel selection execution modules 200 closer to the output side; the first channel selection output unit 210 and the second channel selection output unit 220 of the channel selection execution module 200 closest to the input side are used to receive the input signal ( Figure 4 The input signals IN1, IN2, IN3, IN4, IN7, IN8, ..., IN(4n-1), IN4n) are used to receive the output signals of the channel selection execution module 200 at the intermediate level. The first channel selection output unit 210 and the second channel selection output unit 220 are respectively used to receive the output signals of the channel arbitration output units 230 of the two adjacent channel selection execution modules 200 corresponding to them in the previous stage (for example, ...). Figure 4 The outputs of channel selection execution modules 3 and 4 are used as the inputs of channel selection execution module 34. The channel arbitration output unit 230 of the channel selection execution module 200 closest to the output side is used to output the one with the first rising edge of all the input signals.

[0043] Therefore, the edge timing arbitration and channel selection circuit provided by the present invention, when having multiple channel selection execution modules 200, adopts a design method in which the number of channel selection execution modules 200 near the input side is twice that of the adjacent channel selection execution modules 200 near the output side, and adopts a cascaded connection of parallel and series connections. The logic is simple and easy to implement.

[0044] It should be noted that those skilled in the art should understand that Figure 4 The connection method shown is merely an illustrative example of a preferred embodiment and not a limitation of the present invention. The present invention does not impose any limitations on the cascading method of the multiple channel selection execution modules 200 or the number of adjacent levels. When implementing the present invention, the cascading method of the multiple channel selection execution modules 200 can be reasonably set according to actual needs. For example, when there are 3 input signals, 2 cascaded channel selection execution modules 200 can be used.

[0045] For example, please see Figure 5 and Figure 6 ,in, Figure 6 for Figure 5 A schematic diagram of the circuit topology of the middle channel selection execution module in one specific example. (See diagram below.) Figure 6As shown, in some exemplary embodiments, the channel reset module 100 includes a first OR gate 110. The input of the first OR gate 110 is used to receive all the input signals, and its output is connected to the reset terminals of the first channel selection output unit 210, the second channel selection output unit 220, and the first input terminal of the channel arbitration output unit 230 of all the channel selection execution modules 200. Therefore, by using the first OR gate 110 to implement the channel reset module 100, a reset signal RST can be output when the rising edge of any of the input signals arrives. This enables the edge timing arbitration and channel selection circuit provided by the present invention to support cycle-by-cycle detection, while also having the advantages of high detection accuracy and ease of implementation.

[0046] It should be understood that the use of the first OR gate 110 to implement the channel reset module 100 is merely an exemplary description of a preferred embodiment and not a limitation of the present invention. Any logic circuit that can output a reset signal RST to reset all the first channel selection output units 210 and the second channel selection output units 220 of the channel selection execution module 200 when the rising edge of any of the input signals arrives is acceptable, thereby enabling the edge timing arbitration and channel selection circuit to support cycle-by-cycle detection. For example, in other embodiments, the channel reset module 100 can also be implemented using designs including but not limited to NOR gates + NOT gates and multiple NAND gates, which will not be exemplified here.

[0047] For example, please continue to see Figure 5 and Figure 6 ,like Figure 5 and Figure 6 As shown, in some exemplary embodiments, the first channel selection output unit 210 includes a first delay sub-circuit 211 ( Figure 6 (Using gray area for illustration), first flip-flop 212, first transmission gate SW1, first inverter 213 and first resistor R1; the second channel selection output unit 220 includes a second delay sub-circuit 221 ( Figure 6(Using green area for illustration), second flip-flop 222, second transmission gate SW2, second inverter 223, and second resistor R2. Further, the input terminal of the first delay sub-circuit 211 receives the first input signal IN1, its output terminal is connected to the clock terminal CP of the first flip-flop 212, the reset terminal CDN of the first flip-flop 212 is connected to the output terminal of the channel reset module 100, its data input terminal D is connected to its inverted output terminal QN, and its output terminal Q is connected to the input terminal of the first transmission gate SW1; the output terminal of the first transmission gate SW1 is connected to the first terminal of the first resistor R1, the second input terminal of the channel arbitration output unit 230 is connected to the first node N1, its control terminal is connected to the output terminal of the first inverter 213, its inverting control terminal is connected to the input terminal of the first inverter 213, the third input terminal of the channel arbitration output unit 230 is connected to the second node N2, and the second terminal of the first resistor R1 is connected to reference ground. The input terminal of the second delay sub-circuit 221 receives the second input signal IN2, and its output terminal is connected to the clock terminal CP of the second flip-flop 222. The reset terminal CDN of the second flip-flop 222 is connected to the output terminal of the channel reset module 100, its data input terminal D is connected to its inverting output terminal QN, and its output terminal Q is connected to the input terminal of the second transmission gate SW2. The output terminal of the second transmission gate SW2 is connected to the first terminal of the second resistor R2, the third input terminal of the channel arbitration output unit 230 is connected to the second node N2, its control terminal is connected to the output terminal of the second inverter 223, its inverting control terminal is connected to the input terminal of the second inverter 223, the second input terminal of the channel arbitration output unit 230 is connected to the first node N1, and the second terminal of the second resistor R2 is connected to the reference ground.

[0048] Therefore, the edge timing arbitration and channel selection circuit provided by the present invention, in which the first channel selection output unit 210 and the second channel selection output unit 220 adopt the same circuit structure design, can not only further improve the timing arbitration accuracy of the present invention, but also be easy to implement; furthermore, the first channel selection output unit 210 and the second channel selection output unit 220 both adopt the design of flip-flops, transmission gates, inverters and resistors, which not only have strong anti-noise interference ability, but also have simple structure and are easy to implement.

[0049] It should be noted that, Figure 6The design of the first channel selection output unit 210 and the second channel selection output unit 220 using the same circuit structure shown is merely an illustrative example of a preferred embodiment and not a limitation of the present invention. In other embodiments, the first channel selection output unit 210 and the second channel selection output unit 220 can also be implemented using different circuit structures, as long as the first channel selection output unit 210 outputs the first intermediate signal at a high level and the second channel selection output unit 220 outputs the second intermediate signal at a low level when the rising edge of the first input signal IN1 precedes the rising edge of the second input signal IN2 after receiving the reset signal RST; and the first channel selection output unit 210 outputs the first intermediate signal at a low level and the second channel selection output unit 220 outputs the second intermediate signal at a high level when the rising edge of the second input signal IN2 precedes the rising edge of the first input signal IN1.

[0050] It should also be noted that the present invention does not limit the type of the first trigger 212 and the second trigger 222. For example, in some preferred embodiments, the first trigger 212 and the second trigger 222 are preferably D triggers.

[0051] For example, in some exemplary embodiments, the initial potentials of the first flip-flop 212 and the second flip-flop 222 are high. Therefore, by setting the initial potentials of the first flip-flop 212 and the second flip-flop 222 to high, it can be ensured that the system starts from a known and definite state. On the one hand, this avoids logic errors caused by uncertain initial states, thereby improving the reliability of the invention; on the other hand, compared to resetting first and then setting high, it can also reduce delays, thereby further improving the timing arbitration accuracy of the invention.

[0052] It should be noted that those skilled in the art should understand that the present invention does not impose excessive limitations on the specific values ​​of the initial potentials of the first flip-flop 212 and the second flip-flop 222. When implementing the present invention, these values ​​can be reasonably set according to actual needs. For example, in some exemplary embodiments, the initial potentials of the first flip-flop 212 and the second flip-flop 222 can be 5V.

[0053] For example, please continue to see Figure 6 ,like Figure 6As shown, in some exemplary embodiments, the first delay sub-circuit 211 includes a third inverter 2111, a first delay sub-module 2112, and a fourth inverter 2113. The input terminal of the third inverter 2111 receives the first input signal IN1, and its output terminal is connected to the input terminal of the first delay sub-module 2112. The output terminal of the first delay sub-module 2112 is connected to the input terminal of the fourth inverter 2113, and the output terminal of the fourth inverter 2113 is connected to the clock terminal CP of the first flip-flop 212. Similarly, the second delay sub-circuit 221 includes a fifth inverter 2211, a second delay sub-module 2212, and a sixth inverter 2213. The input terminal of the fifth inverter 2211 receives the second input signal IN2, and its output terminal is connected to the input terminal of the second delay sub-module 2212. The output terminal of the second delay sub-module 2212 is connected to the input terminal of the sixth inverter 2213, and the output terminal of the sixth inverter 2213 is connected to the clock terminal CP of the second flip-flop 222. Thus, the first delay sub-circuit 211 ensures that the first flip-flop 212 receives the first input signal IN1 only after receiving the reset signal RST, and the second delay sub-circuit 221 ensures that the second flip-flop 222 receives the second input signal IN2 only after receiving the reset signal RST, thereby effectively ensuring the normal operation of the first flip-flop 212 and the second flip-flop 222. Furthermore, by employing an inverter and a delay submodule design, the accuracy of the first input signal IN1 input to the first flip-flop 212 and the second input signal IN2 input to the second flip-flop 222 can be further improved.

[0054] It should be noted that, Figure 6 The design of the first delay sub-circuit 211 and the second delay sub-circuit 221 using the same circuit structure shown is merely an illustrative example of a preferred embodiment and not a limitation of the invention. In other embodiments, the first delay sub-circuit 211 and the second delay sub-circuit 221 can also be implemented using different circuit structures, as long as it can be ensured that the delay duration of the first delay sub-circuit 211 for the first input signal IN1 is the same as the delay duration of the second delay sub-circuit 221 for the second input signal IN2. It should also be noted that, although Figure 6The first delay submodule 2112 and the second delay submodule 2212 in the example adopt an RC delay topology structure of resistor + capacitor. However, it is obvious that this is only an illustrative example of a preferred embodiment and not a limitation of the invention. For example, in other embodiments, the first delay submodule 2112 and / or the second delay submodule 2212 may also be implemented using methods including but not limited to timers. In addition, the present invention does not limit the delay duration of the first delay subcircuit 211 and the second delay subcircuit 221, which can be reasonably set according to actual needs when implementing the present invention.

[0055] For example, please continue to see Figure 5 and Figure 6 ,like Figure 5 and Figure 6 As shown, in some exemplary embodiments, the channel arbitration output unit 230 includes a timing arbitration sub-circuit 231 ( Figure 6 (Using blue area for illustration) and channel selection sub-circuit 232 ( Figure 6 (The yellow area is used for illustration); the first input terminal of the timing arbitration sub-circuit 231 is connected to the first node N1, its second input terminal is connected to the second node N2, and its third input terminal is connected to the output terminal of the channel reset module 100. Figure 5 The reset signal RST is shown in the diagram. Its output terminal is connected to the fifth input terminal of the channel selection sub-circuit 232 and is used to output a pulse signal CH when the rising edge of either the first input signal IN1 or the second input signal IN2 arrives. The first input terminal of the channel selection sub-circuit 232 receives the first input signal IN1, its second input terminal receives the second input signal IN2, its third input terminal is connected to the first node N1, its fourth input terminal is connected to the second node N2, and its output terminal is used to output the first of the rising edges of the first input signal IN1 and the second input signal IN2.

[0056] Therefore, the channel arbitration output unit 230 is implemented using the timing arbitration sub-circuit 231 and the channel selection sub-circuit 232. On the one hand, the pulse signal CH obtained by the timing arbitration sub-circuit 231 can compensate for the delay of the first input signal IN1 by the first delay sub-circuit 211 in the first channel selection output unit 210 and the delay of the second input signal IN2 by the second delay sub-circuit 221 in the second channel selection output unit 220, so that the channel arbitration output unit 230 can output a complete high-level signal of one of the first input signal IN1 and the second input signal IN2 whose rising edge arrives first. On the other hand, it also has the advantages of clear logic and ease of implementation.

[0057] For example, please continue to see Figure 6 ,like Figure 6 As shown, in some exemplary embodiments, the timing arbitration sub-circuit 231 includes a seventh inverter 2311, a first AND gate 2312, an eighth inverter 2313, a second AND gate 2314, and a third AND gate 2315. The input of the seventh inverter 2311 is connected to the first node N1, and its output is connected to the first input of the first AND gate 2312. The second input of the first AND gate 2312 receives the reset signal RST, and its output is connected to the first input of the third AND gate 2315. The input of the eighth inverter 2313 is connected to the second node N2, and its output is connected to the first input of the second AND gate 2314. The second input of the second AND gate 2314 receives the reset signal RST, and its output is connected to the second input of the third AND gate 2315. The output of the third AND gate 2315 is connected to the fifth input of the channel selection sub-circuit 232 and is used to output a pulse signal CH when the rising edge of either the first input signal IN1 or the second input signal IN2 arrives.

[0058] Therefore, the design method of using the seventh inverter 2311, the first AND gate 2312, the eighth inverter 2313, the second AND gate 2314, and the third AND gate 2315 to implement the timing arbitration sub-circuit 231 not only has strong anti-noise interference capability, but also has simple logic and is easy to implement.

[0059] It should be noted that those skilled in the art will understand that the use of the seventh inverter 2311, the first AND gate 2312, the eighth inverter 2313, the second AND gate 2314, and the third AND gate 2315 to implement the timing arbitration sub-circuit 231 is merely an illustrative example of a preferred embodiment and not a limitation of the present invention. The present invention does not impose excessive limitations on the specific implementation of the timing arbitration sub-circuit 231; the timing arbitration sub-circuit 231 only needs to output a pulse signal CH when the rising edge of either the first input signal IN1 or the second input signal IN2 arrives. For example, in other embodiments, inverters, multiplexers, or NOR gates can also be used to implement the timing arbitration sub-circuit 231; these will not be exemplified here.

[0060] For example, please continue to see Figure 6 ,like Figure 6As shown, in some exemplary embodiments, the channel selection sub-circuit 232 includes a fourth AND gate 2321, a fifth AND gate 2322, and a second OR gate 2323. The first input of the fourth AND gate 2321 receives the first input signal IN1, its second input is connected to the first node N1, and its output is connected to the first input of the second OR gate 2323. The first input of the fifth AND gate 2322 is connected to the second node N2, its second input receives the second input signal IN2, and its output is connected to the second input of the second OR gate 2323. The third input of the second OR gate 2323 is connected to the output of the timing arbitration sub-circuit 231, and its output outputs the first of the rising edges of the first input signal IN1 and the second input signal IN2.

[0061] Therefore, by using the fourth AND gate 2321, the fifth AND gate 2322 and the second OR gate 2323 to implement the channel selection sub-circuit 232, the design not only has strong anti-noise interference capability, but also has simple logic and is easy to implement.

[0062] To facilitate a better understanding of this invention, the following section will use a four-channel input signal as an example. Figure 6 , Figure 7 as well as Figure 8 The working principle of the present invention will be explained, for example, please continue to refer to Figure 6 , Figure 7 and Figure 8 ,in, Figure 7 This is a block diagram illustrating the edge timing arbitration and channel selection circuit provided by the present invention for arbitration and channel selection of four-channel input signals. Figure 8 To adopt Figure 7 The timing diagram of the timing arbitration and channel selection signals in one specific example of the edge timing arbitration and channel selection circuit is shown. Figure 8 IN1, IN2, IN3, and IN4 represent the waveforms of the first input signal IN1, the second input signal IN2, the third input signal IN3, and the fourth input signal IN4, respectively. Figure 8 OUT12 in the diagram represents the timing waveform of the first input signal IN1, which arrives first at its rising edge among the first input signal IN1 and the second input signal IN2. Figure 8 OUT34 in the diagram represents the timing waveform of the third input signal IN3, which arrives first among the third input signal IN3 and the fourth input signal IN4. Figure 8 OUT34 in the first input signal IN1 to make the timing waveform of the input signal IN4 the first one to arrive at the rising edge in each timing cycle.

[0063] First, such as Figure 7As shown, the edge timing arbitration and channel selection circuit in this example has three channel selection execution modules 12, 34, and 1234 to implement edge timing arbitration and channel selection output for input signals IN1, IN2, IN3, and IN4. Specifically, for input signals IN1 and IN2, the channel selection signal output by channel selection execution module 12 is OUT12; for input signals IN3 and IN4, the channel selection signal output by channel selection execution module 34 is OUT34. Channel selection signals OUT12 and OUT34 serve as the first and second input signals of channel selection execution module 1234, respectively, to continue timing arbitration and channel selection, resulting in the final timing arbitration and channel selection signal 1234 for input signals IN1, IN2, IN3, and IN4. To avoid redundancy, the following text will combine... Figure 6 The following explanation uses the edge timing arbitration and channel selection output of input signals IN1 and IN2 as an example.

[0064] (1) Please see Figure 7 and Figure 6 The four-channel input signal reset module 100 (i.e., the first OR gate 110) is configured to receive IN1, IN2, IN3, and IN4 input signals. Figure 6 The channel reset module 100 (input signals IN3 and IN4 are not shown) outputs a reset signal RST to reset the first flip-flop 212 of the first channel selection output unit 210 and the second flip-flop 222 of the second channel selection output unit 220. When the reset signal RST goes high, the reset state of the first flip-flop 212 and the second flip-flop 222 is released, so that the first channel selection output unit 210 and the second channel selection output unit 220 work together to output the input signal whose rising edge arrives first.

[0065] (2) For example Figure 6 As shown, due to the presence of weak pull-down resistors R1 and R2, the initial potentials of the first node N1 and the second node N2 are 0V. The first transmission gate SW1 and the second transmission gate SW2 are both in the on state. The potentials of the third node N3 and the fifth node N5 are also 0V. The potential of the inverting output terminal QN of the first flip-flop 212 and the second flip-flop 222 is 5V, that is, the initial potential is high.

[0066] (3) Please continue to see Figure 6When the rising edge of the voltage signal of the first delayed signal IN1_DLY after the input signal IN1 passes through the first delayed sub-circuit 211 arrives, the first flip-flop 212 samples the voltage at the D terminal, the potential of the third node N3 is pulled high, and after passing through the first transmission gate SW1, the potential of the first intermediate signal output at the first node N1 is pulled high. At the same time, the second transmission gate SW2 is closed. Because of the presence of the weak pull-down second resistor R2, the potential of the second intermediate signal output by the second channel selection output unit 220 at the second node N2 is 0V. After passing through the seventh inverter 2313, the potential of the sixth node N6 is pulled high. The potential of the output signal IN2_CH of the second AND gate 2314 is the potential of the reset signal RST; at the same time, the output signal IN1_CH of the first AND gate 2312 is the result of the logical AND of the reset signal RST and the output signal of the seventh inverter 2311 at the fourth node N4 (i.e., the inverted signal of the first intermediate signal output by the first channel selection output unit 210 at the first node N1). Because the rising edge of the reset signal RST arrives before the rising edge of the first delay signal IN1_DLY, the output signal IN1_CH of the first AND gate 2312 is a positive pulse signal CH.

[0067] (4) Please continue to see Figure 6 and Figure 8 Taking the first input signal IN1 and the second input signal IN2 as examples, the reset signal RST is the input signals IN1, IN2, IN3 and IN4 passed through the first OR gate 110 ( Figure 6 The signals after the input signals IN3 and IN4 are not shown. The rising edge of the voltage of the first node N1 is determined by the rising edge of the first delayed signal IN1_DLY. The falling edge of the first input signal IN1 is no later than the falling edge of the reset signal RST, which causes the falling edge of the first intermediate signal to be determined by the reset signal RST. After processing by the fourth AND gate 2321, the rising edge of the signal OUT1 output by the fourth AND gate 2321 is determined by the rising edge of the first delayed signal IN1_DLY, and its falling edge is determined by the falling edge of the first input signal IN1. Since the second transmission gate SW2 is not turned on, the potential of the second node N2 is 0V, and the signal OUT2 output by the fifth AND gate 2322 is 0V. The signals CH, OUT1 and OUT2 are output by the second OR gate 2323 after selecting the input signal IN1.

[0068] (5) Similarly, for input signals IN3 and IN4, the channel selection signal OUT34 output by the channel selection execution module 34 is the input signal IN3; repeating the above logic, the channel selection execution module 1234 continues to perform timing arbitration and channel selection on the timing arbitration and channel selection signals OUT12 and OUT34 to obtain the channel selection signal OUT1234, as follows: Figure 8 As shown.

[0069] Another embodiment of the present invention provides a chip on which the edge timing arbitration and channel selection circuit described in any of the above embodiments is integrated.

[0070] It is understood that the present invention does not limit the manufacturing process of the chip. For example, the chip may be, but is not limited to, a 180nm chip, a 130nm chip, and a 90nm chip.

[0071] Another embodiment of the present invention provides an electronic device, the electronic device including the edge timing arbitration and channel selection circuit as described in any of the above embodiments or the chip as described in the above embodiments.

[0072] Since the chip and electronic device provided by this invention belong to the same inventive concept as the edge timing arbitration and channel selection circuit provided by this invention, the chip and electronic device provided by this invention have at least all the above-mentioned advantages of the edge timing arbitration and channel selection circuit provided by this invention. To avoid redundancy, they will not be described in detail here.

[0073] It is understood that the electronic device provided in this embodiment, in addition to at least a processor and memory, may further include display components, communication components, sensor components, power supply components, multimedia components, and input / output interfaces, depending on actual needs. The display components, memory, communication components, sensor components, power supply components, multimedia components, and input / output interfaces are all connected to the processor. The memory can be static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, etc. The processor can be a central processing unit (CPU), graphics processing unit (GPU), field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), digital signal processing (DSP) chip, etc. Other communication components, sensor components, power supply components, multimedia components, etc., can all be implemented using general-purpose components; due to space limitations, they will not be described in detail here. For more detailed information, please refer to the relevant technical adaptation understanding known to those skilled in the art.

[0074] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0075] Therefore, compared with the prior art, the edge timing arbitration and channel selection circuit, chip, and electronic device provided by the present invention have the following beneficial effects: The edge timing arbitration and channel selection circuit provided by the present invention allows the channel reset module to output a reset signal when the rising edge of any input signal received by all the channel selection execution modules arrives, thereby enabling the edge timing arbitration and channel selection circuit provided by the present invention to support cycle-by-cycle detection; furthermore, each of the channel selection execution modules can support real-time arbitration and selection of two channels of input signals, thus allowing the number of channel selection execution modules to be reasonably set according to the number of input signals to achieve real-time arbitration and selection of multi-channel input signals; and further still, the channel arbitration output unit can, according to the... The rising edge of the first input signal, the second input signal, the first intermediate signal and the second intermediate signal output by the first channel selection output unit and the second channel selection output unit respectively, and the input signal of the channel selection execution module where the reset signal is output arrive first, thereby effectively realizing real-time arbitration and selection of multi-channel input signals. Furthermore, the edge-timing arbitration and channel selection circuit provided by the present invention adopts a design of a channel reset module, a channel selection execution module including a first channel selection output unit, a second channel selection output unit and a channel arbitration output unit, which is simple in structure, easy to implement and has strong anti-interference ability. Furthermore, by using logic gates, flip-flops and resistors to implement the present invention, the timing arbitration accuracy of the present invention can be significantly improved.

[0076] In summary, the above embodiments have provided detailed descriptions of different configurations of the edge timing arbitration and channel selection circuit, chip, and electronic device provided by the present invention. Of course, the above descriptions are only descriptions of preferred embodiments of the present invention and are not intended to limit the scope of the present invention in any way. The present invention includes but is not limited to the configurations listed in the above embodiments. Those skilled in the art can draw inferences from the above embodiments. Any changes or modifications made by those skilled in the art based on the above disclosure are within the protection scope of the claims.

Claims

1. An edge-timing arbitration and channel selection circuit, characterized in that, The system includes a channel reset module and one or more cascaded channel selection execution modules; each of the channel selection execution modules includes a first channel selection output unit for receiving a first input signal, a second channel selection output unit for receiving a second input signal, and a channel arbitration output unit; the first input signal and the second input signal are pulse signals with rising edges at different timings; The channel reset module is configured to output a reset signal when the rising edge of any input signal received by all the channel selection execution modules arrives, so that the first channel selection output unit outputs a first intermediate signal and the second channel selection output unit outputs a second intermediate signal; and when the rising edge of the first input signal precedes the rising edge of the second input signal, the first intermediate signal is high and the second intermediate signal is low; when the rising edge of the second input signal precedes the rising edge of the first input signal, the first intermediate signal is low and the second intermediate signal is high. The channel arbitration output unit is coupled to the first channel selection output unit and the second channel selection output unit to the first node and the second node, respectively, and is configured to output one of the first input signal and the second input signal whose rising edge arrives first, based on the first input signal, the second input signal, the first intermediate signal, the second intermediate signal and the reset signal.

2. The edge timing arbitration and channel selection circuit according to claim 1, characterized in that, The edge timing arbitration and channel selection circuit includes multiple channel selection execution modules, and the number of channel selection execution modules near the input side is twice that of the adjacent channel selection execution modules near the output side. The first channel selection output unit and the second channel selection output unit of the channel selection execution module closest to the input side are used to receive the input signal. The first channel selection output unit and the second channel selection output unit of the channel selection execution module located in the middle stage are respectively used to receive the output signals of the channel arbitration output units of the two corresponding channel selection execution modules of the adjacent previous stage. The channel arbitration output unit of the channel selection execution module closest to the output side is used to output the one with the first rising edge among all the input signals.

3. The edge timing arbitration and channel selection circuit according to claim 1, characterized in that, The channel reset module includes a first OR gate, the input of which is used to receive all the input signals, and its output is respectively connected to the reset terminal of the first channel selection output unit, the reset terminal of the second channel selection output unit, and the first input terminal of the channel arbitration output unit of all the channel selection execution modules.

4. The edge timing arbitration and channel selection circuit according to claim 1, characterized in that, The first channel selection output unit includes a first delay sub-circuit, a first flip-flop, a first transmission gate, a first inverter, and a first resistor; the second channel selection output unit includes a second delay sub-circuit, a second flip-flop, a second transmission gate, a second inverter, and a second resistor. The input terminal of the first delay sub-circuit receives the first input signal, its output terminal is connected to the clock terminal of the first flip-flop, the reset terminal of the first flip-flop is connected to the output terminal of the channel reset module, its data input terminal is connected to its inverting output terminal, and its output terminal is connected to the input terminal of the first transmission gate. The output terminal of the first transmission gate is connected to the first terminal of the first resistor, the second input terminal of the channel arbitration output unit is connected to the first node, its control terminal is connected to the output terminal of the first inverter, its inversion control terminal is connected to the input terminal of the first inverter, the third input terminal of the channel arbitration output unit is connected to the second node, and the second terminal of the first resistor is connected to the reference ground. The input terminal of the second delay sub-circuit receives the second input signal, its output terminal is connected to the clock terminal of the second flip-flop, the reset terminal of the second flip-flop is connected to the output terminal of the channel reset module, its data input terminal is connected to its inverting output terminal, and its output terminal is connected to the input terminal of the second transmission gate. The output terminal of the second transmission gate is connected to the first terminal of the second resistor, the third input terminal of the channel arbitration output unit is connected to the second node, its control terminal is connected to the output terminal of the second inverter, its inversion control terminal is connected to the input terminal of the second inverter, the second input terminal of the channel arbitration output unit is connected to the first node, and the second terminal of the second resistor is connected to the reference ground.

5. The edge timing arbitration and channel selection circuit according to claim 4, characterized in that, The first delay sub-circuit includes a third inverter, a first delay sub-module, and a fourth inverter. The input terminal of the third inverter receives the first input signal, and its output terminal is connected to the input terminal of the first delay sub-module. The output terminal of the first delay sub-module is connected to the input terminal of the fourth inverter, and the output terminal of the fourth inverter is connected to the clock terminal of the first flip-flop. and / or The second delay sub-circuit includes a fifth inverter, a second delay sub-module, and a sixth inverter. The input terminal of the fifth inverter receives the second input signal, and its output terminal is connected to the input terminal of the second delay sub-module. The output terminal of the second delay sub-module is connected to the input terminal of the sixth inverter, and the output terminal of the sixth inverter is connected to the clock terminal of the second flip-flop.

6. The edge timing arbitration and channel selection circuit according to claim 1, characterized in that, The channel arbitration output unit includes a timing arbitration sub-circuit and a channel selection sub-circuit. The first input terminal of the timing arbitration sub-circuit is connected to the first node, its second input terminal is connected to the second node, its third input terminal is connected to the output terminal of the channel reset module, and its output terminal is connected to the fifth input terminal of the channel selection sub-circuit. It is used to output a pulse signal when the rising edge of either the first input signal or the second input signal arrives. The first input terminal of the channel selection sub-circuit receives the first input signal, its second input terminal receives the second input signal, its third input terminal is connected to the first node, its fourth input terminal is connected to the second node, and its output terminal is used to output the first of the rising edges of the first input signal and the second input signal.

7. The edge timing arbitration and channel selection circuit according to claim 6, characterized in that, The timing arbitration sub-circuit includes a seventh inverter, a first AND gate, an eighth inverter, a second AND gate, and a third AND gate. The input of the seventh inverter is connected to the first node, and its output is connected to the first input of the first AND gate. The second input of the first AND gate receives the reset signal, and its output is connected to the first input of the third AND gate. The input of the eighth inverter is connected to the second node, and its output is connected to the first input of the second AND gate. The second input of the second AND gate receives the reset signal, and its output is connected to the second input of the third AND gate. The output of the third AND gate is connected to the fifth input of the channel selection sub-circuit and is used to output a pulse signal when the rising edge of either the first input signal or the second input signal arrives.

8. The edge timing arbitration and channel selection circuit according to claim 6, characterized in that, The channel selection sub-circuit includes a fourth AND gate, a fifth AND gate, and a second OR gate. The first input of the fourth AND gate receives the first input signal, its second input is connected to the first node, and its output is connected to the first input of the second OR gate. The first input of the fifth AND gate is connected to the second node, its second input receives the second input signal, and its output is connected to the second input of the second OR gate. The third input of the second OR gate is connected to the output of the timing arbitration sub-circuit, and its output outputs the first of the rising edges of the first input signal and the second input signal.

9. A chip, characterized in that, The chip integrates an edge timing arbitration and channel selection circuit as described in any one of claims 1 to 8.

10. An electronic device, characterized in that, The electronic device includes the edge timing arbitration and channel selection circuit as described in any one of claims 1 to 8 or the chip as described in claim 9.

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