A level conversion circuit and chip

Abstract

This invention provides a level conversion circuit and chip, belonging to the field of electronic circuit technology. The circuit includes: a pull-down control module, a pull-up control module, and an acceleration module. The pull-down control module is connected to the acceleration module via a first node group, and the acceleration module is connected to the pull-up control module via a second node group. The pull-down control module generates a first node voltage group on the first node group based on the input signal. The pull-up control module generates a second node voltage group on the second node group based on the first node voltage group. The acceleration module accelerates the output level conversion signal based on the first node voltage group and / or the second node voltage group. This invention can speed up the level switching speed, ensure accurate signal timing, and achieve stable and efficient voltage conversion.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a level conversion circuit and chip. Background Technology

[0002] Level conversion circuits are essential components in modern electronic design for cross-voltage domain communication. Their core function is to achieve signal compatibility between different voltage systems, ensuring stable communication and protecting equipment safety. With the significant increase in communication circuit speed and the drastic acceleration of signal edge rates, higher demands are placed on the conversion speed and accuracy of level conversion circuits.

[0003] Traditional level-shifting circuits typically control the switching of transistors via input signals to achieve signal conversion from a low-voltage domain to a high-voltage domain. However, in such traditional circuits, when the input signal flips, internal nodes need to charge from the reference ground voltage to a higher supply voltage, or discharge from the supply voltage to the reference ground voltage. Because the voltage changes during charging and discharging are large, typically full-swing, and the charging current is limited by the conduction characteristics of the transistors in the latch structure, the voltage changes at internal nodes are slow, thus limiting the overall circuit's switching speed. In high-speed clock signal applications, this switching delay can lead to signal timing errors, logic corruption, or even system failure, becoming a bottleneck restricting circuit performance improvement. Summary of the Invention

[0004] This invention provides a level conversion circuit and chip that can accelerate level switching speed, ensure accurate signal timing, and achieve stable and efficient voltage conversion.

[0005] In a first aspect, the present invention provides a level conversion circuit, including a pull-down control module, a pull-up control module, and an acceleration module; wherein the pull-down control module is connected to the acceleration module through a first node group, and the acceleration module is connected to the pull-up control module through a second node group; The pull-down control module is used to generate a first node voltage group on the first node group according to the input signal; The pull-up control module is used to generate a second node voltage group on the second node group according to the first node voltage group. The acceleration module is used to accelerate the output level conversion signal according to the first node voltage group and / or the second node voltage group.

[0006] In some embodiments, the first node group includes a first node and a second node, the second node group includes a third node and a fourth node, and the acceleration module includes a first acceleration unit and a second acceleration unit; wherein, the first acceleration unit is connected to the pull-down control module through the first node and to the pull-up control module through the third node; the second acceleration unit is connected to the pull-down control module through the second node and to the pull-up control module through the fourth node; The first acceleration unit is configured to clamp the voltage difference between the first node and the third node to a first preset threshold based on the voltages of the first node and the third node. The second acceleration unit is used to clamp the voltage difference between the second node and the fourth node to a second preset threshold based on the voltages of the second node and the fourth node.

[0007] In some embodiments, the pull-down control module includes a first pull-down control unit and a second pull-down control unit, and the first node voltage group includes a first voltage and a second voltage; wherein, a first terminal of the first pull-down control unit receives a first input signal, a first terminal of the second pull-down control unit receives a second input signal, a second terminal of the first pull-down control unit and a second terminal of the second pull-down control unit are connected to a first power supply, a third terminal of the first pull-down control unit is connected to a third terminal of the first acceleration unit through the first node, and a third terminal of the second pull-down control unit is connected to a third terminal of the second acceleration unit through the second node; The first pull-down control unit is configured to generate the first voltage at the first node under the action of the first power supply, based on the first input signal; or generate the second voltage at the first node under the action of the first acceleration unit. The second pull-down control unit is used to generate the first voltage at the second node under the action of the first power supply according to the second input signal; or to generate the second voltage at the second node under the action of the second acceleration unit; wherein the first input signal and the second input signal are inverses of each other.

[0008] In some embodiments, the pull-up control module includes a first pull-up control unit and a second pull-up control unit, and the second node voltage group includes a third voltage and a fourth voltage; wherein, the second terminals of the first pull-up control unit and the second pull-up control unit are connected to a second power supply, the first terminals of the first pull-up control unit, the second pull-up control unit, the first terminal of the first acceleration unit, and the first terminal of the second acceleration unit form a cross-coupled connection relationship, the third terminal of the first pull-up control unit is connected to the second terminal of the first acceleration unit through the third node, and the third terminal of the second pull-up control unit is connected to the second terminal of the second acceleration unit through the fourth node; The first pull-up control unit is used to generate the third voltage on the third node under the action of the second power supply, or to generate the fourth voltage on the third node under the action of the first acceleration unit, based on the first node voltage group. The second pull-up control unit is used to generate the third voltage at the fourth node under the action of the second power supply, based on the first node voltage group; or to generate the fourth voltage at the fourth node under the action of the second acceleration unit.

[0009] In some embodiments, the level conversion circuit further includes an output module, the input terminal of which is connected to the acceleration module; The output module is used to generate the level conversion signal based on the output voltage of the acceleration module.

[0010] In some embodiments, the output module includes a first output unit and a second output unit. The first output unit is connected to a first node in the first node group and a third node in the second node group, respectively. The second output unit is connected to a second node in the first node group and a fourth node in the second node group, respectively. The first output unit is configured to output a first level conversion signal based on the first node voltage group and the second node voltage group, and the second output unit is configured to output a second level conversion signal based on the first node voltage group and the second node voltage group; wherein the first level conversion signal and the second level conversion signal are inverses of each other.

[0011] In some embodiments, both the first output unit and the second output unit include a pull-up output transistor and a pull-down output transistor connected in series. The first end of the pull-up output tube is connected to the corresponding node in the second node group, the second end of the pull-up output tube is connected to the second power supply, the third end of the pull-up output tube is connected to the third end of the corresponding pull-down output tube, the first end of the pull-down output tube is connected to the corresponding node in the first node group, and the second end of the pull-down output tube is connected to the first power supply.

[0012] In some embodiments, both the first acceleration unit and the second acceleration unit include a preset number of switching transistors.

[0013] In some embodiments, the switching transistor is a PMOS transistor.

[0014] Secondly, the present invention also provides a chip including the level conversion circuit described in the first aspect.

[0015] This invention, through the introduction of an acceleration module, reduces the voltage swing of the first node group from full swing to partial swing, increasing the speed of voltage rise and fall, thereby significantly improving the circuit switching speed. Furthermore, it can be implemented with only a few additional components compared to traditional circuits, resulting in low cost and easy integration. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced one by one below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of a fast level switching circuit provided in an embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0019] Figure 1 This is a schematic diagram of a level conversion circuit provided in an embodiment of the present invention. Figure 1As shown, the level conversion circuit includes a pull-down control module 1, a pull-up control module 2, and an acceleration module 3. The pull-down control module 1 is connected to the acceleration module 3 through a first node group, and the acceleration module 3 is connected to the pull-up control module 2 through a second node group. The pull-down control module 1 is used to generate a first node voltage group on the first node group according to the input signal. The pull-up control module 2 is used to generate a second node voltage group on the second node group according to the first node voltage group. The acceleration module 3 is used to accelerate the output level conversion signal according to the first node voltage group and / or the second node voltage group.

[0020] Specifically, pull-down control module 1 refers to a circuit unit used to receive external input signals and control the first node voltage group according to the input signals. The first node group refers to a group of nodes whose voltage state changes with the input signal. This group of nodes includes at least two nodes, and the voltages of these nodes affect each other during the operation of the level conversion circuit. The first node voltage group refers to the voltage on each node in the first node group. Pull-up control module 2 refers to a circuit unit used to form a positive feedback structure and maintain the stable state of the circuit, and it is connected to the second node group. The second node group refers to a group of nodes whose voltage is correlated with the first node voltage group. This group of nodes includes at least two nodes. The second node voltage group refers to the voltage on each node in the second node group. Acceleration module 3 refers to a circuit unit connected between the first node group and the second node group. When the voltage of the first node group changes, it affects the voltage change process of the first node group and the second node group through its connection relationship with the first node group and the second node group. First power supply VSS2 refers to a power supply terminal that provides a reference ground potential. The voltage of the first power supply VSS2 can be, for example, 0V. The second power supply VDD2 refers to the power supply terminal that provides a high level. The voltage of the second power supply VDD2 can be, for example, 1.8V. It should be noted that the input signal includes the clock signal.

[0021] This embodiment of the invention uses acceleration module 3 to limit the voltage change range of the first node group and the second node group during the level transition process, thereby accelerating the output level transition signal. Taking the transition process of the input signal changing from high level to low level as an example, where the first node group includes the first node NETA and the second node NETB, and the second node group includes the third node NETC and the fourth node NETD, the following is an explanation: In the initial state when the input signal is high level, pull-down control module 1 pulls down the voltage of the first node NETA in the first node group to the voltage of the first power supply VSS2 according to the input signal. Correspondingly, pull-up control module 2 pulls up the voltage of the second node NETB in the first node group to a voltage close to the voltage of the second power supply VDD2 through cross-coupling. At this time, through the cooperation of acceleration module 3, pull-down control module 1, and pull-up control module 2, the voltage difference between the first node NETA and the third node NETC is clamped to a first preset threshold, and the voltage difference between the second node NETB and the fourth node NETD is clamped to a second preset threshold.

[0022] When the input signal flips, the output signal level of the pull-down control module 1 changes, releasing the pull-down effect on the first node NETA. Simultaneously, under the action of the first power supply, it begins to pull down the voltage of the second node NETB. In conventional circuits, the voltage of the first node NETA needs to be charged from 0V to the voltage of the second power supply VDD2. During this time, the voltage change range of the first node NETA during the level transition is a full swing of 1.8V, resulting in a relatively long level transition time. However, in this embodiment of the invention, by introducing the acceleration module 3, the pull-up control module 2 is connected to the second node group instead of directly to the first node group. Therefore, when the voltage of the first node NETA begins to rise, the voltage of the first node NETA does not need to reach the voltage of the second power supply VDD2 to complete the final output signal level transition and obtain the level transition signal. It only needs to reach the voltage of the second power supply VDD2 minus the first preset threshold, that is, only need to reach the second voltage, to start the positive feedback process of the pull-up control module 2 in advance, so that the circuit can quickly complete the state flip. Because the voltage swing of the first node NETA is reduced from the traditional 0V to the voltage of the second power supply VDD2 to 0V to the voltage of the second power supply VDD2 - Vth, and the voltage of the second power supply VDD2 - Vth is equal to the second voltage, where Vth is the first preset threshold, which is related to the acceleration module 3, and Vth is also the threshold voltage of the switching transistor. Assuming Vth is 0.6V, the voltage change range of the first node group and the second node group during the level transition can be reduced from the traditional 1.8V to 1.2V. Therefore, the voltage rise and fall speed is increased, and the switching speed is accelerated by 33.3%, thereby realizing the accelerated output level transition signal.

[0023] Therefore, by introducing the acceleration module 3, the voltage swing of the first node group in this embodiment of the invention is reduced from full swing to partial swing, and the speed at which the voltage rises to the target high level and falls to the target low level is increased, thereby significantly improving the circuit switching speed. Furthermore, this can be achieved simply by adding the acceleration module 3 to a traditional circuit, resulting in low cost and easy integration. Simultaneously, the connection relationship between the pull-down control module 1, the pull-up control module 2, and the acceleration module 3 ensures that the circuit can stably switch between the two states, achieving stable and efficient voltage conversion.

[0024] In some embodiments, the first node group includes a first node NETA and a second node NETB. The second node group includes a third node NETC and a fourth node NETD. The acceleration module 3 includes a first acceleration unit M5 and a second acceleration unit M6. The first acceleration unit M5 is connected to the pull-down control module 1 via the first node NETA and to the pull-up control module 2 via the third node NETC. The second acceleration unit M6 is connected to the pull-down control module 1 via the second node NETB and to the pull-up control module 2 via the fourth node NETD. The first acceleration unit M5 is used to clamp the voltage difference between the first node NETA and the third node NETC to a first preset threshold based on the voltages of the first node NETA and the third node NETC. The second acceleration unit M6 is used to clamp the voltage difference between the second node NETB and the fourth node NETD to a second preset threshold based on the voltages of the second node NETB and the fourth node NETD.

[0025] Specifically, the first preset threshold refers to the voltage difference between the first node NETA and the third node NETC, and the value of the first preset threshold can be set according to actual conditions. The second preset threshold refers to the voltage difference between the second node NETB and the fourth node NETD, and the value of the second preset threshold can also be set according to actual conditions. The first acceleration unit M5 is connected between the first node NETA and the third node NETC. Its function is to adjust the voltage of the first node NETA and the third node NETC during circuit operation, clamping the voltage difference between the first node NETA and the third node NETC to the first preset threshold, thereby adjusting the voltage swing between the first node NETA and the third node NETC and accelerating the output level conversion signal. When the voltage of the first node NETA changes, the voltage of the third node NETC changes accordingly, but always maintains a fixed voltage difference with the first node NETA. The second acceleration unit M6 is connected between the second node NETB and the fourth node NETD. Its function is to adjust the voltage difference between the second node NETB and the fourth node NETD during circuit operation, clamping the voltage difference between them to a second preset threshold. This adjusts the voltage swing between the second node NETB and the fourth node NETD, accelerating the output level conversion signal. When the voltage of the second node NETB changes, the voltage of the fourth node NETD changes accordingly, but always maintains a fixed voltage difference with the second node NETB.

[0026] Through the cooperation of acceleration module 3, pull-down control module 1, and pull-up control module 2, under the clamping action of the first acceleration unit M5, when the input signal flips from high level to low level, as the voltage of the first node NETA rises from the voltage of the first power supply VSS2 to high level, the voltage of the third node NETC also rises accordingly. However, the voltage of the third node NETC is always higher than the voltage of the first node NETA by a first preset threshold. When the voltage of the first node NETA rises to the second voltage, that is, the voltage of the second power supply VDD2 minus the first preset threshold, the voltage of the third node NETC just reaches the voltage of the second power supply VDD2, thereby initiating the positive feedback process of the pull-up control module 2 in advance, enabling the circuit to quickly complete the state flip. In this way, the voltage of the first node NETA does not need to rise from 0V to the voltage of the second power supply VDD2 during the level transition; it only needs to rise to the second voltage, that is, the voltage of the second power supply VDD2 minus the first preset threshold. This reduces the voltage flipping amplitude of the first node NETA and the third node NETC during the level transition, thereby accelerating the conversion speed of the first level transition signal during the level transition of the input signal. Similarly, through the clamping effect of the second acceleration unit M6, the voltage swing of the second node NETB and the fourth node NETD during the same level transition is reduced, thereby accelerating the conversion speed of the second level transition signal during the level transition of the input signal, and further improving the overall conversion speed of the circuit.

[0027] It should be noted that in actual design, the first preset threshold and the second preset threshold can be set independently according to the circuit requirements. They can be designed to be equal to ensure the symmetry of the circuit, for example, both can be set to the threshold voltage Vth described in the above embodiment. Alternatively, they can be designed to be unequal according to the actual application scenario to optimize the performance of the circuit under asymmetrical working conditions.

[0028] Therefore, in this embodiment of the invention, through the clamping action of the first acceleration unit M5 and the second acceleration unit M6, the voltage swing of the first node NETA and the second node NETB is reduced from full swing to partial swing, and the voltage rise and fall speeds are increased, thereby significantly improving the circuit switching speed. Simultaneously, the first acceleration unit M5 and the second acceleration unit M6 are structurally symmetrical, handling the voltage clamping of the two branches respectively, which helps to ensure the symmetry of the circuit operation.

[0029] In some embodiments, the pull-down control module 1 includes a first pull-down control unit M1 and a second pull-down control unit M2. A first node voltage group includes a first voltage and a second voltage, wherein the first voltage is low and the second voltage is high. Input signals include a first input signal CLKBB and a second input signal CLKB. A first terminal of the first pull-down control unit M1 receives the first input signal CLKBB, and a first terminal of the second pull-down control unit M2 receives the second input signal CLKB. The second terminals of the first pull-down control unit M1 and the second terminal of the second pull-down control unit M2 are connected to a first power supply VSS2. A third terminal of the first pull-down control unit M1 is connected to the third terminal of the first acceleration unit M5 via a first node NETA. A third terminal of the second pull-down control unit M2 is connected to the third terminal of the second acceleration unit M6 via a second node NETB.

[0030] The first pull-down control unit M1 is used to generate a first voltage at the first node NETA under the action of the first power supply VSS2, based on the first input signal CLKBB; or to generate a second voltage at the first node NETA under the action of the first acceleration unit M5. The second pull-down control unit M2 is used to generate a first voltage at the second node NETB under the action of the first power supply VSS2, based on the second input signal CLKB; or to generate a second voltage at the second node NETB under the action of the second acceleration unit M6.

[0031] Specifically, the first input signal CLKBB and the second input signal CLKB are inverses of each other. When the first input signal CLKBB is high and the second input signal CLKB is low, the first pull-down control unit M1 is turned on, and the second pull-down control unit M2 is turned off. After the first pull-down control unit M1 is turned on, it pulls down the voltage of the first node NETA to the voltage of the first power supply VSS2, that is, pulls it down to the first voltage. At the same time, under the combined action of the first acceleration unit M5, the second acceleration unit M6, and the pull-up control module 2, the second voltage generated on the second node NETB is made to be high, and the second voltage is equal to the voltage of the second power supply VDD2 - Vth.

[0032] When the first input signal CLKBB transitions to a low level and the second input signal CLKB transitions to a high level, the first pull-down control unit M1 is turned off, and the second pull-down control unit M2 is turned on. After the second pull-down control unit M2 is turned on, it pulls down the voltage of the second node NETB to the voltage of the first power supply VSS2, i.e., pulls it down to the first voltage. Simultaneously, under the combined action of the first acceleration unit M5, the second acceleration unit M6, and the pull-up control module 2, the second voltage generated on the first node NETA is made high, and the second voltage is equal to the voltage of the second power supply VDD2 minus Vth. During the circuit switching process, the first acceleration unit M5, through its clamping action, influences the voltage change of the first node NETA, accelerating its rise from the first voltage to the second voltage. Similarly, during the circuit switching process, the second acceleration unit M6, through its clamping action, influences the voltage change of the second node NETB, accelerating its rise from the first voltage to the second voltage.

[0033] Therefore, in this embodiment of the invention, the complementary conduction of the first pull-down control unit M1 and the second pull-down control unit M2 ensures that the voltages of the first node NETA and the second node NETB are always complementary. The first pull-down control unit M1 and the second pull-down control unit M2 directly pull down the corresponding node voltages to the voltage of the first power supply VSS2. The nodes of the pull-down control module 1 and the acceleration module 3 are connected, so that the voltage changes of the first node NETA and the second node NETB can be accelerated by the acceleration module 3.

[0034] For example, the pull-down control module 1 may further include a signal generation unit 11, which generates a first input signal CLKBB and a second input signal CLKB from the signal CLK. The signal generation unit 11 includes a first inverter and a second inverter. The power supply terminal of the first inverter is electrically connected to a third power supply VDD1, the input terminal of the first inverter is connected to the signal CLK, and the output terminal of the first inverter outputs the second input signal CLKB. The power supply terminal of the second inverter is also electrically connected to the third power supply VDD1, the input terminal of the second inverter is connected to the second input signal CLKB, and the output terminal of the second inverter outputs the first input signal CLKBB.

[0035] In some embodiments, the pull-up control module 2 includes a first pull-up control unit M3 and a second pull-up control unit M4. The second node voltage group includes a third voltage and a fourth voltage, wherein the third voltage is high and the fourth voltage is low. The second terminal of the first pull-up control unit M3 and the second terminal of the second pull-up control unit M4 are connected to the second power supply VDD2. The first terminals of the first pull-up control unit M3, the second pull-up control unit M4, the first terminals of the first acceleration unit M5, and the second acceleration unit M6 form a cross-coupled connection. The third terminal of the first pull-up control unit M3 is connected to the second terminal of the first acceleration unit M5 through the third node NETC. The third terminal of the second pull-up control unit M4 is connected to the second terminal of the second acceleration unit M6 through the fourth node NETD.

[0036] The first pull-up control unit M3 is used to generate a third voltage at the third node NETC under the action of the second power supply VDD2, based on the first node voltage group; or to generate a fourth voltage at the third node NETC under the action of the first acceleration unit M5. The second pull-up control unit M4 is used to generate a third voltage at the fourth node NETD under the action of the second power supply VDD2, based on the first node voltage group; or to generate a fourth voltage at the fourth node NETD under the action of the second acceleration unit M6.

[0037] Specifically, let's take a stable state where the voltage of the first node NETA is low and the voltage of the second node NETB is high as an example. When the voltage of the first node NETA is low and the voltage of the second node NETB is high, the second pull-up control unit M4 is turned on, pulling the fourth node NETD up to a voltage close to the voltage of the second power supply VDD2. At this time, a third voltage is generated on the fourth node NETD, which is the voltage of the second power supply VDD2. The fourth node NETD keeps the second node NETB at a high level through the second acceleration unit M6. At the same time, the first pull-up control unit M3 is turned off, and the voltage of the third node NETC is not pulled up. Instead, through the action of the first acceleration unit M5, the voltage of the third node NETC is converted to a fourth voltage, which is the voltage of the first power supply VSS2 + Vth, and is in a low-level state.

[0038] When the circuit flips, for example, when the first input signal CLKBB changes from low to high and the second input signal CLKB changes from high to low, the voltage of the first node NETA begins to rise, and the voltage of the second node NETB begins to fall under the action of the second pull-down unit M2. The rise in the voltage of the first node NETA causes the second pull-up control unit M4 to gradually turn off, and the voltage of the fourth node NETD begins to fall from the third voltage. The fall in the voltage of the fourth node NETD is accelerated by the second acceleration unit M6 to fall the voltage of the second node NETB. The fall in the voltage of the second node NETB causes the first pull-up control unit M3 to gradually turn on, and the first pull-up control unit M3 pulls the voltage of the third node NETC to the third voltage, that is, the voltage of the second power supply VDD2, so that the third voltage is generated on the third node NETC. At the same time, through the action of the first acceleration unit M5, the rise in the voltage of the first node NETA is accelerated, forming positive feedback.

[0039] After the circuit flips, it enters another stable state, where the voltage of the first node NETA is high and the voltage of the second node NETB is low. At this point, the high level of the first node NETA causes the second pull-up control unit M4 to turn off, and the voltage of the fourth node NETD is no longer pulled up. Instead, through the action of the second acceleration unit M6, a fourth voltage is generated on the fourth node NETD, which is the voltage of the first power supply VSS2 + Vth. Simultaneously, the low level of the second node NETB causes the first pull-up control unit M3 to turn on, pulling up the voltage of the third node NETC to the third voltage, which is the voltage of the second power supply VDD2, thus generating the third voltage on the third node NETC. Therefore, the first pull-up control unit M3 alternately generates the third voltage and the fourth voltage at the third node NETC according to the state of the first node voltage group; the second pull-up control unit M4 alternately generates the third voltage and the fourth voltage at the fourth node NETD according to the state of the first node voltage group. For example, when the first input signal CLKBB is high and the second input signal CLKB is low, the first pull-up control unit M3 is turned on when the second node NETB is low, and under the action of the second power supply VDD2, it generates the third voltage at the third node NETC, that is, the voltage of the second power supply VDD2. Alternatively, when the first input signal CLKBB is low and the second input signal CLKB is high. When the first input signal CLKBB is high and the second input signal CLKB is low, the second pull-up control unit M4, under the action of the second acceleration unit M6, generates a fourth voltage at the fourth node NETD, which is the voltage of the first power supply VSS2 + Vth. Alternatively, when the first input signal CLKBB is low and the second input signal CLKB is high, the first pull-up control unit M3 is turned on in the low-level state of the first node NETA and generates a third voltage at the third node NETC under the action of the second power supply VDD2, which is the voltage of the second power supply VDD2. In both stable states, the voltage states of the third node NETC and the fourth node NETD are always complementary. Thus, this embodiment of the invention provides positive feedback using a cross-coupling structure, which, combined with the action of the acceleration module 3, accelerates the circuit switching speed.

[0040] In some embodiments, the level conversion circuit further includes an output module, the input terminal of which is connected to the acceleration module 3. The output module is used to generate a level conversion signal based on the output voltage of the acceleration module 3, wherein the level conversion signal refers to the signal that has undergone level conversion and is finally output by the circuit. It should be noted that the common connection terminal between the acceleration module 3 and the pull-up control module 2 can be directly used as an output module for output. For example, the acceleration module 3 accelerates the level conversion and outputs a first level conversion signal at the common connection terminal between the second acceleration unit M6 and the second pull-up control unit M4. Then, under the action of the inverter, a second level conversion signal is generated based on the first level conversion signal. Alternatively, the first level conversion signal can be output at the common connection terminal between the first acceleration unit M5 and the first pull-up control unit M3, and then, under the action of the inverter, a second level conversion signal is generated based on the first level conversion signal. Alternatively, an additional output module can be added at the common connection terminal between the acceleration module 3 and the pull-up control module 2 as a circuit output.

[0041] Acceleration module 3 outputs first node group voltage and second node group voltage during circuit operation. This output voltage reflects the voltage state changes of the first and second node groups. The first terminal of the output module is connected to acceleration module 3 to receive the first and second node group voltages output by acceleration module 3. When acceleration module 3 completes a level flip, the state of its output voltage changes. Based on this output voltage state, the output module generates a corresponding level conversion signal. Therefore, in this embodiment of the invention, the output module buffers and drives the output voltage of acceleration module 3, providing a stable, complete, and precisely timed level conversion signal for subsequent circuits.

[0042] In some embodiments, the output module includes a first output unit 41 and a second output unit 42. The first output unit 41 is connected to a first node NETA in a first node group and a third node NETC in a second node group, respectively. The second output unit 42 is connected to a second node NETB in the first node group and a fourth node NETD in a second node group, respectively. The first output unit 41 is used to output a first level conversion signal CLKOUT based on the first node voltage group and the second node voltage group. The second output unit 42 is used to output a second level conversion signal CLKOUT_B based on the first node voltage group and the second node voltage group. The first level conversion signal CLKOUT and the second level conversion signal CLKOUT_B are inverses of each other.

[0043] Specifically, the first output unit 41 receives the voltages of the first node NETA and the third node NETC output by the acceleration module 3. When the voltage of the first node NETA is the first voltage (i.e., the voltage of the first power supply VSS2), and the voltage of the third node NETC is a low level that is higher than the voltage of the first node NETA (i.e., the voltage of the first power supply VSS2) by a first preset threshold (i.e., the voltage of the third node NETC is the fourth voltage), the first output unit 41 outputs a high level. For example, the voltage of the first level conversion signal output by the first output unit 41 is the third voltage (i.e., the voltage of the second power supply VDD2). When the voltage of the first node NETA is a high level that is lower than the third voltage (i.e., the voltage of the second power supply VDD2) by a first preset threshold (i.e., the voltage of the first node NETA is the second voltage), and the voltage of the third node NETC is the third voltage (i.e., the voltage of the second power supply VDD2), the first output unit 41 outputs a low level. For example, the voltage of the second level conversion signal output by the second output unit 42 is the voltage of the first power supply VSS2. The second output unit 42 simultaneously receives the voltages of the second node NETB and the fourth node NETD output by the acceleration module 3.

[0044] When the voltage of the second node NETB is low (VSS, i.e., the first voltage), and the voltage of the fourth node NETD is low (above a first preset threshold than the voltage of the second node NETB, i.e., the voltage of the fourth node NETD is the fourth voltage), the second output unit 42 outputs a high level. For example, the voltage of the first level conversion signal output by the second output unit 42 is the third voltage, i.e., the voltage of the second power supply VDD2. When the voltage of the second node NETB is high (below a first preset threshold than the third voltage, i.e., the voltage of the second power supply VDD2, i.e., the voltage of the second node NETB is the second voltage), and the voltage of the fourth node NETD is the third voltage, i.e., the voltage of the second power supply VDD2, the second output unit 42 outputs a low level. For example, the voltage of the second level conversion signal output by the second output unit 42 is the voltage of the first power supply VSS2. Since the voltages of the first node NETA and the second node NETB are complementary, and the voltages of the third node NETC and the fourth node NETD are complementary, the level conversion signals output by the first output unit 41 and the second output unit 42 are also inversely related.

[0045] Therefore, in this embodiment of the invention, the first output unit 41 and the second output unit 42 have symmetrical structures, and the rise and fall times of the generated output signals are consistent, which is beneficial for maintaining the duty cycle of the clock signal. The first output unit 41 and the second output unit 42 can use larger transistors to provide sufficient driving capability to drive subsequent loads.

[0046] In some embodiments, both the first output unit 41 and the second output unit 42 include a pull-up output transistor and a pull-down output transistor connected in series. The first end of the pull-up output transistor is connected to a corresponding node in the second node group, the second end of the pull-up output transistor is connected to the second power supply VDD2, and the third end of the pull-up output transistor is connected to the third end of the corresponding pull-down output transistor. The first end of the pull-down output transistor is connected to a corresponding node in the first node group, and the second end of the pull-down output transistor is connected to the first power supply VSS2.

[0047] Specifically, the first output unit 41 includes a first pull-up output transistor M7 and a first pull-down output transistor M8 connected in series. The first terminal of the first pull-up output transistor M7 is connected to the third node NETC, the second terminal of the first pull-up output transistor M7 is connected to the second power supply VDD2, and the third terminal of the first pull-up output transistor M7 is connected to the third terminal of the first pull-down output transistor M8, serving as the output terminal of the first level conversion signal CLKOUT. The first terminal of the first pull-down output transistor M8 is connected to the first node NETA, and the second terminal of the first pull-down output transistor M8 is connected to the first power supply VSS2.

[0048] The second output unit 42 includes a second pull-up output transistor M9 and a second pull-down output transistor M10 connected in series. The first end of the second pull-up output transistor M9 is connected to the fourth node NETD, the second end of the second pull-up output transistor M9 is connected to the second power supply VDD2, and the third end of the second pull-up output transistor M9 is connected to the third end of the second pull-down output transistor M10, serving as the output terminal of the second level conversion signal CLKOUT_B. The first end of the second pull-down output transistor M10 is connected to the second node NETB, and the second end of the second pull-down output transistor M10 is connected to the first power supply VSS2.

[0049] The first output unit 41 constitutes a two-input controlled inverter. When the voltage of the third node NETC is low (e.g., the fourth voltage VSS2+Vth) and the voltage of the first node NETA is low (e.g., the first voltage VSS2), the first pull-up output transistor M7 is turned on and the first pull-down output transistor M8 is turned off, and the first level conversion signal CLKOUT is pulled up to a high level, which is the voltage of the second power supply VDD2. When the voltage of the third node NETC is high (e.g., the fourth voltage VDD2) and the voltage of the first node NETA is high (e.g., the second voltage VDD2-Vth), the first pull-up output transistor M7 is turned off and the first pull-down output transistor M8 is turned on, and the first level conversion signal CLKOUT is pulled down to a low level, which is equal to the voltage of the first power supply VSS2. During the switching process, the timing of the voltage changes of the third node NETC and the first node NETA ensures the rapid switching of the first level conversion signal CLKOUT. Since the voltage of the third node NETC is always higher than the voltage of the first node NETA by a first preset threshold, when the voltage of the first node NETA rises to the second voltage, the voltage of the third node NETC has already reached the third voltage, i.e., the voltage of the second power supply VDD2. At this time, the first pull-up output transistor M7 is cut off, the first pull-down output transistor M8 is turned on, and the first level conversion signal CLKOUT quickly jumps from high level to low level. The working principle of the second output unit 42 is the same as that of the first output unit 41, and will not be described again here.

[0050] Therefore, the output module of this embodiment adopts a CMOS inverter structure, and the output stage has symmetrical driving capability, which can quickly drive the load capacitor. Moreover, the CMOS inverter has no DC path in the static state, resulting in extremely low power consumption. At the same time, the two output units are completely symmetrical, which improves the consistency of the waveform characteristics of the first level conversion signal CLKOUT and the second level conversion signal CLKOUT_B, thereby improving the symmetry of the level conversion circuit output. This further solves the problem of timing asynchrony caused by the delay between the two level conversion signals due to the use of inverters in the output module, ensuring that the final output level conversion signals are synchronized with each other.

[0051] It should be noted that the output module implementation in this embodiment is not limited to the symmetrical structure described above. The output module can also adopt an asymmetrical structure, for example, directly drawing the level conversion signal from the third node NETC or the fourth node NETD of the acceleration module 3. Alternatively, the third node NETC or the fourth node NETD can be selectively configured to output the level conversion signal after passing through one or more inverters. This simplified structure can also achieve the level conversion function. Regardless of whether a symmetrical or asymmetrical output module is used, the voltage swing can be adjusted by the acceleration module 3 to make the voltage swing smaller than the third voltage, i.e., the voltage of the second power supply VDD2, ultimately achieving accelerated output of the level conversion signal.

[0052] In some embodiments, both the first acceleration unit M5 and the second acceleration unit M6 include a preset number of switching transistors. The preset number refers to the number of switching transistors determined according to circuit design requirements, and can be one, two, or more.

[0053] Specifically, taking the first acceleration unit M5 as an example, it includes a preset number of switching transistors. When the preset number is one, a single switching transistor is connected between the first node NETA and the third node NETC, utilizing the threshold voltage characteristics of the switching transistor to generate the first preset threshold described in the above embodiment. When the preset number is multiple, multiple switching transistors are connected in series to form a multi-stage offset structure. Taking two switching transistors connected in series as an example, the drain and gate of the first switching transistor are connected to the first node NETA, the source of the first switching transistor is connected to the drain and gate of the second switching transistor, and the source of the second switching transistor is connected to the third node NETC. At this time, the voltage difference between the third node NETC and the first node NETA is clamped to the first preset threshold, which is the sum of the threshold voltages of the two switching transistors, i.e., 2Vth. It should be noted that the first terminal described in the above embodiment corresponds to the gate of the switch, the second terminal corresponds to the source of the switching transistor, and the third terminal corresponds to the drain of the switch. During the switching process, the voltage of the first node NETA only needs to rise to the second voltage, i.e., the voltage of the second power supply VDD2 minus the first preset threshold, to make the third node NETC reach the third voltage, i.e., the voltage of the second power supply VDD2, triggering the pull-up control module 2 to complete the switching. Therefore, the voltage swing amplitude of the final level-shifting signal output by the level-shifting circuit is related to the number of switching transistors. The second acceleration unit M6 operates on the same principle as the first acceleration unit M5, and it includes a preset number of switching transistors used to control the voltage offset between the second node NETB and the fourth node NETD.

[0054] Therefore, by selecting different numbers of switching transistors, the magnitudes of the first and second preset thresholds can be flexibly adjusted to meet the switching speed requirements of different application scenarios. When multiple switching transistors are connected in series to implement the first acceleration unit M5 and the second acceleration unit M6, the voltage swing can be further reduced to achieve a faster switching speed. It should be noted that the preset number can be flexibly selected according to actual design requirements, facilitating optimization of circuit performance.

[0055] In some embodiments, the switching transistor can be a PMOS transistor. A PMOS transistor is a P-type metal-oxide-semiconductor field-effect transistor, which is turned on when the gate voltage is lower than the source voltage by a threshold voltage.

[0056] Specifically, shorting the gate and drain of a PMOS transistor allows it to exhibit unidirectional conduction characteristics and a fixed voltage drop, similar to a diode. Taking the first acceleration unit M5 as an example, its switching transistor is a diode-connected PMOS transistor. The source of the PMOS transistor is connected to the third node NETC, and the drain and gate are connected to the first node NETA. This connection method allows the PMOS transistor to operate in the saturation region, where its source-drain voltage is approximately equal to its threshold voltage Vth. When current flows from the source to the drain, the source voltage, i.e., the voltage at the third node NETC, is always higher than the drain voltage, i.e., the voltage at the first node NETA, by a threshold voltage Vth. For example, when the first acceleration unit M5 includes two switching transistors, the two diode-connected PMOS transistors are connected in series, and the first preset threshold is the sum of the threshold voltages of the two PMOS transistors. The second acceleration unit M6 is also implemented using a diode-connected PMOS transistor, and its operating principle is the same as that of the first acceleration unit M5, which will not be repeated here.

[0057] Therefore, in this embodiment of the invention, the diode-connected PMOS transistor can provide a relatively stable voltage drop when it is turned on, approximately equal to the threshold voltage, and is less affected by current changes. Furthermore, it can be implemented using a PMOS transistor from standard CMOS processes, making it fully compatible with existing integrated circuit manufacturing processes and requiring no special components.

[0058] In some embodiments, the level conversion circuit may further include a bias adjustment module, which is electrically connected to the substrate of the first acceleration unit M5 and the substrate of the second acceleration unit M6, respectively, and is used to adaptively adjust the magnitude of the first preset threshold and the second preset threshold in the above embodiments according to the voltage change of the first voltage or the voltage change of the third voltage, that is, the voltage change of the second power supply VDD2.

[0059] Specifically, the substrate end refers to the body region of the switching transistors constituting the first acceleration unit M5 and the second acceleration unit M6. Applying a bias voltage to the substrate can change the threshold voltage of the switching transistors. The bias adjustment module is connected to the substrate ends of the first acceleration unit M5 and the second acceleration unit M6, respectively. The bias adjustment module detects changes in either the first voltage (VSS2) or the third voltage (VDD2), determines the current operating conditions, and then applies corresponding bias voltages to the substrate ends of the first acceleration unit M5 and the second acceleration unit M6, thereby changing their threshold voltages and adjusting the magnitudes of the first and second preset thresholds. For example, when an increase in the third voltage (VDD2) is detected, to maintain a relatively constant proportional relationship between the first and second preset thresholds and the third voltage (VDD2), the bias adjustment module can appropriately increase the substrate bias voltages of the first acceleration unit M5 and the second acceleration unit M6, thereby increasing their threshold voltages and thus increasing the first and second preset thresholds.

[0060] Therefore, this embodiment of the invention can automatically adjust the first preset threshold and the second preset threshold according to changes in the power supply voltage, ensuring a fast switching speed under different power supply voltages. Through feedback control, threshold voltage drift caused by power supply voltage changes can be compensated, improving the stability and reliability of the circuit.

[0061] This invention also provides a chip that includes the level conversion circuit described in the above embodiments, thus possessing the beneficial effects described in the above embodiments, which will not be repeated here. The level conversion circuit is integrated into the chip as an integrated circuit, serving as an interface circuit between different voltage domains within the chip. When a digital signal in the low-voltage domain needs to be transmitted to the high-voltage domain, the level conversion circuit receives the input clock signal from the low-voltage domain. Through the coordinated operation of the pull-down control module, the pull-up control module, and the acceleration module, the signal level is quickly converted to the high-voltage domain, and a stable high-voltage domain signal is output by the output module for use by other high-voltage modules within the chip or external devices.

[0062] Therefore, by integrating the level conversion circuit into the chip, the embodiments of the present invention achieve high-speed and stable transmission of signals across voltage domains within the chip, effectively avoiding logic confusion or chip damage caused by level mismatch. On the other hand, the level conversion circuit has a compact structure, occupies a small chip area, and has a fast switching speed, which helps to improve the overall performance and reliability of the chip. It is particularly suitable for high-speed communication chips or system-on-a-chips with high requirements for signal edge rate.

[0063] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A level conversion circuit, characterized in that, It includes a pull-down control module, a pull-up control module, and an acceleration module; wherein, the pull-down control module is connected to the acceleration module through a first node group, and the acceleration module is connected to the pull-up control module through a second node group; The pull-down control module is used to generate a first node voltage group on the first node group according to the input signal; The pull-up control module is used to generate a second node voltage group on the second node group according to the first node voltage group. The acceleration module is used to accelerate the output level conversion signal according to the first node voltage group and / or the second node voltage group.

2. The level conversion circuit according to claim 1, characterized in that, The first node group includes a first node and a second node, the second node group includes a third node and a fourth node, and the acceleration module includes a first acceleration unit and a second acceleration unit; wherein, the first acceleration unit is connected to the pull-down control module through the first node and to the pull-up control module through the third node; the second acceleration unit is connected to the pull-down control module through the second node and to the pull-up control module through the fourth node; The first acceleration unit is configured to clamp the voltage difference between the first node and the third node to a first preset threshold based on the voltages of the first node and the third node. The second acceleration unit is used to clamp the voltage difference between the second node and the fourth node to a second preset threshold based on the voltages of the second node and the fourth node.

3. The level conversion circuit according to claim 2, characterized in that, The pull-down control module includes a first pull-down control unit and a second pull-down control unit. The first node voltage group includes a first voltage and a second voltage. The first terminal of the first pull-down control unit receives a first input signal, the first terminal of the second pull-down control unit receives a second input signal, the second terminals of the first and second pull-down control units are connected to a first power supply, the third terminal of the first pull-down control unit is connected to the third terminal of the first acceleration unit through the first node, and the third terminal of the second pull-down control unit is connected to the third terminal of the second acceleration unit through the second node. The first pull-down control unit is configured to generate the first voltage at the first node under the action of the first power supply, based on the first input signal; or generate the second voltage at the first node under the action of the first acceleration unit. The second pull-down control unit is used to generate the first voltage at the second node under the action of the first power supply according to the second input signal; or to generate the second voltage at the second node under the action of the second acceleration unit; wherein the first input signal and the second input signal are inverses of each other.

4. The level conversion circuit according to claim 2, characterized in that, The pull-up control module includes a first pull-up control unit and a second pull-up control unit, and the second node voltage group includes a third voltage and a fourth voltage; wherein, the second terminals of the first pull-up control unit and the second pull-up control unit are connected to a second power supply, the first terminals of the first pull-up control unit, the second pull-up control unit, the first terminal of the first acceleration unit, and the first terminal of the second acceleration unit form a cross-coupled connection relationship, the third terminal of the first pull-up control unit is connected to the second terminal of the first acceleration unit through the third node, and the third terminal of the second pull-up control unit is connected to the second terminal of the second acceleration unit through the fourth node; The first pull-up control unit is used to generate the third voltage on the third node under the action of the second power supply, or to generate the fourth voltage on the third node under the action of the first acceleration unit, based on the first node voltage group. The second pull-up control unit is used to generate the third voltage at the fourth node under the action of the second power supply, based on the first node voltage group; or to generate the fourth voltage at the fourth node under the action of the second acceleration unit.

5. The level conversion circuit according to claim 2, characterized in that, The level conversion circuit also includes an output module, the input terminal of which is connected to the acceleration module; The output module is used to generate the level conversion signal based on the output voltage of the acceleration module.

6. The level conversion circuit according to claim 5, characterized in that, The output module includes a first output unit and a second output unit. The first output unit is connected to the first node in the first node group and the third node in the second node group, respectively. The second output unit is connected to the second node in the first node group and the fourth node in the second node group, respectively. The first output unit is configured to output a first level conversion signal based on the first node voltage group and the second node voltage group, and the second output unit is configured to output a second level conversion signal based on the first node voltage group and the second node voltage group; wherein the first level conversion signal and the second level conversion signal are inverses of each other.

7. The level conversion circuit according to claim 6, characterized in that, Both the first output unit and the second output unit include a pull-up output transistor and a pull-down output transistor connected in series; The first end of the pull-up output tube is connected to the corresponding node in the second node group, the second end of the pull-up output tube is connected to the second power supply, the third end of the pull-up output tube is connected to the third end of the corresponding pull-down output tube, the first end of the pull-down output tube is connected to the corresponding node in the first node group, and the second end of the pull-down output tube is connected to the first power supply.

8. The level conversion circuit according to claim 2, characterized in that, Both the first acceleration unit and the second acceleration unit include a preset number of switching transistors.

9. The level conversion circuit according to claim 8, characterized in that, The switching transistor is a PMOS transistor.

10. A chip, characterized in that, The level conversion circuit includes any one of claims 1 to 9.

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