A ternary logic inverter and methods of making and using the same

Abstract

This application relates to the field of microelectronics technology, specifically proposing a ternary logic inverter and its fabrication and usage methods. The ternary logic inverter includes a zero-differential transconductance transistor (ZRT) and a load transistor. The active region of the ZRT includes a first active region, a second active region, and a third active region. The first and second active regions are connected in series, and the structure formed by their series connection is connected in parallel with the third active region. The ZRT and the load transistor are connected in series, with the connection node between them serving as the output terminal. The second active region is located between the first active region and the output terminal. The end of the ZRT away from the output terminal is the ground terminal, and the end of the load transistor away from the output terminal is the power supply terminal. The gates of both the ZRT and the load transistor are electrically connected to the input terminal. All components are connected through conductive metal layers. This application improves the stability of the intermediate state output of the ternary logic inverter and enhances the consistency and repeatability of device fabrication.

Description

Technical Field

[0001] This application relates to semiconductor device technology and integrated circuits, and more specifically, to a ternary logic inverter and its fabrication method. Background Technology

[0002] Traditional binary logic circuits represent information using only two logic states, "0" and "1," and have been widely used under current semiconductor manufacturing processes. However, as device sizes continue to shrink, traditional binary logic faces increasingly significant limitations in terms of interconnect count, chip area, and power consumption control. Compared to binary logic, ternary logic can represent more information states in a single logic unit, which helps reduce interconnect count, increase information processing density, and to some extent reduce circuit complexity. Therefore, ternary logic devices, especially ternary logic inverters as fundamental logic units, are gradually becoming an important research direction in the field of multi-valued logic.

[0003] Existing implementations of ternary logic inverters primarily revolve around mechanisms such as negative differential resistance, negative differential transconductance, and zero differential transconductance. Some schemes rely on heterojunctions, tunneling structures, bipolar materials, or specific two-dimensional materials to obtain the electrical characteristics required for multi-valued logic. While these can achieve ternary output under certain conditions, they typically suffer from complex device structures, limited material selection, and narrow fabrication process windows, hindering compatibility with existing process systems and compromising consistent device fabrication and subsequent integration. For zero-differential transconductance ternary logic inverters, existing schemes often employ resistors as load elements. Resistive loads tend to generate continuous power consumption and heat loss when energized, increasing the overall power consumption of the inverter and negatively impacting circuit integration and large-area fabrication. Furthermore, some existing schemes, in order to obtain clear intermediate states, are highly dependent on material systems, device structures, or fabrication conditions, resulting in shortcomings in the clarity of ternary logic and device repeatability.

[0004] Therefore, there is an urgent need for a ternary logic inverter and its fabrication method to achieve clear and stable ternary logic output under relatively simple device structure and easy-to-implement fabrication process conditions, while taking into account the application requirements of low power consumption and high repeatability of the device. Summary of the Invention

[0005] The purpose of this invention is to address the shortcomings of the prior art by providing a ternary logic inverter and its fabrication method, thereby solving the problem that ternary logic inverters in the prior art are difficult to balance low power consumption and reproducible fabrication, thus affecting large-scale integrated applications.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: This application provides a ternary logic inverter, which includes a zero-differential transconductance transistor (ZRT) and a load transistor disposed on a substrate. The active region of the ZRT includes a first active region, a second active region, and a third active region. The first active region and the second active region are connected in series through a conductive metal layer, and the structure formed by the series connection is connected in parallel with the third active region through a conductive metal layer. The ZRT and the load transistor are connected in series through a conductive metal layer, and the connection node between them is the output terminal. The second active region is located between the first active region and the output terminal. The end of the ZRT away from the output terminal is the ground terminal, and the end of the load transistor away from the output terminal is the power supply terminal. The gates of the ZRT and the load transistor are electrically connected to the input terminal.

[0007] This application connects a first active region and a second active region in series, and then connects the resulting structure in parallel with a third active region. A zero-differential transconductance (ZDT) transistor and a load transistor are then connected in series, enabling the ZDT and load transistors to form a coordinated transmission relationship under the control of the same input signal. As the input voltage changes from low to high, the transmission capability of each active region within the ZDT changes sequentially, exhibiting the transmission behavior corresponding to ZDT. The load transistor connected in series is not merely a substitute load element, but rather its parameters are matched with the intermediate-state transmission characteristics of the ZDT, ensuring that the output terminal stably corresponds to high, intermediate, and low levels in different input voltage ranges, thereby achieving ternary logic inversion. Compared to existing schemes using resistive loads, the load transistor in this application can reduce power consumption and heat loss caused by continuous conduction of the resistive load by utilizing its own switching characteristics. Furthermore, by pre-regulating parameters such as threshold voltage and on-state current, it can form a more controllable matching relationship with the ZDT, thereby improving the clarity of intermediate logic states and output stability.

[0008] Furthermore, the threshold voltage of the second active region is the same as that of the active region of the load transistor, and both are lower than the threshold voltages of the first and third active regions. By adjusting the threshold voltages of each active region, the intermediate state level of the zero-differential transconductance transistor becomes more stable and clear, providing a matching basis for the subsequent fabrication of the load transistor.

[0009] Furthermore, the materials for the first active region, second active region, third active region, and the active region of the load transistor are any one of silicon-based semiconductor materials, metal oxides, two-dimensional materials, III-V compounds, Ge-based semiconductor materials, organic semiconductor materials, and carbon nanotubes. This diversity in material selection for the active regions is beneficial for improving the process and integration flexibility of ternary logic inverters and expanding their application scenarios.

[0010] Furthermore, the conductive metal layer can be made of any one of gold, aluminum, titanium, copper, cobalt, palladium, platinum, nickel, or silver. This diversity in material selection for the conductive metal layer improves the versatility of process options for ternary logic inverters and enhances the adaptability of materials for different active regions.

[0011] Furthermore, the gate structure of each transistor can be any one of the following: bottom gate, top gate, dual gate, floating gate, vertical gate, fin gate, or all-around gate. Different gate structures correspond to different application scenarios in integrated circuits. The diversity of gate structure selection improves the environmental adaptability of ternary logic inverters, as well as their adaptability to advanced gate structures.

[0012] Furthermore, the gate structure includes a gate dielectric layer, which is a composite material formed from one or at least two of SiO2, AlN, Al2O3, HfO2, and HfLaO. Different gate dielectric layer materials correspond to different gate control capabilities and also affect carrier mobility. By selecting different gate dielectric layer materials, it is beneficial to meet the different parameter requirements of ternary logic inverter fabrication for different application scenarios.

[0013] This application also proposes a method for fabricating a ternary logic inverter, which includes the following steps: S1. Prepare the first active region, the second active region, the third active region, and the loaded active region respectively; S2. Prepare conductive metal layers corresponding to the first active region, the second active region, the third active region, and the load active region. Connect the first active region and the second active region in series. Connect the structure formed by the series connection and the third active region in parallel to form the active region of the zero-differential transconductance transistor. Connect the load active region and the load transistor formed by the corresponding conductive metal layer in series with the zero-differential transconductance transistor to obtain a ternary logic inverter.

[0014] This application pre-sets parameters such as threshold voltage, conduction capability, and channel shape required between the zero-differential transconductance transistor and the load transistor during the active region formation stage by fabricating a first active region, a second active region, a third active region, and a load active region. This provides a foundation for subsequently forming matched transmission characteristics. Furthermore, by fabricating conductive metal layers corresponding to each active region, the active regions are connected according to a preset relationship to form an overall structure capable of achieving ternary logic inversion. Therefore, this application divides the formation process of the ternary logic inverter into three levels: active region fabrication, active region characteristic formation, and connection relationship construction. This not only facilitates the separate control of electrical characteristics based on the functional division of different active regions but also enables stable ternary logic output through a clear connection relationship. Simultaneously, this fabrication method completes device construction using relatively common semiconductor process steps, which helps reduce fabrication complexity, improve device consistency and repeatability, and provides a foundation for subsequent integrated applications.

[0015] Furthermore, in step S1, a patterned region is first formed using photolithography, and then each active region is formed in the patterned region using thin film deposition. By using photolithography to form patterned regions corresponding to the active regions, the position, outline, and size relationship of each active region can be predetermined, providing a basis for the subsequent matching of electrical characteristics of each active region and the corresponding setting of conductive metal layers.

[0016] Furthermore, the channel width-to-length ratio of the second active region to the load active region is smaller than that of the first and third active regions. The channel width-to-length ratio affects the efficiency of carrier transport. By adjusting the channel width-to-length ratio of the load active region to the second active region to be significantly smaller than that of the first and third active regions, the on-state current of the load active region and the second active region is significantly different from that of the first and third active regions, thus improving the clarity of the three-valued logic.

[0017] This application also proposes a method for using a ternary logic inverter, wherein electrical signals are input to the gates of the zero-differential transconductance transistor and the load transistor at the input terminal, controlling the zero-differential transconductance transistor and the load transistor to exhibit different conduction states under different inputs and achieving matching under a specific input signal, and outputting an output electrical signal that is inverted from the input signal at the output terminal.

[0018] The ternary logic inverter proposed in this application achieves stable and clear ternary logic through a simple structure and well-defined input and output ports. It relies on the gate control effect of transistors to directly input the input signal through the gate. By matching the load transistor with the zero-differential transconductance transistor, a stable ternary logic output is obtained. This helps to simplify the existing inverter circuit structure, improve process and device compatibility, enhance reconfigurability, and lay the foundation for improving integrated circuit performance.

[0019] Compared with the prior art, the beneficial effects of the present invention are as follows: (1) This application constructs a zero-differential transconductance transistor composed of a first active region, a second active region and a third active region, and connects the zero-differential transconductance transistor in series with the load transistor, so that the zero-differential transconductance transistor forms a phased transmission characteristic during the input voltage change process, and the inverter output terminal can form three stable output states of high level, intermediate level and low level, thereby realizing a clearer three-valued logic inversion.

[0020] (2) This application uses the same fabrication process for the load active region and the second active region to make them have the same threshold voltage, and the channel width-to-length ratio of the second active region and the load active region is the same, making their conduction capabilities more likely to be similar, which is beneficial to improving the stability of intermediate logic states and the clarity of ternary logic conversion.

[0021] (3) The preparation method of this application sets the patterned region, oxygen content of the deposition atmosphere and formation mode of the conductive metal layer for different active regions respectively, so that the formation conditions and connection relationship of each active region are clearer, making it easier to repeat the implementation and improving the consistency and repeatability of the preparation of the three-valued logic inverter. Attached Figure Description

[0022] Figure 1 A schematic diagram of the components and relative positions of a ternary logic inverter provided by the present invention; Figure 2 A flowchart of a method for fabricating a ternary logic inverter provided by the present invention; Figure 3 This is a three-dimensional structural diagram of the ternary logic inverter prepared in Example 2; Figure 4 for Figure 3 The transfer characteristic curve of the zero-differential transconductance transistor in the ternary logic inverter is shown. Figure 5 for Figure 3 The input-output gain curve of the ternary logic inverter is shown below; Figure 6 for Figure 3 The input-output characteristic curve of the ternary logic inverter is shown below; Figure 7 The input-output characteristic curves of a five-valued logic inverter formed based on the principles of this invention are shown.

[0023] Icons: 1-First active region; 2-Second active region; 3-Third active region; 4-Load active region; 5-Gate dielectric layer; 6-Conductive substrate; 7-Conductive metal layer; 8-Zero-differential transconductance transistor; 9-Load transistor. Detailed Implementation

[0024] To make the implementation process of this invention clearer, a detailed description will be provided below in conjunction with the accompanying drawings.

[0025] Example 1:

[0026] This invention provides a ternary logic inverter, such as... Figure 1 As shown, the transistor includes a zero-differential transconductance transistor 8 and a load transistor 9. The zero-differential transconductance transistor 8 includes a first active region 1, a second active region 2, and a third active region 3. The first active region 1 and the second active region 2 are connected in series, and the structure formed by the series connection is connected in parallel with the third active region 3. The load transistor 9 is connected in series with the zero-differential transconductance transistor 8 through a conductive metal layer 7. The connection node between the load transistor 9 and the zero-differential transconductance transistor 8 is the output terminal (V). out The second active region 2 is located between the first active region 1 and the output terminal; the end of the zero-differential transconductance transistor 8 furthest from the output terminal is the ground terminal (GND), and the end of the load transistor 9 furthest from the output terminal is the power supply terminal (V). DD The gate structures corresponding to the first active region 1, the second active region 2, the third active region 3, and the load active region 4 are all connected to the input terminal (V). in Electrical connection.

[0027] In this embodiment, the first active region 1, the second active region 2, and the third active region 3 together form the active region portion of the zero-differential transconductance transistor 8. Specifically, multiple active regions are connected in a predetermined relationship within the same device to form the channel transmission structure in the zero-differential transconductance transistor 8. The first active region 1 and the second active region 2 are connected in series, and the third active region 3 is connected in parallel with the structure formed by the series connection. With this configuration, the zero-differential transconductance transistor 8 utilizes the different switching characteristics of the three active regions under different input ranges, causing the transmission capability of the zero-differential transconductance transistor 8 to exhibit a phased change characteristic with the input signal, thereby forming the transmission behavior corresponding to zero-differential transconductance. The load transistor 9 is connected in series with the zero-differential transconductance transistor 8 to form parameter matching with the transmission characteristics of the zero-differential transconductance transistor 8 in the intermediate level range, enabling the output terminal to stably form an intermediate logic state. The control terminals of the zero-differential transconductance transistor 8 and the load transistor 9 are corresponding gates, formed by the conductive metal layer 7. Figure 1The structure is shown. The specific gate structures of the zero-differential transconductance transistor 8 and the load transistor 9 are not limited. The gate structure is used to form a gate-controlled electric field for the first active region 1, the second active region 2, the third active region 3, and the load active region 4, and to adjust the on-state of each active region and the channel transport capability. Specifically, the gate structure can be any of the following: bottom-gate structure, top-gate structure, dual-gate structure, floating-gate structure, vertical-gate structure, fin gate, or all-around gate. Different gate structures differ in the relative position of the gate and the active region, the gate control capability, and the device integration method, but all should ensure that the zero-differential transconductance transistor 8 and the load transistor 9 are in the same position at the input terminal V. in Formed under the control of Figure 1 The corresponding connection relationship of the structure shown is used to form a preset threshold voltage level and conduction capability level between the first active region 1, the second active region 2, the third active region 3 and the load active region 4, thereby forming the transmission behavior and intermediate state matching relationship corresponding to zero differential transconductance during the input signal change process, and realizing the three-valued logic inverted output.

[0028] In this structure, after a control signal is applied to the input terminal, the zero-differential transconductance transistor 8 and the load transistor 9 synchronously change their transmission states under the same input signal. The output potential is determined by the transmission characteristics of both the zero-differential transconductance transistor 8 and the load transistor 9. Specifically, the threshold voltages of the second active region 2 and the load active region 4 are the same and are both less than the threshold voltages of the first active region 1 and the third active region 3. The on-state currents of the second active region 2 and the load active region 4 are the same and are both less than the on-state currents of the first active region 1 and the third active region 3. In the zero-differential transconductance transistor 8, since the first active region 1, the second active region 2, and the third active region 3 have different threshold voltages and on-state currents, after a control signal is applied to the input terminal, the first active region 1, the second active region 2, and the third active region 3 turn on sequentially as the control signal increases, controlling different current directions. In the structure formed by the series connection of the first active region 1 and the second active region 2, the second active region 2 turns on before the first active region 1 due to its smaller threshold voltage. However, since the first active region 1 is still in the off state, the current of this structure is in a relatively small off range. As the control signal connected to the input terminal gradually increases, when the first active region 1 and the second active region 2 turn on at the same time, the on-state current of this structure will be dominated by the second active region 2, which has a smaller on-state current. At the same time, the third active region 3 is connected in parallel with it. Due to the larger threshold voltage and on-state current of the third active region 3, when the control signal further increases, the active region current dominance of the zero-differential transconductance transistor 8 changes from the structure formed by the series connection of the first active region 1 and the second active region 2 to the third active region 3, thereby making the zero-differential transconductance transistor 8 exhibit a phased change in transmission characteristics.

[0029] Furthermore, the threshold voltages of the second active region 2 and the load active region 4 are the same, and they have the same planar shape and the same thin-film deposition process for the active regions. This configuration allows them to undergo similar turn-on and conduction changes, making it easier for the zero-differential transconductance transistor 8 and the load transistor 9 to match their conduction capabilities when the input is in the middle level range, thereby improving the range and stability of the intermediate logic state at the output.

[0030] In actual operation, the logic state of the input terminal is divided into three states: low level, intermediate level, and high level. Correspondingly, the output terminal forms three states: high level, intermediate level, and low level, thereby realizing the inversion of three-valued logic. Specifically, in use, electrical signals are input to the gates of the zero-differential transconductance transistor and the load transistor at the input terminal. This controls the zero-differential transconductance transistor and the load transistor to exhibit different conduction states under different inputs and achieve matching under specific input signals. The output terminal outputs an output electrical signal that is inverted from the input signal at the input terminal. When the input terminal V... in When in the low-level range, the zero-differential transconductance transistor 8 is in the off state, while the power supply terminal V is connected. DD The load transistor 9 is in the ON state, therefore the output V out Received by power supply terminal V DD The effect remains high. With the input terminal V... in As the voltage level increases, the conduction states of each active region in the zero-differential transconductance transistor 8 change sequentially, causing the zero-differential transconductance transistor 8 to form the transmission stage corresponding to zero-differential transconductance. When the input terminal V... in When entering the intermediate level range, the on-state current of the zero-differential transconductance transistor 8 is dominated by the second active region 2. Simultaneously, since the second active region 2 and the load active region 4 have the same planar shape and the same thin-film deposition process, their conduction capabilities are identical in this range. This results in a relative balance between the transmission capabilities of the zero-differential transconductance transistor 8 and the load transistor 9 near the output terminal, and the output terminal V... out It stabilizes at the intermediate level. When the input terminal V... in After rising further to the high-level range, the equivalent transfer state of the zero-differential transconductance transistor 8 changes further. The on-state current of the third active region 3 in the zero-differential transconductance transistor 8 is larger than that of the load active region 4, and the output V... out The input is more affected by the ground terminal GND and turns to a low level state, thereby realizing the three-level logic inverse relationship of low level input corresponding to high level output, intermediate level input corresponding to intermediate level output, and high level input corresponding to low level output.

[0031] For example, in a ternary logic circuit, low level, middle level, and high level are denoted as "0", "1", and "2", respectively. When the input terminal is "0", the output terminal outputs "2"; when the input terminal is "1", the output terminal remains "1"; and when the input terminal is "2", the output terminal outputs "0". In this process, the zero-differential transconductance transistor 8, through the different switching characteristics of the three active regions under different input intervals, makes the transmission capability of the zero-differential transconductance transistor 8 exhibit a staged change characteristic with the input signal, thus forming the transmission behavior corresponding to zero-differential transconductance. This, in turn, forms a corresponding cooperation with the load transistor 9, thereby forming three distinguishable stable level states at the output terminal. Therefore, in this embodiment, the first active region 1, the second active region 2, and the third active region 3 are used together to form the active region of the zero-differential transconductance transistor 8, and are connected in series with the load transistor 9. At the same time, by correspondingly setting the channel shape and thin film deposition process of the second active region 2 and the load active region 4, the output terminal can not only form two states, high level and low level, during the input signal change process, but also stably form an intermediate level state, thereby realizing clear ternary logic inversion.

[0032] Example 2:

[0033] Based on Example 1, this application also proposes a method for fabricating a ternary logic inverter, such as... Figure 2 As shown. In different embodiments, the gate structure is selected according to the device material system, integration method, and gate control requirements. Among them, bottom gate structure and top gate structure are suitable for the fabrication of thin film transistors and planar devices. The bottom gate structure facilitates the use of the conductive substrate 6 below as a common gate, while the top gate structure facilitates the further setting of local gates after the active region is formed. The dual gate structure is suitable for devices that need to enhance channel control capability or reduce turn-on voltage. The floating gate structure is suitable for devices that need to introduce charge storage or adjustable threshold characteristics. The vertical gate structure, fin gate, and all-around gate are suitable for devices with high integration or enhanced gate control capability. When using the above different gate structures, the relative positions between the gate, gate dielectric layer 5, and each active region can be adjusted accordingly, but it should be ensured that the first active region 1, the second active region 2, the third active region 3, and the load active region 4 can form a preset threshold voltage level, conduction capability level, and intermediate state matching relationship under the control of the input terminal.

[0034] This embodiment uses a bottom-gate thin-film device structure as an example to illustrate the fabrication method of a ternary logic inverter. The first active region 1, the second active region 2, the third active region 3, and the load active region 4 correspond to the active regions of the zero-differential transconductance transistor 8 and the load transistor 9, respectively. Simultaneously, the conductive substrate 6 and the gate dielectric layer 5 serve as the gate structure and are located below each active region. The method includes the following steps: S1. Prepare the first active region 1, the second active region 2, the third active region 3 and the load active region 4 respectively. The first active region 1, the second active region 2, the third active region 3 and the load active region 4 are prepared on the conductive substrate 6 and the gate dielectric layer 5 respectively to form a thin film device with a bottom gate structure.

[0035] Before fabricating the active regions, the conductive substrate 6 is made of phosphorus-doped silicon substrate, which is an n-type doped silicon substrate. This conductive substrate 6 serves as both the carrier substrate for the device and the gate base shared by the control terminals of the first active region 1, the second active region 2, the third active region 3, and the load active region 4. To facilitate subsequent device fabrication, the conductive substrate 6 is pretreated, including cutting, cleaning, and drying. Specifically, the conductive substrate 6 is first cut into small pieces of a predetermined size, and then cleaned sequentially with an organic solvent to remove particles, oil, and other impurities from its surface. After cleaning, it is dried with nitrogen. After pretreatment, a gate dielectric layer 5 is formed on the surface of the conductive substrate 6. The gate dielectric layer 5 is used to electrically isolate the subsequently formed active regions from the conductive substrate 6 and, together with the conductive substrate 6, constitutes the gate structure of each thin-film transistor in this embodiment. The gate dielectric layer 5 is a composite material formed from one or at least two of SiO2, AlN, Al2O3, HfO2, and HfLaO. Different gate dielectric layer 5 materials have different dielectric properties, interface properties, and process compatibility, which will affect the gate's ability to control the active channel. By selecting different gate dielectric layer 5 materials, it is possible to adapt to different active region materials, gate structures, and target turn-on voltage requirements, thereby meeting the fabrication needs of ternary logic inverters in different application scenarios. In specific implementations, silicon dioxide is preferably used as the material for the gate dielectric layer 5, and a phosphorus-doped silicon substrate with a pre-formed silicon dioxide layer on its surface can be used as the starting substrate; alternatively, the silicon dioxide gate dielectric layer 5 can be formed on the surface of the phosphorus-doped silicon substrate through thermal oxidation, chemical vapor deposition, or atomic layer deposition.

[0036] In this step, each active region is prepared in the following order: first, a patterned region is formed; then a thin film is deposited; and finally, post-processing is performed. This ensures that the different active regions meet the preset requirements in terms of location, shape, and electrical properties. Specifically, the preparation of the active regions includes the following steps: (1) Formation of the active region patterning area: First, photoresist (950 PMMA A4) is spin-coated onto the surface of the gate dielectric layer 5 at a spin speed of 2000 rpm, a spin time of 60 s, and an acceleration of 400 rpm / s. After spin-coating, the photoresist is cured by heating at 180°C for 90 s. Subsequently, according to the preset layout described in Example 1, electron beam lithography is used to pattern the first active region 1, the second active region 2, the third active region 3, and the loaded active region 4, with an electron beam dose of 300 μC / cm. 2The accelerating voltage is 20 keV. Specifically, active regions are sequentially arranged on the conductive substrate 6 and the gate dielectric layer 5, with the first active region 1 and the second active region 2 connected in series, and the third active region 3 connected in parallel with the structure formed by the series connection. These regions are then arranged adjacent to the connection nodes corresponding to the input terminal, output terminal, and ground terminal, respectively. With this arrangement, the first active region 1, the second active region 2, and the third active region 3 together form the active region portion of the zero-differential transconductance transistor 8. Furthermore, through the corresponding settings of the second active region 2 and the load active region 4 in terms of channel shape and thin-film deposition process, the output terminal can not only form both high and low levels during input signal changes, but also stably form an intermediate level state, thereby achieving clear ternary logic inversion. Specifically, the channel width-to-length ratio of the second active region 2 and the load active region 4 is smaller than that of the first active region 1 and the third active region 3. Specifically, the active region patterns of the first active region 1 and the third active region 3 have a width-to-length ratio of 10:1, while the active region patterns of the second active region 2 and the load active region 4 have a width-to-length ratio of 1:20. The second active region 2 and the load active region 4 use the same channel width-to-length ratio to maintain consistent channel dimensions and correspond to the same on-state current. The first active region 1 and the third active region 3 use a different channel width-to-length ratio to differentiate their on-state currents from those of the second active region 2 and the load active region 4. With this configuration, the on-state current of each active region satisfies the condition that the on-state current of the second active region 2 is the same as that of the load active region 4, and is smaller than that of the first active region 1 and the third active region 3. After patterning, a developer solution with a volume ratio of 1:3 (MIBK / IPA) of methyl isobutyl ketone and isopropanol was used for development for 50 seconds. Then, isopropanol (IPA) was used for cleaning and nitrogen gas was used for drying to form the position, outline and size relationship of each active region.

[0037] (2) Formation of the active region thin film: After the patterned region is formed, an active region thin film is formed in the corresponding patterned region. The materials of the first active region 1, the second active region 2, the third active region 3, and the loaded active region 4 are any one of silicon-based semiconductor materials, metal oxides, two-dimensional materials, III-V compounds, Ge-based semiconductor materials, organic semiconductor materials, and carbon nanotubes. All of the above materials can form a controlled channel under the action of the gate structure, and different threshold voltages and channel transport capabilities can be formed by adjusting parameters such as channel size, carrier concentration, doping conditions, deposition conditions, thin film thickness, annealing conditions, or contact structure. In this embodiment, the active region thin film is an InSnO thin film. The active region thin film is formed by DC magnetron sputtering. The region corresponding to the first active region 1 is at room temperature and a vacuum degree of 5×10 -6DC magnetron sputtering was performed under conditions of Pa and DC sputtering power of 60 W, with a pre-sputtering time of 400 s and a formal sputtering time of 50 s. The sputtering atmosphere used an argon-oxygen ratio of 50:6 to form an InSnO thin film with a thickness of 10 nm. Each active region was sputtered under the same temperature, vacuum level, sputtering power, pre-sputtering time, and formal sputtering time, differing only in the oxygen content of the sputtering atmosphere. The sputtering atmosphere for the second active region 2 used an argon-oxygen ratio of 50:3; the sputtering atmosphere for the third active region 3 used an argon-oxygen ratio of 50:15; and the sputtering atmosphere for the loaded active region 4 used an argon-oxygen ratio of 50:3. The second active region 2 and the loaded active region 4 had the same oxygen content in their sputtering atmospheres, forming active region films under low oxygen content conditions, resulting in high carrier concentrations and thus achieving the same parameter level for a low threshold voltage. The first active region 1 and the third active region 3 formed higher threshold voltage levels under higher oxygen content conditions. After the above settings are adopted, the threshold voltage of each active region satisfies the condition that the threshold voltages of the second active region 2 and the load active region 4 are the same and less than the threshold voltages of the first active region 1 and the third active region 3, with the threshold voltage of the first active region 1 being less than that of the third active region 3. The second active region 2 and the load active region 4 use the same sputtering atmosphere conditions and the same channel width-to-length ratio, making it easier for them to obtain similar threshold voltages and conduction capabilities, providing a matching basis for the formation of the intermediate logic state at the subsequent output terminal. In addition to the above-mentioned control through the oxygen content of the sputtering atmosphere and the channel width-to-length ratio, in other embodiments, the threshold voltage and on-state current of each active region can also be controlled by thin film deposition time, thin film thickness, doping method, annealing conditions, or other process parameters that can change the carrier concentration and channel transport capability, in order to form the required parameter matching relationship.

[0038] (3) Post-processing of active regions: After the active region thin film is deposited, the surface of the conductive substrate 6 is stripped. Specifically, the deposited conductive substrate 6 is immersed in acetone at 50°C for 20 min, then cleaned with IPA and dried to remove the photoresist outside the patterned area, while retaining the active region within the patterned area. Next, the active region thin film is annealed at 200°C in air for 30 min to improve the stability of the electrical properties of the active region thin film, thus completing the fabrication of each active region.

[0039] S2. Conductive metal layers 7 are fabricated as electrodes on both sides of the first active region 1, the second active region 2, the third active region 3, and the load active region 4, respectively. Simultaneously, conductive metal layers 7 are fabricated as metal interconnects, connecting the first active region 1 and the second active region 2 in series and the third active region 3 in parallel, forming the active region of the zero-differential transconductance transistor 8. The load transistor 9 is connected in series with the zero-differential transconductance transistor 8 to obtain a ternary logic inverter. After the active regions are fabricated, a photolithography process is used to form patterned areas of corresponding electrode structures and metal interconnects to determine the positional relationships of the electrodes in each active region and their interconnections. Subsequently, conductive metal layers 7 are formed within the patterned areas. The conductive metal layers 7 include source electrodes, drain electrodes, and metal interconnects. The material of the conductive metal layers 7 is any one of gold, aluminum, titanium, copper, cobalt, palladium, platinum, nickel, and silver. The aforementioned metallic materials can all serve as conductive materials for the active region electrodes and metal connecting wires, forming electrical connections with the first active region 1, the second active region 2, the third active region 3, and the load active region 4. Each active region is then connected to the zero-differential transconductance transistor 8 and the load transistor 9 according to a preset series or parallel connection. Different metallic materials exhibit varying work functions, conductivity, contact characteristics, and process compatibility. Selection is based on the active region material, contact resistance requirements, and fabrication process conditions to improve the contact stability and connection reliability between the conductive metal layer 7 and each active region.

[0040] In this embodiment, all electrode structures and metal interconnects are made of nickel and formed using a vacuum thermal evaporation process. Specifically, elemental nickel is placed in an evaporation boat. After the thermal evaporation chamber reaches a vacuum state, the heating power is turned on and gradually increased, causing the elemental nickel to evaporate and deposit on the surface of the gate dielectric layer 5. During the evaporation process, the deposition rate of the nickel layer is controlled to be stable at approximately 1 Å / s, ultimately forming a conductive metal layer 7 with a thickness of 60 nm. The electrode structures and metal interconnects are formed using the same thin-film deposition process, ensuring that all three are based on the same conductive layer, thus forming a continuous and well-defined conductive relationship. After the conductive metal layer 7 is deposited, it is immersed in acetone at 50°C for 20 min, then cleaned with isopropanol and dried with a nitrogen gun to remove the photoresist outside the patterned area, while retaining the source electrode, drain electrode, and metal interconnect structure within the patterned area. Subsequently, it is annealed at 90°C for 15 min in an air atmosphere to improve the contact stability between the conductive metal layer 7 and the active region. After the above processing, the first active region 1 and the second active region 2 are connected in series via a metal connecting wire, and are connected in parallel with the third active region 3 to form the active region of the zero-differential transconductance transistor 8. The load transistor 9 is connected in series with the zero-differential transconductance transistor 8, thereby obtaining the following... Figure 3 The ternary logic inverter shown is shown.

[0041] In this embodiment, after fabricating the ternary logic inverter, to verify the ZDT characteristics formed by the zero-differential transconductance transistor 8 and the overall ternary logic output characteristics of the inverter, the electrical performance of the fabricated device was tested. In this embodiment, a high-low temperature vacuum probe station (Lakeshore TTPX) and a semiconductor parameter analyzer (Keithley 4200-SCS) were used to test the device. The test environment was a dark condition below 0.5 mbar to reduce the interference of the external environment on the electrical characteristics of the device. The test results are as follows: Figures 4 to 6 As shown.

[0042] Figure 4 The transfer characteristic curve of the zero-differential transconductance transistor 8 in the inverter is shown. As can be seen from the figure, the transfer characteristic exhibits a "ridge"-like variation, indicating that the zero-differential transconductance transistor 8, composed of the first active region 1, the second active region 2, and the third active region 3, can form the transfer behavior corresponding to ZDT. This result demonstrates that, by setting different channel sizes and active region formation conditions accordingly, the zero-differential transconductance transistor 8 possesses the key foundation required for forming a ternary logic inverter.

[0043] Figure 5 The input-output gain curve of a ternary logic inverter is shown. During testing, a VG is applied to the device from the gate. in The input voltage is -20 V to 10 V, and the power supply terminal V is... DD The voltage was set to 1 V to 10 V in 1 V increments, and the corresponding output was measured. As can be seen from the graph, the inverter exhibits noticeable gain peaks near two input voltage ranges, one of which is located at V... in It is around -10 V, and another peak is located at V. in The voltage is approximately 3 V. The two gain peaks mentioned above correspond to the positions where the output state transitions, indicating that there are two distinct logic transition intervals for this inverter during input voltage changes.

[0044] Figure 6 The input-output characteristic curves of a ternary logic inverter are shown. As the input voltage V... in The output voltage V changes from low to high. out It sequentially presents three stable states: high level, middle level, and low level, meaning the output terminal forms three distinguishable potential levels within different input ranges. Combined with... Figure 5 The position of the gain peak can be seen in the image. Figure 6 The range in which the output state changes and Figure 5 The corresponding range of the gain peak indicates that the prepared inverter can not only form a clear ternary logic output, but also has a relatively clear transition position between each logic state, and has good ternary logic characteristics.

[0045] comprehensive Figures 4 to 6 It can be seen that in the ternary logic inverter prepared in this embodiment, the zero-differential transconductance transistor 8 has formed the ZDT characteristic required to realize the ternary logic inversion, and the inverter as a whole exhibits three stable output states of high-medium-low and a clear logic transition range, indicating that the preparation method can realize the construction of ternary logic inverter, and the obtained device has clear ternary logic characteristics.

[0046] Example 3:

[0047] Based on Embodiments 1 and 2, this embodiment further extends the structure of the ternary logic inverter to illustrate the application of the present application in higher-value logic inverters. Unlike Embodiment 1, this embodiment, while maintaining the same working principle between the zero-differential transconductance transistor 8 and the load transistor 9, further adds a new active region component. This new active region component is then connected to the original structure via a metal connection line, enabling the extended structure to form more stages of transmission states during input voltage changes, thereby resulting in more than three stable output voltage states.

[0048] This embodiment uses the expansion of a quaternary logic inverter and a quinary logic inverter as examples for explanation. Compared to the ternary logic inverter in Embodiment 1, the quaternary logic inverter adds a new active region component to the original active region component. This new active region component includes two active regions. One of the new active regions is connected in parallel to the active region of the original zero-differential transconductance transistor 8, and the other new active region is connected in parallel to the original load active region 4. After the new active region component is connected to the original structure, the expanded zero-differential transconductance transistor 8 adds a new stable state between the original three stable states as the input voltage changes from low to high, thereby forming four distinguishable stable levels at the output. Furthermore, by adding a new active region in parallel to the quaternary logic inverter, the expanded zero-differential transconductance transistor 8 adds another new stable state, thereby forming five distinguishable stable levels at the output, realizing quinary logic inversion.

[0049] When expanding from a ternary logic inverter to a quaternary logic inverter, and then to a pentagonal logic inverter, the newly added active regions are all configured according to the same parameter matching principle as the original active regions. That is, by setting the threshold voltage and conduction capability of the newly added active region components, they are placed at a different parameter level than the original active regions, and participate in the construction of new intermediate states during input voltage changes. This allows the expanded inverter structure to sequentially form multiple relatively stable transmission stages in different input ranges. Thus, the ternary logic inverter of this application can be progressively expanded to quaternary, pentagonal, and even higher-value multi-value logic inverters according to the same principle, thereby realizing multi-valued logic construction.

[0050] Figure 7 The theoretical verification results of the five-valued logic inverter obtained based on the principles of this application are shown. Figure 7 It can be seen that, while maintaining the same basic configuration principle as in Embodiment 1, by increasing the number of active regions and setting the parameter levels of the newly added active regions accordingly, five stable level states can be formed at the output. This result shows that the ternary logic inverter proposed in this application is not only applicable to ternary logic outputs, but can be further extended to multi-valued logic inverters with higher values ​​according to the same principle.

[0051] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A ternary logic inverter comprising a zero differential transconductance transistor and a load transistor disposed on a substrate, characterized by: The active region of the zero-differential transconductance transistor includes a first active region, a second active region, and a third active region. The first active region and the second active region are connected in series through a conductive metal layer, and the structure formed by the series connection is connected in parallel with the third active region through the conductive metal layer. The zero-differential transconductance transistor and the load transistor are connected in series through the conductive metal layer, and the connection node between them is the output terminal. The second active region is located between the first active region and the output terminal. The end of the zero-differential transconductance transistor away from the output terminal is the ground terminal, and the end of the load transistor away from the output terminal is the power supply terminal. The gates of both the zero-differential transconductance transistor and the load transistor are electrically connected to the input terminal.

2. The ternary logic inverter according to claim 1, characterized in that: The threshold voltage of the second active region is the same as that of the active region of the load transistor, and both are less than the threshold voltages of the first active region and the third active region.

3. The ternary logic inverter according to claim 2, characterized in that: The materials of the first active region, the second active region, the third active region, and the active region of the load transistor are any one of silicon-based semiconductor materials, metal oxides, two-dimensional materials, III-V compounds, Ge-based semiconductor materials, organic semiconductor materials, and carbon nanotubes.

4. The ternary logic inverter according to claim 3, characterized in that: The conductive metal layer is made of any one of gold, aluminum, titanium, copper, cobalt, palladium, platinum, nickel, and silver.

5. The ternary logic inverter according to claim 4, characterized in that: The gate structure of each transistor is any one of the following: bottom gate structure, top gate structure, dual gate structure, floating gate structure, vertical gate structure, fin gate, and all-around gate.

6. The ternary logic inverter according to claim 5, characterized in that: The gate structure includes a gate dielectric layer, which is a composite material formed from one or at least two of SiO2, AlN, Al2O3, HfO2, and HfLaO.

7. A method for fabricating a ternary logic inverter, characterized in that: The method includes the following steps: S1. Prepare the first active region, the second active region, the third active region, and the loaded active region respectively; S2. Prepare conductive metal layers corresponding to the first active region, the second active region, the third active region, and the load active region, connect the first active region and the second active region in series, connect the structure formed in series with the third active region to form the active region of the zero-differential transconductance transistor, and connect the load active region and the load transistor formed by the corresponding conductive metal layer in series with the zero-differential transconductance transistor to obtain the ternary logic inverter.

8. The method for fabricating a ternary logic inverter according to claim 7, characterized in that: In step S1, a patterned region is first formed using a photolithography process, and then an active region is formed in the patterned region using a thin film deposition process.

9. The method for fabricating a ternary logic inverter according to claim 8, characterized in that: The channel width-to-length ratio of the second active region to the load active region is less than the channel width-to-length ratio of the first active region and the third active region.

10. A method of using the ternary logic inverter according to claim 1, characterized in that: The method includes the following steps: inputting electrical signals to the gates corresponding to the zero-differential transconductance transistor and the load transistor at the input terminal, controlling the zero-differential transconductance transistor and the load transistor to exhibit different conduction states under different inputs and achieving matching, and outputting an output electrical signal that is inversely phase to the input signal at the input terminal at the output terminal.

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