A switch-tunable simple digital logic reversible counter and method of application

Abstract

This invention relates to the field of counter technology, specifically providing a simple, switch-adjustable, reversible digital logic counter and its application method. The counter includes a counter body and also has a Receiver module circuit, an N module circuit, and a full adder module circuit. The Receiver module circuit, N module circuit, and full adder module circuit are installed in the counter body and electrically connected. The method includes three steps. To overcome the shortcomings of existing traditional unidirectional counters, which are limited by structure and function as described in the background art, this invention, through the combined action of related circuits, adds a timing logic circuit for counting direction control to the traditional unidirectional counter's forward counting. This allows switching between addition / subtraction counting modes via control signals, fully covering all the basic functions of a traditional unidirectional counter. It also supports bidirectional pulse accumulation, forward / reverse counting switching, and carry + borrow dual outputs, achieving reliable bidirectional counting. In summary, this invention has good application prospects.

Description

Technical Field

[0001] This invention relates to the field of counter circuit technology, and in particular to a simple digital logic reversible counter with adjustable switch and its application method. Background Technology

[0002] A counter is a device or logic unit used to record the number of times an event occurs. Its core functions are "accumulation" and "triggering," and it is widely used in electronic circuits, programmable control, industrial automation, and everyday household devices. Depending on the application scenario, it can be divided into three main categories: digital logic type, software variable type, and physical mechanical type. Triggering methods can be categorized as follows: Synchronous counters: all flip-flops share the same clock, state is updated synchronously, strong anti-interference, suitable for high-speed systems; Asynchronous counters: only the first-stage flip-flop receives the clock, and subsequent stages are driven by the output of the previous stage. The structure is simple but there is a propagation delay, mostly used in low-speed scenarios. By number system, it can be categorized as follows: Binary counters (modulo-2)... n ); decimal counters (such as 74LS90); arbitrary base counters (such as base 60 for stopwatches, base 24 for clocks).

[0003] Traditional unidirectional counters, due to structural and functional limitations, can only perform counting in one direction, resulting in significant limitations in counting range and application flexibility. Their fixed and unadjustable counting direction makes them unsuitable for scenarios requiring reversible counting, closed-loop position detection, or bidirectional pulse measurement. Furthermore, these counters lack the ability to switch counting directions and roll back to their original state. When pulse interference, count overflow, or external commands trigger reverse counting, dynamic correction of the count value is difficult, easily leading to accumulated counting errors and system inaccuracies. In addition, the functional architecture of traditional unidirectional counters is relatively simple, lacking the ability to identify and process bidirectional timing signals. This results in poor versatility in typical digital systems such as motor control, position encoding, and frequency measurement, requiring additional direction discrimination and logic switching circuits to expand applications. This increases system hardware complexity, reduces integration, and lowers reliability, making it difficult to meet the design requirements of modern digital logic systems for high-precision, highly adaptable counting units. Summary of the Invention

[0004] To overcome the shortcomings of existing traditional unidirectional counters, which are limited by their structure and function as described in the background art, this invention provides a timing logic circuit that, under the combined action of related circuits, adds counting direction control logic to the traditional unidirectional counter's forward counting. This circuit can switch between addition and subtraction counting modes via control signals, fully covering all the basic functions of a traditional unidirectional counter. It also supports bidirectional pulse accumulation, forward / reverse counting switching, and carry + borrow dual outputs, realizing a reliable bidirectional counting system. This invention is a simple, switchable, reversible digital logic counter and its application method.

[0005] The technical solution adopted by this invention to solve its technical problem is: A simple, switch-adjustable, reversible digital logic counter includes a counter body and a Receiver module circuit, an N-module circuit, and a full adder module circuit. The Receiver module circuit, N-module circuit, and full adder module circuit are installed within the counter body. The power input terminals of the Receiver module circuit, N-module circuit, and full adder module circuit are electrically connected to the two power poles within the counter body. The signal output terminal of the Receiver module circuit is electrically connected to the signal input terminal of the N-module circuit and the first signal input terminal of the full adder module circuit. The signal output terminal of the N-module circuit is electrically connected to the second signal input terminal of the full adder module circuit. The signal output terminal of the full adder module circuit is electrically connected to the trigger signal input terminal of the counter body, and the signal input terminal of the Receiver module circuit is electrically connected to the signal output terminal of the counter body. An application method for this simple, switch-adjustable, reversible digital logic counter includes the following steps. S1: The Receiver module circuit converts the counting pulse signal input to the pulse signal output terminal of the counter body into binary, and performs inversion and high-order bit padding with 0; S2: When the Receiver module circuit input is set to a high potential, it performs forward counting; when set to a low potential, it performs reverse counting. The processed signal is output to the N module circuit; S3: For reverse counting, the N module circuit records the number of clock pulses entering the Receiver module circuit after the Switch is set to a low potential, and outputs the corresponding compensation number 2*N to the next-level full adder module circuit. This number is added to the number processed by the Receiver module circuit. The summation module of the full adder module sums the numbers, removes the highest-order bit, and performs inversion before outputting the result. The counter body then performs reverse counting.

[0006] Furthermore, the Receiver module circuit is composed of five cascaded D flip-flops, with one D flip-flop serving as the first stage. Its clock input is a counting pulse, and its output terminal Q directly outputs A. <0> Feedback end The input D is used as the clock for the next stage D flip-flop, and this process is repeated to obtain a 5-bit main circuit, which converts the input counting pulses into binary.

[0007] Furthermore, the N-module circuit is composed of four cascaded D flip-flops, with one of the D flip-flops considered as the first stage. Its clock input is the clock pulse provided by the Receiver module circuit, and its output terminal Q directly outputs B. <0> ,feedback The feedback is fed back to D as input and used as the clock for the next stage D flip-flop. This process is repeated to obtain the 4-bit main circuit. After processing, the final output is 2*N.

[0008] Furthermore, the full adder module circuit is composed of five cascaded single-stage adders. The output of the previous stage adder serves as one of the inputs of the next stage. The first stage is the first-stage adder. The input terminals B and Ci of the first-stage adder are determined by two preset values ​​from the N module circuit. In the single-stage adder, input terminal A is the output of the Receiver module circuit, input terminal B is the output of the N module circuit, and input terminal C is the output Ci of the previous stage adder. Finally, the full adder module circuit uses the output terminal S to pass the data to the next stage for data processing.

[0009] Furthermore, in the single-stage adder of the full adder module circuit, the input data signals A and B are processed by their own XOR gate and AND gate, respectively. The output and input terminal C of the XOR gate are processed by the AND gate, and the data after the AND gate processing of data signals A and B is input into the OR gate. The output data signal Ci is sent to the next stage. The data after the input terminal C and the data signals A and B are processed by the XOR gate are processed by the next XOR gate to obtain the output S.

[0010] Compared with existing technologies, the advantages of this invention are as follows: This invention not only possesses the forward counting function of a traditional unidirectional counter, but also adds a timing logic circuit for counting direction control. It can switch between addition / subtraction counting modes via control signals, fully covering all the basic functions of a traditional unidirectional counter. During operation, the Receiver module circuit converts the input pulse signal into binary, performs inversion and high-order bit padding (0), and performs forward or reverse counting operations according to the corresponding pulse command signal. The N module circuit is a supplementary circuit that records the number of clock pulses entering the circuit after the Receiver module circuit is set to low potential, and outputs the corresponding compensation number 2*N to the next-level full adder module circuit. The full adder module circuit adds the numbers processed by the Receiver module circuit, sums them using its own summing module, removes the highest-order bit, inverts, and outputs the sum. The counter itself performs reverse counting. This invention also supports bidirectional pulse accumulation, forward / reverse counting switching, and carry + borrow dual output, achieving reliable bidirectional counting and showing good application prospects. Attached Figure Description

[0011] Figure 1 This is a flowchart of an application method for a simple digital logic reversible counter with adjustable switch according to the present invention.

[0012] Figure 2 , 3 Figures 4, 5, and 6 are circuit diagrams of a simple digital logic reversible counter with adjustable switch according to the present invention.

[0013] Figure 7 , 8This is a simulation diagram of a simple digital logic reversible counter with adjustable switch according to the present invention. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] Figure 2 As shown, a simple digital logic reversible counter with switch adjustment includes a counter body and a Receiver module circuit, an N module circuit, and a full adder module circuit. The Receiver module circuit, N module circuit, and full adder module circuit are installed inside the counter body. The power input terminals of the Receiver module circuit, N module circuit, and full adder module circuit are connected to the power supply terminals inside the counter body via wires. The signal output terminal of the Receiver module circuit and the signal input terminal of the N module circuit, as well as the first signal input terminal of the full adder module circuit, are connected by wires; the signal output terminal of the N module circuit and the second signal input terminal of the full adder module circuit are connected by wires; the signal output terminal of the full adder module circuit and the trigger signal input terminal of the counter body are connected by wires; and the signal input terminal of the Receiver module circuit and the signal output terminal of the counter body are connected by wires.

[0016] Figure 3 This is the Receiver module circuit. The Switch and Hold instructions at the pulse signal output of the counter body are not shown in the diagram. The main circuit of the Receiver module consists of five cascaded D flip-flops. The bottom D flip-flop in the diagram is considered the first stage; its clock input is the counting pulse, and the value of its output Q is directly output as A. <0> The feedback terminal is passed to the next stage of the full adder circuit. The input D of the current stage D flip-flop is used as the input and as the clock of the next stage D flip-flop. This process is repeated to obtain a 5-bit main circuit, which converts the counting pulses input to the signal output terminal of the counter into binary. Figure 4 This is an N-module circuit. The main circuit of the N-module circuit consists of four cascaded D flip-flops. The bottom D flip-flop in the diagram is considered the first stage. Its clock input is the clock pulse given by the Receiver module circuit, and the value of its output terminal Q is directly output as B. <0> The feedback is passed to the next stage of the full adder circuit. The input D of the current D flip-flop is fed back as input and serves as the clock for the next stage D flip-flop. This process is repeated in a loop to obtain the 4-bit main circuit. After processing, the sum of the output values ​​B<3:0> in decimal is equal to 2*N, where N is the number of reverse operations mentioned above. Figure 5 As shown, the full adder module circuit consists of five cascaded single-stage adders. The output of the previous stage adder serves as one of the inputs to the next stage. The bottom of the diagram shows the first-stage adder. The input terminals B and Ci of the first-stage adder are determined by two preset values ​​SET1 and SET2 of the N module circuit. In the single-stage adder, input terminal A is the output of the Receiver module circuit, input terminal B is the output of the N module circuit, and input terminal C is the output Ci of the previous stage adder. Finally, the full adder module circuit uses the output terminal S to pass the data to the next stage for processing. Figure 6 As shown, in the single-stage adder of the full adder module circuit, the input data signals A and B are processed by their own XOR gate and AND gate, respectively. The output and input terminal C of the XOR gate are processed by the AND gate, and the data after the AND gate processing of data signals A and B is input into the OR gate. The output data signal Ci is sent to the next stage. The data after the input terminal C and the data signals A and B are processed by the XOR gate are processed by the next XOR gate to obtain the output signal S. S is the summation result of this stage adder. Table 1 shows the truth table of the single-stage adder of the full adder module circuit.

[0017]

[0018] Table 1 Figure 1 , 2 As shown in Figures 3, 4, and 5, this invention specifically provides a simple reversible counter with an output that is always reversible and recoverable. During operation, when the counter body continuously receives clock pulses while maintaining its switch position, the system processes the output and outputs a normal count value. Specifically, after the first change of the Switch state in the Receiver module, the Receiver module circuit records the input value at that time. Upon the arrival of the next input clock pulse, after a series of processing steps by the Receiver module, N module, and full adder module circuits, the output begins to count in reverse. This invention's reversible counter can restore the forward count by changing the switch state again, while simultaneously saving the number of reverse counts already performed so that it can continue counting in reverse when the switch state changes again.

[0019] Figure 1 , 2As shown in Figures 3, 4, and 5, taking a 5-bit reversible counter as an example, the application method of a simple digital logic reversible counter with adjustable switches is as follows. The Receiver module circuit converts the pulse input to the counter body into binary, and performs inversion and high-bit padding (high-bit padding refers to adding zeros in front of the number to fill the gaps when the number of bits is insufficient. For example, the decimal number 17, when converted to binary, is 10001. Here, the high-bit refers to the most significant bit, because in binary, the most significant bit represents the position of the largest power of 2. In this case, zeros need to be added before the most significant bit, becoming 010001. This operation is generally used in the representation of the number of bits and in digital calculations). IN represents the clock pulse input to the counter body. The function of the Hold switch is that when the Receiver module circuit is set to a high potential, after the output reaches the most significant bit 31 (the reversible counter designed in this case is 5-bit, and the most significant bit of 5-bit binary is 11111, which is 31 in decimal), after another input pulse is given to the circuit, The output remains unchanged at 31 (when the Hold switch is high, after the 5-bit reversible counter reaches its counting limit of 11111 (i.e., 31 in decimal), regardless of how many more input pulses are input to the reversible counter, the reversible counter will maintain its counting limit of 11111). If Hold is low, after the output reaches its highest bit of 31, if there is another input pulse, the output will normally jump to 0 (when the Hold switch is low, after the 5-bit reversible counter reaches its counting limit of 11111 (i.e., 31 in decimal), if another input pulse is input to the reversible counter, the count of the reversible counter will jump from 11111 to 00000 and restart counting. For example, when Hold is low, the reversible counter output corresponding to the 31st input pulse is 11111, the reversible counter output corresponding to the 32nd input pulse is 00000, and the reversible counter output corresponding to the 33rd input pulse is 00001). When the Switch control circuit of the counter body performs forward and reverse operations, the forward counting operation is performed when the Switch port of the Receiver module circuit is set to a high potential, and the reverse counting operation is performed when it is set to a low potential. The default is to set it to a high potential. The N module circuit is a supplementary module. Its function is to record the number of clock pulses entering the circuit after the Switch port of the Receiver module circuit is set to a low potential, and output the corresponding compensation number 2*N (N is the number of reverse counting operations. When performing reversible counting, the N module output B<3:0> in decimal is 2*N. After being given to the next-level full adder module circuit, the reverse operation can be completed through calculation). The N module circuit adds the number processed by the Receiver module circuit. The summation module of the full adder module circuit sums the numbers and performs the removal of the highest bit and inversion operation before outputting the result (steps 5 and 6 in Table 2). The counter body then performs reverse counting.

[0020] Table 2 presents the truth table of the reversible counter. Taking a 5-bit reversible counter as an example, N equals the number of reverse operations performed. Before the reverse operation, N=0. Taking the input IN=6 at the start of the reverse operation as an example, after conversion to binary, it is 00110. Inverting it gives 11001, and padding the high-order bits with 0s gives 011001. At this point, one reverse operation has been performed, so N=1. Adding 2*1 through a full adder gives 011011. Removing the highest bit gives 11011, inverting it gives 00100, and finally the output OUT=4, realizing the reversible operation. It is important to emphasize that after closing the reverse operation and continuing the forward operation, N remains unchanged. As shown in the figure, after IN=10, N remains 4. Suppose that after IN=31 in the figure, the second reverse operation is performed. At this time, N starts counting from 5 instead of resetting to 1.

[0021]

[0022] Table 2 The following are the simulation results of this invention. Figure 7 As shown, after the switch signal switches from high to low, the circuit starts counting in reverse after a short delay. By reading the waveform, it can be seen that the circuit output values ​​change sequentially as follows: 01110, 01101, 01100, 01011, 01010, 01001, etc., thus realizing the reverse counting operation. Figure 8 The simulation results of the present invention switching from reverse counting to forward counting are given. Specifically, after the switch signal switches from low to high, the circuit starts forward counting after a short delay. By reading the waveform, it can be seen that the circuit output value changes sequentially as follows: 00111, 01000, 01001, 01010, 01011, 01100, etc., thus realizing the forward counting operation.

[0023] Figure 1 , 2As shown in Figures 3, 4, and 5, the bidirectional synchronous counting capability of the reversible counter of this invention makes it irreplaceable: it can synchronously increase or decrease the count value according to the direction of the event (forward / reverse, in / out, up / down), providing real-time feedback on the bidirectional changes in physical quantities, which is impossible for traditional unidirectional counters. Its application scope is concentrated in scenarios requiring real-time tracking of bidirectional changes, forward / reverse switching, and position / state closed-loop feedback, covering multiple core fields such as industrial control, precision measurement, consumer electronics, communication systems, and aerospace. Reversible counters are most widely used in industrial automation and motion control, fundamentally solving the problem of real-time tracking and closed-loop control of the position, quantity, and state of bidirectional motion in industrial scenarios. They are also a core basic unit of PLCs, CNC systems, and robots, including: closed-loop position control of servo / stepper motors, bidirectional material counting and inventory management on production lines, and stroke and safety control of lifting equipment. Therefore, this invention has good application prospects.

[0024] The foregoing has shown and described the basic principles and main features of the present invention, as well as its advantages. It will be apparent to those skilled in the art that the present invention is limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or basic characteristics. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within the present invention.

[0025] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in the embodiments can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A simple digital logic reversible counter with switch adjustable, comprising a counter body, and further comprising a Receiver module circuit, an N module circuit, and a full adder module circuit; characterized in that The Receiver module circuit, N module circuit, and full adder module circuit are installed inside the counter body. The power input terminals of the Receiver module circuit, N module circuit, and full adder module circuit are electrically connected to the two power poles inside the counter body. The signal output terminal of the Receiver module circuit is electrically connected to the signal input terminal of the N module circuit and the first signal input terminal of the full adder module circuit. The signal output terminal of the N module circuit is electrically connected to the second signal input terminal of the full adder module circuit; the signal output terminal of the full adder module circuit is electrically connected to the trigger signal input terminal of the counter body; and the signal input terminal of the Receiver module circuit is electrically connected to the signal output terminal of the counter body. An application method for a simple digital logic reversible counter with adjustable switch includes the following steps: S1: The Receiver module circuit converts the counting pulse signal input to the pulse signal output terminal of the counter body into binary, and performs inversion and high-bit padding with 0; S2: When the input of the Receiver module circuit is set to a high potential, it performs forward counting; when it is set to a low potential, it performs reverse counting. After processing, the signal is output to the N module circuit. S3: For reverse counting, the N module circuit records the number of clock pulses entering the Receiver module circuit after the Switch is set to low potential, and outputs the corresponding compensation number 2*N to the next-level full adder module circuit. It is added to the number processed by the Receiver module circuit, and the summation module of the full adder module circuit sums the numbers and performs the removal of the highest bit and inversion operation before outputting the result. The counter body performs reverse counting.

2. The switch-adjustable simple digital logic reversible counter according to claim 1, characterized in that, The receiver module circuit consists of five cascaded D flip-flops, with one D flip-flop serving as the first stage. Its clock input is a counting pulse, and its output terminal Q directly outputs A. <0> Feedback end The input D is used as the clock for the next stage D flip-flop, and this process is repeated to obtain a 5-bit main circuit, which converts the input counting pulses into binary.

3. The switch-adjustable simple digital logic reversible counter according to claim 1, characterized in that, The N-module circuit consists of four cascaded D flip-flops, with one of them considered as the first stage. Its clock input is the clock pulse provided by the Receiver module circuit, and its output terminal Q directly outputs B. <0> ,feedback The feedback is fed back to D as input and used as the clock for the next stage D flip-flop. This process is repeated to obtain the 4-bit main circuit. After processing, the final output is 2*N.

4. A switchably adjustable simple digital logic reversible counter according to claim 1, wherein, The full adder module circuit consists of five cascaded single-stage adders. The output of the previous stage adder serves as one of the inputs to the next stage. The first stage is the first-stage adder. The input terminals B and Ci of the first-stage adder are determined by two preset values ​​from the N module circuit. In the single-stage adder, input terminal A is the output from the Receiver module circuit, input terminal B is the output from the N module circuit, and input terminal C is the output Ci from the previous stage adder. Finally, the full adder module circuit uses the output terminal S to pass the data to the next stage for processing.

5. A switchably adjustable simple digital logic reversible counter according to claim 1, wherein, In the single-stage adder of the full adder module circuit, the input data signals A and B are processed by their own XOR gate and AND gate, respectively. The output and input terminal C of the XOR gate are processed by the AND gate, and the data after the AND gate processing of data signals A and B is input into the OR gate. The output data signal Ci is sent to the next stage. The data after the input terminal C and the data signals A and B are processed by the XOR gate are processed by the next XOR gate to obtain the output S.

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