Analog phase-locked loop frequency setting circuit

Abstract

This application discloses an analog phase-locked loop (PLL) frequency setting circuit, comprising: a D / A converter, a phase detector, a programmable gain loop filter, and a voltage-controlled oscillator (VCO). The output of the D / A converter is connected to the DC bias node of the local oscillator input terminal within the phase detector. The error voltage output of the phase detector is connected to the input of the programmable gain loop filter, and the output of the programmable gain loop filter is connected to the tuning control input of the VCO. By physically separating the frequency setting voltage from the PLL control path, this application eliminates the influence of frequency setting on core parameters such as loop gain, bandwidth, and damping coefficient. Simultaneously, it eliminates the operational amplifier adder structure to reduce phase noise at the source, thereby achieving low-voltage, high-precision, and low-noise analog PLL frequency setting.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, specifically relating to an analog phase-locked loop frequency setting circuit. Background Technology

[0002] Existing analog phase-locked loop (PLL) frequency setting techniques have a significant impact on loop gain. When the resistances (including source impedances) used in both directions of the summing network are equal, the loop gain will be halved. Furthermore, due to the active impedance of the analog phase detector, the setting voltage in traditional frequency setting circuits inevitably generates a bias voltage at the output of the analog phase detector, and this bias voltage is proportional to the setting voltage. The presence of this bias voltage will inevitably affect the phase detection sensitivity and output zero point of the analog phase detector, and this effect is unpredictable.

[0003] In view of the above problems, it is necessary to design a frequency setting circuit that does not affect the loop gain. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the purpose of this application is to provide a simulated phase-locked loop (PLL) frequency setting circuit. By physically separating the frequency setting voltage from the PLL control path, this application can eliminate the influence of frequency setting on core parameters such as loop gain, bandwidth, and damping coefficient, and achieve low-voltage, high-precision, and low-noise simulated PLL frequency setting.

[0005] To achieve the above objectives, this application provides the following technical solution: A simulated phase-locked loop frequency setting circuit includes: a D / A converter, a phase detector, a programmable gain loop filter, and a voltage-controlled oscillator (VCO). The output of the D / A converter is connected to the DC bias node of the local oscillator signal input terminal inside the phase detector; the error voltage output terminal of the phase detector is connected to the input terminal of the programmable gain loop filter, and the output terminal of the programmable gain loop filter is connected to the tuning control input terminal of the VCO.

[0006] Optionally, an impedance matching unit is provided between the D / A converter and the phase detector, for achieving wideband impedance matching between the output terminal of the D / A converter and the DC bias node of the local oscillator signal input terminal inside the phase detector, and for filtering out high-frequency ripple and noise in the frequency setting voltage output by the D / A converter.

[0007] Optionally, the impedance matching unit includes: a fourth resistor, a fifth resistor, a sixth resistor, a first capacitor, a second capacitor, and a first inductor, wherein the first end of the fourth resistor and the first end of the first capacitor are simultaneously connected to the output terminal of the D / A converter, and the second end of the first capacitor is connected to the first ground terminal; the second end of the fourth resistor is connected to the first end of the fifth resistor and the first end of the second capacitor, and the second end of the second capacitor is connected to the second ground terminal; the second end of the fifth resistor is connected to the first end of the sixth resistor, and the second end of the sixth resistor is connected to the input terminal of the adjustable bias unit; the first end of the first inductor is connected to the connection point of the fifth resistor and the sixth resistor, and the second end is connected to the third ground terminal.

[0008] Optionally, an adjustable bias unit is provided between the impedance matching unit and the phase detector, which is used to perform DC level shifting and stabilizing bias on the frequency setting voltage after noise is filtered out by the impedance matching unit, so as to drive the DC bias node of the local oscillator signal input terminal inside the phase detector.

[0009] Optionally, the adjustable bias unit includes: a seventh resistor, an eighth resistor, a ninth resistor, a first diode, a second diode, and a third capacitor. The first end of the seventh resistor serves as the input terminal of the adjustable bias unit, and the second end is connected to the anode of the first diode and the cathode of the second diode, respectively. The cathode of the first diode is connected to the first operating voltage via the ninth resistor, and the anode of the second diode is connected to the fourth ground terminal via the eighth resistor. The third capacitor is connected in parallel between the cathode of the first diode and the anode of the second diode. The connection node between the first diode and the second diode serves as the output terminal of the adjustable bias unit and is connected to the center tap of the LO local oscillator input transformer. The center tap is coupled to the DC bias node of the local oscillator signal input terminal inside the phase detector via the transformer.

[0010] Optionally, an isolation and filtering unit is provided between the programmable gain loop filter and the error voltage output terminal of the phase detector to filter out high-frequency noise and provide electrical isolation between the front and rear stages of the error voltage output by the phase detector, while preventing the load effect of the rear circuit from having a reverse effect on the output characteristics of the phase detector.

[0011] Optionally, the isolation and filtering unit includes: a tenth resistor, an eleventh resistor, a twelfth resistor, a fourth capacitor, a fifth capacitor, and a second operational amplifier. The error voltage output terminal of the phase detector is connected to the first terminals of the tenth and eleventh resistors, respectively. The second terminal of the tenth resistor is connected to the first terminals of the fourth and twelfth resistors, respectively. The second terminal of the fourth capacitor is connected to the fifth ground terminal. The second terminal of the eleventh resistor is connected to the sixth ground terminal via the fifth capacitor. The second terminal of the twelfth resistor is connected to the non-inverting input terminal of the first operational amplifier. The inverting input terminal and output terminal of the second operational amplifier are shorted to form a voltage follower. The output terminal of the second operational amplifier serves as the input terminal of the isolation and filtering unit and is connected to the output terminal of the programmable gain loop filter.

[0012] Optionally, the programmable gain loop filter includes: a third operational amplifier, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, and a tenth capacitor. The thirteenth resistor and the sixth capacitor are connected in series to form a first proportional product branch, connected between the inverting input and output of the third operational amplifier. The fourteenth resistor and the seventh capacitor are connected in series to form a second proportional product branch, connected between the inverting input and output of the third operational amplifier. The eighth capacitor serves as an input branch, with its first end connected to the input of the isolation and filtering unit and its second end connected to the inverting input of the third operational amplifier. The ninth capacitor serves as a ground branch, connected between the non-inverting input of the third operational amplifier and the seventh ground terminal. The fifteenth resistor and the tenth capacitor are connected in series and bridging the connection between the thirteenth resistor and the sixth capacitor and the output of the third operational amplifier. The first end of the sixteenth resistor is connected to the output of the third operational amplifier, and its second end is connected to a reference voltage.

[0013] Optionally, a voltage buffer and noise suppression unit is provided between the programmable gain loop filter and the tuning control input terminal of the voltage-controlled oscillator, for high impedance isolation, multi-stage low-pass filtering and ultra-low noise driving of the control voltage output by the programmable gain loop filter.

[0014] Optionally, the voltage buffer and noise suppression unit includes: a fourth operational amplifier, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, and a first field-effect transistor. The first terminal of the seventeenth resistor is connected to the supply voltage, and its second terminal is connected to the first terminal of the twelfth capacitor and the positive terminal of the non-inverting input of the fourth operational amplifier. The second terminal of the twelfth capacitor is connected to the eighteenth ground terminal. The drain of the first field-effect transistor is connected to the second terminal of the seventeenth resistor, its source is connected to the non-inverting input of the fourth operational amplifier, and its gate is connected to a bias voltage. The inverting input and output of the fourth operational amplifier are shorted. The first terminal of the eighteenth resistor is connected to the output of the fourth operational amplifier, and its second terminal is connected to the tenth ground terminal via the eleventh capacitor. The first terminal of the nineteenth resistor is connected to the second terminal of the eighteenth resistor, and its second terminal is connected to the ninth ground terminal and the tuning control input terminal of the voltage-controlled oscillator via the thirteenth capacitor.

[0015] Compared with the prior art, the beneficial effects of this application are as follows: 1. This application directly applies the frequency setting voltage output by the D / A converter to the DC bias node of the phase detector LO local oscillator side, which physically separates it from the phase detector IF error voltage output path, loop filter and VCO control path. This can eliminate the influence of frequency setting on core parameters such as loop gain, bandwidth and damping coefficient, ensure the stability of the dynamic performance of the phase-locked loop and greatly simplify the loop debugging process.

[0016] 2. This application abandons the traditional operational amplifier adder structure, eliminating the 1 / f noise and thermal noise introduced by the operational amplifier and its peripheral circuits from the root. By combining voltage buffer and noise suppression unit with multi-stage low-pass filtering, the phase noise of the frequency synthesizer can be reduced. The actual test results show that the output phase noise is basically the same as the reference phase noise.

[0017] 3. This application does not require increasing the setting voltage to compensate for loop gain loss. It only requires a low-voltage DC signal from the D / A output in conjunction with an adjustable bias unit to achieve accurate preset of the VCO center frequency. This avoids the circuit safety and integration difficulties caused by high-voltage bias in traditional solutions, and has good low power consumption and high integration adaptability. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the circuit structure of an existing analog phase-locked loop frequency setting circuit; Figure 2 This is a schematic diagram of another existing analog phase-locked loop frequency setting circuit. Figure 3 This is a schematic diagram of the circuit structure of a simulated phase-locked loop frequency setting circuit provided in one embodiment of this application; Figure 4 Based on Figure 3 A schematic diagram of the improved circuit structure of a simulated phase-locked loop frequency setting circuit; Figure 5 yes Figure 4 A schematic diagram of the circuit structure of the impedance matching unit; Figure 6 yes Figure 4 A schematic diagram of the circuit structure of the adjustable bias unit; Figure 7 yes Figure 4 A schematic diagram of the circuit structure of the isolation and filtering unit; Figure 8 yes Figure 4 A schematic diagram of the circuit structure of a programmable gain loop filter; Figure 9 yes Figure 4 A schematic diagram of the circuit structure of the medium voltage buffer and noise control unit; Figure 10 yes Figure 4 The actual test block diagram of the circuit shown. Detailed Implementation

[0019] Specific embodiments of this application will now be described in detail with reference to the accompanying drawings. While specific embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.

[0020] It should be noted that certain terms are used in the specification and claims to refer to specific components. Those skilled in the art will understand that different terms may be used to refer to the same component. This specification and claims do not distinguish components based on differences in terminology, but rather on differences in function. The terms "comprising" or "including" used throughout the specification and claims are open-ended and should be interpreted as "comprising but not limited to." The following descriptions in the specification are preferred embodiments for carrying out this application; however, these descriptions are for the purpose of understanding the general principles of the specification and are not intended to limit the scope of this application. The scope of protection of this application shall be determined by the appended claims.

[0021] To facilitate understanding of the embodiments of this application, the following will provide further explanation and description with reference to the accompanying drawings and specific embodiments, and the accompanying drawings do not constitute a limitation on the embodiments of this application.

[0022] Traditional analog phase-locked loop frequency setting circuits mainly include two structures: one is as follows Figure 1 The circuit shown is a voltage summing circuit based on an operational amplifier; another type is as follows: Figure 2 The circuit shown is a direct summing circuit based on a passive resistor network.

[0023] exist Figure 1 In the circuit shown, the source impedance of the phase detector is The source impedance of the D / A converter is The output voltage of this circuit can be expressed as: (1) In this circuit, the loop gain is only related to the second term in equation (1). Because it can be set... Therefore, the frequency setting circuit affects the loop gain. Furthermore, operational amplifier U1 introduces significant loop noise at high gain, making this structure less than ideal for practical applications.

[0024] exist Figure 2 In the circuit shown, the output voltage can be expressed as: (2) The loop gain is only related to the second term in equation (2), because Always less than Therefore, this circuit will also cause loop gain loss. Considering and Since the values ​​are usually small, equation (2) can be simplified to: (3) In equation (3), if in order to reduce the loss of loop gain due to frequency setting, it is necessary to make As close to 1 as possible, this will lead to Approaching 0, thus requiring a significant increase This is to maintain loop lockout. However, in practical applications, the power supply voltage range often limits the availability of such a high setpoint voltage, thus necessitating a sacrifice of loop gain.

[0025] In summary, traditional analog phase-locked loop (PLL) frequency setting circuits have the following problems: First, both circuit structures have an adverse effect on the loop gain, affecting the stability and dynamic performance of the PLL; second, the operational amplifier structure introduces additional noise, reducing the phase noise performance of the frequency synthesizer; and third, the passive resistor network structure requires a higher setting voltage under low loop gain loss conditions, which is difficult to achieve in practical applications.

[0026] Figure 3 This is a schematic diagram of the circuit structure of a simulated phase-locked loop frequency setting circuit according to an embodiment of this application, as shown below. Figure 3As shown, the circuit includes a D / A converter, a phase detector, a loop filter, and a voltage-controlled oscillator (VCO). The output of the D / A converter is connected to the DC bias node of the local oscillator signal input terminal inside the phase detector. The reference signal input terminal of the phase detector is connected to an external RF reference signal. The error voltage output terminal IF of the phase detector is connected to the input terminal of the loop filter. The output terminal of the loop filter is connected to the tuning control input terminal of the voltage-controlled oscillator.

[0027] In this embodiment, the circuit adjusts the DC operating point of the LO local oscillator by directly connecting the frequency setting voltage V2 output from the D / A converter to the DC bias node on the input side of the LO local oscillator inside the phase detector, thereby achieving precise preset of the VCO center frequency. Simultaneously, the reference signal input terminal of the phase detector is connected to an external RF reference signal, and its LO local oscillator input terminal is connected to the local oscillator signal fed back from the VCO. After comparing the phases of the two signals, the phase detector outputs an error voltage V1 from the error voltage output terminal IF. This error voltage is only connected to the input terminal of the loop filter. After smoothing and filtering by the loop filter, a voltage-controlled oscillator control voltage V0 is generated and directly fed to the tuning control input terminal of the voltage-controlled oscillator (VCO) to control its output frequency, thus forming a complete phase-locked loop. In this circuit, since the frequency setting voltage V2 no longer participates in the signal path of the loop filter and voltage-controlled oscillator (VCO) control, but instead acts directly on the DC bias node of the phase detector (LO) side, the center frequency of the VCO is changed by adjusting the DC operating point of the LO local oscillator. This physically separates the frequency setting from the phase-locked loop (PLL) control path. Therefore, adjusting the frequency setting voltage V2 does not change core parameters such as loop gain, bandwidth, and damping coefficient. This eliminates the noise introduced by traditional operational amplifier adders and avoids the impact of frequency setting on loop dynamic performance, while achieving low-voltage, high-precision frequency setting. Furthermore, since the frequency setting voltage V2 acts on the bias of the LO side, and the LO signal itself comes from the VCO output, the frequency setting voltage V2 indirectly affects the center frequency of the VCO by changing the DC operating point of the LO, but does not affect the phase detector's comparison process of phase differences, nor does it affect the output characteristics of the error voltage V1.

[0028] In summary, in traditional solutions, whether using an operational amplifier-based adder circuit or a passive resistor network-based adder circuit, the frequency setting voltage V2 must be superimposed on the error voltage V1 output by the phase detector. This inevitably causes the frequency setting voltage V2 to affect the loop gain. Figure 1 In the circuit shown, the high-gain state introduces additional noise, while... Figure 2In the circuit shown, the passive resistor causes loop gain loss, and to reduce gain loss, the frequency setting voltage V2 often needs to be significantly increased, which is severely limited in practical applications. This application, however, directly connects the frequency setting voltage V2 output from the D / A converter to the DC bias node on the LO local oscillator input side inside the phase detector. This is used only to adjust the DC operating point of the LO local oscillator, thereby achieving the preset center frequency of the voltage-controlled oscillator. Simultaneously, the error voltage V1 output from the phase detector is separately fed into the loop filter via the reference signal output terminal for filtering, generating the VCO control voltage V0 to form a phase-locked loop. Since the frequency setting voltage V2 is physically completely separated from the error voltage output terminal IF of the phase detector, the loop filter, and the VCO control path, adjusting the frequency setting voltage V2 will not change the core parameters such as loop gain, bandwidth, and damping coefficient, fundamentally eliminating the impact of frequency setting on loop dynamic performance. At the same time, this circuit abandons the traditional op-amp adder structure, eliminating the 1 / f noise and thermal noise introduced by the op-amp and its peripheral circuits at the source, and significantly reducing the phase noise of the frequency synthesizer. In addition, since there is no need to increase the setting voltage to compensate for loop gain loss, this application only requires a low-voltage DC signal (such as 0~5V) from the D / A output to achieve high-precision frequency setting, and has good low power consumption and high integration adaptability.

[0029] It should be noted that, although Figure 3 The circuit shown can solve the problems of traditional solutions, but it still has the following defects in practical applications: 1. Changes in the bias voltage on the LO side may be coupled to the error voltage output terminal IF through the incomplete isolation inside the phase detector, causing zero-point drift of the error voltage V1; 2. Impedance mismatch between the D / A converter and the DC bias node of the local oscillator signal input terminal inside the phase detector will reduce the transmission accuracy of the frequency setting voltage V2; 3. Traditional fixed-parameter loop filters are difficult to adapt to the different requirements of VCOs for locking speed and noise suppression in different frequency bands; and when the output terminal of the loop filter is directly connected to the VCO tuning input terminal, changes in the VCO input impedance will produce a load effect, affecting the stability of the control voltage V0.

[0030] To address the aforementioned problems, this application, while maintaining the core inventive concept, makes the following changes: Figure 3 The circuit structure shown has been improved, thereby enabling... Figure 3 The principle verification scheme has been improved into a low-noise, high-precision frequency synthesizer scheme that can be applied in practical engineering.

[0031] like Figure 4 As shown, compared to Figure 3The improved circuit includes: an impedance matching unit and an adjustable bias unit connected in series between the D / A converter and the phase detector; the loop filter is improved to a programmable gain loop filter; an isolation and filtering unit is provided between the programmable gain loop filter and the error voltage output terminal IF of the phase detector; and a voltage buffer and noise suppression unit is provided between the programmable gain loop filter and the tuning control input terminal of the voltage-controlled oscillator.

[0032] Below, this application combines Figures 5 to 9 The improved circuit will be described in detail.

[0033] like Figure 5 As shown, the impedance matching unit is used to achieve wideband impedance matching between the output terminal of the D / A converter and the DC bias node of the local oscillator signal input terminal inside the phase detector, and to filter out high-frequency ripple and noise in the frequency setting voltage V2. It includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first capacitor C1, a second capacitor C2, and a first inductor L1. The first end of the fourth resistor R4 and the first end of the first capacitor C1 are connected to the output terminal of the D / A converter, and the second end of the first capacitor C1 is connected to the first ground terminal GND1. The second end of the fourth resistor R4 is connected to the first end of the fifth resistor R5 and the first end of the second capacitor C2, and the second end of the second capacitor C2 is connected to the second ground terminal GND2. The second end of the fifth resistor R5 is connected to the first end of the sixth resistor R6, and the second end of the sixth resistor R6 is connected to the input terminal of the adjustable bias unit. The first end of the first inductor L1 is connected to the connection point of the fifth resistor R5 and the sixth resistor R6, and the second end is connected to the third ground terminal GND3.

[0034] In this embodiment, the impedance matching unit, through the coordinated operation of a multi-stage resistor network and a high-frequency filtering path, can achieve wideband impedance matching and noise suppression between the DC bias node of the D / A converter output and the local oscillator signal input of the phase detector. Specifically, the fourth resistor R4 and the fifth resistor R5 form a first-stage voltage divider attenuation network, responsible for reducing the impact of the source impedance at the D / A converter output on subsequent bias nodes. Simultaneously, the first capacitor C1 provides a high-frequency bypass path to filter out high-frequency ripple on V2. The second capacitor C2 and the sixth resistor R6 form an RC low-pass filter, which further smooths the DC setting voltage and suppresses noise from the D / A converter. The switching noise of the converter; the first inductor L1 is connected in parallel to the connection node of the fifth resistor R5 and the sixth resistor R6 to ground. The low DC resistance of the inductor maintains the stable transmission of the low-frequency bias voltage, while presenting high impedance at high frequencies to block high-frequency interference signals that may be coupled back from the phase detector LO side; overall, this impedance matching unit can reduce the transmission error caused by impedance mismatch through resistor voltage division, and achieve the gradual attenuation of high-frequency noise through the combination of capacitor and inductor, ensuring that the frequency setting voltage V2 is transmitted to the adjustable bias unit in a high-precision, low-ripple form, while preventing the LO signal inside the phase detector from back-polluting the output of the D / A converter.

[0035] like Figure 6 As shown, the adjustable bias unit includes a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a first diode D1, a second diode D2, and a third capacitor C3. The first end of the seventh resistor R7 serves as the input terminal of the adjustable bias unit, and the second end is connected to the anode of the first diode D1 and the cathode of the second diode D2. The cathode of the first diode D1 is connected to the first operating voltage VCC (e.g., +5V) via the ninth resistor R9, and the anode of the second diode D2 is connected to the fourth ground terminal GND4 via the eighth resistor R8. The third capacitor C3 is connected in parallel between the cathode of the first diode D1 and the anode of the second diode D2. The connection node between the first diode D1 and the second diode D2 serves as the output terminal of the adjustable bias unit and is connected to the center tap of the LO local oscillator input transformer. The center tap is coupled to the DC bias node of the local oscillator signal input terminal inside the phase detector via the transformer.

[0036] In this embodiment, the adjustable bias unit utilizes two diodes connected in series with an external resistor voltage divider network to achieve DC level shifting and stable bias output of the D / A converter output setting voltage. The frequency setting voltage V2 input from the impedance matching unit is injected through the seventh resistor R7 into the connection node between the anode of the first diode D1 and the cathode of the second diode D2. The first diode D1 is pulled up to the positive operating voltage VCC through the ninth resistor R9, and the second diode D2 is pulled down to ground through the eighth resistor R8. Thus, the forward conduction characteristics of the two diodes establish a relatively stable DC bias voltage (approximately VCC through R9) at this node. The clamping value between the potential after the voltage drop of D1 and the potential after the voltage drop of D2 via R8 is used. When V2 changes, the voltage of this node changes linearly and drives the center tap of the LO local oscillator input transformer through the low dynamic internal resistance of the first diode D1 and the second diode D2, thereby achieving precise DC bias adjustment. The third capacitor C3 is connected in parallel between the cathode and anode of the first diode D1 and the second diode D2. It is responsible for providing high-frequency AC bypass, filtering out high-frequency noise that may be introduced by VCC and the ground plane, and enhancing the AC grounding performance of the bias node to ensure that the differential symmetry of the LO local oscillator signal is not affected by the bias adjustment.

[0037] This adjustable bias unit can convert the low-voltage D / A output signal into a drive level suitable for the DC bias requirements of the phase detector's LO side, while ensuring the stability of the bias voltage and low noise characteristics.

[0038] like Figure 7 As shown, the isolation and filtering unit includes a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a fourth capacitor C4, a fifth capacitor C5, and a second operational amplifier U2. The error voltage output terminal IF of the phase detector is connected to the first terminals of the tenth resistor R10 and the eleventh resistor R11, respectively. The second terminal of the tenth resistor R10 is connected to the first terminals of the fourth capacitor C4 and the twelfth resistor R12, respectively. The second terminal of the fourth capacitor C4 is connected to the fifth ground terminal GND5. The second terminal of the eleventh resistor R11 is connected to the sixth ground terminal GND6 via the fifth capacitor C5. The second terminal of the twelfth resistor R12 is connected to the non-inverting input terminal of the first operational amplifier U1. The inverting input terminal and the output terminal of the second operational amplifier U2 are shorted to form a voltage follower. The output terminal of the second operational amplifier U2 serves as the input terminal of the isolation and filtering unit and is connected to the output terminal of the programmable gain loop filter.

[0039] In this embodiment, the isolation and filtering unit, through dual-path signal processing and voltage follower buffering, can achieve efficient filtering, noise suppression, and isolation between the phase detector IF output error voltage and the preceding and following stages. Specifically, the error voltage V1 output by the phase detector IF is split into two paths by the tenth resistor R10 and the eleventh resistor R11. The tenth resistor R10 and the fourth capacitor C4 form a first-order RC low-pass filter to filter out high-frequency noise, and then the voltage is fed to the non-inverting input of the second operational amplifier U2 via the twelfth resistor R12. The eleventh resistor R11 and the fifth capacitor C5 form a high-frequency bypass network, directly guiding fast-switching glitches or parasitic coupling signals in V1 to the sixth ground terminal GND6, preventing them from entering subsequent filtering stages. The second operational amplifier U2 is configured as a voltage follower (with the inverting input and output shorted). Its extremely high input impedance prevents the load effect of the subsequent circuit from affecting the transmission characteristics of the filter network in reverse. At the same time, its low output impedance drive capability ensures that the filtered error voltage can be transmitted to the programmable gain loop filter without attenuation. In addition, the parallel connection of the tenth resistor R10 and the eleventh resistor R11 can effectively reduce the equivalent load impedance of the phase detector IF output. Together with the fourth capacitor C4 and the fifth capacitor C5, they form a complementary filter structure, which can suppress the residual AC component coupled from the internal LO of the phase detector and the crosstalk noise introduced by the D / A bias adjustment to the maximum extent while retaining the DC component of the error voltage.

[0040] like Figure 8 As shown, the programmable gain loop filter includes a third operational amplifier U3, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, and a tenth capacitor C10. The thirteenth resistor R13 and the sixth capacitor C6 are connected in series to form a first proportional product branch, which is connected between the inverting input and output of the third operational amplifier U3. The fourteenth resistor R14 and the seventh capacitor C7 are connected in series to form a second proportional product branch, which is connected between the inverting input and output of the third operational amplifier U3. Between the output terminals; the eighth capacitor C8 serves as the input branch, with its first end connected to the input terminal of the isolation and filtering unit and its second end connected to the inverting input terminal of the third operational amplifier U3; the ninth capacitor C9 serves as the ground branch, connected between the non-inverting input terminal of the third operational amplifier U3 and the seventh ground terminal GND7; the fifteenth resistor R15 and the tenth capacitor C10 are connected in series and are connected across the connection point of the thirteenth resistor R13 and the sixth capacitor C6 and the output terminal of the third operational amplifier U3; the first end of the sixteenth resistor R16 is connected to the output terminal of the third operational amplifier U3, and the second end is connected to the reference voltage VREF.

[0041] In this embodiment, the programmable gain loop filter is based on a multi-proportional product branch parallel connection and a local compensation network, which can realize flexible gain adjustment of error voltage and optimization of loop filtering characteristics. The error voltage output from the isolation and filtering unit is AC-coupled to the inverting input of the third operational amplifier U3 via the eighth capacitor C8. The non-inverting input of the third operational amplifier U3 is grounded through the ninth capacitor C9 to filter out common-mode noise. The first proportional product branch, composed of the thirteenth resistor R13 and the sixth capacitor C6 in series, and the second proportional product branch, composed of the fourteenth resistor R14 and the seventh capacitor C7 in series, are connected in parallel between the inverting input and output of U3. Different resistors and capacitors can be selected to achieve this. The combination allows for independent adjustment of the loop gain and integral time constant, thus adapting to the varying requirements of different VCO frequency bands for lock-in speed and noise suppression. The fifteenth resistor R15 and the tenth capacitor C10 are connected in series and then bridged between the connection node of the thirteenth resistor R13 and the sixth capacitor C6 in the first proportional product branch and the output of the third operational amplifier U3, forming a local lead-lag compensation network to improve the loop's phase margin and suppress high-frequency parasitic oscillations. The sixteenth resistor R16 connects the output of the third operational amplifier U3 to the reference voltage VREF, providing a stable bias of the output DC level for the active filter, preventing the output of the third operational amplifier U3 from saturating and ensuring the normal operation of the subsequent voltage buffer unit.

[0042] Overall, this unit, through a programmable proportional-integral path and compensation network, can achieve precise filtering and gain control of the phase detector error signal, and the loop parameters can be adjusted independently without being affected by the frequency setting voltage V2.

[0043] like Figure 9As shown, the voltage buffer and noise control unit includes a fourth operational amplifier U4, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, an eleventh capacitor C11, a twelfth capacitor C12, a thirteenth capacitor C13, and a first field-effect transistor Q1. The first terminal of the seventeenth resistor R17 is connected to the supply voltage VCC, and the second terminal is connected to both the first terminal of the twelfth capacitor C12 and the positive terminal of the non-inverting input of the fourth operational amplifier U4. The second terminal of the twelfth capacitor C12 is connected to the eighteenth ground terminal GND18. The drain of the first field-effect transistor Q1 is connected to the seventeenth resistor R17. The second terminal of resistor 7 has its source connected to the non-inverting input of the fourth operational amplifier U4, and its gate connected to the bias voltage Vbias. The inverting input and output of the fourth operational amplifier U4 are shorted. The first terminal of the eighteenth resistor R18 is connected to the output of the fourth operational amplifier U4, and its second terminal is connected to the tenth ground terminal GND10 via the eleventh capacitor C11. The first terminal of the nineteenth resistor R19 is connected to the second terminal of the eighteenth resistor R18, and its second terminal is connected to the ninth ground terminal GND9 via the thirteenth capacitor C13 and to the tuning control input of the voltage-controlled oscillator VCO.

[0044] In this embodiment, the voltage buffer and noise control unit achieves high-precision transmission and ultra-low noise drive of the output control voltage of the programmable gain loop filter through field-effect transistor isolation, operational amplifier follower, and multi-stage RC filtering. The control voltage from the programmable gain loop filter is sent to the control unit through the nineteenth resistor R19, and high-frequency ripple is first filtered out by the thirteenth capacitor C13. The fourth operational amplifier U4 is configured as a voltage follower (the inverting input and output are shorted), and its non-inverting input is driven by the source of the first field-effect transistor Q1. The drain of the first field-effect transistor Q1 is connected to the supply voltage VCC through the seventeenth resistor R17, and the gate is connected to the bias voltage Vbias. The ultra-high input impedance characteristic of the FET is used to minimize the current noise between the front-end circuit and the input of the operational amplifier. Meanwhile, the twelfth capacitor C12 decouples the FET drain power supply to suppress power supply noise coupling; the output of the fourth operational amplifier U4 is first filtered by a first-order RC low-pass filter network composed of the eighteenth resistor R18 and the eleventh capacitor C11, and then second filtered by a second-order RC low-pass filter network composed of the nineteenth resistor R19 and the thirteenth capacitor C13, further attenuating the broadband noise generated by the operational amplifier itself and the residual interference from the power supply; finally, the control voltage after two stages of filtering is sent to the tuning control input of the voltage-controlled oscillator (VCO) through the tuning controller to ensure that the VCO obtains a tuning voltage with extremely low noise, thereby improving the phase noise performance and frequency stability of the output signal.

[0045] Figure 10This paper presents a practical test block diagram of a novel analog phase-locked loop (PLL) frequency setting circuit proposed in this application. This circuit is used to verify the core inventive concept of a "D / A bias phase detector, op-amp-less adder," and can effectively evaluate the impact of the frequency setting method on PLL performance. The specific connection method of this test circuit is as follows: A 100MHz crystal oscillator output is connected to the reference signal input of the analog phase detector, providing a stable 100MHz reference clock for the phase-locked loop (PLL). The D / A converter output generates a 2V frequency setting voltage, which is directly connected to the DC bias adjustment node inside the analog phase detector. The error voltage output of the analog phase detector is connected to the input of the loop filter, sending the error signal generated after phase comparison to the loop filter for filtering. The output of the loop filter is connected to the tuning control input of a 100MHz VCO, adjusting the VCO's output frequency by controlling the voltage. The VCO output is connected to the input of a power divider, which splits the signal into two paths: one path is fed back to the local oscillator input of the analog phase detector, forming a closed-loop PLL; the other path serves as a 100MHz output signal for external testing.

[0046] Through the above connection, the test circuit can fully realize the goal of the frequency setting voltage acting only on the phase detector LO side bias and not participating in the loop filter and VCO control path, thereby verifying the technical advantages of this application in eliminating operational amplifier noise, decoupling loop parameters and frequency setting, and realizing low-voltage high-precision frequency setting.

[0047] In addition, it should be noted that, Figure 10 In this circuit, the phase detector used is the SENERGY PDZ-K2, with a gain of 0.675V / RAD. The VCO is the RF POS-100, with a voltage-controlled sensitivity of 7.8MHz / V. The loop filter is a passive proportional-integral filter, with a series resistor of 150Ω and a parallel resistor of 150Ω, and an integrating capacitor of 1000pF. The calculated natural resonant frequency of the loop is fn = 1.6MHz, and the damping coefficient is 0.859. After loop locking, the phase noise performance test results are shown in Table 1. Table 1. Test results of phase noise performance in the simulated loop experiment (dBc / Hz)

[0048] As shown in Table 1, the test data indicates that the simulated phase-locked loop frequency setting circuit provided in this application does not cause any loss in phase noise performance, and the setting circuit does not affect the loop parameters and loop gain.

[0049] In summary, through methods such as Figures 4 to 9 The improvements shown in this application enable the following technical effects: 1. Completely eliminate operational amplifier noise interference: Abandon the frequency setting architecture of traditional operational amplifier adders, and use the V2 signal output by D / A only to adjust the bias of the phase detector LO local oscillator, without participating in the signal transmission of the phase-locked loop control path. This eliminates the 1 / f noise and thermal noise introduced by the operational amplifier and its peripheral circuits from the source, and significantly reduces the phase noise of the frequency synthesizer.

[0050] 2. Achieve complete decoupling between loop parameters and frequency settings: The frequency setting circuit and the phase-locked loop control path are electrically separated through isolation resistors, buffer units, etc. Modifying V2 only adjusts the LO local oscillator bias and will not change parameters such as loop gain, bandwidth, and damping, ensuring the stability of the dynamic performance of the phase-locked loop and simplifying the loop debugging process.

[0051] 3. Achieve low-voltage, high-precision, wide-range frequency setting: By outputting a low-voltage DC signal (0~5V) through a D / A converter and working with an adjustable bias unit, the VCO center frequency can be accurately preset, avoiding the circuit safety and integration difficulties caused by high-voltage bias in traditional solutions, and adapting to the application requirements of low-power, highly integrated frequency synthesizers.

[0052] 4. Enhanced loop filtering and noise suppression capabilities: The programmable gain loop filter adapts to multi-band requirements, and the voltage buffer and noise suppression unit further optimizes the signal quality of the VCO control path, improving the locking speed, anti-interference capability, and long-term stability of the output frequency of the phase-locked loop.

[0053] The above embodiments are only for illustrating the technical concept and features of this application, and are intended to enable those skilled in the art to understand the content of this application and implement it accordingly. They should not be construed as limiting the scope of protection of this application. All equivalent changes or modifications made in accordance with the spirit and essence of this application should be included within the scope of protection of this application.

Claims

1. An analog phase-locked loop frequency setting circuit, comprising: The circuit includes: The components include a D / A converter, a phase detector, a programmable gain loop filter, and a voltage-controlled oscillator. The output of the D / A converter is connected to the DC bias node of the local oscillator signal input terminal inside the phase detector; The error voltage output of the phase detector is connected to the input of the programmable gain loop filter, and the output of the programmable gain loop filter is connected to the tuning control input of the voltage-controlled oscillator.

2. The circuit according to claim 1, characterized in that, A connection is provided between the D / A converter and the phase detector: Impedance matching unit is used to achieve wideband impedance matching between the output of the D / A converter and the DC bias node of the local oscillator signal input in the phase detector, and to filter out high-frequency ripple and noise in the frequency setting voltage output by the D / A converter.

3. The circuit according to claim 2, characterized in that, The impedance matching unit includes: The fourth resistor, the fifth resistor, the sixth resistor, the first capacitor, the second capacitor, and the first inductor, wherein, The first end of the fourth resistor and the first end of the first capacitor are both connected to the output terminal of the D / A converter, and the second end of the first capacitor is connected to the first ground terminal. The second end of the fourth resistor is connected to the first end of the fifth resistor and the first end of the second capacitor, and the second end of the second capacitor is connected to the second ground terminal. The second end of the fifth resistor is connected to the first end of the sixth resistor, and the second end of the sixth resistor is connected to the input of the adjustable bias unit. The first end of the first inductor is connected to the junction of the fifth and sixth resistors, and the second end is connected to the third ground terminal.

4. The circuit according to claim 2, characterized in that, The impedance matching unit and the phase detector are provided with the following: The adjustable bias unit is used to shift and stabilize the frequency setting voltage after noise is filtered out by the impedance matching unit, so as to drive the DC bias node of the local oscillator signal input terminal inside the phase detector.

5. The circuit according to claim 4, characterized in that, The adjustable bias unit includes: The seventh resistor, the eighth resistor, the ninth resistor, the first diode, the second diode, and the third capacitor, among which, The first end of the seventh resistor serves as the input terminal of the adjustable bias unit, and the second end is connected to the anode of the first diode and the cathode of the second diode, respectively. The cathode of the first diode is connected to the first operating voltage via the ninth resistor, and the anode of the second diode is connected to the fourth ground terminal via the eighth resistor. The third capacitor is connected in parallel between the cathode of the first diode and the anode of the second diode; The connection node between the first diode and the second diode serves as the output terminal of the adjustable bias unit, which is connected to the center tap of the LO local oscillator input transformer. This center tap is coupled to the DC bias node of the local oscillator signal input terminal inside the phase detector via the transformer.

6. The circuit according to claim 1, characterized in that, An isolation and filtering unit is provided between the programmable gain loop filter and the error voltage output terminal of the phase detector. This unit is used to filter out high-frequency noise and provide electrical isolation between the phase detector and the preceding and following stages for the error voltage output by the phase detector. At the same time, it prevents the load effect of the following stage circuit from having a reverse effect on the output characteristics of the phase detector.

7. The circuit according to claim 6, characterized in that, The isolation and filtering unit includes: The tenth resistor, eleventh resistor, twelfth resistor, fourth capacitor, fifth capacitor, and second operational amplifier, wherein, The error voltage output terminal of the phase detector is connected to the first terminal of the tenth resistor and the first terminal of the eleventh resistor, respectively. The second end of the tenth resistor is connected to the first end of the fourth capacitor and the first end of the twelfth resistor, respectively. The second end of the fourth capacitor is connected to the fifth ground terminal. The second end of the eleventh resistor is connected to the sixth grounding terminal via the fifth capacitor; The second end of the twelfth resistor is connected to the non-inverting input of the first operational amplifier. The inverting input of the second operational amplifier and its output are shorted to form a voltage follower. The output of the second operational amplifier is connected to the output of the programmable gain loop filter as the input of the isolation and filtering unit.

8. The circuit according to claim 7, characterized in that, The programmable gain loop filter includes: The third operational amplifier, the thirteenth resistor, the fourteenth resistor, the fifteenth resistor, the sixteenth resistor, the sixth capacitor, the seventh capacitor, the eighth capacitor, the ninth capacitor, and the tenth capacitor, among which, The thirteenth resistor and the sixth capacitor are connected in series to form the first proportional product branch, which is connected between the inverting input and output of the third operational amplifier. The fourteenth resistor and the seventh capacitor are connected in series to form the second proportional product branch, which is connected between the inverting input and output of the third operational amplifier. The eighth capacitor serves as the input branch, with its first end connected to the input terminal of the isolation and filtering unit and its second end connected to the inverting input terminal of the third operational amplifier. The ninth capacitor serves as a grounding branch, connected between the non-inverting input of the third operational amplifier and the seventh grounding terminal. The fifteenth resistor and the tenth capacitor are connected in series and are connected across the connection point of the thirteenth resistor and the sixth capacitor and the output terminal of the third operational amplifier. The first end of the sixteenth resistor is connected to the output of the third operational amplifier, and the second end is connected to the reference voltage.

9. The circuit according to claim 1, characterized in that, A connection is provided between the programmable gain loop filter and the tuning control input of the voltage-controlled oscillator: The voltage buffer and noise suppression unit is used to perform high impedance isolation, multi-stage low-pass filtering, and ultra-low noise driving on the control voltage output by the programmable gain loop filter.

10. The circuit according to claim 9, characterized in that, The voltage buffer and noise suppression unit includes: The fourth operational amplifier, the seventeenth resistor, the eighteenth resistor, the nineteenth resistor, the eleventh capacitor, the twelfth capacitor, the thirteenth capacitor, and the first field-effect transistor, wherein, The first end of the seventeenth resistor is connected to the power supply voltage, and the second end is connected to the first end of the twelfth capacitor and the positive terminal of the non-inverting input of the fourth operational amplifier, respectively. The second end of the twelfth capacitor is connected to the eighteenth ground terminal. The drain of the first field-effect transistor is connected to the second terminal of the seventeenth resistor, the source is connected to the non-inverting input terminal of the fourth operational amplifier, and the gate is connected to the bias voltage. The inverting input and output of the fourth operational amplifier are shorted; the first end of the eighteenth resistor is connected to the output of the fourth operational amplifier, and the second end is connected to the tenth ground terminal via the eleventh capacitor. The first end of the nineteenth resistor is connected to the second end of the eighteenth resistor. The second end of the nineteenth resistor is connected to the ninth ground terminal and the tuning control input terminal of the voltage-controlled oscillator via the thirteenth capacitor.

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