Low noise driving and detecting circuit and method for quartz beam accelerometer

Abstract

The application discloses a quartz vibrating beam acceleration sensor low-noise driving and detecting circuit and method. The circuit comprises a high-frequency oscillation signal generation module, a logic frequency division module, a time measurement module and a power supply filtering isolation module. The high-frequency oscillation signal generation module generates a high-frequency square wave signal, and the logic frequency division module performs integer frequency division on the high-frequency square wave signal to obtain a low-frequency square wave driving signal. The low-frequency driving signal retains the phase noise characteristics of the high-frequency signal, and the phase noise spectral density of the low-frequency driving signal is reduced relative to the high-frequency signal after the integer frequency division processing. The power supply filtering isolation module has a power supply filtering isolation structure between the power supply ports of the logic frequency division module, and the time measurement module has an independent clock source and an independent power supply link. The application reduces the phase noise of the driving signal through the cooperative design of high-frequency oscillation and integer frequency division, and suppresses mutual interference through power supply isolation and clock isolation, thereby effectively improving the measurement accuracy and stability of the quartz vibrating beam acceleration sensor.

Description

Technical Field

[0001] This invention relates to the field of quartz beam accelerometer technology, and more particularly to a low-noise driving and detection circuit and method for quartz beam accelerometers. Background Technology

[0002] Quartz beam accelerometers are widely used in aerospace, inertial navigation, and precision measurement fields due to their high precision, high stability, and excellent long-term reliability. The core sensing element of a quartz beam accelerometer is the quartz beam. Its working principle involves using the inertial force caused by acceleration to change the resonant frequency of the quartz beam, and calculating the acceleration value by detecting the frequency shift.

[0003] In the driving and detection system of a quartz beam accelerometer, the phase noise level of the driving signal directly affects the resonant stability and frequency detection accuracy of the quartz beam. Existing technologies suffer from the following technical problems: First, direct low-frequency oscillation schemes struggle to achieve sufficiently low phase noise at the quartz beam's resonant frequency. Second, the shared power network between the logic divider module and the high-frequency oscillation module leads to transient noise coupling during switching. Third, the lack of clock and power isolation between the time measurement module and the driving module results in mutual interference between the measurement clock and the driving clock. Therefore, reducing the phase noise of the quartz beam accelerometer's driving signal, suppressing power noise coupling and clock interference, and improving frequency detection accuracy have become pressing technical problems to be solved in this field. Summary of the Invention

[0004] The purpose of this invention is to provide a low-noise driving and detection circuit and method for a quartz vibrating beam accelerometer, thereby solving the aforementioned problems existing in the prior art.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] In a first aspect, this application provides a low-noise driving and detection circuit for a quartz vibrating beam accelerometer, comprising:

[0007] A high-frequency oscillation signal generation module is used to generate a first high-frequency square wave signal;

[0008] The logic frequency divider module has its signal input terminal connected to the signal output terminal of the high-frequency oscillation signal generation module. It is used to perform integer frequency division processing on the first high-frequency square wave signal to obtain the second low-frequency square wave drive signal. The frequency of the first high-frequency square wave signal is higher than the frequency of the second low-frequency square wave drive signal.

[0009] The quartz vibrating beam acceleration sensing module has its drive signal input terminal connected to the signal output terminal of the logic frequency divider module, which is used to receive the second low-frequency square wave drive signal and generate a high-frequency vibration frequency signal.

[0010] The time measurement module, whose signal input terminal is connected to the output terminal of the quartz vibrating beam acceleration sensing module, is used to measure the period of the high-frequency vibration signal;

[0011] The power supply filtering and isolation module has its output connected to the power supply terminal of the high-frequency oscillation signal generation module, and its input connected to the system's main power supply.

[0012] The logic frequency divider module is configured to divide the first high-frequency square wave signal by an integer frequency division ratio N greater than 1 to obtain the second low-frequency square wave driving signal. The second low-frequency square wave driving signal retains the phase noise characteristics of the first high-frequency square wave signal, and the phase noise spectral density of the second low-frequency square wave driving signal is reduced by 20logN dB compared with the phase noise spectral density of the first high-frequency square wave signal.

[0013] In one possible implementation, the logic divider module includes a programmable divider with a division ratio of an integer N greater than 1.

[0014] In one possible implementation, the high-frequency oscillation signal generation module has a two-channel independent structure, which generates a first-channel high-frequency oscillation signal and a second-channel high-frequency oscillation signal respectively.

[0015] The logic frequency divider module is a programmable logic device. The programmable logic device divides the high-frequency oscillation signal of the first channel into a first low-frequency square wave drive signal and divides the high-frequency oscillation signal of the second channel into a second low-frequency square wave drive signal, so as to drive the two quartz beam acceleration sensing modules respectively to form a differential detection architecture.

[0016] In one possible implementation, the programmable logic device has a separate power input pin; the power input pin of the programmable logic device is connected to a power filter network, and the ground terminal of the power filter network is separated from the power ground of the programmable logic device by a physical isolation strip.

[0017] In one possible implementation, the power filtering and isolation module includes a first-stage DC-DC converter circuit and a ferrite bead filter circuit. The input of the first-stage DC-DC converter circuit is connected to the main power supply of the system, and the output is connected to the input of the ferrite bead filter circuit. The output of the ferrite bead filter circuit is connected to the power supply of the PLL regulator of the programmable logic device.

[0018] The ferrite bead filter circuit is configured to suppress the current ripple at the switching transient frequency of the logic divider module, and the power traces of the power supply filter isolation module to the high-frequency oscillation signal generation module and the power traces to the logic divider module are independent of each other in the printed circuit board layout and do not share the same power plane.

[0019] In one possible implementation, the power supply filtering and isolation module also includes a second-stage low-dropout linear regulator circuit. The second-stage low-dropout linear regulator circuits of the two high-frequency oscillation signal generation circuits are completely independent, reducing the impact of power supply interference on the high-frequency oscillation signals.

[0020] In one possible implementation, the high-frequency oscillation signal generation module includes a crystal resonant oscillation unit and a waveform shaping output unit;

[0021] The crystal resonant oscillation unit is used to generate an initial oscillation signal based on a quartz crystal oscillator;

[0022] The waveform shaping output unit is connected to the output terminal of the quartz crystal oscillator unit and is used to shape the initial oscillation signal into a first high-frequency square wave signal.

[0023] In one possible implementation, the crystal resonant oscillation unit includes a first inverter, a feedback resistor, a quartz crystal, and a first capacitor;

[0024] A feedback resistor is connected between the input and output of the first inverter, a first capacitor is connected between the input of the first inverter and ground, and the input and output of the first inverter are respectively connected to the two pins of the quartz crystal.

[0025] The waveform shaping output unit includes a Schmitt inverter. The input terminal of the Schmitt inverter is connected to the output terminal of the first inverter, and the output terminal of the Schmitt inverter serves as the output terminal of the first high-frequency square wave signal.

[0026] In one possible implementation, the time measurement module includes a time-to-digital converter chip and a local clock oscillator;

[0027] The measurement signal input terminal of the time-to-digital converter chip is connected to the signal output terminal of the quartz vibrating beam acceleration sensor module;

[0028] The clock input of the time-to-digital converter chip is connected to the output of the local clock oscillator. The local clock oscillator and the high-frequency oscillation signal generation module have independent clock sources and independent power supply links.

[0029] The second aspect of this application provides a low-noise driving and detection method for a quartz vibrating beam accelerometer, comprising the following steps:

[0030] The power supply filtering and isolation module supplies power to the high-frequency oscillation signal generation module, driving the high-frequency oscillation signal generation module to generate a first high-frequency square wave signal. There is a power supply filtering and isolation structure between the power supply ports of the power supply filtering and isolation module and the logic frequency divider module. The power supply traces of the power supply filtering and isolation module supplying power to the high-frequency oscillation signal generation module and the power supply traces supplying power to the logic frequency divider module are independent of each other in the printed circuit board layout and do not share the same power plane.

[0031] The first high-frequency square wave signal is divided by an integer using a logic frequency divider module to obtain a second low-frequency square wave driving signal. The second low-frequency square wave driving signal retains the phase noise characteristics of the first high-frequency square wave signal. After integer frequency division, the phase noise spectral density of the second low-frequency square wave driving signal is reduced by 20logN dB compared to the phase noise spectral density of the first high-frequency square wave signal, where N is the integer frequency division ratio.

[0032] The second low-frequency square wave drive signal is input to the quartz vibrating beam acceleration sensing module to drive the quartz vibrating beam to a resonant state.

[0033] The high-frequency vibration signal output by the quartz vibrating beam acceleration sensor module is acquired.

[0034] The period of the high-frequency vibration signal is measured by the time measurement module, and the frequency offset is calculated. The time measurement module has an independent clock source and an independent power supply link to isolate the mutual interference between the measurement clock and the drive clock.

[0035] The acceleration value is calculated based on the frequency offset.

[0036] The beneficial effects of this invention are:

[0037] This application uses a high-frequency oscillation signal generation module to generate a high-frequency square wave signal, and then uses a logic frequency divider module to perform integer frequency division to obtain a low-frequency square wave drive signal. Since integer frequency division has a suppressive effect on phase noise, the phase noise spectral density of the low-frequency drive signal is significantly reduced compared to the high-frequency source signal, thereby obtaining a drive signal with lower phase noise at the resonant frequency of the quartz vibrating beam, improving resonance stability and frequency detection accuracy.

[0038] This application supplies power to the high-frequency oscillation signal generation module through a power supply filtering and isolation module, and sets a power supply filtering and isolation structure between the power supply ports of the power supply filtering and isolation module and the logic frequency divider module. This effectively blocks the coupling path of the switching transient noise of the logic frequency divider module to the high-frequency oscillation signal generation module through the power network, and further purifies the spectral purity of the drive signal.

[0039] This application configures the time measurement module to have an independent clock source and an independent power supply link, so that the measurement clock and the driving clock are isolated from each other, avoiding mutual interference caused by power sharing or clock pull, thereby improving the accuracy and stability of frequency period measurement.

[0040] In the implementation using a dual-channel differential detection architecture, two independent high-frequency oscillation and frequency division channels drive two quartz vibrating beam acceleration sensing modules respectively. Combined with the power supply filtering network and physical isolation band design of the programmable logic device, common-mode interference and crosstalk between channels are effectively suppressed, improving the common-mode rejection ratio and overall measurement reliability of the system. Attached Figure Description

[0041] Figure 1 This application provides a structural block diagram of a low-noise driving and detection circuit for a quartz vibrating beam accelerometer.

[0042] Figure 2 A schematic diagram of a high-frequency drive signal generation circuit and a high-precision power supply filtering and isolation circuit provided in the embodiments of this application;

[0043] Figure 3 A schematic diagram of a logic frequency divider circuit provided in an embodiment of this application;

[0044] Figure 4 A schematic diagram of the power supply section of a logic frequency divider circuit and the debugging and testing port of the circuit provided in an embodiment of this application;

[0045] Figure 5 A schematic diagram of a frequency signal measurement circuit and an SPI communication port provided in an embodiment of this application;

[0046] Figure 6 This is a flowchart illustrating a low-noise driving and detection method for a quartz vibrating beam accelerometer, as provided in an embodiment of this application. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0048]

Implementation Method 1: Overall Circuit Architecture

[0049] Reference Figures 1 to 5 The embodiment shown provides an overall architecture for a low-noise driving and detection circuit for a quartz beam accelerometer. This circuit includes a high-frequency oscillation signal generation module, a logic frequency division module, a quartz beam accelerometer sensing module, a time measurement module, and a power supply filtering and isolation module.

[0050] A high-frequency oscillation signal generation module is used to generate a first high-frequency square wave signal. In this embodiment, the high-frequency oscillation signal generation module uses a quartz crystal oscillator circuit to generate a first high-frequency square wave signal with a frequency of approximately 32.768MHz. This high-frequency square wave signal has a low phase noise floor, providing a high-quality clock source for subsequent integer frequency division.

[0051] The signal input terminal of the logic frequency divider module is connected to the signal output terminal of the high-frequency oscillation signal generation module. The logic frequency divider module is configured to perform integer frequency division processing on the first high-frequency square wave signal with an integer division ratio N greater than 1 to obtain a second low-frequency square wave drive signal. The frequency of the second low-frequency square wave drive signal is equal to the frequency of the first high-frequency square wave signal divided by the integer division ratio N. For example, when the frequency of the first high-frequency square wave signal is 32.768MHz and the division ratio N=1000, the frequency of the second low-frequency square wave drive signal is 32.768kHz.

[0052] According to the phase noise theory of integer frequency division, the second low-frequency square wave driving signal retains the phase noise characteristics of the first high-frequency square wave signal, and the phase noise spectral density of the second low-frequency square wave driving signal is reduced by 20logN dB compared to the phase noise spectral density of the first high-frequency square wave signal. Taking N=1000 as an example, the phase noise spectral density is reduced by 60dB. This means that at a frequency offset of 1kHz from the carrier, if the phase noise of the high-frequency source signal is -100dBc / Hz, the phase noise of the frequency-divided low-frequency driving signal at the corresponding frequency offset will be improved to -160dBc / Hz, thereby obtaining a driving signal with extremely low phase noise at the resonant frequency of the quartz beam.

[0053] The drive signal input terminal of the quartz beam accelerometer module is connected to the signal output terminal of the logic frequency divider module to receive the second low-frequency square wave drive signal and generate a high-frequency vibration frequency signal. The quartz beam accelerometer module contains a quartz beam, which generates stable mechanical resonance under the excitation of the second low-frequency square wave drive signal. When external acceleration is applied to the quartz beam, its resonant frequency shifts proportional to the acceleration.

[0054] The signal input terminal of the time measurement module is connected to the output terminal of the quartz vibrating beam acceleration sensing module to measure the period of the high-frequency vibration signal. The time measurement module has an independent clock source and an independent power supply link, which isolates the measurement clock domain from the driving clock domain, avoiding measurement errors caused by clock traction and power supply noise coupling.

[0055] The output of the power supply filtering and isolation module is connected to the power supply terminal of the high-frequency oscillation signal generation module, while the input of the power supply filtering and isolation module is connected to the system's main power supply. A power supply filtering and isolation structure exists between the power supply ports of the power supply filtering and isolation module and the logic frequency divider module, effectively blocking the coupling path of the switching transient noise generated by the logic frequency divider module to the high-frequency oscillation signal generation module through the power network.

[0056] Through the synergistic design of high-frequency oscillation and integer frequency division, this embodiment obtains a driving signal with lower phase noise than the direct low-frequency oscillation scheme at the resonant frequency of the quartz beam. At the same time, the mutual interference between modules is suppressed through power supply isolation and clock isolation, effectively improving the measurement accuracy and stability of the quartz beam accelerometer.

[0057]

Implementation Method 2: Programmable Frequency Divider

[0058] The logic frequency divider module includes a programmable frequency divider, and the division ratio of the programmable frequency divider is an integer N greater than 1.

[0059] In this embodiment, the programmable frequency divider is integrated into a programmable logic device. The programmable logic device can be a complex programmable logic device or a field-programmable gate array (FPGA). The programmable frequency divider implements integer frequency division logic using a hardware description language, and its division ratio N can be flexibly set through programming configuration.

[0060] The programmable frequency divider receives a first high-frequency square wave signal from the high-frequency oscillation signal generation module and internally performs N-fold frequency division using a counter chain. Specifically, the output signal flips once each time the counter reaches N-1, thus achieving N-fold frequency division of the input high-frequency square wave signal. Since the frequency division process is integer-wise, it does not introduce spurious components of fractional-wise division, resulting in a low-frequency square wave drive signal with clean spectral characteristics.

[0061] The division ratio N of the programmable frequency divider can be configured according to the resonant frequency requirements of the quartz beam accelerometer module. For example, when the resonant frequency of the quartz beam is approximately 32kHz, if the high-frequency oscillation signal generation module generates a high-frequency square wave signal of 32.768MHz, the division ratio N can be configured to 1000 to obtain a low-frequency square wave drive signal of 32.768kHz, which precisely matches the resonant frequency of the quartz beam.

[0062] By employing a programmable frequency divider, this implementation method enables flexible configuration of the division ratio, allowing the same circuit hardware platform to adapt to quartz beam accelerometers with different resonant frequencies, thereby improving the circuit's versatility and scalability.

[0063]

Implementation Method 3: Dual-Channel Differential Detection Architecture

[0064] This embodiment provides a dual-channel differential detection architecture. The high-frequency oscillation signal generation module has two independent structures, generating a first-channel high-frequency oscillation signal and a second-channel high-frequency oscillation signal respectively.

[0065] Specifically, the first channel high-frequency oscillation signal is generated by a crystal resonant oscillation unit and a waveform shaping output unit, including a first inverter, a first quartz crystal, a first feedback resistor group, a first load capacitor group, and a first Schmitt inverter. The second channel high-frequency oscillation signal is generated by a second inverter, a second quartz crystal, a second feedback resistor group, a second load capacitor group, and a second Schmitt inverter. The two high-frequency oscillation circuits are completely independent in physical structure and are powered by independent low-dropout linear regulators to avoid power supply crosstalk between channels.

[0066] The logic divider module is a programmable logic device (PLD). The PLD receives a first-channel high-frequency oscillation signal and a second-channel high-frequency oscillation signal. Internally, the PLD integrates two independent programmable dividers: one divides the first-channel high-frequency oscillation signal into a first-channel low-frequency square wave drive signal, and the other divides the second-channel high-frequency oscillation signal into a second-channel low-frequency square wave drive signal.

[0067] The first and second low-frequency square wave drive signals drive the first and second quartz beam accelerometer modules, respectively, forming a differential detection architecture. In this architecture, the two quartz beam accelerometers are installed in opposite directions. When subjected to the same acceleration, the resonant frequency of one sensor increases while that of the other decreases. This frequency differential output effectively cancels out common-mode interference, significantly improving the system's measurement accuracy and common-mode rejection ratio.

[0068] Programmable logic devices also have independent power input pins and independent power filtering networks, which further suppress common-mode interference and crosstalk between channels.

[0069]

Implementation Method 4: Power Supply Filtering and Physical Isolation of Programmable Logic Devices

[0070] This embodiment provides a detailed description of the power supply structure for programmable logic devices.

[0071] Programmable logic devices have independent power input pins, including input / output power pins and analog power pins. These power pins are connected to independent power filter networks to provide filtered, clean power to different functional modules within the programmable logic device.

[0072] Specifically, the system's main power supply, after being filtered by a ferrite bead, is connected to the power supply terminal of the phase-locked loop regulator of the programmable logic device. The ferrite bead and the filter capacitor form a π-type filter network, which effectively suppresses high-frequency noise.

[0073] The ground terminal of the power supply filter network is physically separated from the power ground of the programmable logic device (PLD). In printed circuit board layout design, the physical isolation band is a narrow, copper-free area reserved between the ground copper foil of the power supply filter network and the power ground copper foil of the PLD, or a ground isolation trench is set between the two. The physical isolation band prevents noise current from directly coupling to the sensitive analog circuitry of the PLD through the ground plane, ensuring that the effective suppression of switching transient noise by the power supply filter network is not bypassed by ground plane noise.

[0074] Through the above-mentioned independent power input pin configuration, power filtering network, and physical isolation band design, this implementation effectively suppresses the transmission of digital switching noise inside the programmable logic device to the high-frequency oscillation signal generation module, while also suppressing common-mode interference between channels in the dual-channel architecture.

[0075]

Implementation Method 5: Multi-stage filtering and PCB layout isolation of power supply filtering and isolation modules

[0076] This embodiment provides a detailed description of the structure of the power supply filtering and isolation module.

[0077] The power supply filtering and isolation module includes a first-stage DC-DC conversion circuit and a ferrite bead filter circuit. In this embodiment, the first-stage DC-DC conversion circuit is implemented by a DC-DC conversion chip. The DC-DC conversion chip converts the system's main power supply into an intermediate power supply, which is the first-stage voltage conversion.

[0078] The ferrite bead filter circuit includes a ferrite bead. The system's main power supply, after being filtered by the ferrite bead, is connected to the power supply terminal of the phase-locked loop regulator of the programmable logic device. The impedance-frequency characteristic of the ferrite bead is configured to present high impedance at the switching transient frequency of the logic divider module, thereby effectively suppressing current ripple at that frequency. For example, if the switching transient frequency of the logic divider module is approximately tens to hundreds of MHz, a ferrite bead with several hundred ohms of impedance in that frequency band is selected.

[0079] Furthermore, the power supply traces from the power filtering and isolation module to the high-frequency oscillation signal generation module and to the logic divider module are independent of each other on the printed circuit board layout and do not share the same power plane. Specifically, the two circuits of the high-frequency oscillation signal generation module are powered by independent low-dropout linear regulators. Although the inputs of both low-dropout linear regulators are connected to the system main power supply, their respective power supply traces are independent traces on the printed circuit board and do not share the power plane with other modules. The power supply for the logic divider module is provided through independent traces filtered by ferrite beads. This physical isolation design of the power supply traces blocks the coupling path of noise through the power plane, ensuring that each module receives a clean power supply.

[0080]

Implementation Method Six: Independent Design of the Second-Stage Low-Dropout Linear Regulator Circuit

[0081] This embodiment provides a detailed description of the second-stage low-dropout linear regulator circuit in the power supply filtering and isolation module.

[0082] The power supply filtering and isolation module also includes a second-stage low-dropout linear regulator circuit. In this embodiment, the second-stage low-dropout linear regulator circuit is implemented by a first low-dropout linear regulator and a second low-dropout linear regulator.

[0083] For the first channel high-frequency oscillation signal generation circuit, the system main power supply is connected to the input terminal of the first low-dropout linear regulator; the ground terminal of the first low-dropout linear regulator is connected to ground; the input terminal of the first low-dropout linear regulator is connected to the input filter capacitor; the output terminal of the first low-dropout linear regulator is connected to the output filter capacitor, and simultaneously outputs power specifically for the first channel clock oscillation circuit.

[0084] For the second channel high-frequency oscillation signal generation circuit, the system main power supply is connected to the input terminal of the second low-dropout linear regulator; the ground terminal of the second low-dropout linear regulator is connected to ground; the input terminal of the second low-dropout linear regulator is connected to the input filter capacitor; the output terminal of the second low-dropout linear regulator is connected to the output filter capacitor, and simultaneously outputs power specifically for the second channel clock oscillation circuit.

[0085] The second-stage low-dropout linear regulator circuits of the two high-frequency oscillation signal generation circuits are completely independent in physical structure and electrical connection. Each low-dropout linear regulator has an independent input filter capacitor, an independent output filter capacitor, and an independent power supply trace. This completely independent design ensures that power fluctuations in one high-frequency oscillation signal generation circuit will not couple to the other through the power network, thereby reducing the impact of power supply interference on the high-frequency oscillation signal, ensuring the stability and consistency of the two high-frequency oscillation signals, and providing a high-quality clock source for subsequent differential detection.

[0086]

Implementation Method Seven: Two-Stage Structure of High-Frequency Oscillation Signal Generation Module

[0087] This embodiment provides a detailed description of the internal structure of the high-frequency oscillation signal generation module.

[0088] The high-frequency oscillation signal generation module includes a crystal resonant oscillation unit and a waveform shaping output unit.

[0089] The crystal resonant oscillation unit is used to generate an initial oscillation signal based on a quartz crystal. Taking the first channel as an example, the crystal resonant oscillation unit includes a first inverter, a first feedback resistor, a first quartz crystal, and a first load capacitor bank. The second pin of the first inverter is connected to the first feedback resistor, the second pin of the first quartz crystal, and the first load capacitor, with the other end of the first load capacitor connected to ground; the third pin of the first inverter is connected to ground; the other end of the first feedback resistor is connected to the fourth pin of the first inverter, the second feedback resistor, and the second pin of the first Schmitt trigger inverter; the other end of the second feedback resistor is connected to the sixth pin of the first quartz crystal and the second load capacitor, with the other end of the second load capacitor connected to ground; the fifth pin of the first inverter is connected to the output terminal of the first low-dropout linear regulator and the third load capacitor, with the other end of the third load capacitor connected to ground.

[0090] The first inverter, the first feedback resistor, the first quartz crystal, and the first load capacitor bank constitute the Pierce oscillator circuit. The first feedback resistor is connected between the input and output terminals of the first inverter, providing DC bias to the inverter and enabling it to operate in the linear amplification region. The first quartz crystal is connected between the input and output terminals of the first inverter, utilizing the piezoelectric effect and high frequency selectivity of the quartz crystal to generate a stable mechanical resonance at a specific frequency. This resonance, through the piezoelectric effect, forms positive feedback with the circuit, maintaining continuous oscillation. The first load capacitor bank serves as the load capacitor, and together with the first quartz crystal, determines the precise value of the oscillation frequency.

[0091] The waveform shaping output unit is connected to the output of the crystal resonant oscillation unit and is used to shape the initial oscillation signal into a first high-frequency square wave signal. The waveform shaping output unit includes a first Schmitt inverter. The second pin of the first Schmitt inverter is connected to the output of the crystal resonant oscillation unit, the third pin of the first Schmitt inverter is connected to ground, the fourth pin of the first Schmitt inverter outputs the first high-frequency square wave signal to the programmable logic device, and the fifth pin of the first Schmitt inverter is connected to the power supply and a fourth load capacitor, the other end of the fourth load capacitor is connected to ground.

[0092] The first Schmitt inverter utilizes its hysteresis characteristic to shape the approximately sinusoidal or noisy oscillation signal output from the crystal resonant oscillator into a high-frequency square wave signal with steep edges and stable amplitude. The hysteresis characteristic enables the Schmitt inverter to suppress noise and jitter in the input signal, further purifying the spectral purity of the output signal and providing a high-quality clock source for subsequent integer frequency division.

[0093] [Implementation Method 8: Circuit Details of the Crystal Resonant Oscillation Unit and Waveform Shaping Output Unit]

[0094] This embodiment provides a more detailed description of the circuit connection relationship between the crystal resonant oscillation unit and the waveform shaping output unit.

[0095] The crystal resonant oscillation unit includes a first inverter, a first feedback resistor, a first quartz crystal, and a first load capacitor.

[0096] A first feedback resistor is connected between the input and output terminals of the first inverter. The resistance value of the first feedback resistor is usually selected in the range of 1MΩ to 10MΩ to provide appropriate DC negative feedback to the first inverter, so that its operating point is stabilized at the midpoint of the linear region, ensuring that the oscillation circuit can start reliably.

[0097] The first load capacitor is connected between the input terminal of the first inverter and ground. The first load capacitor is the load capacitor on one side of the quartz crystal, and its value is selected according to the load capacitor specification of the quartz crystal, usually from a few pF to tens of pF.

[0098] The input and output terminals of the first inverter are respectively connected to the two pins of the first quartz crystal. In the positive feedback loop formed by the first inverter, the first feedback resistor, and the load capacitor, the first quartz crystal utilizes its piezoelectric resonance characteristics to exhibit extremely low impedance at the series resonant frequency, satisfying the Barkhausen phase condition and amplitude condition, and maintaining stable continuous oscillation.

[0099] The waveform shaping output unit includes a first Schmitt inverter. The input terminal of the first Schmitt inverter is connected to the output terminal of the first inverter. The output terminal of the first Schmitt inverter serves as the output terminal of a first high-frequency square wave signal and is connected to a programmable logic device.

[0100] The power supply terminal of the first Schmitt inverter is connected to the power supply, and the ground terminal is connected to ground. The first Schmitt inverter has an upper threshold voltage and a lower threshold voltage. When the input signal voltage is higher than the upper threshold, the output is low; when it is lower than the lower threshold, the output is high. The difference between the two thresholds forms a hysteresis window. This hysteresis characteristic effectively suppresses noise and ripple superimposed on the input signal, prevents edge jitter and glitches in the output signal, and ensures that the output first high-frequency square wave signal has a clean spectrum and stable phase.

[0101] The crystal resonant oscillation unit and waveform shaping output unit of the second channel have a circuit structure symmetrical to that of the first channel, including a second inverter, a second feedback resistor, a second quartz crystal, a second load capacitor group, and a second Schmitt inverter. Their connection relationship and working principle are the same as those of the first channel, and will not be described again here.

[0102]

Implementation Method Nine: Independent Clock and Power Supply Design for the Time Measurement Module

[0103] This embodiment provides a detailed description of the structure of the time measurement module.

[0104] The time measurement module includes a time-to-digital converter chip and a local clock oscillator.

[0105] The time-to-digital converter (TDDC) chip's measurement signal input terminal is connected to the signal output terminal of the quartz vibrating beam acceleration sensor module. Specifically, the TDDC chip receives two high-frequency vibration frequency signals output from the quartz vibrating beam acceleration sensor module through its first and second measurement input pins, respectively. The frequencies of the two high-frequency vibration frequency signals shift with changes in external acceleration.

[0106] The clock input of the time-to-digital converter (TD-SCDMA) chip is connected to the output of a local clock oscillator. The local clock oscillator includes a second quartz crystal. The second pin of the second quartz crystal is connected to ground, the third pin is connected to a resistor, and the fourth pin is connected to the system main power supply and a filter capacitor. The other end of the filter capacitor is connected to ground. The clock input pin of the TD-SCDMA chip is connected to the third pin of the second quartz crystal via a resistor to receive the clock signal as the measurement time base.

[0107] The local clock oscillator and the high-frequency oscillation signal generation module have independent clock sources. Their oscillation frequencies differ and are generated by different quartz crystals, eliminating frequency pulling and phase locking relationships. This clock isolation design prevents noise and jitter from the driving clock domain from coupling to the measurement clock domain through the clock network, ensuring the independence and accuracy of time measurements.

[0108] Furthermore, the local clock oscillator and the high-frequency oscillation signal generation module have independent power supply links. The time-to-digital converter (TD-SCDMA) chip is powered by an independent power network: multiple power supply pins of the TD-SCDMA chip are connected to the system main power supply and corresponding filter capacitors; the reference voltage pin, analog power supply pin, and output of the DC-DC converter chip are all connected together and grounded through a filter capacitor. The input pin of the DC-DC converter chip is connected to another power supply pin of the TD-SCDMA chip and a filter capacitor bank, which is then grounded. The DC-DC converter chip provides an independent low-dropout linear regulated power supply for the time measurement module, and its power supply link is completely independent of the power supply link of the high-frequency oscillation signal generation module.

[0109] By designing an independent clock source and an independent power supply link, this implementation achieves complete isolation between the measurement domain and the driving domain, avoiding mutual interference caused by power sharing or clock traction, thereby improving the accuracy and stability of frequency period measurement.

[0110]

Implementation Method 10: Low-Noise Driving and Detection Method

[0111] Figure 6 A flowchart of a low-noise driving and detection method for a quartz vibrating beam accelerometer provided in an embodiment of this application is shown.

[0112] Step S101: High-frequency square wave signal generation and low-noise power supply

[0113] The power supply filter isolation module supplies power to the high-frequency oscillation signal generation module, driving the high-frequency oscillation signal generation module to generate the first high-frequency square wave signal.

[0114] In this step, the system's main power supply, after undergoing first-stage DC-DC conversion, ferrite bead filtering, and second-stage low-dropout linear regulation by the power supply filtering and isolation module, provides a low-noise power supply voltage to the high-frequency oscillation signal generation module. Because the power supply ports of the power supply filtering and isolation module and the logic divider module have a power supply filtering and isolation structure, and their power supply traces are independent of each other on the printed circuit board layout and do not share the same power plane, the switching transient noise generated by the logic divider is effectively blocked, ensuring that the first high-frequency square wave signal has high-frequency spectral purity.

[0115] Specifically, the system's main power supply is converted into an intermediate power supply via a DC-DC converter chip, and then filtered by a ferrite bead and a filter capacitor before being used by the logic frequency divider module. Simultaneously, the system's main power supply is converted into a dedicated power supply via an independent low-dropout linear regulator, specifically for the two crystal oscillator circuits of the high-frequency oscillation signal generation module. The two power supplies are independently laid out on the printed circuit board and do not share a power plane.

[0116] Step S102: Obtain a low-noise drive signal by integer frequency division

[0117] The first high-frequency square wave signal is divided by an integer using a logic frequency divider module to obtain the second low-frequency square wave drive signal.

[0118] The logic frequency divider module divides the first high-frequency square wave signal by an integer division ratio N. The second low-frequency square wave drive signal retains the phase noise characteristics of the first high-frequency square wave signal, and after integer frequency division, the phase noise spectral density of the second low-frequency square wave drive signal is reduced by 20logN dB compared to the phase noise spectral density of the first high-frequency square wave signal, where N is the integer division ratio.

[0119] For example, if the first high-frequency square wave signal is 32.768MHz and the frequency division ratio N=1000, then the second low-frequency square wave drive signal is 32.768kHz, and its phase noise spectral density at a deviation of 1kHz from the carrier is 60dB lower than that of the 32.768MHz source signal. This significant improvement in phase noise results in extremely low phase noise of the drive signal at the resonant frequency of the quartz vibrating beam, laying the foundation for high-precision frequency detection.

[0120] Step S103: Drive the quartz beam to resonate

[0121] The second low-frequency square wave drive signal is input to the quartz vibrating beam acceleration sensing module to drive the quartz vibrating beam to a resonant state.

[0122] The frequency of the second low-frequency square wave driving signal matches the resonant frequency of the quartz resonant beam, enabling the quartz resonant beam to generate stable mechanical resonance under the excitation of the low-frequency square wave driving signal. Due to the extremely low phase noise of the driving signal, the resonant stability of the quartz resonant beam is significantly improved, and random fluctuations in the resonant frequency are effectively suppressed.

[0123] Step S104: Acquire high-frequency vibration signal

[0124] The high-frequency vibration signal output by the quartz vibrating beam acceleration sensor module is collected.

[0125] When an external acceleration is applied to the quartz vibrating beam accelerometer module, the resonant frequency of the quartz vibrating beam shifts proportionally to the acceleration. The quartz vibrating beam accelerometer module outputs a high-frequency vibration signal reflecting the current resonant frequency. The frequency shift of this signal is proportional to the applied acceleration and serves as the basis for subsequent acceleration calculations.

[0126] Step S105: High-precision period measurement and frequency offset calculation

[0127] The period of the high-frequency vibration signal is measured by the time measurement module, and the frequency offset is calculated.

[0128] The time measurement module utilizes its independent local clock oscillator as the measurement time base, and performs high-precision time measurement of the period of the high-frequency vibration signal through a time-to-digital converter chip. Because the time measurement module has an independent clock source and independent power supply link, mutual interference between the measurement clock and the drive clock is effectively isolated, ensuring the accuracy and stability of the period measurement.

[0129] Based on the measured period, the current frequency is calculated, and the frequency offset is further calculated, where the reference frequency is the reference resonant frequency of the quartz vibrating beam in the zero acceleration state.

[0130] Step S106: Acceleration value calculation

[0131] The acceleration value is calculated based on the frequency offset.

[0132] The external acceleration value is calculated using the calibration coefficients of the quartz vibrating beam accelerometer, by the formula that the acceleration value equals the frequency offset divided by the calibration coefficients. The calibration coefficients are predetermined through calibration experiments in a standard gravity field or a precision centrifuge.

[0133] Through the coordinated implementation of the above methods and steps, this embodiment realizes a complete signal chain from high-frequency low-noise oscillation generation, integer frequency division phase noise suppression, power supply noise isolation, clock domain isolation to high-precision time measurement and acceleration calculation, which significantly improves the measurement accuracy, stability and anti-interference capability of the quartz vibrating beam accelerometer.

[0134] The inventive principle of this invention:

[0135] Quartz crystals vibrate mechanically under the influence of an external electric field. Quartz beam accelerometers operate by utilizing the bending vibration mode of an internal quartz beam (made of quartz crystal). When a high-frequency oscillating electrical signal is applied to the quartz beam, the piezoelectric effect of the quartz crystal causes the accelerometer to operate in a resonant state. When an external force is applied to the accelerometer, its vibration frequency changes. By analyzing the change in vibration frequency before and after the force is applied, the force on the accelerometer can be calculated; in other words, the change in acceleration is detected by detecting the shift in the quartz beam's vibration frequency.

[0136] Function: The two input high-frequency oscillation signals, approximately 120kHz square wave signals, are divided into low-frequency square wave signals, which are used to drive two quartz vibrating beam acceleration sensing modules.

[0137] See Figure 2 As shown: Pin C1 of U7A is connected to pin 1 of resistor R5 (CH1_N signal); pin B1 of U7A is connected to pin 1 of resistor R4 (CH1_P signal); pin G7 of U7A is connected to resistor R25, and the other pin of resistor R25 is connected to a 3.3V DC power supply; pin G1 of U7A is connected to pin 5 of connector J2 (output signal TMS); pin J1 of U7A is connected to pin 1 of J2 (output signal TCK); pin H5 of U7A is connected to pin 9 of J2 (signal TDI); pin H4 of U7A is connected to pin 3 of J2 (signal TDO); pin J5 of U7A is connected to resistor R26, and the other pin of resistor R26 is connected to pin 3 of X2 (signal CLK10M); pin R11 of U7A is connected to pin 7 of connector J1 (signal IS); pin P12 of U7A is connected to pin 5 of J1 (signal IC); pin R14 of U7A is connected to pin 6 of J1 (signal ID).

[0138] Pin E6 of U7A is connected to pin 1 of resistor R32, and the other pin of resistor R32 is connected to a 3.3V DC power supply. Pin D6 of U7A is connected to pin 1 of resistor R30, and the other pin of resistor R30 is connected to a 3.3V DC power supply. Pin A5 of U7A is connected to the inverting terminal of diode D1, and the forward terminal of diode D1 is connected to pin 1 of resistor R24, and the other pin of resistor R24 ​​is connected to a 3.3V DC power supply. Pin E8 of U7A is connected to pin 1 of resistor R28, and the other pin of resistor R28 is connected to a 3.3V DC power supply. Pin D8 of U7A is connected to pin 1 of resistor R27, and the other pin of resistor R27 is connected to GND. Pin J15 of U7A is connected to pin 4 of U4 (signal CH1_1), and pin G15 of U7A is connected to pin 4 of U6 (signal CH1_2). (Signals CH1_1 and CH1_2 are high-frequency oscillation signals generated by the crystal oscillator high-frequency oscillation circuit, and are input signals.)

[0139] See Figure 3 As shown: Pins R1, R15, M2, M6, M10, L12, J7, H8, H14, G4, G9, E5, E12, D5, D9, B2, A1, and A15 of U7B are all connected to GND; Pins F2, H2, L2, L14, P5, P10, and P11 of U7B are all connected to a 3.3V DC power supply; Pins G14 and F14 of U7B are connected to the non-GND pin of capacitor C36 (power supply VCCIO6); Pins B5, B9, and B10 of U7B are simultaneously connected to a 3.3V DC power supply; pins N2, D14, B3, and P13 of U7B are simultaneously connected to the non-grounded terminals of capacitors C37 and C38 (power supply VCCA); pins J8, H7, H9, and G8 of U7B are simultaneously connected to a 3.3V DC power supply.

[0140] A 3.3V DC power supply is connected to one end of the ferrite bead L1. The other end of the ferrite bead L1 is connected to capacitors C37 and C38. The non-grounded ends of capacitors C37 and C38 are also connected to pin N2 of U7B. The other end of capacitors C37 and C38 is connected to GND.

[0141] The 3.3V DC power supply is connected to pin 1 of resistor R29, the 1.8V DC power supply is connected to pin 1 of resistor R31, and the other pins of resistor R29, resistor R31, and capacitor C36 (output power supply VCCIO6) are connected together to pin G14 of U7B. The other pin of capacitor C36 is connected to GND.

[0142] Function: Programming and debugging port circuit for this oscillation drive signal circuit.

[0143] Pin J1 (signal TCK) of U7A is connected to pin 1 of connector J2. Pin 1 of J2 is connected to pin 1 of resistor R36, and the other pin of resistor R36 is connected to GND. Pin H4 (signal TDO) of U7A is connected to pin 3 of J2 and pin 1 of resistor R35. The other pin of resistor R35 is connected to a 3.3V DC power supply. Pin G1 (signal TMS) of U7A is connected to pin 5 of J2 and pin 1 of resistor R34. The other pin of resistor R34 is connected to a 3.3V DC power supply. Pin H5 (signal TDI) of U7A is connected to pin 9 of J2 and pin 1 of resistor R33. The other pin of resistor R33 is connected to a 3.3V DC power supply. Pin 2 of J2 is connected to GND. The 3.3V DC power supply is connected to pin 4 of J2 and pin 1 of capacitor C42. The other pin of capacitor C42 is connected to GND. Pin 10 of J2 is connected to GND.

[0144] See Figure 4 As shown: Function: The connector J1 of this circuit includes a power input port, control line input, and SPI data communication port design.

[0145] Connect the 3.3V DC power supply to capacitor C1 and pin 1 of connector J1; connect the other pin of capacitor C1 to GND. Connect the 3.3V DC power supply to pin 2 of J1. Connect pins 3 and 4 of J1 to GND. Connect pin 5 of J1 to pin P12 (signal IC) of U7A. Connect pin 6 of J1 to pin R14 (signal ID) of U7A. Connect pin 7 of J1 to pin R11 (signal IS) of U7A. Connect pin 13 of J1 to pin 34 of U2 (signal DRDY). Connect pin 17 of J1 to pin 36 of U2 (signal SPIO_CLK). Connect pin 18 of J1 to pin 35 of U2 (signal SPIO_CS0). Connect pin 19 of J1 to pin 37 of U2 (signal SPIO_MOSI). Connect pin 20 of J1 to pin 38 of U2 (signal SPIO_MISO).

[0146] Function: Circuit for converting 3.3V DC power supply to 1.8V DC power supply.

[0147] Pin 1 of U1 is connected to capacitor C4 and pin 3 of U1. Pin 1 of U1 is also connected to a 3.3V DC power supply. The other pin of capacitor C4 is connected to GND. Pin 2 of U1 is connected to GND. Pin 4 of U1 is connected to capacitor C6. The other pin of capacitor C6 is connected to GND. Pin 5 of U1 is connected to capacitor C5 (outputting a 1.8V DC power supply). The other pin of capacitor C5 is connected to GND.

[0148] Function: Generates a high-frequency oscillation signal, a square wave signal with a frequency of 120KHz, to drive the quartz vibrating beam acceleration sensing module in channel 1.

[0149] Function: Converts 3.3V DC power to 1.8V DC power, specifically for supplying the clock oscillator circuit.

[0150] The 3.3V DC power supply is connected to resistor R20 and pin 3 of U8; pin 2 of U8 is connected to GND, pin 3 of U8 is connected to capacitor C22, and the other pin of capacitor C22 is connected to GND; pin 4 of U8 is connected to capacitor C23, and simultaneously outputs a 1.8V DC power supply (dedicated to the clock oscillation circuit, i.e., dedicated to U3 and U4), and the other pin of capacitor C23 is connected to GND.

[0151] Function: Design of a high-frequency oscillation signal circuit for channel 1.

[0152] Pin 2 of U3 is connected to resistor R15, pin 2 of X1, and capacitor C10. The other pin of capacitor C10 is connected to GND. Pin 3 of U3 is connected to GND. The other pin of resistor R15 is connected to pin 4 of U3, resistor R16, and pin 2 of U4. The other pin of resistor R16 is connected to pin 6 of X1 and capacitor C11. The other pin of capacitor C11 is connected to GND. Pin 5 of U3 is connected to pin 4 of U8 and capacitor C8. The other pin of capacitor C8 is connected to GND. Pin 3 of U4 is connected to GND. Pin 4 of U4 is connected to pin J15 of U7A (signal CH1_1). Pin 5 of U4 is connected to pin 4 of U8 and capacitor C9. The other pin of capacitor C9 is connected to GND.

[0153] Function: Generates a high-frequency oscillation signal, a square wave signal with a frequency of 120KHz, to drive the quartz vibrating beam accelerometer in channel 2.

[0154] Function: Converts 3.3V DC power to 1.8V DC power, specifically for supplying the clock oscillation circuit.

[0155] The 3.3V DC power supply is connected to resistor R23 and pin 3 of U9; pin 2 of U9 is connected to GND; pin 3 of U9 is connected to capacitor C27, and the other pin of capacitor C27 is connected to GND; pin 4 of U9 is connected to capacitor C28, and at the same time, a 1.8V DC power supply is output (dedicated to the clock oscillation circuit, i.e., dedicated to U5 and U6), and the other pin of capacitor C28 is connected to GND.

[0156] Function: Design of high-frequency oscillation signal circuit for channel 2.

[0157] Pin 2 of U5 is connected to resistor R21, pin 2 of X3, and capacitor C25. The other pin of capacitor C25 is connected to GND. Pin 3 of U5 is connected to GND. The other pin of resistor R21 is connected to pin 4 of U5, resistor R22, and pin 2 of U6. The other pin of resistor R22 is connected to pin 6 of X2 and capacitor C26. The other pin of capacitor C26 is connected to GND. Pin 5 of U5 is connected to pin 4 of U9 and capacitor C20. The other pin of capacitor C20 is connected to GND. Pin 3 of U6 is connected to GND. Pin 4 of U6 is connected to pin G15 of U7A (signal CH1_2). Pin 5 of U6 is connected to pin 4 of U9 and capacitor C21. The other pin of capacitor C21 is connected to GND.

[0158] See Figure 5 As shown: Function: Design a high-frequency signal measurement circuit for a time measurement chip to measure the frequency of the high-frequency oscillation signal output by the quartz beam accelerometer module (i.e., the frequency values ​​of the output signal CH1P of the quartz beam accelerometer module 1 and the output signal CH1N of the quartz beam accelerometer sensor module 2).

[0159] Pin 2 of U2 is connected to a 3.3V DC power supply and capacitor C7. The other pin of capacitor C7 is connected to GND. Pin 11 of U2 is connected to GND. Pins 12 and 14 of U2 and pin 1 of capacitor C12 are simultaneously connected to a 3.3V DC power supply. The other pin of capacitor C12 is connected to GND. Pins 13 and 15 of U2, capacitors C16 and C17, and resistor R19 are simultaneously connected to a 3.3V DC power supply. The other pins of capacitors C16 and C17 are connected to GND. Pins 16 and 17 of U2 are simultaneously connected to GND. The other pin of resistor R19 is connected to pins 18 and 19 of U2, capacitor C19, and pin 5 of U1. The other pin of capacitor C19 is connected to GND. Pin 1 of U1 is connected to pin 20 of U2, capacitor C14, and capacitor C15, with capacitors C14 and C15 connected to GND. Pins 23 and 30 of U2 are also connected to GND. Pin 24 of U2 is connected to resistor R13, with the other pin of resistor R13 connected to GND. Pin 25 of U2 is connected to resistor R7, with the other pin of resistor R7 connected to pin 3 of X2. Pin 26 of U2 is connected to resistor R3, with the other pin of resistor R3 connected to GND. Pin 27 of U2 is connected to a 3.3V DC power supply. Pin 28 of U2 is connected to resistor R5, with the other pin of resistor R5 connected to pin C1 of U7A. Pin 29 of U2 is connected to resistor R4, with the other pin of resistor R4 connected to U7A. Pin B1 of U1; Pin 5 of U1 is connected to Pin 31 of U2 and capacitor C3, with the other pin of capacitor C3 connected to GND; Pin 34 of U2 is connected to Pin 13 of connector J1 (DRDY signal); Pin 35 of U2 is connected to Pin 18 of connector J1 (SPI_CS0); Pin 36 of U2 is connected to Pin 17 of connector J1 (SPI_CLK); Pin 37 of U2 is connected to Pin 19 of connector J1 (SPI_MOSI); Pin 38 of U2 is connected to Pin 20 of connector J1 (SPI_MISO); Pin 39 of U2 is connected to GND; Pin 40 of U2 is connected to a 3.3V DC power supply and capacitor C2, with the other pin of capacitor C2 connected to GND.

[0160] Function: 10MHz high-frequency signal circuit.

[0161] Pin 2 of crystal oscillator X2 is connected to GND; pin 3 of X2 is connected to pin 1 of resistor R26; pin 4 of X2 is connected to a 3.3V DC power supply and capacitor C24, and the other pin of capacitor C24 is connected to GND.

[0162] When used in conjunction with a quartz beam accelerometer operating in the low-to-mid frequency range, the acceleration measurement frequency band of the quartz beam accelerometer circuit is concentrated in the 0-80Hz low-frequency range, and the acceleration circuit structure of the quartz beam accelerometer circuit is simplified. The effective frequency band of an accelerometer is generally evaluated using a vibration table test of its amplitude-frequency characteristics. Several frequency points are selected from the low-frequency point to the highest frequency point for testing. If the output sensitivity value at the highest frequency point is ≥ 0.707 × the sensitivity value at the reference frequency point, then the sensor's operating frequency band is considered to be the range from the low-frequency point to the high-frequency point.

[0163] Amplitude-frequency characteristic data of a quartz vibrating beam accelerometer (obtained from measurements on a low-frequency standard vibration table).

[0164] Frequency (Hz) Acceleration (m / s²) Peak-to-peak output acceleration (g) Sensitivity (g / (m / s²)) 0.1 0.01 0.0026 0.26 1 1.0012 0.2052 0.2050 5 4.0051 0.822 0.2052 10 9.5274 1.940 0.2036 20 9.3071 1.882 0.2022 31.5 9.3204 1.865 0.2001 40 9.3228 1.838 0.1972 63 9.3496 1.758 0.1880 80 9.3697 1.676 0.1798

[0174] With the assistance of the circuit of this invention, the quartz vibrating beam accelerometer underwent the above amplitude-frequency characteristic parameter tests. The test frequency range was from 0.1Hz to 80Hz. Taking the sensitivity value of the sensor at 20Hz as the reference point, the sensitivity value at 63Hz dropped to 0.9298 (0.1880 / 0.2022=0.9298) of the reference value, and the sensitivity value at 80Hz dropped to 0.8892 (0.1798 / 0.2022=0.8892) of the reference value. The output sensitivity value at 80Hz was still greater than 0.707 times the reference value. Therefore, with the assistance of the circuit of this invention, the quartz vibrating beam accelerometer's measurement frequency band meets the requirement of 0-80Hz.

[0175] As can be seen from the above embodiments, this invention, through the synergistic design of high-frequency oscillation and integer frequency division, utilizes the phase noise suppression characteristics of integer frequency division to obtain a drive signal with extremely low phase noise at the resonant frequency of the quartz beam. Through the multi-stage filtering and circuit isolation structure of the isolated power supply module, the coupling of transient noise from the logic frequency divider switch to the high-frequency oscillation module via the power network is blocked. The independent clock source and independent power supply link design of the time measurement module achieve complete isolation between the measurement domain and the drive domain. In the dual-channel differential detection architecture, the independent power supply filtering network and physical isolation band design further suppress inter-channel crosstalk. The synergistic effect of these multiple low-noise protection mechanisms significantly improves the measurement accuracy, stability, and anti-interference capability of the quartz beam accelerometer.

[0176] The above are merely preferred embodiments of the present invention and are not intended to limit the invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0177] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A low noise drive and sense circuit for a quartz tuning fork acceleration sensor, characterized by, include: A high-frequency oscillation signal generation module is used to generate a first high-frequency square wave signal; The logic frequency divider module has its signal input terminal connected to the signal output terminal of the high-frequency oscillation signal generation module. It is used to perform integer frequency division processing on the first high-frequency square wave signal to obtain a second low-frequency square wave drive signal. The frequency of the first high-frequency square wave signal is higher than the frequency of the second low-frequency square wave drive signal. The quartz vibrating beam acceleration sensing module has its drive signal input terminal connected to the signal output terminal of the logic frequency divider module, and is used to receive the second low-frequency square wave drive signal and generate a high-frequency vibration frequency signal. The time measurement module has its signal input terminal connected to the output terminal of the quartz vibrating beam acceleration sensing module, and is used to measure the period of the high-frequency vibration signal; The power supply filtering and isolation module has its output terminal connected to the power supply terminal of the high-frequency oscillation signal generation module, and its input terminal connected to the system main power supply. The logic frequency division module is configured to divide the first high-frequency square wave signal by an integer frequency division ratio N greater than 1 to obtain the second low-frequency square wave driving signal. The second low-frequency square wave driving signal retains the phase noise characteristics of the first high-frequency square wave signal, and the phase noise spectral density of the second low-frequency square wave driving signal is reduced by 20logN dB relative to the phase noise spectral density of the first high-frequency square wave signal.

2. The low-noise driving and detection circuit for the quartz vibrating beam accelerometer according to claim 1, characterized in that: The logic frequency division module includes a programmable frequency divider, and the division ratio of the programmable frequency divider is an integer N greater than 1.

3. The low-noise driving and detection circuit for the quartz vibrating beam accelerometer according to claim 1 or 2, characterized in that: The high-frequency oscillation signal generation module has a two-channel independent structure, which generates a first-channel high-frequency oscillation signal and a second-channel high-frequency oscillation signal respectively. The logic frequency division module is a programmable logic device. The programmable logic device divides the high-frequency oscillation signal of the first channel into a first low-frequency square wave drive signal and divides the high-frequency oscillation signal of the second channel into a second low-frequency square wave drive signal, so as to drive the two quartz beam acceleration sensing modules respectively to form a differential detection architecture.

4. The low-noise driving and detection circuit for the quartz vibrating beam accelerometer according to claim 3, characterized in that: The programmable logic device has an independent power input pin; the power input pin of the programmable logic device is connected to a power filter network, and the ground terminal of the power filter network is separated from the power ground of the programmable logic device by a physical isolation strip.

5. The low-noise driving and detection circuit for the quartz vibrating beam accelerometer according to claim 1, characterized in that: The power filtering and isolation module includes a first-stage DC-DC converter circuit and a ferrite bead filter circuit. The input terminal of the first-stage DC-DC converter circuit is connected to the main power supply of the system, and the output terminal is connected to the input terminal of the ferrite bead filter circuit. The output terminal of the ferrite bead filter circuit is connected to the power supply terminal of the PLL regulator of the programmable logic device. The ferrite bead filter circuit is configured to suppress the current ripple at the switching transient frequency of the logic frequency divider module, and the power traces of the power supply filter isolation module supplying power to the high-frequency oscillation signal generation module and the power traces supplying power to the logic frequency divider module are independent of each other in the printed circuit board layout and do not share the same power plane.

6. The low-noise driving and detection circuit for the quartz vibrating beam accelerometer according to claim 5, characterized in that: The power supply filtering and isolation module also includes a second-stage low-dropout linear regulator circuit. The second-stage low-dropout linear regulator circuits of the two high-frequency oscillation signal generation circuits are completely independent, reducing the impact of power supply interference on the high-frequency oscillation signals.

7. The low-noise driving and detection circuit for the quartz vibrating beam accelerometer according to claim 1, characterized in that: The high-frequency oscillation signal generation module includes a crystal resonant oscillation unit and a waveform shaping output unit; The crystal resonant oscillation unit is used to generate an initial oscillation signal based on a quartz crystal oscillator; The waveform shaping output unit is connected to the output terminal of the quartz crystal oscillator unit and is used to shape the initial oscillation signal into the first high-frequency square wave signal.

8. The low-noise driving and detection circuit for the quartz vibrating beam accelerometer according to claim 7, characterized in that: The crystal resonant oscillation unit includes a first inverter, a feedback resistor, a quartz crystal, and a first capacitor; The feedback resistor is connected between the input and output terminals of the first inverter, the first capacitor is connected between the input terminal of the first inverter and ground, and the input and output terminals of the first inverter are respectively connected to the two pins of the quartz crystal. The waveform shaping output unit includes a Schmitt inverter, the input of which is connected to the output of the first inverter, and the output of the Schmitt inverter serves as the output of the first high-frequency square wave signal.

9. The low-noise driving and detection circuit for the quartz vibrating beam accelerometer according to claim 1, characterized in that: The time measurement module includes a time-to-digital converter chip and a local clock oscillator; The measurement signal input terminal of the time-to-digital converter chip is connected to the signal output terminal of the quartz vibrating beam acceleration sensing module; The clock input terminal of the time-to-digital converter chip is connected to the output terminal of the local clock oscillator. The local clock oscillator and the high-frequency oscillation signal generation module have independent clock sources and independent power supply links.

10. A low noise driving and detecting method for a quartz beam-lead acceleration sensor, characterized in that, Includes the following steps: The power supply filtering and isolation module supplies power to the high-frequency oscillation signal generation module, driving the high-frequency oscillation signal generation module to generate a first high-frequency square wave signal. There is a power supply filtering and isolation structure between the power supply ports of the power supply filtering and isolation module and the logic frequency divider module. The power supply traces of the power supply filtering and isolation module supplying power to the high-frequency oscillation signal generation module and the power supply traces supplying power to the logic frequency divider module are independent of each other in the printed circuit board layout and do not share the same power plane. The first high-frequency square wave signal is divided by an integer frequency by a logic frequency divider module to obtain a second low-frequency square wave driving signal. The second low-frequency square wave driving signal retains the phase noise characteristics of the first high-frequency square wave signal. After the integer frequency divider, the phase noise spectral density of the second low-frequency square wave driving signal is reduced by 20logN dB relative to the phase noise spectral density of the first high-frequency square wave signal, where N is the integer frequency division ratio. The second low-frequency square wave driving signal is input to the quartz vibrating beam acceleration sensing module to drive the quartz vibrating beam to a resonant state. The high-frequency vibration signal output by the quartz vibrating beam acceleration sensing module is acquired; The period of the high-frequency vibration signal is measured by a time measurement module, and the frequency offset is calculated. The time measurement module has an independent clock source and an independent power supply link to isolate the mutual interference between the measurement clock and the driving clock. The acceleration value is calculated based on the frequency offset.

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