Phase-locked loop circuit and storage device including the same

Abstract

A storage device and a phase-locked loop circuit are provided. The storage device can include a nonvolatile memory device and a storage controller including a phase-locked loop circuit, the phase-locked loop circuit can include a phase detector configured to output a phase difference signal corresponding to a phase difference between a reference clock signal and a feedback clock signal, a voltage generator configured to generate an input voltage corresponding to the phase difference signal and output the input voltage, an oscillator configured to generate an output clock signal having a frequency corresponding to the input voltage and output the output clock signal, a reset synchronization circuit configured to synchronize a reset signal based on the reference clock signal and output the synchronized reset signal, and a frequency divider configured to reset based on the synchronized reset signal, generate the feedback clock signal by dividing the output clock signal, and output the feedback clock signal.

Description

Cross-reference of related applications

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2025-0017516, filed on February 11, 2025, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to a semiconductor device, and more specifically, to a phase-locked loop circuit, a storage device including the phase-locked loop circuit, and a method of operating the storage device. Background Technology

[0003] Semiconductor memories are divided into volatile memory devices (such as SRAM and DRAM) that lose stored data when the power supply is cut off, and non-volatile memory devices (such as flash memory devices, PRAM, MRAM, RRAM and FRAM) that retain stored data even when the power supply is cut off.

[0004] A phase-locked loop (PLL) receives a reference clock signal and can generate output clock signals with frequencies higher than the reference clock signal by using the reference clock signal. Electronic devices are designed to operate based on clock signals with specific frequencies. Therefore, PLLs are essential devices used in electronic devices.

[0005] A phase-locked loop (PLL) needs time to lock its output clock signal to a target frequency. The electronic device can only function properly once the PLL's output clock signal is locked to the target frequency. Therefore, as the locking speed of the PLL increases, the operating speed of the electronic device can be increased. Summary of the Invention

[0006] Embodiments of this disclosure provide a phase-locked loop circuit that can have an improved locking speed, a storage device including the phase-locked loop circuit, and a method of operating the storage device.

[0007] According to one aspect of this disclosure, a storage device may include a non-volatile memory device and a storage controller configured to control the non-volatile memory device and communicate with an external host device. The storage controller includes a phase-locked loop (PLL) circuit, which may include: a phase detector configured to receive a reference clock signal and a feedback clock signal, and output a phase difference signal corresponding to the phase difference between the reference clock signal and the feedback clock signal; a voltage generator configured to receive the phase difference signal, generate an input voltage corresponding to the phase difference signal, and output the input voltage; an oscillator configured to receive the input voltage, generate an output clock signal having a frequency corresponding to the input voltage, and output the output clock signal; a reset synchronization circuit configured to receive a reset signal and a reference clock signal, synchronize the reset signal based on the reference clock signal to generate a synchronized reset signal, and output the synchronized reset signal; and a frequency divider configured to receive the synchronized reset signal and the output clock signal, perform a reset based on the synchronized reset signal, generate a feedback clock signal by dividing the output clock signal, and output the feedback clock signal.

[0008] According to one aspect of this disclosure, a phase-locked loop (PLL) circuit may include: a phase detector configured to receive a reference clock signal and a feedback clock signal, and output a phase difference signal corresponding to the phase difference between the reference clock signal and the feedback clock signal; a reset synchronization circuit configured to receive a reset signal and a reference clock signal, synchronize the reset signal based on the reference clock signal to generate a synchronization reset signal, and output the synchronization reset signal; and a frequency divider configured to receive the synchronization reset signal and the output clock signal, reset based on the synchronization reset signal, generate a feedback clock signal by dividing the output clock signal, and output the feedback clock signal to the phase detector. The PLL circuit may be configured to perform a locking operation for locking the phase of the output clock signal based on the reference clock signal and the synchronized reset signal when powered on.

[0009] According to one aspect of this disclosure, a method for operating a memory device including a memory controller and a non-volatile memory device, the non-volatile memory device including a phase-locked loop circuit, the method may include: generating a synchronous reset signal synchronized to a reference clock signal; resetting a frequency divider in the phase-locked loop circuit based on the synchronous reset signal; generating an output clock signal; generating a feedback clock signal by dividing the output clock signal; detecting a phase difference between the reference clock signal and the feedback clock signal; generating an input voltage corresponding to the phase difference; and generating an output clock signal having a frequency corresponding to the input voltage.

[0010] According to one aspect of this disclosure, a phase-locked loop circuit may include: a phase detector configured to receive a reference clock signal and a feedback clock signal, and output a phase difference signal corresponding to the phase difference between the reference clock signal and the feedback clock signal; a voltage generator configured to receive the phase difference signal, generate an input voltage corresponding to the phase difference signal, and output the input voltage; an oscillator configured to receive the input voltage, generate an output clock signal having a frequency corresponding to the input voltage, and output the output clock signal; a reset synchronization circuit configured to receive a reset signal and a reference clock signal, synchronize the reset signal based on the reference clock signal to generate a synchronized reset signal, and output the synchronized reset signal; and a frequency divider configured to receive the synchronized reset signal and the output clock signal, perform a reset based on the synchronized reset signal, generate a feedback clock signal by dividing the output clock signal, and output the feedback clock signal. Attached Figure Description

[0011] The above and other aspects, features, and advantages of specific embodiments of the present disclosure will become more apparent from the following description with reference to the accompanying drawings, in which: Figure 1 This is a block diagram illustrating a phase-locked loop circuit according to one or more embodiments; Figure 2 This illustrates one or more embodiments. Figure 1 Block diagram of a phase-locked loop circuit; Figure 3 This illustrates one or more embodiments. Figure 1 Timing diagram of the operation of the phase-locked loop circuit; Figure 4 It is shown Figure 1 Block diagram of a phase-locked loop circuit; Figure 5 This is a diagram illustrating the operation of a phase-locked loop circuit according to one or more embodiments; Figure 6 This is a diagram illustrating the operation of a phase-locked loop circuit according to one or more embodiments; Figure 7 This is a block diagram illustrating a phase-locked loop circuit according to one or more embodiments; Figure 8 This is a block diagram illustrating a phase-locked loop circuit according to one or more embodiments; Figure 9 This illustrates one or more embodiments. Figure 1 A flowchart of the operation method of a phase-locked loop circuit; Figure 10 This is a block diagram illustrating a storage system according to one or more embodiments; Figure 11 This is a more detailed illustration according to one or more embodiments. Figure 10 A block diagram of the host interface circuit; Figure 12 This illustrates one or more embodiments. Figure 10 A flowchart illustrating an example of how the storage controller operates; Figure 13 This illustrates one or more embodiments. Figure 10 A flowchart illustrating an example of the operation method of a storage controller; and Figure 14 This is a diagram illustrating a system employing a phase-locked loop circuit according to one or more embodiments. Detailed Implementation

[0012] Hereinafter, exemplary embodiments of the present disclosure will be described clearly and in detail so that those skilled in the art can readily implement the present disclosure.

[0013] Figure 1 This is a block diagram illustrating a phase-locked loop circuit according to one or more embodiments.

[0014] In one or more embodiments, components of the phase-locked loop (PLL) circuit 100 may be manufactured using semiconductor processes. For example, components of the PLL circuit 100 may be included in at least one chip (or die), and the at least one chip may be included in at least one semiconductor package.

[0015] In one or more embodiments, the PLL circuit 100 may receive a reference clock signal REF_CLK and a reset signal RST, and may output a clock signal OUT_CLK. The PLL circuit 100 may perform a locking operation to lock the frequency of the output clock signal OUT_CLK to a target frequency. The PLL circuit 100 may generate the output clock signal OUT_CLK based on the reference clock signal REF_CLK. The output clock signal OUT_CLK may be synchronized to the reference clock signal REF_CLK. The output clock signal OUT_CLK may have a frequency that is doubled from the frequency of the reference clock signal REF_CLK. The output clock signal OUT_CLK may be a clock signal with a locked phase or frequency.

[0016] In one or more embodiments, the reference clock signal REF_CLK may have a lock-in frequency similar to that of a crystal oscillator and may be referred to as an oscillation signal. In one or more embodiments, such as Figure 1 As shown, the PLL circuit 100 may include a phase detector 110, a voltage generator 120, an oscillator 130, a reset synchronization circuit 140, and a frequency divider 150. However, this disclosure is not limited thereto. For example, the number of frequency dividers in the PLL circuit 100 may be increased or decreased depending on the implementation.

[0017] Phase detector 110 can receive a reference clock signal REF_CLK and a feedback clock signal FB_CLK, and can output a phase difference signal PD. Phase detector 110 can receive the feedback clock signal FB_CLK from frequency divider 150. Phase detector 110 can generate the phase difference signal PD. For example, phase detector 110 can detect the phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK. Phase detector 110 can generate a phase difference signal PD corresponding to the detected phase difference.

[0018] In one or more embodiments, the phase difference signal PD may include a rising signal and a falling signal. The rising signal is activated when the phase of the feedback clock signal FB_CLK lags behind the phase of the reference clock signal REF_CLK, and the falling signal is activated when the phase of the feedback clock signal FB_CLK leads the phase of the reference clock signal REF_CLK. In one or more embodiments, the phase detector 110 may include logic gates and may also be referred to as a phase frequency detector.

[0019] Voltage generator 120 may receive a phase difference signal PD from phase detector 110 and may generate an input voltage VIN. Voltage generator 120 may generate an input voltage VIN corresponding to the phase difference signal PD. For example, voltage generator 120 may generate an input voltage VIN having an amplitude corresponding to the phase difference indicated by the phase difference signal PD. In one or more embodiments, voltage generator 120 may include a charge pump 121 and a loop filter 122.

[0020] For example, loop filter 122 may include a low-pass filter (LPF). Charge pump 121 may receive a phase difference signal PD including a rising signal and a falling signal. Charge pump 121 may provide charge to loop filter 122 in response to an activated rising signal and may draw charge from loop filter 122 in response to an activated falling signal. Therefore, the input voltage VIN generated by loop filter 122 may have an amplitude corresponding to the phase difference. In one or more embodiments, loop filter 122 may filter out noise frequencies. For example, loop filter 122 may include at least one resistor or at least one capacitor.

[0021] Oscillator 130 can receive an input voltage VIN from voltage generator 120. Oscillator 130 can receive a positive power supply voltage from voltage regulator and can generate an output clock signal OUT_CLK. Oscillator 130 can output a clock signal OUT_CLK. Oscillator 130 can generate an output clock signal OUT_CLK with a frequency corresponding to the input voltage VIN. For example, oscillator 130 can generate an output clock signal OUT_CLK with a frequency corresponding to the amplitude of the input voltage VIN based on power supplied from the positive power supply voltage.

[0022] For example, oscillator 130 may include an inductor and a capacitor, and may generate an output clock signal OUT_CLK having the resonant frequency of the inductor and capacitor. Therefore, oscillator 130 may generate an output clock signal OUT_CLK with low jitter. Here, oscillator 130 may be referred to as a voltage-controlled oscillator (VCO), and specifically, oscillator 130 using the resonant frequency of the inductor and capacitor may be referred to as an LC VCO.

[0023] The reset synchronization circuit 140 can receive a reference clock signal REF_CLK and a reset signal RST. The reset synchronization circuit 140 can generate a synchronous reset signal SYNC_RST. The reset synchronization circuit 140 can output the synchronous reset signal SYNC_RST to the frequency divider 150. The reset synchronization circuit 140 can synchronize the reset signal RST to the reference clock signal REF_CLK. The reset synchronization circuit 140 can synchronize the reset signal RST based on the reference clock signal REF_CLK. The reset synchronization circuit 140 can generate a synchronous reset signal SYNC_RST synchronized to the reference clock signal REF_CLK.

[0024] In one or more embodiments, in response to the activation of the reset signal RST, the reset synchronization circuit 140 can be synchronized to the reference clock signal REF_CLK, and thus activate the synchronization reset signal SYNC_RST. For example, in response to the activation of the synchronization reset signal SYNC_RST, the frequency divider 150 can be reset.

[0025] Frequency divider 150 can receive the output clock signal OUT_CLK and the synchronization reset signal SYNC_RST, and can output the feedback clock signal FB_CLK. Frequency divider 150 can receive the output clock signal OUT_CLK from oscillator 130. Frequency divider 150 can receive the synchronization reset signal SYNC_RST from reset synchronization circuit 140. Frequency divider 150 can generate the feedback clock signal FB_CLK.

[0026] In one or more embodiments, the frequency divider 150 can generate a feedback clock signal FB_CLK by dividing the output clock signal OUT_CLK. For example, the frequency divider 150 can divide the output clock signal OUT_CLK based on 1 / N as a preset division ratio. Therefore, the output clock signal OUT_CLK can have a frequency corresponding to N times the frequency of the reference clock signal REF_CLK. In one or more embodiments, the frequency divider 150 can be omitted, and the output clock signal OUT_CLK can be provided to the phase detector 110 as the feedback clock signal FB_CLK (i.e., N=1).

[0027] In one or more embodiments, the frequency divider 150 may be reset in response to a synchronization reset signal SYNC_RST. The frequency divider 150 may generate a feedback clock signal FB_CLK synchronized to the reference clock signal REF_CLK based on the synchronization reset signal SYNC_RST. The frequency divider 150 may generate a feedback clock signal FB_CLK with a phase similar to that of the reference clock signal REF_CLK based on the synchronization reset signal SYNC_RST. The frequency divider 150 may generate a feedback clock signal FB_CLK with a phase difference of a threshold or less compared to the reference clock signal REF_CLK based on the synchronization reset signal SYNC_RST. The phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK may be less than the phase difference when a reset signal RST synchronized to the output clock signal OUT_CLK is received. Therefore, the latch-up time or operating time of the PLL circuit 100 may be reduced.

[0028] As described above, the PLL circuit 100 according to one or more embodiments can generate a synchronous reset signal SYNC_RST by synchronizing a reset signal RST to a reference clock signal REF_CLK. The PLL circuit 100 can reset the frequency divider 150 based on the synchronous reset signal SYNC_RST. Therefore, the frequency divider 150 can generate a feedback clock signal FB_CLK synchronized to the reference clock signal REF_CLK. Therefore, the PLL circuit 100 can reduce the initial phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK. The PLL circuit 100 can adjust the initial phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK to a preset value. The lock time of the PLL circuit 100 can be reduced.

[0029] Figure 2 yes Figure 1 Block diagram of phase-locked loop circuit 100. Figure 3 It is shown Figure 1 The timing diagram of the operation of the phase-locked loop circuit 100.

[0030] Reference Figure 1 , Figure 2 and Figure 3 The PLL circuit 100 may include a phase detector 110, a voltage generator 120, an oscillator 130, a reset synchronization circuit 140, and a frequency divider 150. For ease of description, repeated descriptions of the above components are omitted.

[0031] In one or more embodiments, the reset synchronization circuit 140 may include a flip-flop FF. The flip-flop FF may include a clock input terminal, an input terminal D, and an output terminal Q. The flip-flop FF may receive a reference clock signal REF_CLK via the clock input terminal, receive a reset signal RST via the input terminal D, and output a synchronization reset signal SYNC_RST via the output terminal Q.

[0032] The flip-flop FF operates in response to a reference clock signal REF_CLK. The flip-flop FF responds to the rising (or falling) edge of the reference clock signal REF_CLK by outputting a logic level (e.g., high or low) of the reset signal RST via the output terminal Q as a synchronous reset signal SYNC_RST. Therefore, the synchronous reset signal SYNC_RST is synchronized to the reference clock signal REF_CLK.

[0033] The reset signal RST may not be synchronized with the reference clock signal REF_CLK. The transition time of the reset signal RST may differ from the transition time of the reference clock signal REF_CLK. For example, the reset signal RST may be activated at a first time point t1. The reset signal RST may transition from logic low to logic high at the first time point t1. The reference clock signal REF_CLK may transition from logic low to logic high at a second time point t2. The synchronous reset signal SYNC_RST may be activated at the second time point t2. The synchronous reset signal SYNC_RST may transition from logic low to logic high at the second time point t2. The synchronous reset signal SYNC_RST may be synchronized with the reference clock signal REF_CLK.

[0034] Figure 4 It is shown Figure 1 Block diagram of PLL circuit 100. Figure 5 and Figure 6 These are diagrams illustrating the operation of the PLL circuit. Figure 5 An example is shown where the output clock signal is output as a selection clock signal, and Figure 6 This shows an example where the reference clock signal is output as a selection clock signal.

[0035] Reference Figure 1 , Figure 4 , Figure 5 and Figure 6 The PLL circuit 100 may include a phase detector 110, a voltage generator 120, an oscillator 130, a reset synchronization circuit 140, and a frequency divider 150. For ease of description, repeated descriptions of the above components are omitted.

[0036] In one or more embodiments, the reset synchronization circuit 140 may receive a selection signal, an output clock signal OUT_CLK, a reference clock signal REF_CLK, and a reset signal RST. The reset synchronization circuit 140 may receive the output clock signal OUT_CLK from the oscillator 130. The reset synchronization circuit 140 may select a clock signal for synchronizing the reset signal RST. The reset synchronization circuit 140 may select one of the reference clock signal REF_CLK and the output clock signal OUT_CLK as a selection clock signal SCLK based on the selection signal. The reset synchronization circuit 140 may generate a synchronized reset signal SYNC_RST synchronized to the selection clock signal SCLK.

[0037] In one or more embodiments, the reset synchronization circuit 140 may include a flip-flop FF and a multiplexer MUX. In one or more embodiments, the multiplexer MUX may receive a select signal, a reference clock signal REF_CLK, and an output clock signal OUT_CLK. The multiplexer MUX may output a select clock signal SCLK. The multiplexer MUX may output one of the reference clock signal REF_CLK and the output clock signal OUT_CLK as the select clock signal SCLK. The multiplexer MUX may output one of the reference clock signal REF_CLK and the output clock signal OUT_CLK as the select clock signal SCLK in response to the select signal. For example, when the select signal is logic low, the multiplexer MUX may output the output clock signal OUT_CLK as the select clock signal SCLK. Alternatively, when the select signal is logic high, the multiplexer MUX may output the reference clock signal REF_CLK as the select clock signal SCLK.

[0038] The trigger FF may include a clock input terminal, an input terminal D, and an output terminal Q. The trigger FF receives the select clock signal SCLK via the clock input terminal, receives the reset signal RST via the input terminal D, and outputs the synchronous reset signal SYNC_RST via the output terminal Q.

[0039] For example, when the select signal is logic low, the flip-flop FF can operate in response to the output clock signal OUT_CLK. The flip-flop FF can also respond to the rising (or falling) edge of the output clock signal OUT_CLK by outputting a reset signal RST via the output terminal Q at a logic level (e.g., high or low) as a synchronous reset signal SYNC_RST. The synchronous reset signal SYNC_RST can be synchronized to the output clock signal OUT_CLK.

[0040] In one or more embodiments, the frequency divider 150 may be reset synchronously with the output clock signal OUT_CLK. The frequency divider 150 may generate a feedback clock signal FB_CLK synchronized to the output clock signal OUT_CLK. The feedback clock signal FB_CLK may not be synchronized to the reference clock signal REF_CLK. The phase difference between the feedback clock signal FB_CLK and the reference clock signal REF_CLK may be large. The phase difference between the feedback clock signal FB_CLK synchronized to the output clock signal OUT_CLK and the reference clock signal REF_CLK may be a first value. The lock-in time in the PLL circuit 100 may be increased.

[0041] Reference Figure 5 The phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK can be relatively large. At the first time point t1, the output clock signal OUT_CLK can transition from logic low to logic high, and the feedback clock signal FB_CLK can also transition from logic low to logic high. At the second time point t2, the reference clock signal REF_CLK can transition from logic low to logic high. The phase difference between the feedback clock signal FB_CLK and the reference clock signal REF_CLK can be the first time point T1.

[0042] For example, when the select signal is logic high, the flip-flop FF can operate in response to the reference clock signal REF_CLK. The flip-flop FF can also output a reset signal RST at a logic level (e.g., high or low) via output terminal Q in response to the rising (or falling) edge of the reference clock signal REF_CLK as a synchronous reset signal SYNC_RST. The synchronous reset signal SYNC_RST can be synchronized to the reference clock signal REF_CLK.

[0043] In one or more embodiments, the frequency divider 150 may be reset synchronously with the reference clock signal REF_CLK. The frequency divider 150 may generate a feedback clock signal FB_CLK synchronized to the reference clock signal REF_CLK. The feedback clock signal FB_CLK may be synchronized to the reference clock signal REF_CLK. When a synchronization reset signal SYNC_RST synchronized to the reference clock signal REF_CLK is provided to the frequency divider 150, the feedback clock signal FB_CLK may have a phase similar to that of the reference clock signal REF_CLK. The phase difference between the feedback clock signal FB_CLK and the reference clock signal REF_CLK may be small. The phase difference between the feedback clock signal FB_CLK synchronized to the reference clock signal REF_CLK and the reference clock signal REF_CLK may be a second value. The second value is smaller than the first value. This can reduce the lockout time in the PLL circuit 100.

[0044] Reference Figure 6 The phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK can be small. At the first time point t1, the output clock signal OUT_CLK can transition from logic low to logic high. At the third time point t3, the feedback clock signal FB_CLK can transition from logic low to logic high. At the second time point t2, the reference clock signal REF_CLK can transition from logic low to logic high. The phase difference between the feedback clock signal FB_CLK and the reference clock signal REF_CLK can be small. The timing difference between the edge of the feedback clock signal FB_CLK and the edge of the reference clock signal REF_CLK can be the second time T2. The second time T2 is less than the first time T1. That is, because the synchronous reset signal SYNC_RST is generated based on the reference clock signal REF_CLK, the phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK can be small. Therefore, the latch time or operating time in the PLL circuit 100 can be reduced.

[0045] As described above, the multiplexer MUX can respond to a selection signal by outputting either the reference clock signal REF_CLK or the output clock signal OUT_CLK as the selection clock signal SCLK. The phase difference between the feedback clock signal FB_CLK generated by providing the synchronous reset signal SYNC_RST, which is synchronized to the reference clock signal REF_CLK, to the frequency divider 150 can be smaller than the phase difference between the feedback clock signal FB_CLK generated by providing the synchronous reset signal SYNC_RST, which is synchronized to the output clock signal OUT_CLK, to the frequency divider 150 and the reference clock signal REF_CLK.

[0046] Figure 7 This is a block diagram illustrating a PLL circuit according to one or more embodiments.

[0047] Reference Figure 1 and Figure 7 The PLL circuit 100a may include a phase detector 110, a voltage generator 120, an oscillator 130, a reset synchronization circuit 140, a first frequency divider 150a, and a second frequency divider 150b. Because the PLL circuit 100a, phase detector 110, voltage generator 120, oscillator 130, and reset synchronization circuit 140 are respectively connected to… Figure 1 The PPL circuit 100, phase detector 110, voltage generator 120, oscillator 130 and reset synchronization circuit 140 are the same or similar, so their repeated descriptions are omitted.

[0048] The second frequency divider 150b can receive the output clock signal OUT_CLK and can generate and output an intermediate clock signal ICLK. The second frequency divider 150b can generate the intermediate clock signal ICLK by dividing the output clock signal OUT_CLK. For example, the second frequency divider 150b can perform frequency division on the output clock signal OUT_CLK based on a preset first division ratio.

[0049] The first frequency divider 150a can receive an intermediate clock signal ICLK and a synchronous reset signal SYNC_RST, and can generate and output a feedback clock signal FB_CLK. The first frequency divider 150a can generate the feedback clock signal FB_CLK by dividing the intermediate clock signal ICLK. For example, the first frequency divider 150a can divide the intermediate clock signal ICLK based on a preset second division ratio. For example, the second division ratio may be equal to or different from the first division ratio.

[0050] In one or more embodiments, the first frequency divider 150a may be reset in response to a synchronization reset signal SYNC_RST. The first frequency divider 150a may generate a feedback clock signal FB_CLK synchronized to the reference clock signal REF_CLK based on the synchronization reset signal SYNC_RST. The first frequency divider 150a may generate a feedback clock signal FB_CLK having a phase similar to that of the reference clock signal REF_CLK based on the synchronization reset signal SYNC_RST.

[0051] In one or more embodiments, the second frequency divider 150b may be reset based on a reset signal synchronized to the output clock signal OUT_CLK. For example, an intermediate clock signal ICLK may be synchronized to the output clock signal OUT_CLK. Alternatively, the intermediate clock signal ICLK may have a phase similar to that of the output clock signal OUT_CLK.

[0052] Figure 8 This is a block diagram illustrating a PLL circuit according to one or more embodiments.

[0053] Reference Figure 1 and Figure 8 The PLL circuit 100b may include a phase detector 110, a voltage generator 120, an oscillator 130, a reset synchronization circuit 140, and first frequency dividers 150a to Nth frequency dividers 150n. The first frequency dividers 150a to Nth frequency dividers 150n can be connected in series. This is because the PLL circuit 100b, phase detector 110, voltage generator 120, oscillator 130, and reset synchronization circuit 140 are respectively connected to… Figure 1The PLL circuit 100, phase detector 110, voltage generator 120, oscillator 130 and reset synchronization circuit 140 are the same or similar, so their repeated descriptions are omitted.

[0054] The Nth frequency divider 150n can receive the output clock signal OUT_CLK and can generate and output a first intermediate clock signal ICLK1. For example, the Nth frequency divider 150n can perform frequency division based on a preset first frequency division ratio of the output clock signal OUT_CLK. The Nth frequency divider 150n can output the first intermediate clock signal ICLK1 to the (N-1)th frequency divider 150n-1.

[0055] The (N-1)th frequency divider 150n-1 can receive a first intermediate clock signal ICLK1 and can generate and output a second intermediate clock signal ICLK2 (not shown). The (N-1)th frequency divider 150n-1 can generate the second intermediate clock signal ICLK2 by dividing the first intermediate clock signal ICLK1. For example, the (N-1)th frequency divider 150n-1 can divide the first intermediate clock signal ICLK1 based on a preset second division ratio. The second division ratio can be equal to or different from the first division ratio. The (N-1)th frequency divider 150n-1 can output the second intermediate clock signal ICLK2 to the (N-2)th frequency divider 150n-2 (not shown).

[0056] The second frequency divider 150b can receive the (N-2)th intermediate clock signal ICLKn-2 (not shown) and can generate and output the (N-1)th intermediate clock signal ICLKn-1. The second frequency divider 150b can generate the (N-1)th intermediate clock signal ICLKn-1 by dividing the (N-2)th intermediate clock signal ICLKn-2. For example, the second frequency divider 150b can divide the (N-2)th intermediate clock signal ICLKn-2 based on a preset (N-1)th division ratio. For example, the (N-1)th division ratio can be equal to or different from the first to the (N-2)th division ratios. The second frequency divider 150b can output the (N-1)th intermediate clock signal ICLKn-1 to the first frequency divider 150a.

[0057] The first frequency divider 150a can receive the (N-1)th intermediate clock signal ICLKn-1 and the synchronization reset signal SYNC_RST, and can generate and output a feedback clock signal FB_CLK. The first frequency divider 150a can generate the feedback clock signal FB_CLK by dividing the (N-1)th intermediate clock signal ICLKn-1. For example, the first frequency divider 150a can divide the (N-1)th intermediate clock signal ICLKn-1 based on a preset Nth division ratio. For example, the Nth division ratio can be equal to or different from the first to the (N-1)th division ratios. The first frequency divider 150a can output the feedback clock signal FB_CLK to the phase detector 110.

[0058] In one or more embodiments, the first frequency divider 150a may be reset in response to a synchronization reset signal SYNC_RST. The first frequency divider 150a may generate a feedback clock signal FB_CLK synchronized to the reference clock signal REF_CLK based on the synchronization reset signal SYNC_RST synchronized to the reference clock signal REF_CLK. The first frequency divider 150a may generate a feedback clock signal FB_CLK having a phase similar to that of the reference clock signal REF_CLK.

[0059] In one or more embodiments, the first frequency divider 150a may be reset based on a synchronization reset signal SYNC_RST synchronized to the reference clock signal REF_CLK. The PLL circuit 100b may utilize the synchronization reset signal SYNC_RST to reset only the first frequency divider 150a connected to the phase detector 110, thereby adjusting the phase of the feedback clock signal FB_CLK generated by the first frequency divider 150a to be similar to the phase of the reference clock signal REF_CLK.

[0060] Figure 9 yes Figure 1 The flowchart shows the operation method of the PLL circuit 100.

[0061] Reference Figure 1 and Figure 9 The operation method of PLL circuit 100 may include operations S110 to S170.

[0062] In operation S110, PLL circuit 100 can generate a synchronous reset signal SYNC_RST synchronized to the reference clock signal REF_CLK. Reset synchronization circuit 140 can receive the reset signal RST and the reference clock signal REF_CLK, and can output a synchronous reset signal SYNC_RST with a phase equal to or similar to that of the reference clock signal REF_CLK.

[0063] In operation S120, PLL circuit 100 can reset frequency divider 150 in response to the synchronous reset signal SYNC_RST. Frequency divider 150 can receive the synchronous reset signal SYNC_RST and can be reset in response to the activated synchronous reset signal SYNC_RST.

[0064] In operation S130, PLL circuit 100 can generate an output clock signal OUT_CLK. For example, oscillator 130 can receive input voltage VIN and generate an output clock signal OUT_CLK with a frequency corresponding to the input voltage VIN.

[0065] In operation S140, PLL circuit 100 can generate feedback clock signal FB_CLK by dividing the output clock signal OUT_CLK. For example, frequency divider 150 can generate feedback clock signal FB_CLK synchronized to reference clock signal REF_CLK. Frequency divider 150 can generate feedback clock signal FB_CLK with a phase equal to or similar to that of reference clock signal REF_CLK.

[0066] In operation S150, the PLL circuit 100 can detect the phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK. The phase detector 110 can generate a phase difference signal PD corresponding to the detected phase difference.

[0067] In operation S160, PLL circuit 100 can generate an input voltage VIN corresponding to the phase difference. Voltage generator 120 can receive the phase difference signal PD from phase detector 110 and can generate the input voltage VIN. Voltage generator 120 can generate an input voltage VIN corresponding to the phase difference signal PD.

[0068] In operation S170, PLL circuit 100 can generate an output clock signal OUT_CLK with a frequency corresponding to the input voltage VIN. For example, oscillator 130 can generate an output clock signal OUT_CLK with a frequency corresponding to the amplitude of the input voltage VIN based on power supplied from the positive power supply voltage.

[0069] As described above, the PLL circuit 100 can synchronize the reset signal RST to the reference clock signal REF_CLK. The PLL circuit 100 can generate a feedback clock signal FB_CLK synchronized to the reference clock signal REF_CLK based on the synchronized reset signal SYNC_RST. Therefore, the PLL circuit 100 can have improved lockout time. The operating speed of the PLL circuit 100 can be increased.

[0070] Figure 10 This is a block diagram illustrating a storage system according to one or more embodiments.

[0071] Reference Figure 1 and Figure 10 The storage system 1000 may include a host device 10 and a storage device 1100. The storage device 1100 may include a storage controller 1200 and a non-volatile memory device 1300.

[0072] In one or more embodiments, the memory controller 1200 and the non-volatile memory device 1300 may be implemented by semiconductor chips that are separate from each other. Additionally, according to one or more embodiments, the components of this disclosure may be defined by various other terms. For example, the memory device 1100 may be referred to as a memory system or a data processing system, and the memory controller 1200 may be referred to as a memory controller, etc.

[0073] Storage device 1100 may include a storage medium for storing data in response to a request from host device 10. For example, storage device 1100 may include one or more solid-state drives (SSDs). When storage device 1100 includes an SSD, non-volatile memory device 1300 may include a plurality of flash memory chips (e.g., NAND chips) for non-volatile storage of data.

[0074] As another example, storage device 1100 may include various types of memory. For example, storage device 1100 may include non-volatile memory such as magnetic random access memory (MRAM), spin-torque MRAM, conductive bridge RAM (CBRAM), ferroelectric RAM (FeRAM), phase change RAM (PRAM), resistive RAM (RRAM), nanotube RAM, polymer RAM (PoRAM), nanofloating gate memory (NFGM), holographic memory, molecular electronic memory, or insulator resistance change memory.

[0075] Storage device 1100 can communicate with host device 10 via various interfaces. For example, storage device 1100 can communicate with host device 10 via various interfaces such as Universal Serial Bus (USB), Multimedia Card (MMC), Peripheral Component Interconnect High Speed ​​(PCIe), Advanced Technology Accessories (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Compute High Speed ​​Link (CXL), and Non-Volatile Memory High Speed ​​(NVMe).

[0076] In one or more embodiments, host device 10 may include host processor 11 and host memory 12. Host device 10 may be implemented by a variety of electronic devices, such as computers, laptops, smartphones, smart tablets, and smartwatches. Host processor 11 can control all operations of host device 10 by executing instructions stored in host memory 12. Host device 10 can encode or decode packets that satisfy standards defined in a particular interface. Host device 10 can generate packets indicating write or read operations as commands. Additionally, host device 10 can receive responses provided from storage device 1100.

[0077] The non-volatile memory device 1300 may include one or more NAND chips (or non-volatile memory), and each of the one or more NAND chips may include a memory cell array and peripheral circuitry. For example, the peripheral circuitry of each NAND chip may perform write, read, and erase operations on data based on the control of the memory controller 1200, and the memory cell array of each NAND chip may include one or more blocks.

[0078] The storage controller 1200 can control the non-volatile memory device 1300. The storage controller 1200 can communicate with the host device 10. The storage controller 1200 may include a processor 1210, internal memory 1220, error correction code (ECC) engine 1230, host interface circuitry 1240, memory interface circuitry 1250, and bus 1260.

[0079] In one or more embodiments, various types of software executable by processor 1210 may be loaded onto internal memory 1220, and as an example, a flash translation layer (FTL) may be loaded onto internal memory 1220. Internal memory 1220 may store or output stored data under the control of storage controller 1200. In one or more embodiments, internal memory 1220 may include volatile memory. Internal memory 1220 may include RAM. For example, internal memory 1220 may include static RAM or dynamic RAM. However, this disclosure is not limited thereto.

[0080] At least one processor 1210 can control all operations of the memory controller 1200 by executing various software (or instructions) stored in the internal memory 1220. The processor 1210 can drive an operating system or firmware for driving the memory controller 1200. The processor 1210 can read interpreted requests stored in the internal memory 1220 and can generate commands and addresses for controlling the non-volatile memory device 1300. The processor 1210 can transmit the generated commands and addresses to the memory interface circuitry 1250.

[0081] Processor 1210 may store various metadata used for managing storage device 1100 in internal memory 1220. Processor 1210 may temporarily store data received from host device 10 and to be written to non-volatile memory 1300 or data read from non-volatile memory 1300 and to be transmitted to host device 10 in internal memory 1220.

[0082] Processor 1210 can control host interface circuit 1240 to send data stored in internal memory 1220 to host device 10 outside storage device 1100. Processor 1210 can control memory interface circuit 1250 to store data received from non-volatile memory device 1300 in internal memory 1220. Processor 1210 can control host interface circuit 1240 to store data received from external host device 10 in internal memory 1220.

[0083] The memory interface circuit 1250 provides an interface to one or more NAND chips contained in the non-volatile memory device 1300. For example, the memory interface circuit 1250 can communicate independently with the NAND chips via multiple channels.

[0084] The host interface circuit 1240 can communicate with the host via various interfaces such as PCIe and NVMe. The host interface circuit 1240 can store decoded requests in internal memory 1220. Furthermore, the host interface circuit 1240 can store data received from the external host device 10 in internal memory 1220. Additionally, the host interface circuit 1240 can send data stored in internal memory 1220 to the external host device 10. The host interface circuit 1240 can send various responses to the external host device 10. The host interface circuit 1240 can exchange signals with the external host device 10 based on a defined communication protocol.

[0085] ECC engine 1230 performs error detection and error correction on read data read from non-volatile memory device 1300. More specifically, ECC engine 1230 generates parity bits for write data to be written to non-volatile memory device 1300, and the generated parity bits are stored in non-volatile memory device 1300 along with the write data. When reading data from non-volatile memory device 1300, ECC engine 1230 can correct errors in the read data by using the parity bits read from non-volatile memory device 1300 along with the read data, and can output error-corrected read data.

[0086] Bus 1260 provides a communication channel between components in storage controller 1200. Host interface circuitry 1240 can receive various requests from external host device 10 and can interpret the received requests.

[0087] In one or more embodiments, the storage controller 1200 may receive a reference clock signal REF_CLK from an external host device 10. The host interface circuitry 1240 may include a PLL circuitry 1241. The PLL circuitry 1241 may include a reference clock signal REF_CLK. Figures 1 to 9 The described PLL circuit 100. The PLL circuit 1241 can be referenced... Figures 1 to 9 The described method generates the output clock signal OUT_CLK. The PLL circuit 1241 can be referenced... Figures 1 to 9 The described method performs a locking operation.

[0088] In one or more embodiments, PLL circuit 1241 may generate output clock signal OUT_CLK based on reference clock signal REF_CLK. Memory controller 1200 may establish a link with host device 10 by using output clock signal OUT_CLK as an internal clock signal. Memory controller 1200 may access non-volatile memory device 1300 based on requests transmitted from host device 10 via this link or according to internally determined scheduling.

[0089] When returning from a low-power mode (e.g., L1 state) to an enabled mode (e.g., L0 state), the memory device struggles to perform the mode switch within the standard required time due to the excessively long lockout time in the PLL circuitry. Therefore, there is a limitation that the PLL circuitry cannot be powered down when the memory device enters a low-power mode. The lockout time in the PLL circuitry is determined based on the initial phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK.

[0090] As described above, the storage device 1100 according to one or more embodiments can generate a synchronous reset signal SYNC_RST by synchronizing a reset signal RST to a reference clock signal REF_CLK. The storage device 1100 can reset the divider in the PLL circuit 1241 based on the synchronous reset signal SYNC_RST. Therefore, the storage device 1100 can generate a feedback clock signal FB_CLK synchronized to the reference clock signal REF_CLK. Thus, the storage device 1100 can reduce the initial phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK. The lock time in the PLL circuit 1241 can be reduced. The storage device 1100 can power down the PLL circuit 1241 in a low-power mode (e.g., L1 state). Both the storage device 1100 and the storage system 1000 are provided with reduced power consumption. In other words, the PLL circuit 1241 is configured to power down based on entering a low-power mode.

[0091] Figure 11 To show in more detail Figure 10 Block diagram of the host interface circuit 1240.

[0092] Reference Figure 1 , Figure 10 and Figure 11The host interface circuit 1240 may include a PLL circuit 1241, a receiver 1242, a deserializer 1243, a decoder 1244, a receiver logic 1245, a transmitter logic 1246, an encoder 1247, a serializer 1248, and a driver 1249.

[0093] PLL circuit 1241 can receive a reference clock signal REF_CLK and output an output clock signal OUT_CLK synchronized to the reference clock signal REF_CLK. Receiver 1242 can receive signals from host device 10 via a link. Receiver 1242 can be synchronized to the output clock signal OUT_CLK and receive signals. The signals received by receiver 1242 can be of a first type (e.g., serial type). The signals received by receiver 1242 can be part of a packet or a symbol. Receiver 1242 can amplify the received signals and transmit the amplified signals to deserializer 1243.

[0094] Deserializer 1243 can receive signals from receiver 1242. Deserializer 1243 can deserialize (or parallelize) the received signals. Deserializer 1243 can transmit a second type (e.g., parallel type) of deserialized (or parallel) signals to decoder 1244.

[0095] Decoder 1244 can receive a second type of signal from deserializer 1243. Decoder 1244 can decode the second type of signal. For example, decoder 1244 can perform symbol decoding to extract bits from a symbol. Decoder 1244 can extract 8 bits of data from a 10-bit symbol. Alternatively, decoder 1244 can extract 128 bits of data from a 130-bit symbol. Decoder 1244 can transmit the decoded signal to receiver logic 1245.

[0096] Receiver logic 1245 can receive decoded signals from decoder 1244. Receiver logic 1245 can determine the compliance of the decoded signals by performing a mode check on the decoded signals. For example, receiver logic 1245 can determine whether the decoded signals conform to a communication protocol (e.g., PCIe), and if the decoded signals conform to a communication protocol (e.g., PCIe), it can determine which generation of the protocol the decoded signals conform to. When the mode check is successful, receiver logic 1245 can transmit the decoded signals to processor 1210 via bus 1260.

[0097] Transmitter logic 1246 may receive a second type (e.g., parallel type) signal from processor 1210 via bus 1260. Transmitter logic 1246 may combine a mode with the second type of signal. For example, the mode may indicate which generation of communication protocol (e.g., PCIe) the mode corresponds to. Transmitter logic 1246 may transmit the combined signal to encoder 1247.

[0098] Encoder 1247 can receive combined signals from transmitter logic 1246. Encoder 1247 can encode the combined signals. For example, encoder 1247 can perform symbol encoding for generating symbols from bits. Encoder 1247 can generate 10-bit symbols from 8-bit data. Alternatively, encoder 1247 can generate 130-bit symbols from 128-bit data. Encoder 1247 can transmit the encoded signal to serializer 1248.

[0099] Serializer 1248 can receive encoded signals from encoder 1247. Serializer 1248 can receive an output clock signal OUT_CLK from PLL circuit 1241. Serializer 1248 can generate a first type (e.g., serial type) signal based on the output clock signal OUT_CLK by serializing the encoded signal. Serializer 1248 can transmit the first type signal to driver 1249. Driver 1249 can receive the first type signal from serializer 1248. Driver 1249 can transmit the first type signal to host device 10.

[0100] In one or more embodiments, the link between the storage controller 1200 and the host device 10 may have multiple states. For example, the multiple states may include an initial state, a detection state, a polling state, a configuration state, an L0 state, an L0s state, an L1 state, an L2 state, a disabled state, a recovery state, a loopback state, and / or a hot reset state.

[0101] In one or more embodiments, the storage controller 1200 may enter an L0 state after a configuration state. The L0 state may be an enabled state or a normal state. In the L0 state, the storage controller 1200 may communicate with the host device 10 via a link. The storage controller 1200 may enter an L1 state from the L0 state. The L1 state may be a power-saving state or a low-power state for reducing power consumption. For example, the L0 state may correspond to an enabled mode or a high-speed mode, and the L1 state may correspond to a low-power mode.

[0102] In one or more embodiments, the PLL circuit 1241 can be de-energized when the memory controller 1200 transitions from an L0 state to an L1 state. The PLL circuit 1241 can be energized when the memory controller 1200 transitions from an L1 state to an L0 state (or exits from an L1 state). In response to energizing the PLL circuit 1241, the PLL circuit 1241 can output a clock signal OUT_CLK based on a reference clock signal REF_CLK. The PLL circuit 1241 can perform a locking operation to lock the phase of the output clock signal OUT_CLK.

[0103] In one or more embodiments, in the L0 state, the PLL circuit 1241 is powered on and can generate and output a clock signal OUT_CLK. For example, the PLL circuit 1241 can provide the output clock signal OUT_CLK to the receiver 1242, serializer 1248, etc. The memory controller 1200 can communicate with the host device 10 via a link. In the L1 state, the PLL circuit 1241 is powered off and may not generate the output clock signal OUT_CLK. Therefore, power consumption can be reduced.

[0104] Figure 12 It is shown Figure 10 A flowchart illustrating an example of the operation method of the storage controller 1200.

[0105] Reference Figure 10 and Figure 12 During operation S210, the storage controller 1200 may enter a low-power mode. In one or more embodiments, the storage controller 1200 may switch from an L0 state to an L1 state.

[0106] In operation S220, the storage controller 1200 can de-energize the PLL circuit 1241. The storage controller 1200 can de-energize the PLL circuit 1241 in response to entering a low-power mode. For example, the storage controller 1200 can de-energize the PLL circuit 1241 based on entering an L1 state. Therefore, the power consumption of the storage device 1100 can be reduced.

[0107] In one or more embodiments, in a low-power mode (or L1 state), the PLL circuit 1241 may be powered off. The PLL circuit 1241 may not generate an output clock signal OUT_CLK. Alternatively, in a low-power mode (or L1 state), the PLL circuit 1241 may be powered off. The PLL circuit 1241 may not output a clock signal OUT_CLK.

[0108] As described above, in low-power mode, the storage controller 1200 can power off the PLL circuit 1241, thereby reducing the power consumption of the storage controller 1200.

[0109] Figure 13It is shown Figure 10 A flowchart illustrating an example of the operation method of the storage controller 1200.

[0110] Reference Figure 10 and Figure 13 In operation S310, the storage controller 1200 can exit the low-power mode. The storage controller 1200 can exit the L1 state. For example, when a data request is detected, the storage controller 1200 can switch from the L1 state to the L0 state. In other words, the PLL circuit 1241 can be powered on based on exiting the low-power mode.

[0111] In operation S320, the storage controller 1200 can energize the PLL circuit 1241. In operation S330, in response to the energization of the PLL circuit 1241, the storage controller 1200 can synchronize the reset signal RST based on the reference clock signal REF_CLK, thereby enabling the PLL circuit 1241 to perform a locking operation. The PLL circuit 1241 can generate a synchronous reset signal SYNC_RST by synchronizing the reset signal RST to the reference clock signal REF_CLK. The PLL circuit 1241 can reset the frequency divider 150 based on the synchronous reset signal SYNC_RST. The PLL circuit 1241 can generate a feedback clock signal FB_CLK synchronized to the reference clock signal REF_CLK. The PLL circuit 1241 can lock the phase of the output clock signal OUT_CLK. The PLL circuit 1241 can reduce the phase difference between the feedback clock signal FB_CLK and the reference clock signal REF_CLK, thereby reducing the time required to perform the locking operation.

[0112] During operation S340, the storage controller 1200 can return to the enabled mode. The storage controller 1200 can enter the L0 state. The storage controller 1200 can communicate with the host device 10 based on the output clock signal OUT_CLK.

[0113] As described above, the memory controller 1200 can generate a feedback clock signal FB_CLK with a phase equal to or similar to that of the reference clock signal REF_CLK by using the synchronous reset signal SYNC_RST. Therefore, the latch time in the PLL circuit 1241 can be reduced. During the process of returning from low-power mode to enable mode, the required timing conditions can be met as the time for the PLL circuit 1241 to perform the latch operation is reduced.

[0114] Figure 14 This is a diagram of a system that utilizes a PLL circuit according to one or more embodiments. Figure 14The system 2000 can essentially be a mobile system, such as a portable communication terminal (e.g., a mobile phone), a smartphone, a tablet PC, a wearable device, a healthcare device, or an Internet of Things (IoT) device. However, Figure 14 The System 2000 is not necessarily limited to mobile systems, and can be a PC, laptop computer, server, media player, or automotive device (e.g., navigation device).

[0115] Reference Figure 14 System 2000 may include a main processor 2100, memory (e.g., 2200a and 2200b), and storage devices (e.g., 2300a and 2300b). Additionally, system 2000 may include at least one of an image capture device 2410, a user input device 2420, a sensor 2430, a communication device 2440, a display 2450, a speaker 2460, a power supply device 2470, and a connection interface 2480.

[0116] The main processor 2100 can control all operations of the system 2000, and more specifically, can control the operations of other components included in the system 2000. The main processor 2100 can be implemented as a general-purpose processor, a special-purpose processor, or an application processor.

[0117] The main processor 2100 may include at least one CPU core 2110 and a controller 2120 configured to control memories 2200a and 2200b and / or storage devices 2300a and 2300b. In one or more embodiments, the main processor 2100 may also include an accelerator 2130, which is dedicated circuitry for high-speed data operations such as artificial intelligence (AI) data operations. The accelerator 2130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and may be implemented as a chip physically separate from other components of the main processor 2100.

[0118] Memory 2200a and 2200b may be used as the main memory device of system 2000. Although each of memory 2200a and 2200b may include volatile memory (such as static RAM (SRAM) and / or dynamic RAM (DRAM)), each of memory 2200a and 2200b may include non-volatile memory (such as flash memory, PRAM and / or RRAM). Memory 2200a and 2200b may be implemented in the same package as main processor 2100.

[0119] Storage devices 2300a and 2300b can be used as non-volatile storage devices configured to store data regardless of power supply, and have a larger storage capacity than memories 2200a and 2200b. Storage devices 2300a and 2300b may each include storage controllers 2310a and 2310b and non-volatile memory (NVM) 2320a and 2320b configured to store data under the control of storage controllers 2310a and 2310b. Although NVMs 2320a and 2320b may include flash memory with a two-dimensional (2D) or three-dimensional (3D) V-NAND structure, NVMs 2320a and 2320b may include other types of NVMs, such as PRAM and / or RRAM.

[0120] Storage devices 2300a and 2300b may be physically separate from the main processor 2100 and included in the system 2000, or implemented in the same package as the main processor 2100. Additionally, storage devices 2300a and 2300b may be of the type of solid-state drive (SSD) or memory card, and may be removably combined with other components of the system 2000 via an interface such as connection interface 2480, which will be described below. Storage devices 2300a and 2300b may be devices applying standard protocols, such as Universal Flash Memory (UFS), embedded multimedia card (eMMC), or Non-Volatile Memory High Speed ​​(NVMe), but are not limited to these.

[0121] Image capture device 2410 can capture still images or moving images. Image capture device 2410 may include a camera, video camera, and / or webcam.

[0122] User input device 2420 can receive various types of data input by the user of system 2000, and includes a touchpad, keypad, mouse and / or microphone.

[0123] Sensor 2430 can detect various types of physical quantities that can be obtained from outside the system 2000 and convert the detected physical quantities into electrical signals. Sensor 2430 may include temperature sensors, pressure sensors, illuminance sensors, position sensors, acceleration sensors, biosensors, and / or gyroscope sensors.

[0124] The communication device 2440 can send and receive signals between other devices outside the system 2000 according to various communication protocols. The communication device 2440 may include an antenna, a transceiver, and / or a modem.

[0125] The display 2450 and the speaker 2460 can be used as output devices configured to output visual and auditory information to the user of the system 2000, respectively.

[0126] The power supply unit 2470 can appropriately convert power supplied from a battery embedded in the system 2000 and / or an external power source, and provide the converted power to each component of the system 2000.

[0127] The connection interface 2480 provides a connection between the system 2000 and an external device that connects to the system 2000 and is able to send and receive data from the system 2000. The connection interface 2480 can be implemented using various interface schemes such as ATA, SATA, external SATA (e-SATA), SCSI, SAS, PCI, PCIe, NVMe, IEEE 1394, USB, Secure Digital (SD) card interface, Multimedia Card (MMC) interface, eMMC interface, UFS interface, Embedded UFS (eUFS) interface, and Compact Flash (CF) card interface.

[0128] In one or more embodiments, each of the storage devices 2300a and 2300b may include a reference. Figures 1 to 13 The described PLL circuit. Each of the storage devices 2300a and 2300b can synchronize the feedback clock signal FB_CLK to the reference clock signal REF_CLK, as referenced... Figures 1 to 13 As described. Therefore, each of the storage devices 2300a and 2300b can minimize the lock-in time in the PLL circuit and can have reduced power consumption.

[0129] According to one aspect of this disclosure, a method of operating a memory device including a memory controller and a non-volatile memory device, the memory controller including a phase-locked loop circuit, the method comprising: generating a synchronous reset signal synchronized to a reference clock signal; resetting a frequency divider in the phase-locked loop circuit based on the synchronous reset signal; generating an output clock signal; generating a feedback clock signal by dividing the output clock signal; detecting a phase difference between the reference clock signal and the feedback clock signal; generating an input voltage corresponding to the phase difference; and generating an output clock signal having a frequency corresponding to the input voltage.

[0130] The feedback clock signal can be synchronized with the reference clock signal.

[0131] The operation method may also include receiving a reference clock signal from an external host device.

[0132] The operation method may also include: entering a low-power mode; and, based on entering the low-power mode, de-energizing the phase-locked loop circuit.

[0133] The operation method may also include: exiting the low-power mode; energizing the phase-locked loop circuit; based on the energization of the phase-locked loop circuit, synchronizing the synchronous reset signal based on the reference clock signal, performing a locking operation to lock the phase of the output clock signal; and returning to the enabled mode.

[0134] The low-power mode corresponds to the L1 state of the PCIe high-speed standard, and the enabled mode corresponds to the L0 state of the PCIe standard.

[0135] Although certain exemplary embodiments of this disclosure have been specifically shown and described, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A storage device, comprising: Non-volatile memory devices; as well as A storage controller configured to control the non-volatile memory device and communicate with an external host device, the storage controller including a phase-locked loop circuit. The phase-locked loop circuit includes: A phase detector is configured to receive a reference clock signal and a feedback clock signal, and output a phase difference signal corresponding to the phase difference between the reference clock signal and the feedback clock signal; A voltage generator is configured to receive the phase difference signal, generate an input voltage corresponding to the phase difference signal, and output the input voltage. An oscillator is configured to receive the input voltage, generate an output clock signal having a frequency corresponding to the input voltage, and output the output clock signal. A reset synchronization circuit is configured to receive a reset signal and the reference clock signal, synchronize the reset signal based on the reference clock signal to generate a synchronized reset signal, and output the synchronized reset signal; and The frequency divider is configured to receive the synchronous reset signal and the output clock signal, reset based on the synchronous reset signal, generate the feedback clock signal by dividing the output clock signal, and output the feedback clock signal.

2. The storage device as claimed in claim 1, wherein, The feedback clock signal is synchronized to the reference clock signal.

3. The storage device as claimed in claim 1, wherein, The voltage generator includes: A loop filter, configured to filter out noise frequencies; and A charge pump configured to provide charge to or draw charge from the loop filter based on the phase difference signal.

4. The storage device as claimed in claim 1, wherein, The reset synchronization circuit includes a flip-flop configured to receive the reference clock signal via a clock input terminal, receive the reset signal via an input terminal, and output the synchronization reset signal via an output terminal.

5. The storage device as claimed in claim 1, wherein, The reset synchronization circuit includes: A multiplexer configured to receive a selection signal, the reference clock signal, and the output clock signal, and to output one of the reference clock signal and the output clock signal as a selection clock signal based on the selection signal. A trigger is configured to receive the selected clock signal via a clock input terminal, receive the reset signal via an input terminal, and output the synchronous reset signal via an output terminal.

6. The storage device as claimed in claim 1, wherein, The storage controller is also configured to receive the reference clock signal from the external host device.

7. The storage device as claimed in claim 1, wherein, The storage controller is also configured to power off the phase-locked loop circuit based on entering a low-power mode.

8. The storage device as claimed in claim 1, wherein, The storage controller is also configured to power the phase-locked loop circuit based on exiting the low-power mode.

9. The storage device as claimed in claim 8, wherein, The phase-locked loop circuit is configured to perform a locking operation to lock the phase of the output clock signal by synchronizing the reset signal with the reference clock signal when powered on.

10. The storage device of claim 8, wherein, The low-power mode corresponds to the L1 state of the PCI high-speed PCIe standard.

11. A phase-locked loop circuit, comprising: A phase detector is configured to receive a reference clock signal and a feedback clock signal, and output a phase difference signal corresponding to the phase difference between the reference clock signal and the feedback clock signal; A reset synchronization circuit is configured to receive a reset signal and the reference clock signal, synchronize the reset signal based on the reference clock signal to generate a synchronized reset signal, and output the synchronized reset signal. as well as A frequency divider is configured to receive the synchronous reset signal and an output clock signal, perform a reset based on the synchronous reset signal, generate the feedback clock signal by dividing the output clock signal, and output the feedback clock signal to the phase detector. The phase-locked loop circuit is configured to perform a locking operation to lock the phase of the output clock signal by synchronizing the reset signal with the reference clock signal when powered on.

12. The phase-locked loop circuit as described in claim 11, wherein, The reset synchronization circuit includes a flip-flop configured to receive the reference clock signal via a clock input terminal, receive the reset signal via an input terminal, and output the synchronization reset signal via an output terminal.

13. The phase-locked loop circuit as described in claim 11, wherein, The reset synchronization circuit includes: A multiplexer configured to receive a selection signal, the reference clock signal, and the output clock signal, and to output one of the reference clock signal and the output clock signal as a selection clock signal based on the selection signal. A trigger is configured to receive the selected clock signal via a clock input terminal, receive the reset signal via an input terminal, and output the synchronous reset signal via an output terminal.

14. The phase-locked loop circuit as described in claim 11, wherein, The phase-locked loop circuit is configured to power off based on entering a low-power mode.

15. The phase-locked loop circuit as described in claim 11, wherein, The phase-locked loop circuit is configured to be powered on based on exiting the low-power mode.

16. The phase-locked loop circuit as described in claim 14, wherein, The low-power mode corresponds to the L1 state of the PCI high-speed PCIe standard.

17. A phase-locked loop circuit, comprising: A phase detector is configured to receive a reference clock signal and a feedback clock signal, and output a phase difference signal corresponding to the phase difference between the reference clock signal and the feedback clock signal. A voltage generator is configured to receive the phase difference signal, generate an input voltage corresponding to the phase difference signal, and output the input voltage. An oscillator is configured to receive the input voltage, generate an output clock signal having a frequency corresponding to the input voltage, and output the output clock signal. A reset synchronization circuit is configured to receive a reset signal and the reference clock signal, synchronize the reset signal based on the reference clock signal to generate a synchronized reset signal, and output the synchronized reset signal. as well as The frequency divider is configured to receive the synchronous reset signal and the output clock signal, reset based on the synchronous reset signal, generate the feedback clock signal by dividing the output clock signal, and output the feedback clock signal.

18. The phase-locked loop circuit as described in claim 17, wherein, The feedback clock signal is synchronized to the reference clock signal.

19. The phase-locked loop circuit as described in claim 17, wherein, The reset synchronization circuit includes a flip-flop configured to receive the reference clock signal via a clock input terminal, receive the reset signal via an input terminal, and output the synchronization reset signal via an output terminal.

20. The phase-locked loop circuit as described in claim 17, wherein, The reset synchronization circuit includes a flip-flop and a multiplexer. The multiplexer is configured to receive a selection signal, a reference clock signal, and an output clock signal, and to output one of the reference clock signal and the output clock signal as a selection clock signal based on the selection signal. The trigger is configured to receive the selection clock signal via a clock input terminal, receive the reset signal via an input terminal, and output the synchronous reset signal via an output terminal.

Images