Control word digital adjustment circuit

Abstract

The application provides a control word digital adjustment circuit applied to a retimer based on a fractional N phase-locked loop, comprising a digital low-pass filter module, a control word adjustment module and a rate conversion module; wherein the digital low-pass filter module is used for filtering high-frequency jitter and part of low-frequency jitter in an initial control word to generate a filtered control word; the control word adjustment module is used for adjusting the filtered control word to generate an adjusted control word; the rate conversion module is used for speed conversion processing on the adjusted control word to generate a speed-converted control word; and the speed-converted control word is used for replacing the initial control word as an input of a transmitter fractional N phase-locked loop in the retimer. The application can effectively solve the problem that the existing scheme cannot simultaneously realize rate conversion and jitter elimination.

Description

Technical Field

[0001] This invention relates to the field of high-speed signal transmission technology, and more specifically, to a control word digital adjustment circuit. Background Technology

[0002] With the increasing demand for transmission bandwidth in applications such as large-scale data centers and high-performance computing, signal attenuation has become a more serious problem. The integrity and stability of signal transmission have become limiting factors for further increases in transmission speed and distance. Retimers offer a cost-effective solution to signal attenuation. Retimer chips have strong signal recovery capabilities and long data transmission distances, enabling large-scale data transmission in fields such as AI servers.

[0003] The primary function of a retimer is to recover the received signal and retransmit it, ensuring signal integrity and stability during long-distance transmission or in complex topologies. The retimer recovers the clock and retransmits the received data via a CDR (Clock Data Recovery unit). However, the clock recovered by the CDR often contains significant jitter, which affects the quality of the transmitted signal. During retransmission, a noticeable jitter shift occurs, further impacting signal quality and leading to performance degradation at the target node or the inability to fully recover the original data sent by the node.

[0004] like Figure 1This is a simplified block diagram of a retimer implemented based on an ADC (Analog to Digital Converter) + DSP (Digital Signal Processing) architecture using a fractional-N phase-locked loop (FnPLL). The data sampled by the ADC is processed in the DEMOD (demodulation) module, such as performing equalization and MLSD (Maximum Likelihood Sequence Detection) signal processing. On one hand, it recovers the data transmitted from the TX (Transmitter) end, outputs parallel symbol information, and writes it into a FIFO (First In First Out) buffer using the RX (Receiver) clock. On the other hand, the DEMOD module contains TE (Timing Error) information generated by a TED (Timing Error Detector). For example, TED can obtain TE information through a Bang-Bang phase detector or a Mueller-Muller phase detector.

[0005] Subsequently, the TE information is processed by a filter in the Clock Data Recovery Loop Filter (CDR Loop Filter) to obtain the FCW (Frequency Control Word) control information for controlling the FnPLL. For example, the CDR Loop Filter can be a second-order loop filter, which is a typical proportional-integral control system. This second-order loop filter controls the FnPLL through two channels, where, for the first channel, TE is multiplied by the phase coefficient K. P For the second channel, TE is multiplied by the integral coefficient K. I The signals are then accumulated to obtain the frequency offset signal, which is then added to the first channel and multiplied by the loop gain control factor K. G This allows us to obtain the control signal FCW for FnPLL, which is then used to control FnPLL.

[0006] In practical use, two FnPLLs are usually used, namely RX FnPLL and TX FnPLL. RX FnPLL is used to generate RX clock, and TX FnPLL is used to generate TX clock. Both FnPLLs are controlled by the FCW recovered by the clock data recovery loop filter.

[0007] However, for the above-mentioned retimer architecture, the FCW recovered by the clock data recovery loop filter has significant jitter. Therefore, the TX clock generated by using this FCW through the TX FnPLL also has significant jitter. When the signal is retransmitted in the future, there will be obvious jitter transfer, which will affect the performance of the retimer.

[0008] In addition, since the FCW recovered by the clock data recovery loop filter often has a large bit width, when it is output to TX for asynchronous reading, the correct FCW value may not be read, which will cause frequency deviation jitter between the RX clock and the TX clock, resulting in overflow or underflow when reading data in the FIFO.

[0009] To address the technical issues arising from the aforementioned retimer architecture, the traditional approach is to adjust the bandwidth of the LPF (Low Pass Filter) in the TX FnPLL to filter out high-frequency and some low-frequency jitter in the TX clock. However, this approach significantly amplifies the low-frequency noise of the output TX clock and leads to a decrease in jitter tolerance performance.

[0010] In addition, existing solutions also add a PLL (phase-locked loop) to perform low-pass filtering on the TX clock, filtering out high-frequency and some low-frequency jitter; however, the main problem with this solution is that the PLL implementation is costly, occupies a large area, and may introduce additional analog non-ideal factors, thereby reducing the jitter tolerance performance of the target node.

[0011] Furthermore, neither of the above two solutions can resolve the frequency deviation jitter issue of the RX and TX clocks caused by FCW due to errors in reading values ​​from the asynchronous interface.

[0012] To address the frequency jitter issue in FCW caused by erroneous readings of values ​​from the asynchronous interface between the RX and TX clocks, patent CN120710500A proposes a retimer scheme based on FnPLL, such as... Figure 2 As shown, this scheme eliminates jitter through digital low-pass filtering and adjusts the filtered FCW by controlling the deviation of the FIFO read / write pointer, thereby solving the problem of frequency deviation jitter in the RX and TX clocks caused by erroneous readings from the asynchronous interface.

[0013] However, research shows that the jitter cancellation scheme provided by patent CN120710500A is only applicable to application scenarios where the transmit and receive data rates are the same. In some specific use cases, the transmit path rate and the receive path rate may differ. Therefore, the filtered FCW control TX FnPLL in patent CN120710500A cannot be directly used for transmission. For example, in the port splitting mode of a switch, a 100Gbps receive channel can be forwarded through two 50Gbps channels. In this case, the transmit rate of each channel is different from that of each receive channel. Another example is in OTN (Optical Transport Network) applications. The data received by the RX may need to have its ODU (Optical Data Unit) overhead removed to obtain the payload. Then, the payload is 64 / 66b encoded and a header is added to generate a new transmission sequence for transmission. In this case, the transmit data rate is different from the receive data rate. Furthermore, there are some loop timing application scenarios where the transmit clock uses the RX clock (i.e., forward clock transmission), and the transmit data rate is independent of the RX rate; that is, the received data is not transmitted.

[0014] Based on the application requirements of different transmission and reception rates, the traditional solution to support variable rates is to design a dedicated PLL or DPLL (digital phase-locked loop) for rate conversion and jitter elimination. However, the disadvantage of this solution is that it requires a complete PLL or DPLL design, which has high design cost and complexity, and also has a large implementation overhead.

[0015] Based on the aforementioned technical issues, there is an urgent need to design a low-cost solution that can achieve rate conversion and jitter elimination. Summary of the Invention

[0016] In view of the above problems, the purpose of this invention is to provide a control digit adjustment circuit to solve the problem that existing solutions cannot simultaneously achieve rate conversion and jitter elimination.

[0017] The control word digital adjustment circuit provided by this invention is applied in a timer based on a fractional-N frequency-locked loop, and includes: a digital low-pass filter module, a control word adjustment module, and a rate conversion module; wherein, The digital low-pass filter module is used to filter out high-frequency jitter and some low-frequency jitter in the initial control word to generate a filtered control word; The control word adjustment module is used to adjust the filter control word to generate an adjustment control word; The rate conversion module is used to perform speed adjustment processing on the adjustment control word to generate a speed adjustment control word; The speed control word is used to replace the initial control word as the input of the fractional N-division frequency-locked loop in the transmitter of the re-timer.

[0018] Alternatively, the rate conversion module may include a multiplier; wherein, The multiplier is positioned before the digital low-pass filter module. The multiplier is used to multiply the initial control word by a scaling factor K, so that the adjustment control word becomes the speed control word; or... The multiplier is located after the digital low-pass filter module. The multiplier is used to multiply the adjustment control word by a scaling factor K to generate the speed control word.

[0019] Alternatively, in the retimer based on fractional-N PLL, the frequency of the transmitter's fractional-N PLL output clock is a multiple of the frequency of the receiver's fractional-N PLL output clock by a scaling factor of K.

[0020] Alternatively, the control word adjustment module can be used to adjust the filter control word based on the write pointer and read pointer of the first-in-first-out buffer in the re-timer, in order to generate an adjustment control word; and, The control word adjustment module includes a read / write pointer comparison unit, a correction amount generation unit, and a control word correction unit. The read / write pointer comparison unit calculates a write pointer lead indication and a read pointer lag indication based on the write pointer and the read pointer. The correction amount generation unit generates a correction amount based on the write pointer lead indication and the read pointer lag indication. The control word correction unit accumulates the correction amount with the filter control word to generate the adjustment control word.

[0021] Alternatively, the read / write pointer comparison unit may include a read / write pointer interval calculation subunit and a comparison judgment subunit; wherein, The write-read pointer interval calculation subunit is used to calculate the write-read pointer interval based on the write pointer and the read pointer; wherein, the write-read pointer interval = the indicator bit of the write pointer - the indicator bit of the read pointer; The comparison and judgment subunit is used to compare the write-read pointer interval with a preset threshold, and determine the write pointer advance indication and the read pointer lag indication based on the comparison result; wherein, if the write-read pointer interval is greater than the preset threshold, the write pointer advance indication = 1, otherwise the write pointer advance indication = 0; If the write / read pointer interval is less than a negative preset threshold, then the read pointer hysteresis indication = 1. ， Otherwise, the read pointer lag indication is 0.

[0022] Alternatively, the correction amount generation unit may include a frequency control word adjustment amount calculation subunit and a correction amount calculation subunit; wherein, The frequency control word adjustment calculation subunit is used to calculate the frequency control word adjustment based on the write pointer advance indication and the read pointer lag indication; The correction calculation subunit is used to calculate the correction amount based on the frequency control word adjustment amount through a preset control word adjustment working mode.

[0023] Alternatively, if the write pointer advance indication = 1, the first adjustment amount is obtained by multiplying the first preset value of the frequency control word adjustment amount by the preset first frequency control word adjustment factor, the second adjustment amount is obtained by multiplying the result of the read pointer lag indication selection by the preset second frequency control word adjustment factor, and the first adjustment amount and the second adjustment amount are added together to obtain the frequency control word adjustment amount. If the read pointer lag indication = 1, then the third adjustment amount is obtained by multiplying the second preset value of the frequency control word adjustment amount by the preset second frequency control word adjustment factor, the fourth adjustment amount is obtained by multiplying the result of the write pointer advance indication selection by the first frequency control word adjustment factor, and the third adjustment amount and the fourth adjustment amount are added together to obtain the frequency control word adjustment amount.

[0024] Alternatively, the control word adjustment mode may include an accumulation mode and a direct adjustment mode; wherein, In the direct adjustment mode, the frequency control word adjustment amount is used as the correction amount; In the accumulation mode, the frequency control word adjustment amounts obtained at least two times are accumulated to obtain the frequency control word adjustment accumulation value, and the frequency control word adjustment accumulation value is used as the correction amount.

[0025] Alternatively, in the accumulation mode, the frequency control word adjustment amount is accumulated once every preset time interval T to obtain the frequency control word adjustment accumulation value.

[0026] Alternatively, the digital low-pass filter module can be constructed based on an alpha filter.

[0027] Compared with existing technologies, the above-mentioned timer based on the control word digital adjustment circuit and the fractional N-division frequency-locked loop has the following advantages: By setting a digital low-pass filter module, high-frequency jitter and some low-frequency jitter in the initial control word can be filtered out to generate a filtered control word. By setting a control word adjustment module, the filtered control word is adjusted to generate an adjusted control word, so that the transmitter's fractional-N PLL can generate the correct TX clock based on the adjusted control word, thereby solving the problem of frequency deviation jitter between the RX and TX clocks caused by erroneous readings from the asynchronous interface in the FCW. By setting a rate conversion module on the FCW generation path of the input TX FnPLL, rate conversion can be achieved with high frequency accuracy and stable performance.

[0028] To achieve the foregoing and related objectives, one or more aspects of the invention include the features which will be described in detail below and specifically pointed out in the claims. The following description and accompanying drawings illustrate certain exemplary aspects of the invention. However, these aspects indicate only a few of the various ways in which the principles of the invention can be used. Furthermore, the invention is intended to include all such aspects and their equivalents. Attached Figure Description

[0029] Other objects and results of the invention will become more apparent and readily understood with reference to the following description taken in conjunction with the accompanying drawings and the contents of the claims, and with a more complete understanding of the invention. In the drawings: Figure 1 The topology of the existing retimer based on fractional N frequency division phase-locked loop; Figure 2 The topology of the re-timer based on fractional-N frequency-locked loop provided by the existing patent CN120710500A; Figure 3 This is a topology for a re-timer based on a fractional-N frequency-locked loop, provided according to an embodiment of the present invention; Figure 4 An enlarged view of the topology of the first control word digital adjustment circuit provided according to an embodiment of the present invention; Figure 5 A partially enlarged view of the topology of the first control word digital adjustment circuit provided according to an embodiment of the present invention; Figure 6 This is a second re-timer topology based on a fractional-N frequency-locked loop provided according to an embodiment of the present invention; Figure 7 This is an enlarged view of the topology of the second control word digital adjustment circuit provided according to an embodiment of the present invention; Figure 8 This is a topology of a first digital low-pass filter module based on an alpha filter provided according to an embodiment of the present invention; Figure 9This is a topology of a second digital low-pass filter module based on an alpha filter provided according to an embodiment of the present invention; Figure 10 This is an address illustration in a first type of first-in-first-out buffer provided according to an embodiment of the present invention; Figure 11 This is an enlarged view of the topology of the correction amount generation unit provided according to an embodiment of the present invention; Figure 12 This is an address illustration of a second type of first-in-first-out (FIFO) buffer provided according to an embodiment of the present invention. Detailed Implementation

[0030] In the following description, numerous specific details are set forth for illustrative purposes and to provide a thorough understanding of one or more embodiments. However, it will be apparent that these embodiments may also be implemented without these specific details. In other instances, well-known structures and devices are shown in block diagram form for ease of description of one or more embodiments.

[0031] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or server that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0032] In the several embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and other division methods may be used in actual implementation.

[0033] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0034] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.

[0035] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0036] Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be embraced within the invention. No appended diagram markings in the claims should be construed as limiting the scope of the claims.

[0037] Figure 3 This illustrates a first re-timer topology based on a fractional-N frequency-locked loop according to an embodiment of the present invention. Figure 4 An enlarged view of the topology of a first control word digital adjustment circuit according to an embodiment of the present invention is shown, in conjunction with... Figure 3 and Figure 4 As can be seen, the control word digital adjustment circuit provided by the present invention is applied in a re-timer based on a fractional-N frequency-locked loop, including: a digital low-pass filter module, a control word adjustment module, and a rate conversion module; wherein, the digital low-pass filter module is used to filter out high-frequency jitter and some low-frequency jitter in the initial control word to generate a filtered control word; the control word adjustment module is used to adjust the filtered control word to generate an adjusted control word; the rate conversion module is used to perform speed adjustment processing on the adjusted control word to generate a speed control word; the speed control word is used to replace the initial control word as the input of the fractional-N frequency-locked loop of the transmitter in the re-timer.

[0038] Furthermore, such as Figure 3 As shown, the retimer based on a fractional-N frequency-locked loop provided by the present invention includes an analog-to-digital conversion module, a demodulation module, a clock data recovery module, and the aforementioned control word digital adjustment circuit. The data sampled by the analog-to-digital conversion module is processed by the demodulation module to generate timing error information. The clock data recovery module generates an initial control word based on the timing error information. The control word digital adjustment circuit adjusts the initial control word to generate an adjusted control word. The fractional-N frequency-locked loop of the transmitter generates and transmits the channel clock based on the adjusted control word.

[0039] It should be noted that the retimer based on fractional-N frequency-locked loop further includes a first-in-first-out (FIFO) buffer; wherein, the data sampled by the analog-to-digital conversion module is processed by the demodulation module to generate initial transmission data, which is stored in the FIFO buffer; and, the control word digital adjustment circuit adjusts the initial control word based on the digital low-pass filter module and the write and read pointers of the FIFO buffer; wherein, the control word adjustment module is specifically used to adjust the filter control word based on the write and read pointers of the FIFO buffer in the retimer to generate an adjustment control word.

[0040] Specifically, such as Figure 3 As shown, in the control word digital adjustment circuit, the FCW (initial control word) output by the CDR module is first subjected to frequency control word digital low-pass filtering in the digital low-pass filtering module before being forwarded to the TX FnPLL. This filters out high-frequency and some low-frequency jitter, resulting in a filtered control word. Then, in the control word adjustment module, based on the FIFO read / write pointer deviation, a control word correction amount is generated and accumulated on the filtered control word to obtain the adjusted control word. This adjusted control word corrects the frequency deviation jitter problem between the RX clock and TX clock caused by the FCW reading error of the asynchronous interface, and eliminates the jitter. It is then sent to the TX FnPLL to control the generation of the transmit channel clock, thereby enabling the TX clock to achieve clock jitter elimination and clock synchronization with the RX clock.

[0041] Furthermore, in Figure 3 In this circuit, ADC->DEMOD->CDR->RX FnPLL-ADC forms the receive channel clock control loop, used to control the reception of data transmitted by the original node. This invention uses two FnPLLs: one is the RX FnPLL, controlled by the CDR to generate the ADC sampling clock, and the other is the TX FnPLL, used to generate the retransmission clock for the retimer. Both FnPLLs use the same reference oscillator and common phase-locked loop to provide the clock. The initial control word output by the CDR also needs to pass through... Figure 3 The control word digital adjustment circuit shown processes the control word to obtain the adjustment control word controlling TX FnPLL.

[0042] Specifically, in the control word digital adjustment circuit, the RX FCW output by the CDR first undergoes digital low-pass filtering to remove high-frequency jitter and some low-frequency jitter, thus achieving jitter elimination. It should be noted that there are various methods to implement digital low-pass filtering, such as using an alpha filter or a moving average filter.

[0043] In one specific embodiment of the present invention, to adjust the frequency of the output clock of the fractional-N division phase-locked loop (PLL) of the transmitter, the rate conversion module includes a multiplier; wherein, the multiplier is disposed before the digital low-pass filter module, and the multiplier is used to multiply the initial control word by a scaling factor of K so that the adjustment control word is used as the speed control word; or, the multiplier is disposed after the digital low-pass filter module, and the multiplier is used to multiply the adjustment control word by a scaling factor of K to generate the speed control word; and, in the retimer based on the fractional-N division PLL, the frequency of the output clock of the transmitter's fractional-N division PLL is a multiple of the frequency of the receiver's fractional-N division PLL by a scaling factor of K.

[0044] Specifically, such as Figure 4 As shown, the initial control word output by the CDR needs to be processed by the control word digital adjustment circuit provided by this invention to obtain the speed control word for controlling the fractional N frequency division phase-locked loop of the transmitter. The adjustment control word processed by the digital low-pass filter module and the control word adjustment module is multiplied by the K scaling factor to obtain the speed control word, which is used to control the fractional N frequency division phase-locked loop of the transmitter, thereby realizing the function of rate conversion.

[0045] Furthermore, such as Figure 5 As shown, let the adjustment control word be FCW1, and the speed control word obtained by multiplying by the scaling factor K be FCW2. Let the FCW reference value of the receiver's fractional-N PLL be FCW_PRESET1, and the output frequency be Fvco1. Let the FCW reference value of the transmitter's fractional-N PLL be FCW_PRESET2, and the output frequency be Fvco2. Let Fref be the reference clock of the receiver's fractional-N PLL and the transmitter's fractional-N PLL, i.e., the frequency output by the common PLL. Then, the principle of rate conversion can be expressed mathematically as follows: Fvco2 / Fvco1 =Fref FCW_P2 / (Fref FCW_P1) =FCW_P2 / FCW_P1 =(FCW_PRESET2+FCW2) / (FCW_PRESET1+FCW1) =(FCW_PRESET1 Kscale+FCW1 Kscale) / (FCW_PRESET1+FCW1) = K scaling factor.

[0046] Therefore, adjusting the output frequency proportionally by a factor of K achieves the purpose of rate conversion. In the above mathematical expression, FCW_P = FCW_PRESET + FCW represents adding the adjustment amount of FCW to the reference FCW PRESET, which is the absolute FCW value controlling the fractional-N PLL. Here, FCW_P1 represents the absolute FCW value controlling the fractional-N PLL of the receiver, and FCW_P2 represents the absolute FCW value controlling the fractional-N PLL of the transmitter. This rate conversion can reduce the transmission rate, in which case the scaling factor K is less than 1; of course, it can also increase the rate, in which case the scaling factor K is greater than 1. When the scaling factor K is 1, the transmission and reception rates are the same. For example, if the scaling factor K = 2, the frequency of the TX FnPLL output clock is twice the frequency of the RX FnPLL output clock, while if the scaling factor K = 0.5, the frequency of the TX FnPLL output clock is half the frequency of the RX FnPLL output clock.

[0047] It should be noted that the reference clocks for both RX FnPLL and TX FnPLL must originate from a common phase-locked loop (PLL) of the same source pair, and the preset value of FCW_P for TX FnPLL must also be configured as a multiple of the preset value of FCW for RX FnPLL by a scaling factor of K. Only in this way can the rate conversion be achieved, so that the frequency of the TX clock equals the frequency of the RX clock. K is the scaling factor. In practice, the K scaling factor can be a decimal, and the precision depends on the requirements.

[0048] also, Figure 6 This illustrates a second re-timer topology based on a fractional-N frequency-locked loop according to an embodiment of the present invention, such as... Figure 6 As shown, in practical applications, for some scenarios, the data source for transmission does not actually originate from the received data (in this case, the entire structure is not a true timer). For such applications, FIFO read / write pointers can be omitted for control word adjustment. In this case, the initial control word is directly converted to a higher rate after jitter elimination via a digital low-pass filter module, and output to the transmitter via a fractional-N frequency-locked loop to generate the clock required for transmission. Such applications include, but are not limited to, loop timing scenarios, or scenarios where the transmission clock needs to follow the receiving clock but the received data is not directly transmitted.

[0049] Of course, the location of the multiplier can be selected as needed. Figure 7 An enlarged view of the topology of the second control word digital adjustment circuit provided according to an embodiment of the present invention, as shown below. Figure 7As shown, the multiplier used to implement the multiplication by the scaling factor K can also be placed before the digital low-pass filter module, or it can be placed at the front end inside the fractional-N frequency-locked loop of the transmitter; as long as it can realize the function of multiplying the adjustment control word by the scaling factor K.

[0050] The following uses the alpha filter as an example to give an implementation scheme of a digital low-pass filter. Other similar implementation schemes of low-pass filters are also within the scope of protection of this invention. Figure 8 The topology of a first digital low-pass filter module based on an alpha filter, as provided in an embodiment of the present invention, is shown. Figure 8 As shown, the result of multiplying RX FCW by the alpha factor, adding FCW AVG (average value), and subtracting the result of multiplying FCW AVG by the alpha factor is updated to FCWAVG. Here, FCW AVG is the result of the alpha filter, which is output as the result of the FCW digital filter for subsequent FCW adjustment processing. When the digital filter is reset, FCW AVG is reset to 0. The alpha factor takes values ​​between (0, 1), and for simplification, it is often chosen to be 0. The form is where m is a positive integer; through such multiplication operations, digital low-pass filters can be constructed using bit shifting, reducing implementation overhead.

[0051] It should be noted that, in Figure 3 In the process, the parallel symbol data after DEMOD (i.e., the initial transmission data) is written to the FIFO using the RX clock, and then the data in the FIFO (the initial transmission data) is read using the TX clock generated after filtering and adjustment. The supported FIFO addresses for reading and writing are as follows: Figure 5 As shown in the background section, asynchronous interface reading of FCW values ​​may result in discrepancies between the asynchronously read FCW and the actual transmitted FCW due to timing issues, leading to erroneous readings. This causes frequency deviation jitter between the RX and TX clocks, which gradually causes the FIFO write pointer (based on the RX clock) and the read pointer (based on the TX clock) to deviate, resulting in underflow during read operations or overflow during write operations, leading to data loss. To solve this problem, this invention first determines whether the current FIFO operation is too fast or too slow based on the FIFO write and read pointers. Then, it corrects the reading by adding a control word correction amount to the digital filter's control word, thereby achieving clock synchronization between the TX and RX clocks. Alternatively, other methods can be used to implement a digital low-pass filter module based on an alpha filter. Figure 9 The topology of a second digital low-pass filter module based on an alpha filter, provided by an embodiment of the present invention, is shown, as follows: Figure 9As shown, the configuration of the digital low-pass filter module is achieved by introducing a filter factor and setting corresponding paths. Figure 9 In this architecture, the filter factor is configured as a positive integer. The current RX FCW is fed into the positive input of the adder. One output of the current adder is directly output, weighted by right shifting the filter factor, and used as the current filtered FCW. The other output is latched into the D register to obtain the output value of the previous cycle. The output value of the previous cycle is then weighted by right shifting the filter factor and fed into the negative input of the adder. After the adder completes the operation, it is weighted again by the filter factor to output the smoothed filtered FCW. Simultaneously, the adder output is fed into the D register and buffered for feedback in the next clock cycle. Based on this architecture, the digital low-pass filter module has the advantages of high accuracy and low computational complexity.

[0052] In one specific embodiment of the present invention, Figure 10 This diagram illustrates the address representation in a first-in-first-out (FIFO) buffer according to an embodiment of the present invention. Figure 11 This is an enlarged view of the topology of the correction amount generation unit provided according to an embodiment of the present invention; combined with Figure 4 , Figure 10 as well as Figure 11 It is understood that the control word adjustment module may include a read / write pointer comparison unit, a correction amount generation unit, and a control word correction unit; wherein, the read / write pointer comparison unit is used to calculate the write pointer lead indication and the read pointer lag indication of the first-in-first-out buffer based on the write pointer and the read pointer; the correction amount generation unit is used to generate a correction amount based on the write pointer lead indication and the read pointer lag indication; the control word correction unit is used to accumulate the correction amount with the filter control word to generate the adjustment control word.

[0053] Specifically, the read / write pointer comparison unit includes a write / read pointer interval calculation subunit and a comparison and judgment subunit. The write / read pointer interval calculation subunit is used to calculate the write / read pointer interval based on the write pointer and the read pointer, defined as: write / read pointer interval = indicator bit of the write pointer - indicator bit of the read pointer. The comparison and judgment subunit is used to compare the write / read pointer interval with a preset threshold, and determine the write pointer advance indication and the read pointer lag indication based on the comparison result. Specifically, the write / read pointer interval is judged to be greater than or equal to the configured preset threshold. If the write / read pointer interval > the preset threshold, then the write pointer advance indication = 1, otherwise the write pointer advance indication = 0. If the write / read pointer interval < - the preset threshold, then the read pointer lag indication = 1, otherwise the read pointer lag indication = 0.

[0054] More specifically, the correction amount generation unit includes a frequency control word adjustment amount calculation subunit and a correction amount calculation subunit; wherein, the frequency control word adjustment amount calculation subunit is used to calculate the frequency control word adjustment amount based on the write pointer lead indication and the read pointer lag indication; the correction amount calculation subunit is used to calculate the correction amount based on the frequency control word adjustment amount through a preset control word adjustment working mode; wherein, if the write pointer lead indication = 1, the first preset value of the frequency control word adjustment amount is multiplied by a preset first frequency control word adjustment factor to obtain the first adjustment amount; the result of the read pointer lag indication selection is multiplied by a preset second frequency control word adjustment factor to obtain the second adjustment amount, and the first adjustment amount and the second adjustment amount are added to obtain the frequency control word adjustment amount; if the read pointer lag indication = 1, the second preset value of the frequency control word adjustment amount is multiplied by a second frequency control word adjustment factor to obtain the third adjustment amount, the result of the write pointer lead indication selection is multiplied by a first frequency control word adjustment factor to obtain the fourth adjustment amount, and the third adjustment amount and the fourth adjustment amount are added to obtain the frequency control word adjustment amount.

[0055] It should be noted that for digital circuits, whether the write pointer lead indicator is 1 or the read pointer lag indicator is 1, the selection result of the write pointer lead indicator is always the first preset value of the preset frequency control word adjustment or 0, and the selection result of the read pointer lag indicator is always the second preset value of the preset frequency control word adjustment or 0.

[0056] Furthermore, in the control word adjustment module, each clock cycle first determines the size of the write / read pointer interval and the preset threshold to obtain the write pointer lead indication and the read pointer lag indication; subsequently, the frequency control word adjustment amount is generated based on the write pointer lead indication and the read pointer lag indication, and then the filter control word is corrected and adjusted by the frequency control word adjustment amount.

[0057] To achieve the correction and adjustment of the filter control word through the adjustment amount of the frequency control word, such as Figure 10As shown, the control word adjustment has two working modes: FCW selection control terminal = 0 for accumulation mode and FCW selection control terminal = 1 for direct adjustment mode. It should be noted that at any given time, only one of the write pointer lead indicator and read pointer lag indicator will be active. If the active indicator is set to 1, it needs to be multiplied by the corresponding frequency control word adjustment amount. For example, at a certain time, if the write pointer lead indicator = 1, the first preset value of the frequency control word adjustment amount is multiplied by the first frequency control word adjustment factor, and simultaneously the result of the read pointer lag indicator selection is multiplied by the second frequency control word adjustment factor to obtain the frequency control word adjustment. The frequency control word adjustment amount is calculated as follows: If the read pointer hysteresis indicator is 1, the second preset value of the selected frequency control word adjustment amount is multiplied by the second frequency control word adjustment factor, and the result of the write pointer advance indicator selection is multiplied by the first frequency control word adjustment factor to obtain the frequency control word adjustment amount. If the FCW selection control terminal is 1, the frequency control word adjustment amount is the FCW correction amount. If the FCW selection control terminal is 0, the obtained frequency control word adjustment amount is accumulated to obtain the FCW integral compensation value, which is the FCW correction amount. In the FCW selection control terminal = 0 mode, the FCW integral compensation value is reset to 0 upon reset.

[0058] In addition, in the FCW selection control terminal = 0 mode, a countdown counting control mode can be added. That is, the frequency control word adjustment is not accumulated every clock cycle, but is accumulated once at a certain interval of T. Specifically, in the control mode of FCW selection control terminal = 0, the initial value of the counter is set to T, and it is decremented by 1 every clock cycle. When it is reduced to 0, the frequency control word adjustment is accumulated once, and the counter is set to T again, and so on.

[0059] It should be noted that, in practical implementation, the first preset value of the frequency control word adjustment, the first frequency control word adjustment factor, the second preset value of the frequency control word adjustment, and the second frequency control word adjustment factor can all be configured and controlled through registers. The time interval T between the FCW selection of the control terminal mode and the countdown counting control mode can also be controlled through registers. The length of the FIFO can also be determined according to actual needs, and the preset threshold can also be configured through registers. Furthermore, it should be noted that the control word digital adjustment circuit operates in the TX clock domain, while writing to the FIFO uses the RX clock; therefore, the TX clock needs to be used to synchronously obtain the write pointer for reading and writing pointer comparison.

[0060] also, Figure 12 This diagram illustrates the address representation in a second type of first-in-first-out (FIFO) buffer according to an embodiment of the present invention. Figure 12It can be seen that the bias at which the read pointer starts reading the FIFO can also be controlled by introducing another read start offset parameter; that is, the read pointer only starts reading the FIFO after the write pointer starts writing to the FIFO and reaches the read start offset parameter. Then, the same calculation as the first scheme is performed, that is, the write-read pointer interval = write pointer indicator bit - read pointer indicator bit, and the size of the write-read pointer interval and the configured preset threshold are judged: if the write-read pointer interval > the preset threshold, the write pointer lead indicator = 1, otherwise the write pointer lead indicator = 0; if the write-read pointer interval < - the preset threshold, the read pointer lag indicator = 1, otherwise the read pointer lag indicator = 0. In the FCW adjustment submodule, each clock cycle first judges the size of the write-read pointer interval and the preset threshold to obtain the write pointer lead indicator and the read pointer lag indicator, and then the method of adjusting the filter control word based on the write pointer lead indicator and the read pointer lag indicator remains unchanged.

[0061] It should be noted that the advantage of introducing a read start offset parameter is that it can control the initial deviation of the read and write pointers. Specifically, it allows for a larger initial frequency offset between the write FIFO clock and the read FIFO clock, and also enables the function of stabilizing the read and write pointer intervals. Existing methods only use a preset threshold parameter. If a large initial frequency offset between the write FIFO clock and the read FIFO clock is required, the preset threshold must be set relatively high. This results in significant jitter when adjusting the FCW after stabilization, introducing additional jitter. The solution provided by this invention, by introducing both a read start offset and a preset threshold, effectively avoids introducing additional jitter.

[0062] As can be seen from the above specific embodiments, the control word digital adjustment circuit and the timer re-timer based on fractional N frequency division phase-locked loop provided by the present invention have at least the following advantages: 1. High-frequency jitter and some low-frequency jitter in the initial control word are filtered out by a digital low-pass filter module. The filtering is low in cost, occupies little area and consumes little power, and has a good jitter elimination effect. 2. By using the write and read pointers of the FIFO to determine the frequency deviation between the RX clock and the TX clock, and then using the control word adjustment module to filter the control word to generate the adjustment control word, the problem of frequency deviation jitter between the RX clock and the TX clock can be solved. This can be achieved because the asynchronous interface may read the FCW value differently from the actual transmitted FCW due to timing reasons, resulting in incorrect reading values.

[0063] 3. The control word digital adjustment circuit has the advantages of simple implementation, low logic overhead, and stable performance; 4. The correction calculation subunit in the control word adjustment module supports two modes, which can cover application scenarios with different frequency deviations between the RX clock and the TX clock. 5. It can synchronize the RX clock and the TX clock; 6. Compared with the existing phase-locked loop (PLL) scheme, the low-pass filter scheme does not introduce additional noise and has relatively better performance; 7. Unaffected by PVT (Process Voltage Temperature), its performance is consistent; 8. The control word digital adjustment circuit is flexible. The alpha factor of the digital low-pass filter and the parameters involved in adjusting the control word can be modified according to the configuration. The length of the FIFO can be determined according to actual needs. 9. Introduce a read start offset parameter in the FIFO-based read / write pointer function to control the initial deviation of the read / write pointer. This enables the write FIFO clock and read FIFO clock to have a large initial frequency offset, and also achieves low jitter after stabilization. 10. The output FCW is simply multiplied by a scaling factor K to achieve rate conversion. This method is simple to implement, has high frequency accuracy, and stable performance. Furthermore, different values ​​of the scaling factor K, such as greater than 1, less than 1, or equal to 1, respectively achieve the functions of increasing, decreasing, and keeping the TX clock rate constant.

[0064] As per the above reference Figures 3 to 12 The control word digit adjustment circuit according to the present invention is described by way of example. However, those skilled in the art will understand that various modifications can be made to the control word digit adjustment circuit proposed in the present invention without departing from the scope of the invention. Therefore, the scope of protection of the present invention should be determined by the contents of the appended claims.

Claims

1. A control word digital adjustment circuit; characterized by, This is applied to a re-timer based on a fractional-N frequency-locked loop, and includes: a digital low-pass filter module, a control word adjustment module, and a rate conversion module; among which, The digital low-pass filter module is used to filter out high-frequency jitter and some low-frequency jitter in the initial control word to generate a filtered control word; The control word adjustment module is used to adjust the filter control word to generate an adjustment control word; The rate conversion module is used to perform speed adjustment processing on the adjustment control word to generate a speed adjustment control word; The speed control word is used to replace the initial control word as the input of the fractional N-division frequency-locked loop in the transmitter of the re-timer.

2. The control word digital adjustment circuit as described in claim 1, characterized in that, The rate conversion module includes a multiplier; wherein... The multiplier is positioned before the digital low-pass filter module. The multiplier is used to multiply the initial control word by a scaling factor K, so that the adjustment control word becomes the speed control word; or... The multiplier is located after the digital low-pass filter module. The multiplier is used to multiply the adjustment control word by a scaling factor K to generate the speed control word.

3. The control word digital adjustment circuit as described in claim 2, characterized in that, In the retimer based on fractional-N frequency-locked loop, the frequency of the output clock of the transmitter's fractional-N frequency-locked loop is a multiple of the frequency of the receiver's fractional-N frequency-locked loop's output clock by a scaling factor of K.

4. The control word digital adjustment circuit as described in claim 1, characterized in that, The control word adjustment module is used to adjust the filter control word based on the write pointer and read pointer of the first-in-first-out buffer in the re-timer, so as to generate an adjustment control word; and, The control word adjustment module includes a read / write pointer comparison unit, a correction amount generation unit, and a control word correction unit. The read / write pointer comparison unit calculates a write pointer lead indication and a read pointer lag indication based on the write pointer and the read pointer. The correction amount generation unit generates a correction amount based on the write pointer lead indication and the read pointer lag indication. The control word correction unit accumulates the correction amount with the filter control word to generate the adjustment control word.

5. The control word digital adjustment circuit of claim 4, wherein, The read / write pointer comparison unit includes a read / write pointer interval calculation subunit and a comparison judgment subunit; wherein... The write-read pointer interval calculation subunit is used to calculate the write-read pointer interval based on the write pointer and the read pointer; wherein, the write-read pointer interval = the indicator bit of the write pointer - the indicator bit of the read pointer; The comparison and judgment subunit is used to compare the write-read pointer interval with a preset threshold, and determine the write pointer advance indication and the read pointer lag indication based on the comparison result; wherein, if the write-read pointer interval is greater than the preset threshold, the write pointer advance indication = 1, otherwise the write pointer advance indication = 0; if the write-read pointer interval < negative of the preset threshold, then the read pointer lag indication = 1 ， else the read pointer lag indication = 0.

6. The control word digital adjustment circuit as described in claim 5, characterized in that, The correction amount generation unit includes a frequency control word adjustment amount calculation subunit and a correction amount calculation subunit; wherein... The frequency control word adjustment calculation subunit is used to calculate the frequency control word adjustment based on the write pointer advance indication and the read pointer lag indication; The correction calculation subunit is used to calculate the correction amount based on the frequency control word adjustment amount through a preset control word adjustment working mode.

7. The control word digital adjustment circuit as described in claim 6, characterized in that, If the write pointer advance indication = 1, then the first adjustment amount is obtained by multiplying the first preset value of the frequency control word adjustment amount by the preset first frequency control word adjustment factor, the second adjustment amount is obtained by multiplying the result of the read pointer lag indication selection by the preset second frequency control word adjustment factor, and the first adjustment amount and the second adjustment amount are added together to obtain the frequency control word adjustment amount. If the read pointer lag indication = 1, then the third adjustment amount is obtained by multiplying the second preset value of the frequency control word adjustment amount by the preset second frequency control word adjustment factor, the fourth adjustment amount is obtained by multiplying the result of the write pointer advance indication selection by the first frequency control word adjustment factor, and the third adjustment amount and the fourth adjustment amount are added together to obtain the frequency control word adjustment amount.

8. The control word digital adjustment circuit as described in claim 7, characterized in that, The control word adjustment modes include an accumulation mode and a direct adjustment mode; wherein... In the direct adjustment mode, the frequency control word adjustment amount is used as the correction amount; In the accumulation mode, the frequency control word adjustment amounts obtained at least two times are accumulated to obtain the frequency control word adjustment accumulation value, and the frequency control word adjustment accumulation value is used as the correction amount.

9. The control word digital adjustment circuit as described in claim 8, characterized in that, In the accumulation mode, the frequency control word adjustment amount is accumulated once every preset time interval T to obtain the frequency control word adjustment accumulation value.

10. The control word digital adjustment circuit as described in any one of claims 1 to 9, characterized in that, The digital low-pass filter module is built based on the alpha filter.

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