Signal debugging method and device, equipment, storage medium and program product

Abstract

The application discloses a signal debugging method and device, equipment, storage medium and program product, relates to the test technical field, and the signal debugging method comprises the following steps: according to the received signal debugging demand, calculating the relative time offset required by a plurality of digital-to-analog converters and amplitude parameters, the signal debugging demand includes target rise time and target waveform requirement;According to the relative time offset, a plurality of digital waveform data with time sequence interleaving characteristics are generated, and the plurality of digital waveform data are transmitted to corresponding digital-to-analog converters respectively;The plurality of digital-to-analog converters are controlled to convert the received digital waveform data into analog signal output according to the amplitude parameters;According to the analog signals output by each digital-to-analog converter, a target signal meeting the signal debugging demand is synthesized.Based on the scheme, the application can solve the technical problem of high test cost.

Description

Technical Field

[0001] This application relates to the field of testing technology, and in particular to a signal debugging method, apparatus, device, storage medium, and program product. Background Technology

[0002] The rise time of the output signal of a DAC (Digital-to-Analog Converter) is essentially determined by the physical properties of the semiconductor device. These include the manufacturing process node, parasitic capacitance of the output stage, and the internal buffer amplifier. Once a DAC chip is selected, the maximum voltage conversion rate achievable by its core cannot be substantially improved through subsequent external digital algorithm compensation, digital filtering, or conventional analog filtering circuits.

[0003] To achieve extremely short rise times in the picosecond (ps) or even sub-nanosecond range, a single high-performance, high-bandwidth DAC chip is typically chosen. However, this approach, which relies on the physical limits of a single high-performance DAC chip to achieve a high rise time, results in high hardware costs and significantly increases the costs of supporting high-speed power supplies, PCB (Printed Circuit Board) wiring, and other hardware, thus increasing overall testing costs. Summary of the Invention

[0004] The main objective of this application is to provide a signal debugging method, apparatus, device, storage medium, and program product, which aims to solve the technical problem of high testing costs.

[0005] To achieve the above objectives, this application proposes a signal debugging method, which includes: Based on the received signal debugging requirements, calculate the relative time offset and amplitude parameters required by the multi-channel digital-to-analog converter. The signal debugging requirements include the target rise time and the target waveform requirements. Based on the relative time offset, multi-channel digital waveform data with time-interleaved characteristics are generated, and the multi-channel digital waveform data are transmitted to the corresponding digital-to-analog converters respectively. The multi-channel digital-to-analog converter is controlled to convert the received digital waveform data into an analog signal output according to the amplitude parameter; Based on the analog signals output from each digital-to-analog converter, a target signal that meets the signal debugging requirements is synthesized.

[0006] In one embodiment, the target waveform requirement includes a target edge shape, the target signal includes a signal having the target edge shape, and the step of synthesizing a target signal that meets the signal debugging requirements based on the analog signals output from each digital-to-analog converter includes: Based on the target edge shape, an operation configuration instruction for defining the operation relationship between multiple analog signals is determined, and the operation configuration instruction is transmitted to the programmable signal operation module so that the programmable signal operation module can perform operations on each analog signal according to the operation configuration instruction to synthesize an initial signal. Based on the initial signal, a signal with the target edge shape is generated.

[0007] In one embodiment, after the step of generating a signal having a target edge shape based on the initial signal, the method further includes: The analog-to-digital converter is controlled to sample the initial signal, convert the sampled signal into target digital feedback data, and feed it back to the local system. Calculate the error value between the target digital feedback data and the signal debugging requirements; If the error value is greater than the preset threshold, then according to the received signal debugging requirements and the error value, the steps of recalculating the relative time offset and amplitude parameters required by the multi-channel digital-to-analog converter are repeated until the error value is less than or equal to the preset threshold, and a signal with the target edge shape is obtained.

[0008] In one embodiment, before the step of controlling the analog-to-digital converter to sample the initial signal, convert the sampled signal into target digital feedback data, and feed it back locally, the method further includes: The initial signal is input to the signal integration module, which smooths the initial signal to generate a continuous waveform signal. The signal enhancement module enhances the signal strength of the continuous waveform signal according to the load requirements, thereby generating an enhanced waveform signal. The target digital feedback data also includes digital feedback data after waveform quality improvement. Before the step of calculating the error value between the target digital feedback data and the signal debugging requirements, the method further includes: The enhanced waveform signal is sampled by an analog-to-digital converter, and the sampled signal is converted into digital feedback data with improved waveform quality and fed back to the local machine.

[0009] In one embodiment, after the step of synthesizing a target signal that meets the signal debugging requirements based on the analog signals output from each digital-to-analog converter, the method further includes: Real-time monitoring of whether the target digital feedback data meets the signal debugging requirements; When the target digital feedback data meets the signal debugging requirements, an enable signal is generated to control the signal switching module to turn on, and the target signal is output to the load. When the target digital feedback data does not meet the signal debugging requirements, the signal switch module is controlled to remain in the off state to block the signal output to the load.

[0010] In one embodiment, the step of generating multi-channel digital waveform data with time-interleaved characteristics based on relative time offset includes at least one of the following: Maintaining the sampling clock synchronization of each digital-to-analog converter, and generating multi-channel digital waveform data with timing interleaving characteristics by embedding the relative time offset into the multi-channel digital waveform data; To maintain the synchronization of digital waveform data transmitted to each digital-to-analog converter, the control clock phase shift circuit generates a sampling clock for each digital-to-analog converter with a phase difference corresponding to the relative time offset. The phase difference of the sampling clock enables each digital-to-analog converter to convert the synchronized digital waveform data at staggered times, generating multi-channel digital waveform data with time-interleaved characteristics.

[0011] Furthermore, to achieve the above objectives, this application also proposes a signal debugging device, which includes: The calculation module is used to calculate the relative time offset and amplitude parameters required by the multi-channel digital-to-analog converter based on the received signal debugging requirements, wherein the signal debugging requirements include the target rise time and the target waveform requirements. The transmission module is used to generate multiple digital waveform data with time-interleaved characteristics according to the relative time offset, and transmit the multiple digital waveform data to the corresponding digital-to-analog converters respectively. The conversion module is used to control the multi-channel digital-to-analog converter to convert the received digital waveform data into an analog signal output according to the amplitude parameter; The generation module is used to synthesize a target signal that meets the signal debugging requirements based on the analog signals output by each digital-to-analog converter.

[0012] In addition, to achieve the above objectives, this application also proposes a signal debugging device, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the signal debugging method described above.

[0013] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the signal debugging method described above.

[0014] In addition, to achieve the above objectives, this application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the signal debugging method described above.

[0015] One or more technical solutions proposed in this application have at least the following technical effects: This application calculates the relative time offset and amplitude parameters required by multiple digital-to-analog converters (DACs) based on the received signal debugging requirements. These requirements include target rise time and target waveform requirements. By accurately calculating and allocating the phase offset and amplitude parameters of each DAC based on the target rise time, independent control of the timing and amplitude of the multiple DAC outputs is achieved. Based on the relative time offset, multiple digital waveform data with timing interleaving characteristics are generated, and these data are transmitted to their respective DACs. By driving multiple DACs in parallel, synchronous generation and independent control of multiple analog signals are achieved, overcoming the limitation of a single DAC in the number of output channels. The multiple DACs are controlled to convert the received digital waveform data into analog signals according to the amplitude parameters. Based on the analog signals output by each DAC, a target signal satisfying the signal debugging requirements is synthesized. In other words, by superimposing the outputs of multiple ordinary DACs, high-frequency components exceeding the bandwidth limitations of a single channel can be constructed. This eliminates the reliance on the physical limits of a single chip, allowing the use of low-cost, low-bandwidth mature process DAC arrays to replace expensive high-speed single chips, thereby reducing overall hardware and testing costs, including the chip itself, high-speed power supplies, and complex PCB layouts. Ultimately, this reduced testing costs. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating an embodiment of the signal debugging method of this application. Figure 2 This is a diagram of the signal debugging system architecture provided in Embodiment 1 of the signal debugging method of this application; Figure 3 This is a schematic diagram illustrating a scenario of an embodiment of the signal debugging method of this application; Figure 4This is a schematic diagram of the module structure of the signal debugging device according to an embodiment of this application; Figure 5 This is a schematic diagram of the device structure of the hardware operating environment involved in the signal debugging method in the embodiments of this application.

[0019] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0020] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0021] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0022] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or an electronic device or signal debugging device capable of performing the above functions. The following description uses a signal debugging device as an example to illustrate this embodiment and the subsequent embodiments.

[0023] Based on this, embodiments of this application provide a signal debugging method, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the signal debugging method of this application.

[0024] In this embodiment, the signal debugging method includes steps S10 to S40: Step S10: Calculate the relative time offset and amplitude parameters required by the multi-channel digital-to-analog converter based on the received signal debugging requirements. The signal debugging requirements include the target rise time and the target waveform requirements. Step S20: Generate multi-channel digital waveform data with time-interleaved characteristics based on the relative time offset, and transmit the multi-channel digital waveform data to the corresponding digital-to-analog converters respectively; Step S30: Control the multi-channel digital-to-analog converter to convert the received digital waveform data into an analog signal output according to the amplitude parameter; Step S40: Based on the analog signals output by each digital-to-analog converter, synthesize a target signal that meets the signal debugging requirements.

[0025] It should be noted that the signal debugging device can be an external DSP (Digital Signal Processor) or FPGA (Field-Programmable Gate Array). This embodiment uses an FPGA as an example for specific explanation.

[0026] Signal debugging requirements are the specific performance requirements that users put forward for the final output signal; these requirements include target rise time and target waveform requirements.

[0027] The target rise time is the time required for the output signal to rise from a stable low level (e.g., 10% of the amplitude) to a stable high level (e.g., 90% of the amplitude). The target rise time quantifies the steepness of the signal edge; a smaller value indicates a steeper edge, and a larger value indicates a smoother edge. Target waveform requirements include requirements for the overall waveform shape of the output signal, such as pulse width, duty cycle, signal period, amplitude stability, signal smoothness, and waveform distortion.

[0028] Users can input signal debugging requirements through a host computer software interface, command line commands, script configuration files, or external trigger signals. The FPGA receives these requirements and calculates the relative time offset and amplitude parameters required by the multi-channel digital-to-analog converter using internal algorithms. For example, based on the edge characteristics that can be synthesized from the output signals of multiple DACs through subsequent addition / subtraction operations, the time misalignment (i.e., relative time offset) between the multiple DACs and the required output signal strength (i.e., amplitude parameter) for achieving the target edge can be derived by reverse deduction.

[0029] Specifically, the FPGA can have a pre-built lookup table that stores the optimal set of DAC phase offset and amplitude parameters for different target rise times and waveform combinations. When a debugging request is received, the FPGA directly retrieves the relevant parameters by looking up the table.

[0030] Relative time offset refers to the time difference set between the waveform data to be generated by different digital-to-analog converters (DACs) on the time axis. This difference allows the output signals of each DAC to be out of sync in time. Amplitude parameters are configuration values ​​used to control the voltage or current amplitude of the output signals of each DAC.

[0031] Furthermore, the FPGA can perform timing orchestration when generating digital waveform data based on the calculated relative time offset required for each DAC. For example, if a certain DAC needs to output T nanoseconds later than other DACs, the control unit will insert a T nanosecond delay when generating the corresponding digital waveform data, making it lag behind the reference waveform in time. After such timing orchestration, the control unit generates multiple digital waveform data with precise and controllable time differences between them (i.e., with timing interleaving characteristics), and then transmits these digital waveform data to the input terminals of their respective DAC chips through a Low-Voltage Differential Signaling (LVDS) interface.

[0032] In this embodiment, the method for generating multi-channel digital waveform data with time-interleaved characteristics based on relative time offset includes at least one of the following: To maintain the synchronization of the sampling clocks of each digital-to-analog converter (DAC), the relative time offset is embedded in the multi-channel digital waveform data to generate multi-channel digital waveform data with timing interleaving characteristics. To maintain the synchronization of the digital waveform data transmitted to each DAC, the clock phase shift circuit is controlled to generate a sampling clock with a phase difference corresponding to the relative time offset for each DAC. The phase difference of the sampling clock enables each DAC to convert the synchronized digital waveform data at interleaved times, thereby generating multi-channel digital waveform data with timing interleaving characteristics.

[0033] It's important to note that the sampling clock refers to the clock signal provided to the DAC. The DAC performs a conversion on the input digital waveform data at each edge of the sampling clock (e.g., the rising edge), outputting the corresponding analog signal value. The frequency and phase of the sampling clock directly determine the DAC's conversion timing. Phase difference refers to the offset on the time axis between two or more clock signals of the same frequency, usually expressed in degrees or time.

[0034] Specifically, the FPGA can maintain a fully synchronized sampling clock for each DAC. In this case, the timing interleaving characteristic is achieved through the digital waveform data itself. Specifically, when the control unit generates multiple digital waveform data streams via the LVDS interface, it injects a corresponding time delay into each data stream at the data level based on the calculated relative time offset.

[0035] For example, for channels requiring delayed output, the control unit inserts a corresponding number of no-operation or delay cycles into its digital waveform sequence. When each DAC converts its received digital waveform, which already contains time offsets, under a synchronized sampling clock, the output analog signals naturally form a preset timing interleaving relationship. Thus, timing control is achieved through data processing without the need for complex adjustments to the clock network.

[0036] Alternatively, the FPGA can maintain perfectly synchronized digital waveform data output to each DAC. In this case, the timing interleaving feature is achieved by providing each DAC with a sampling clock with a different phase. Specifically, the control unit sends a relative time offset to a clock phase shift circuit, which generates multiple clock signals from the same reference clock source, where the phase difference of each clock signal is matched to the corresponding relative time offset.

[0037] Then, these sampling clocks with precise phase differences are fed into each DAC. When each DAC, driven by its own sampling clock with a different phase, converts the synchronously received digital waveform data, it also produces analog outputs with interleaved timing. Thus, by introducing a phase difference in the clock domain to achieve timing control, the timing convergence problems that may be introduced by inserting delays in the high-speed data transmission path are avoided.

[0038] Furthermore, after generating and transmitting digital waveform data, the FPGA can write amplitude parameters to each digital-to-analog converter (DAC) via a configuration interface. These amplitude parameters can configure the DAC's internal reference voltage, current source bias, or output amplifier gain, thereby precisely controlling the amplitude range of its output analog signal.

[0039] When each DAC receives its own digital waveform data with interleaved timing characteristics, each DAC, driven by its sampling clock, sequentially converts each digital codeword into an analog voltage or current output with the corresponding amplitude. Ultimately, multiple DACs simultaneously output multiple independent analog signals (DAC_0_OUT to DAC_N_OUT, see reference...). Figure 2 The analog signals shown are 0 to N, which are interleaved in time but independent in amplitude.

[0040] Alternatively, instead of directly writing amplitude parameters to each DAC individually, the FPGA uses a multi-channel analog switch matrix to time-divisionally switch a programmable precision reference voltage source to the reference voltage input of each DAC. Based on the relative time offset, the FPGA configures the required reference voltage for different DACs at different time periods, thereby achieving independent control of the output amplitude of each DAC. This reduces the number of control pins while enabling flexible configuration of amplitude parameters.

[0041] Furthermore, the FPGA synthesizes and processes the multiple independent analog signals output from the multiplex digital-to-analog converter, ultimately generating a single target signal that meets the debugging requirements.

[0042] Specifically, an FPGA can use a programmable transconductance amplifier array as a signal processing module. By configuring the transconductance coefficients of each transconductance amplifier in the array, a programmable weighted summation of multiple input analog signals can be achieved, ultimately generating a single target signal that meets the debugging requirements.

[0043] In this embodiment, by synthesizing and processing the multiple independent analog signals output by the multiplex digital-to-analog converter, the edge characteristics (such as rise time) of the final target signal are no longer limited by the physical bandwidth and slew rate of any single DAC.

[0044] Specifically, when an extremely short rise time is required, multiple analog signals with highly overlapping timing can be added together to achieve the superposition of multiple energy sources, thereby synthesizing a steep edge that far exceeds the output capability of a single DAC; when a gentle rise time is required, the timing offset and amplitude of each signal can be adjusted to synthesize a gently sloping edge.

[0045] In this embodiment, the relative time offset and amplitude parameters required by the multi-channel digital-to-analog converter can be calculated using an edge slope decomposition algorithm according to the received signal debugging requirements. Specifically, the total edge change corresponding to the target rise time is decomposed into multiple sub-edge segments according to a preset time slice. Based on the slope contribution required by each sub-edge segment, the relative time offset of each DAC is reverse-engineered and pre-allocated, so that the edge contribution of the analog signal output by each DAC in subsequent addition / subtraction operations is non-linearly distributed on the time axis, so as to synthesize an asymmetric or target edge shape with a specific contour.

[0046] Among them, a sub-edge segment refers to multiple consecutive time intervals obtained by dividing the rising or falling edge of the target according to the time axis, and each interval corresponds to an edge segment with a specific slope.

[0047] The overall edge variation corresponding to the target rise time is decomposed into multiple sub-edge segments, and a nonlinearly distributed relative time offset is pre-assigned to each DAC. This allows the edge of the subsequently synthesized target signal to no longer be limited to the symmetrical and monotonous ramp shape produced by traditional multi-channel superposition. For example, by assigning differentiated slope contributions to different sub-edge segments, asymmetric rise edges (such as steep at the beginning and gentle at the end or gentle at the beginning and steep at the end), stepped edges with specific inflection points, and even complex edge shapes with plateau regions in the middle of the edge can be achieved.

[0048] The slope contribution refers to the weighted contribution of each DAC output signal to the slope change of the target edge within a certain time interval. By adjusting the slope contribution of different DACs, fine control of the local shape of the edge can be achieved.

[0049] In this embodiment, the specific implementation method for back-deriving and pre-allocating the relative time offset of each DAC based on the slope contribution required for each sub-edge segment can be: The FPGA discretizes the continuous slope curve of the target edge with high precision on the time axis, obtaining M discrete time nodes, each corresponding to an instantaneous slope value. Based on the magnitude of the instantaneous slope at each time node, the contribution weight of that time node to the overall edge change is calculated. The larger the instantaneous slope at a time node, the more drastic the edge change, requiring more superimposed energy.

[0050] An N×M mapping matrix is ​​constructed using the FPGA, where N is the number of DAC channels and M is the number of discrete time nodes. Each element in the matrix represents the energy contribution coefficient of the i-th DAC at time node j. This mapping matrix follows these constraints: the timing position (relative time offset) of each DAC determines the time window corresponding to its output signal during synthesis; by adjusting the coefficient distribution of the mapping matrix, a precise correspondence between the timing position of each DAC and the energy contribution of each edge at each time node can be achieved. The energy contribution coefficient, in the mapping matrix, represents the proportion of energy contribution of the i-th DAC at time node j to the final synthesized edge. The energy contribution coefficient is determined by the DAC's amplitude parameters, timing position, and the weights of subsequent addition / subtraction operations.

[0051] Using the energy weights at each time node as the objective and the mapping matrix as the constraint, the FPGA uses an optimization algorithm to inversely deduce the optimal timing positions of each DAC. The deduction results in the following: in regions with rapid edge changes (large instantaneous slope), the timing positions of multiple DACs are densely distributed within this time window, achieving high-density energy superposition; in regions with gentle edge changes (small instantaneous slope), the timing positions of each DAC are sparsely distributed within this time window, achieving low-density energy superposition or dispersed distribution. The resulting relative time offsets of each DAC exhibit a non-uniform distribution on the time axis.

[0052] K channels (K≥1) are reserved in the N-channel DAC as redundant calibration channels, and their initial timing positions are configured according to the optimal timing positions.

[0053] In this embodiment, the interval with a large instantaneous slope in the target edge is configured as a dense region of multi-channel DAC timing, so that energy is superimposed on multiple channels at the moment when the edge change is most drastic, thereby achieving the required edge steepness with the fewest number of DAC channels. At the same time, the interval with a small instantaneous slope is configured as a sparse region of timing, avoiding the power consumption waste and edge overshoot risk caused by unnecessary high-density superposition.

[0054] In this embodiment, multiple analog signals, controlled in both time and amplitude, are synthesized into a single target signal through computation. The edge characteristics of the final output signal are determined by the temporal and energy superposition of the multiple signals. This allows multiple ordinary DACs (as opposed to high-performance DACs) to operate in parallel. By precisely controlling the time interleaving and amplitude ratio of each signal, energy can be concentrated or dispersed along the time axis at the synthesis end, resulting in a continuously adjustable rise time ranging from extremely steep to extremely gentle.

[0055] Therefore, this embodiment can still achieve a rise time adjustment range and accuracy far exceeding the physical capabilities of a single ordinary DAC without the need to use high-cost, high-power ultra-high-performance DAC chips. This fundamentally solves the technical problems of high hardware costs, increased supporting costs, and increased overall testing costs caused by relying on the physical limits of a single DAC.

[0056] Based on the first embodiment of this application, in the second embodiment of this application, the same or similar content as the above embodiment can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 2 The method for synthesizing the target signal that meets the signal debugging requirements based on the analog signals output from each digital-to-analog converter can be as follows: Based on the target edge shape, an operation configuration instruction for defining the operation relationship between multiple analog signals is determined, and the operation configuration instruction is transmitted to the programmable signal operation module so that the programmable signal operation module can perform operations on each analog signal according to the operation configuration instruction to synthesize an initial signal; and generate a signal with the target edge shape according to the initial signal.

[0057] In this embodiment, the target waveform requirements also include specific requirements for the shape of the output signal edges, including edge linearity, overshoot amplitude, ringing amplitude, monotonicity, and edge curve shape. The target edge shape refers to the waveform shape desired by the user or system for the final output signal during transitions, such as a steep vertical rising edge, a gentle sloping rising edge, a stepped rising edge, or a rising edge with overshoot. The target signal includes signals with the target edge shape.

[0058] A programmable signal processing module (PSP) is a circuit module capable of performing configurable operations on multiple input signals according to external instructions. A PSP includes signal adders and signal subtractors. The operation configuration instructions are control commands issued by the FPGA to the PSP, used to define the operational relationships between multiple input analog signals (such as addition, subtraction, weighted summation, differential operations, etc.), as well as the coefficients or weights of each input signal in the operation.

[0059] Upon receiving a debugging request containing the target edge shape, the FPGA first determines the operational relationship between the multiple analog signals required to achieve that specific edge shape based on a preset waveform synthesis algorithm. For example, if a steep rising edge needs to be synthesized, the operational relationship can be set to add multiple analog signals with highly overlapping timings in phase; if a stepped rising edge needs to be synthesized, it can be set to weighted sum of multiple analog signals with different timing offsets according to specific weights.

[0060] The FPGA transmits the corresponding computation configuration instructions to the programmable signal processing module. This module configures its computation network according to the instructions and performs preset addition, subtraction, or weighted operations on the received analog signals in real time, synthesizing them into an initial signal. This initial signal already possesses the core characteristics of the target edge shape (such as steepness, stepped shape, etc.).

[0061] In one feasible implementation, the programmable signal processing module can also employ a programmable gain amplifier array based on operational amplifiers. The FPGA configures the feedback resistor network of each channel in the array through a digital interface, thereby dynamically adjusting the weighting coefficients of each input signal at the summing node, realizing nonlinear weighted combination of multiple signals to synthesize more complex edge shapes (such as exponential rising edges or pulse edges with pre-emphasis).

[0062] This embodiment precisely defines the operational relationships between multiple analog signals through operational configuration instructions, and the programmable signal processing module performs corresponding addition, subtraction and other operations according to the instructions to synthesize the initial signal, so that the edge shape of the final signal is no longer limited to the inherent shape of a single DAC output.

[0063] In one feasible implementation, after the step of generating a signal with a target edge shape based on the initial signal, the following may also be added: The system controls the analog-to-digital converter to sample the initial signal, converts the sampled signal into target digital feedback data, and feeds it back to the local system; calculates the error value between the target digital feedback data and the signal debugging requirements; if the error value is greater than a preset threshold, the system recalculates the relative time offset and amplitude parameters required by the multi-channel digital-to-analog converter based on the received signal debugging requirements and the error value, until the error value is less than or equal to the preset threshold, thus obtaining a signal with the target edge shape.

[0064] It should be noted that the target digital feedback data refers to the digital signal data obtained after the ADC (Analog-to-Digital Converter) samples and converts the output signal. This data truly reflects the actual waveform characteristics of the output signal (such as actual rise time, actual edge shape, etc.).

[0065] After the programmable signal processing module synthesizes the initial signal, the FPGA controls the analog-to-digital converter (ADC) to sample the signal at high speed. The ADC converts the acquired analog signal into target digital feedback data and sends it back to the FPGA via a high-speed interface such as LVDS. After receiving the feedback data, the FPGA extracts key characteristic parameters of the actual output waveform (such as actual rise time and actual edge shape) and compares them with the signal debugging requirements (such as target rise time and target waveform requirements) to obtain the error value.

[0066] The FPGA determines whether the error value is greater than a preset threshold: if the error value is greater than the preset threshold, it indicates that the current output signal does not meet the requirements. Then, the FPGA re-executes step S10 according to the original debugging requirements and the current error value, that is, recalculates the relative time offset and amplitude parameters required by the multiplex digital-to-analog converter, and sequentially drives steps S20, S30, and S40 to generate a new round of output signals; if the error value is less than or equal to the preset threshold, it indicates that the output signal has met the accuracy requirements, then the calibration loop ends and the current signal with the target edge shape is output.

[0067] This complete closed-loop system enables dynamic calibration and precise control of the output signal. It allows the entire signal debugging system to perceive its output status in real time and proactively correct deviations. Specifically, when changes in ambient temperature cause DAC output characteristic drift, power supply noise introduces signal jitter, or manufacturing process variations between multiple DACs lead to deviations between actual output and theoretical calculations, this closed-loop system can capture these deviations in real time via the ADC and perform targeted compensation by recalculating the relative time offset and amplitude parameters. This significantly improves the system's rise time accuracy and output stability over long-term operation.

[0068] In one feasible implementation, the FPGA can employ an adaptive iterative algorithm: in each calibration cycle, the FPGA dynamically adjusts the step size of parameter correction according to the magnitude and direction of the error value: when the error is large, a large step size is used to quickly approach the target range; when the error is small and enters the vicinity of the threshold, a small step size is used for fine adjustment to avoid oscillation at the threshold boundary and achieve a smoother and more efficient convergence process.

[0069] In one feasible implementation, the FPGA can perform spectral analysis on the error value between the target digital feedback data and the signal debugging requirements, decomposing the error into different frequency components; based on the frequency characteristics of the error, the corresponding control parameters are selectively updated: when the error is mainly manifested as low-frequency drift (such as temperature drift), the amplitude parameters of the multi-channel DAC are adjusted first; when the error is mainly manifested as high-frequency jitter (such as clock phase noise), the relative time offset of the multi-channel DAC is adjusted first; when the error is manifested as periodic ripple at a specific frequency, the specific DAC channel that generates the ripple is locked, and the phase or amplitude parameters of that channel are corrected specifically.

[0070] It's understandable that when the error manifests as low-frequency drift, the amplitude parameter should be adjusted first, as it is sensitive to temperature changes and adjusting the amplitude parameter yields the highest compensation efficiency for low-frequency drift. When the error manifests as high-frequency jitter, the relative time offset should be adjusted first, as fine-tuning the time offset can directly compensate for phase noise on the clock path. When the error manifests as periodic ripple at a specific frequency, the corresponding DAC channel should be locked and corrected individually to avoid introducing unnecessary disturbances to other normal channels when adjusting global parameters. This allows the integration module to dynamically adjust its filtering characteristics based on the current state of the signal.

[0071] The edge transition interval refers to the time interval during which a signal transitions from a low level to a high level (or vice versa). Within this interval, the signal slope is relatively large, and it is the main region reflecting the rise / fall time. The plateau interval refers to the time interval during which the signal remains at a stable high or low level after the edge transition. During this interval, the signal should remain constant, and high noise filtering is required. Overshoot refers to the phenomenon where the actual amplitude of the signal exceeds the target stable amplitude during the edge transition process, usually caused by an excessively fast system response or impedance mismatch.

[0072] In one feasible implementation, the timing position of the redundant channel can be independently and dynamically adjusted according to the deviation between the actual output and the target edge. This is used to compensate for local edge distortion caused by factors such as device nonlinearity and temperature drift, without affecting the overall timing distribution of the main channel. Because the aforementioned global correction method, which adjusts the phase or amplitude of all DACs in the same direction, may disrupt the original non-uniform phase distribution structure, leading to edge shape distortion. This embodiment, by reserving an independent redundant calibration channel, allows the system to dynamically fine-tune the timing position of the redundant channel only during closed-loop calibration, using it to compensate for local distortion within a specific time interval of the edge, without disturbing the already optimized non-uniform phase distribution of the main channel.

[0073] In one feasible implementation, before the step of controlling the analog-to-digital converter to sample the initial signal, convert the sampled signal into target digital feedback data, and feed it back locally, the following may also be done: The initial signal is input to the signal integration module, which smooths the initial signal to generate a continuous waveform signal. The signal enhancement module then enhances the signal strength of the continuous waveform signal according to the load requirements to generate an enhanced waveform signal.

[0074] In this embodiment, after the programmable signal processing module synthesizes the initial signal and before the ADC sampling feedback, a signal integration module and a signal enhancement module can be introduced to optimize the waveform.

[0075] The signal integrator module is a circuit module that performs integration operations on the input signal, typically composed of operational amplifiers, resistors, and capacitors. This module smooths abrupt signal edges, filters out high-frequency noise and glitches, resulting in a more continuous and smooth waveform. The signal enhancement module is a circuit module used to improve the driving capability of a signal, typically composed of buffers, amplifiers, or power amplifiers. This module enhances the current output capability or voltage amplitude of the signal to ensure good waveform integrity during long-distance transmission or driving heavy loads.

[0076] Specifically, after the programmable signal processing module performs operations on each analog signal and synthesizes the initial signal according to the operation configuration instructions, the FPGA first inputs the initial signal to the signal integration module. The signal integration module performs integration operations on the initial signal, filtering out high-frequency noise and edge glitches that may be generated during the operation, making the signal edge transition smoother and more continuous, and generating a continuous waveform signal.

[0077] In one feasible implementation, the signal integration module can employ a programmable integrator whose integration time constant can be dynamically configured by the FPGA. When high-frequency oscillations or overshoots are detected in the output signal, the FPGA can increase the integration time constant to enhance the smoothing effect; when it is necessary to preserve the fast edge characteristics of the signal, the integration time constant can be decreased. This configurable integration method allows the system to dynamically balance edge steepness and waveform smoothness to adapt to different application requirements.

[0078] The continuous waveform signal is fed into the signal enhancement module. The signal enhancement module can increase the current driving capability or voltage amplitude of the signal according to the load requirements, ensuring that the waveform is not distorted during subsequent long-distance transmission or driving heavy loads, and generating an enhanced waveform signal.

[0079] In one feasible implementation, load requirements refer to the electrical characteristics requirements of the external device or circuit ultimately driven by the target signal on the input signal, mainly including factors such as input impedance, required drive current, input voltage range, and transmission distance. Different loads correspond to different drive requirements. Signal strength refers to the driving capability of an analog signal, specifically including output current capability, output voltage amplitude, or output power.

[0080] The specific implementation method for generating an enhanced waveform signal by using a signal enhancement module to amplify the signal strength of the continuous waveform signal according to the load demand can be as follows: The FPGA obtains the current load demand and calculates the optimal gain factor and output impedance configuration required by the signal enhancement module. The gain factor determines the amplification factor of the signal amplitude, while the output impedance configuration determines the impedance matching degree between the module and the load to maximize power transfer and reduce signal reflection.

[0081] The FPGA transmits the calculated gain and impedance configuration instructions to the signal enhancement module. The programmable gain amplifier within this module adjusts its feedback network according to the instructions, setting the corresponding gain factor. Simultaneously, the output impedance matching network switches its internal resistor array or adjusts the parameters of the impedance transformation circuit according to the instructions, ensuring that the module's output impedance matches the load impedance.

[0082] Finally, after the continuous waveform signal is input to the signal enhancement module, it first undergoes amplitude amplification by a programmable gain amplifier, then impedance transformation through an output impedance matching network, ultimately generating an enhanced waveform signal output. This enhanced waveform signal meets the load's voltage requirements in terms of amplitude and its current requirements in terms of driving capability. Furthermore, due to good impedance matching, signal reflection and loss during transmission are minimized. This allows the signal enhancement module to dynamically adjust the gain coefficient and output impedance according to load requirements, achieving load adaptive capability in the signal enhancement process.

[0083] In one feasible implementation, the target digital feedback data further includes digital feedback data after waveform quality improvement. Before the step of calculating the error value between the target digital feedback data and the signal debugging requirement, the following may also be done: The enhanced waveform signal is sampled by an analog-to-digital converter, and the sampled signal is converted into digital feedback data with improved waveform quality and fed back to the local machine.

[0084] The FPGA can also control the analog-to-digital converter to sample the enhanced waveform signal, instead of directly sampling the initial signal. The ADC converts the acquired enhanced waveform signal into digital feedback data with improved waveform quality and sends it back to the FPGA via high-speed interfaces such as LVDS.

[0085] The improved waveform feedback data refers to the digital feedback data obtained by the ADC through sampling and conversion of the signal after smoothing and drive enhancement. Compared to directly sampling the initial signal, this data reflects the actual output quality after optimization of the entire signal chain, including the waveform improvement effects brought about by smoothing and drive enhancement.

[0086] This embodiment uses a signal integration module to smooth the initial signal, effectively eliminating high-frequency glitches and edge abrupt changes that may occur during addition / subtraction operations of multiple signals, making the output waveform more continuous and smooth. The drive enhancement module improves the signal driving capability, ensuring the waveform integrity of the signal at the transmission link and load end.

[0087] In one feasible implementation, during the smoothing process of the initial signal by the signal integration module, the FPGA can monitor the current progress status of the target edge in real time and dynamically switch the integration time constant of the signal integration module: when the signal is detected to be in the edge transition interval, the integration time constant is switched to the first level (smaller value) to minimize the attenuation of edge steepness; when the signal is detected to enter the plateau interval or after the transition is completed, the integration time constant is switched to the second level (larger value) to enhance the filtering effect of high-frequency noise and glitches; when overshoot or ringing is detected at the signal edge, the integration time constant is temporarily switched to an intermediate level between the first and second levels within the edge transition interval to achieve dynamic suppression of overshoot.

[0088] It is understandable that in this embodiment, the integration time constant is switched to a smaller level in the edge transition range, thereby preserving the steepness and shape characteristics of the target edge generated by the precise synthesis of multiple DACs to the maximum extent. In the plateau range, the integration time constant is switched to a larger level, thereby effectively filtering out multi-DAC switching noise, high-frequency glitches generated by addition / subtraction operations, and external interference. When overshoot or ringing is detected, the system temporarily switches to an intermediate level in the edge transition range, achieving dynamic suppression of overshoot without significantly sacrificing the steepness of the edge. Furthermore, it is precisely because the collaborative operation of multiple DACs may introduce multi-channel switching noise that enhancing noise filtering in the plateau range is of necessary value.

[0089] In one feasible implementation, after the step of synthesizing a target signal that meets the signal debugging requirements based on the analog signals output from each digital-to-analog converter, the following can also be added: The system monitors in real time whether the target digital feedback data meets the signal debugging requirements. When the target digital feedback data meets the signal debugging requirements, an enable signal is generated to control the signal switch module to turn on and output the target signal to the load. When the target digital feedback data does not meet the signal debugging requirements, the system controls the signal switch module to remain in the off state to block the signal output to the load.

[0090] After obtaining the target signal that meets the requirements through a closed-loop calibration process (i.e., iteratively correcting the error value between the target digital feedback data and the debugging requirements), the FPGA continues to execute the output monitoring and control functions. The FPGA monitors the target digital feedback data returned by the analog-to-digital converter in real time and continuously compares this data with the original signal debugging requirements (such as target rise time, target waveform requirements, etc.) to determine whether the current output signal always meets the requirements.

[0091] When the FPGA determines that the target digital feedback data meets the signal debugging requirements (e.g., the error between the actual rise time and the target rise time is within a preset threshold range, and the waveform shape meets the requirements), the FPGA generates a valid enable signal and transmits it to the control terminal of the signal switch module. Upon receiving the valid enable signal, the signal switch module turns on, establishes an output path, and outputs the verified target signal to the load.

[0092] The enable signal is a control signal generated by the FPGA to turn the signal switching module on or off. When the enable signal is valid, the signal switching module is turned on, allowing the target signal to be output to the load; when the enable signal is invalid, the signal switching module is turned off, blocking the signal output.

[0093] When the FPGA determines that the target digital feedback data does not meet the signal debugging requirements (for example, due to sudden noise interference, power fluctuations, or other abnormal conditions causing the output signal to deviate from the acceptable range), the control signal switch module remains in or switches to the off state. At this time, the output path is blocked, and the unacceptable target signal cannot be output to the load, thus avoiding potential impact on downstream devices or the object under test. This achieves intelligent management of the output signal's on / off state, ensuring that only verified, qualified signals reach the load.

[0094] For example, to help understand the implementation flow of the signal debugging method obtained by combining this embodiment with the above embodiment one, please refer to... Figure 2 , Figure 2 A signal debugging system architecture diagram is provided, specifically: The signal debugging system architecture includes a field-programmable gate array (FPGA), a multi-channel digital-to-analog converter (DAC), a switch matrix, signal adders / subtractors, a signal integrator module, a signal drive enhancement module, an output calibration module, signal switches, and an analog-to-digital converter (ADC).

[0095] The field-programmable gate array (FPGA) is used to output enable signals, a general-purpose control bus, multiple digital waveform data (such as "digital waveform data 0" to "digital waveform data N") and interface protocol signals, and to receive feedback signals from the ADC.

[0096] The multiplexed digital-to-analog converters (e.g., "Digital-to-analog converter 0" to "Digital-to-analog converter N") receive the corresponding digital waveform data and interface protocols respectively, and convert them into analog signals (e.g., "Analog signal 0" to "Analog signal N").

[0097] Each analog signal is input to a switch matrix, which selects or routes the signal before sending it to a signal adder / subtractor for analog domain operations.

[0098] The processed signal undergoes signal integration, signal drive enhancement, and output calibration in sequence, and finally outputs the target waveform through a signal switch controlled by an enable signal.

[0099] Meanwhile, the calibrated output signal can also be fed back to the ADC, converted from analog to digital and then sent back to the field programmable gate array to form a closed-loop correction path, so as to achieve dynamic accuracy compensation and waveform optimization.

[0100] like Figure 3 As shown, the four independent DAC output signals (digital-to-analog converter 0 to digital-to-analog converter 3) exhibit a phase-interleaved distribution on the time axis, that is, the rising edges of each signal are staggered sequentially (digital-to-analog converter 0 is the earliest, and digital-to-analog converter 3 is the latest), which reflects the FPGA's ability to control the independent phase shift of multiple DACs.

[0101] After the four phase-interleaved analog signals are input into the adder and superimposed, the output waveform changes from the original vertical jump to a stepped rising edge. The number of steps is the same as the number of DAC channels, the step width corresponds to the phase difference, and the step height corresponds to the amplitude of each channel, thus initially realizing the discrete control of the edge slope.

[0102] After integrating the stepped wave output by the adder, the originally discrete steps are smoothed into a continuous linear ramp, ultimately obtaining an ideal analog signal edge without glitches and with a precisely adjustable rise time, thus completing the full-link synthesis from "digital phase control" to "analog waveform shaping".

[0103] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the signal debugging method of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0104] This application also provides a signal debugging device, please refer to... Figure 4 The signal debugging device includes: The calculation module 10 is used to calculate the relative time offset and amplitude parameters required by the multi-channel digital-to-analog converter according to the received signal debugging requirements, wherein the signal debugging requirements include the target rise time and the target waveform requirements. The transmission module 20 is used to generate multiple digital waveform data with time-interleaved characteristics according to the relative time offset, and transmit the multiple digital waveform data to the corresponding digital-to-analog converters respectively. The conversion module 30 is used to control the multi-channel digital-to-analog converter to convert the received digital waveform data into an analog signal output according to the amplitude parameter; The generation module 40 is used to synthesize a target signal that meets the signal debugging requirements based on the analog signals output by each digital-to-analog converter.

[0105] In one embodiment, the target waveform is required to include a target edge shape, the target signal includes a signal having the target edge shape, and the generation module 40 includes: The determination submodule is used to determine the operation configuration instructions for defining the operation relationship between multiple analog signals based on the target edge shape, and transmit the operation configuration instructions to the programmable signal operation module so that the programmable signal operation module can perform operations on each analog signal according to the operation configuration instructions to synthesize an initial signal; The first generation submodule is used to generate a signal with a target edge shape based on the initial signal.

[0106] In one embodiment, after the step of generating a signal having a target edge shape based on the initial signal, the method further includes: The conversion submodule is used to control the analog-to-digital converter to sample the initial signal, convert the sampled signal into target digital feedback data, and feed it back to the local unit; The calculation submodule is used to calculate the error value between the target digital feedback data and the signal debugging requirements; The correction submodule is used to recalculate the relative time offset and amplitude parameters required by the multiplex digital-to-analog converter based on the received signal debugging requirements and the error value if the error value is greater than a preset threshold, until the error value is less than or equal to the preset threshold, thus obtaining a signal with the target edge shape.

[0107] In one embodiment, before the step of controlling the analog-to-digital converter to sample the initial signal, convert the sampled signal into target digital feedback data, and feed it back locally, the method further includes: The smoothing submodule inputs the initial signal to the signal integration module, and the signal integration module smooths the initial signal to generate a continuous waveform signal. The signal enhancement submodule enhances the signal strength of the continuous waveform signal according to the load requirements, thereby generating an enhanced waveform signal. The target digital feedback data also includes digital feedback data after waveform quality improvement. Before the step of calculating the error value between the target digital feedback data and the signal debugging requirements, the method further includes: The sampling submodule samples the enhanced waveform signal through an analog-to-digital converter, converts the sampled signal into digital feedback data with improved waveform quality, and feeds it back to the local unit.

[0108] In one embodiment, after the step of synthesizing a target signal that meets the signal debugging requirements based on the analog signals output from each digital-to-analog converter, the method further includes: The monitoring module monitors in real time whether the target digital feedback data meets the signal debugging requirements; The output module generates an enable signal when the target digital feedback data meets the signal debugging requirements, controls the signal switch module to turn on, and outputs the target signal to the load. The control module controls the signal switch module to remain in the off state when the target digital feedback data does not meet the signal debugging requirements, so as to block the signal output to the load.

[0109] In one embodiment, the transmission module 20 includes at least one of the following: The second generation submodule keeps the sampling clocks of each digital-to-analog converter synchronized and generates multi-channel digital waveform data with timing interleaving characteristics by embedding the relative time offset into the multi-channel digital waveform data. The third generation submodule maintains the synchronization of digital waveform data transmitted to each digital-to-analog converter and controls the clock phase shift circuit to generate a sampling clock with a phase difference corresponding to the relative time offset for each digital-to-analog converter. The phase difference of the sampling clock enables each digital-to-analog converter to convert the synchronized digital waveform data at staggered times, generating multi-channel digital waveform data with time-interleaved characteristics.

[0110] The signal debugging device provided in this application, employing the signal debugging method described in the above embodiments, can solve the technical problem of high testing costs. Compared with the prior art, the beneficial effects of the signal debugging device provided in this application are the same as those of the signal debugging method described in the above embodiments, and other technical features in the signal debugging device are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0111] This application provides a signal debugging device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the signal debugging method in the above embodiment 1.

[0112] The following is for reference. Figure 5 The diagram illustrates a structural schematic of a signal debugging device suitable for implementing embodiments of this application. The signal debugging device in the embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, tablets, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital televisions and desktop computers. Figure 5 The signal debugging device shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0113] like Figure 5As shown, the signal debugging device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the signal debugging device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to the I / O interface 1006: input devices 1007 including, for example, a touchscreen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 1003 including, for example, magnetic tape, hard disk, etc.; and communication devices 1009. Communication device 1009 allows the signal debugging equipment to communicate wirelessly or wiredly with other devices to exchange data. Although the figure shows signal debugging equipment with various systems, it should be understood that implementation or possession of all the systems shown is not required. More or fewer systems may be implemented alternatively.

[0114] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0115] The signal debugging device provided in this application, employing the signal debugging method described in the above embodiments, can solve the technical problem of high testing costs. Compared with the prior art, the beneficial effects of the signal debugging device provided in this application are the same as those of the signal debugging method described in the above embodiments, and other technical features of the signal debugging device are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0116] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0117] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0118] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the signal debugging method described in the above embodiments.

[0119] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0120] The aforementioned computer-readable storage medium may be included in the signal debugging equipment; or it may exist independently and not be assembled into the signal debugging equipment.

[0121] The aforementioned computer-readable storage medium carries one or more programs, which, when executed by the signal debugging device, cause the signal debugging device to perform the aforementioned signal debugging method.

[0122] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0123] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0124] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0125] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described signal debugging method, thereby solving the technical problem of high testing costs. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the signal debugging method provided in the above embodiments, and will not be repeated here.

[0126] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the signal debugging method described above.

[0127] The computer program product provided in this application can solve the technical problem of high testing costs. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as those of the signal debugging method provided in the above embodiments, and will not be repeated here.

[0128] The above descriptions are merely some embodiments of this application and do not limit the scope of protection of this application. Any equivalent structural transformations made based on the technical concept of this application and the content of this specification and drawings, or direct / indirect applications in other related technical fields, are included within the scope of protection of this application. All actions involving the acquisition of signals, information, or data in this application are performed in accordance with the relevant data protection laws and policies of the country where the application is located and with authorization from the owner of the corresponding device.

Claims

1. A signal debugging method, characterized by, The signal debugging method includes: Based on the received signal debugging requirements, calculate the relative time offset and amplitude parameters required by the multi-channel digital-to-analog converter. The signal debugging requirements include the target rise time and the target waveform requirements. Based on the relative time offset, multi-channel digital waveform data with time-interleaved characteristics are generated, and the multi-channel digital waveform data are transmitted to the corresponding digital-to-analog converters respectively. The multi-channel digital-to-analog converter is controlled to convert the received digital waveform data into an analog signal output according to the amplitude parameter; Based on the analog signals output from each digital-to-analog converter, a target signal that meets the signal debugging requirements is synthesized.

2. The signal debugging method of claim 1, wherein, The target waveform requirement includes a target edge shape, and the target signal includes a signal having the target edge shape. The step of synthesizing a target signal that meets the signal debugging requirements based on the analog signals output from each digital-to-analog converter includes: Based on the target edge shape, an operation configuration instruction for defining the operation relationship between multiple analog signals is determined, and the operation configuration instruction is transmitted to the programmable signal operation module so that the programmable signal operation module can perform operations on each analog signal according to the operation configuration instruction to synthesize an initial signal. Based on the initial signal, a signal with the target edge shape is generated.

3. The method of claim 2, wherein the signal is a digital signal. After the step of generating a signal with a target edge shape based on the initial signal, the method further includes: The analog-to-digital converter is controlled to sample the initial signal, convert the sampled signal into target digital feedback data, and feed it back to the local system. Calculate the error value between the target digital feedback data and the signal debugging requirements; If the error value is greater than the preset threshold, then according to the received signal debugging requirements and the error value, the steps of recalculating the relative time offset and amplitude parameters required by the multi-channel digital-to-analog converter are repeated until the error value is less than or equal to the preset threshold, and a signal with the target edge shape is obtained.

4. The method of claim 3, wherein the signal is a digital signal. Before the step of controlling the analog-to-digital converter to sample the initial signal, convert the sampled signal into target digital feedback data, and feed it back locally, the method further includes: The initial signal is input to the signal integration module, which smooths the initial signal to generate a continuous waveform signal. The signal enhancement module enhances the signal strength of the continuous waveform signal according to the load requirements, thereby generating an enhanced waveform signal. The target digital feedback data also includes digital feedback data after waveform quality improvement. Before the step of calculating the error value between the target digital feedback data and the signal debugging requirements, the method further includes: The enhanced waveform signal is sampled by an analog-to-digital converter, and the sampled signal is converted into digital feedback data with improved waveform quality and fed back to the local machine.

5. The method of claim 3, wherein the signal is a digital signal. After the step of synthesizing the target signal that meets the signal debugging requirements based on the analog signals output from each digital-to-analog converter, the method further includes: Real-time monitoring of whether the target digital feedback data meets the signal debugging requirements; When the target digital feedback data meets the signal debugging requirements, an enable signal is generated to control the signal switching module to turn on, and the target signal is output to the load. When the target digital feedback data does not meet the signal debugging requirements, the signal switch module is controlled to remain in the off state to block the signal output to the load.

6. The method of claim 1, wherein the signal is a video signal. The step of generating multi-channel digital waveform data with time-interleaved characteristics based on the relative time offset includes at least one of the following: Maintaining the sampling clock synchronization of each digital-to-analog converter, and generating multi-channel digital waveform data with timing interleaving characteristics by embedding the relative time offset into the multi-channel digital waveform data; To maintain the synchronization of digital waveform data transmitted to each digital-to-analog converter, the control clock phase shift circuit generates a sampling clock for each digital-to-analog converter with a phase difference corresponding to the relative time offset. The phase difference of the sampling clock enables each digital-to-analog converter to convert the synchronized digital waveform data at staggered times, generating multi-channel digital waveform data with time-interleaved characteristics.

7. A signal debugging apparatus characterized by comprising: The signal debugging device includes: The calculation module is used to calculate the relative time offset and amplitude parameters required by the multi-channel digital-to-analog converter based on the received signal debugging requirements, wherein the signal debugging requirements include the target rise time and the target waveform requirements. The transmission module is used to generate multiple digital waveform data with time-interleaved characteristics according to the relative time offset, and transmit the multiple digital waveform data to the corresponding digital-to-analog converters respectively. The conversion module is used to control the multi-channel digital-to-analog converter to convert the received digital waveform data into an analog signal output according to the amplitude parameter; The generation module is used to synthesize a target signal that meets the signal debugging requirements based on the analog signals output by each digital-to-analog converter.

8. A signal debugging device, characterized by, The signal debugging device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the signal debugging method as described in any one of claims 1 to 6.

9. A storage medium, characterized by The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the signal debugging method as described in any one of claims 1 to 6.

10. A computer program product, characterised in that, The computer program product includes a computer program that, when executed by a processor, implements the steps of the signal debugging method as described in any one of claims 1 to 6.

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