Beamformer and ultrasound chip

Abstract

This invention provides a beamformer and an ultrasonic chip, comprising: multiple delay units; each delay unit includes a first readout switch R and multiple delay channels; each delay channel includes a sampling capacitor Cu, a write switch W, and a second readout switch R; one end of the write switch W is connected to the input terminal of the delay channel, and the other end is connected to one end of the second readout switch R; one end of the sampling capacitor Cu is connected between the other end of the write switch W and one end of the second readout switch R, and the other end is grounded; the output terminals of the multiple delay channels are connected to the common output terminal of the delay units through the first readout switch R, which isolates the parasitic capacitance of each delay unit, ensuring that each delay unit only connects its own parasitic capacitance to the common output terminal during operation. By adding a first readout switch R to the output terminal of each delay unit, this invention effectively isolates the parasitic capacitance of each delay unit and delay channel, significantly reducing the total parasitic capacitance of the common output terminal.

Description

Technical Field

[0001] This invention relates to ultrasonic chips, and more specifically, to a beamformer and an ultrasonic chip. Background Technology

[0002] Complementary Metal Oxide Semiconductor (CMOS) technology, as a core technology in the semiconductor field, is widely used in integrated circuit manufacturing and many other areas. It can integrate a large number of transistors onto a small chip, continuously developing in accordance with Moore's Law, and driving the evolution of semiconductors towards miniaturization and high performance.

[0003] The working principle of an ultrasonic transducer is based on the direct and inverse piezoelectric effects of piezoelectric materials. It utilizes the periodic vibration of the piezoelectric layer to achieve efficient transmission and reception of ultrasonic signals. When the ultrasonic transducer acts as a transmitter, it essentially converts electrical signals into mechanical vibration energy. Under the action of a driving voltage, the piezoelectric layer deforms due to the inverse piezoelectric effect, radiating ultrasonic waves into the medium. When acting as a receiver, it becomes a sensor that captures mechanical vibration energy. External ultrasonic waves cause the piezoelectric layer to vibrate, converting the acoustic signal into an electrical signal through the direct piezoelectric effect for subsequent processing.

[0004] In ultrasound chips, the CMOS integrated circuit at the transmitting end precisely controls the excitation signal of the ultrasound transducer. For example, it can generate electrical pulse signals with specific frequencies, pulse widths, and amplitudes to drive the ultrasound transducer to emit ultrasonic waves. In some medical ultrasound diagnostic devices, the CMOS integrated circuit optimizes the emitted waveform, improving the emission efficiency and directivity of the ultrasound waves, thereby enhancing the resolution and clarity of the imaging. At the receiving end, the CMOS integrated circuit is responsible for receiving the echo signals received by the ultrasound transducer and performing preprocessing such as pre-amplification and filtering. CMOS integrated circuits can integrate high-performance, low-noise amplifiers to reduce noise interference in the received signal, while simultaneously processing echo signals of different frequencies and amplitudes quickly and accurately, providing high-quality data for subsequent signal processing and image reconstruction.

[0005] Switched-capacitor sampling circuits are widely used in ultrasonic chips, but their parasitic capacitance limits the bandwidth and accuracy of the ultrasonic chip's output signal. This phenomenon is particularly pronounced in two-dimensional array ultrasonic chips that require subarray beamforming. The bandwidth of the beamformer is limited by both sinc filtering and IIR filtering, the parasitic capacitance is too large and difficult to control, the reset design is complex (requiring additional circuitry, increasing power consumption and distortion), and there is a trade-off between noise, area, and parasitic capacitance in the design, which cannot meet the high bandwidth, low distortion, and low power consumption requirements of ICE systems, thus necessitating an improved architecture. Summary of the Invention

[0006] To address the problems in the prior art, the purpose of this invention is to provide a beamformer and an ultrasonic chip.

[0007] The beamformer provided by the present invention includes: a plurality of delay units; each of the delay units includes a first readout switch R and a plurality of delay channels; Each of the aforementioned delay channels includes a sampling capacitor C. u A write switch W and a second read switch R; one end of the write switch W is connected to the input terminal of the delay channel, and the other end is connected to one end of the second read switch R; the sampling capacitor C u One end is connected between the other end of the write switch W and one end of the second read switch R, and the other end is grounded; The output terminals of multiple delay channels are connected to the common output terminal of the delay unit through the first readout switch R. The first readout switch R is used to isolate the parasitic capacitance of each delay unit, so that each delay unit only connects its own parasitic capacitance to the common output terminal when it is working.

[0008] Preferably, each delay channel in each delay unit is used to connect to a transducer array element to receive echo electrical signals.

[0009] Preferably, each of the delay channels has a parasitic capacitance C. p .

[0010] Preferably, each of the delay channels writes the echo signal by closing the write switch W and reads the echo signal by closing the second read switch R.

[0011] Preferably, the echo electrical signal writing time of each delay channel in each delay unit is different; The echo signal readout time of each delay channel in each delay unit is the same.

[0012] Preferably, when the echo signal of one of the delay units is read out, the first readout switch R is closed.

[0013] Preferably, the readout time of the echo electrical signal is different for different delay units; The first readout switch R corresponding to the delay unit is closed only when the echo signal of the delay unit is read out.

[0014] The ultrasonic chip provided by this invention includes the aforementioned beamformer, and further includes: An ultrasonic circuit array includes multiple ultrasonic circuit sub-arrays, each sub-array comprising a beamformer and multiple ultrasonic transceiver array elements. The ultrasonic transceiver array elements are used to connect to ultrasonic transducer array elements, which are used to convert received pulse electrical signals into ultrasonic waves and transmit them, or to convert received ultrasonic echoes into echo electrical signals. The beamformer is used to beamform the echo electrical signal received by the ultrasonic transceiver array element to enhance the echo electrical signal. Preferably, the ultrasonic transceiver array element includes: A pulse transmitting circuit is used to generate pulsed electrical signals to drive the ultrasonic transducer array elements to emit ultrasonic waves; An echo receiving circuit is used to receive the echo electrical signal generated by the ultrasonic transducer array element; A switching switch is used to switch the connection between the ultrasonic transducer array element and the pulse transmitting circuit or the echo receiving circuit.

[0015] Preferably, it also includes a write pointer loopback shift register, a read pointer loopback shift register, and a read strobe logic unit; The write pointer loopback shift register is used to output a write strobe signal to control the on / off state of the corresponding write switch W; The read pointer loopback shift register is used to output the read strobe signal; The read gating logic unit is used to receive the read gating signal and convert it into a read gating target signal for controlling the on / off state of the first readout switch R and the second readout switch R.

[0016] Preferably, it further includes a resampling unit; The signal output terminal of the beamformer is connected to the input terminal of the resampling unit; the resampling unit is used to capture the effective ultrasonic signal in the zero-return waveform output by the beamformer and restore the discontinuous zero-return waveform to an uninterrupted continuous analog ultrasonic echo signal.

[0017] Preferably, the resampling unit includes a timing control module, a first sample-and-hold unit, and a second sample-and-hold unit; The timing control module is used to generate a non-overlapping first sampling clock and a second sampling clock, wherein the effective window of the first sampling clock is aligned with the effective pulse segment of the return-to-zero waveform signal, and the effective window of the second sampling clock is aligned with the forced zero-level gap segment of the return-to-zero waveform signal. The signal input terminal of the first sample-and-hold unit is electrically connected to the signal output terminal of the beamformer, and the control terminal of the first sample-and-hold unit is electrically connected to the first sampling clock output terminal of the timing control module. It is used to complete the sampling of the effective ultrasonic echo signal in the effective pulse segment of the zero-return waveform signal, and to continuously maintain and output the effective signal level obtained by sampling in the forced zero-level gap segment of the zero-return waveform signal. The signal input terminal of the second sample-and-hold unit is electrically connected to the signal output terminal of the beamformer, and the control terminal of the second sample-and-hold unit is electrically connected to the second sampling clock output terminal of the timing control module. It is used to complete the sampling of the effective ultrasonic echo signal in the next effective pulse segment of the zero-level waveform signal, and to continuously maintain and output the effective signal level obtained by sampling in the corresponding forced zero-level gap segment. The timing control module controls the seamless splicing of the signals alternately output by the two sample-and-hold units to form a continuous analog ultrasonic echo signal without forced zero-level gap.

[0018] Preferably, the first sampling clock and the second sampling clock generated by the timing control module are non-overlapping clocks, and a preset dead time is set between the effective windows of the two clocks to avoid sampling conflicts between the first sample-and-hold unit and the second sample-and-hold unit.

[0019] Preferably, both the first sample-and-hold unit and the second sample-and-hold unit include a sampling switch, a readout switch, and a holding capacitor; The control terminal of the sampling switch is connected to the corresponding sampling clock, the input terminal of the sampling switch is connected to the output terminal of the beamformer, the output terminal of the sampling switch is connected to one end of the holding capacitor and the input terminal of the readout switch respectively, the other end of the holding capacitor is grounded, and the output terminal of the readout switch serves as the signal output terminal of the corresponding sample-and-hold unit.

[0020] Compared with the prior art, the present invention has the following beneficial effects: In this embodiment of the invention, by adding a first readout switch R at the output of each delay unit, the parasitic capacitance of each delay unit and delay channel is effectively isolated, significantly reducing the total parasitic capacitance at the common output. Compared to the traditional architecture, the total parasitic capacitance can be reduced by several times (e.g., more than 7 times in the subarray scenario with N=16 and k=14), significantly weakening the IIR filtering effect. This makes the beamformer bandwidth mainly limited by a controllable sinc filter, meeting the core requirements of high bandwidth and low distortion for ICE systems, while avoiding the signal accuracy degradation problem caused by excessive parasitic capacitance. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort. Other features, objects, and advantages of the present invention will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a schematic diagram of an interventional ultrasound application scenario for an integrated circuit system used for intracardiac ultrasound in an embodiment of the present invention; Figure 2 This is a circuit diagram of the ultrasonic chip in an embodiment of the present invention; Figure 3 This is a schematic diagram illustrating the principle of beamforming in an embodiment of the present invention; Figure 4 This is a first circuit diagram of an analog beamformer based on switched capacitors in an embodiment of the present invention; Figure 5 This is a second circuit diagram of an analog beamformer based on switched capacitors in an embodiment of the present invention; Figure 6 This is a schematic diagram of the ultrasonic chip in an embodiment of the present invention; Figure 7 This is a schematic diagram of the ultrasonic transceiver array element in an embodiment of the present invention; Figure 8 This is a schematic diagram illustrating the control of the write switch and read switch in an embodiment of the present invention; Figure 9 This is a timing diagram of the simulated beamformer writing and reading electrical signals in an embodiment of the present invention; Figure 10 This is a circuit diagram of beamforming resampling in an embodiment of the present invention.

[0022] In the picture: 1 is a pulse generator; 2 is a signal amplifier; 3 is a switching switch. Detailed Implementation

[0023] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention. These all fall within the scope of protection of the present invention.

[0024] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0026] The technical solutions of the present invention and how they solve the above-mentioned technical problems will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present invention will now be described with reference to the accompanying drawings.

[0027] Figure 1 This is a schematic diagram illustrating an application scenario of an integrated circuit system for intracardiac ultrasound in an embodiment of the present invention, such as... Figure 1 As shown, during intracardiac ultrasound, a transceiver probe 100 is placed inside the heart via a blood vessel to perform real-time, high-quality imaging or hemodynamic measurements of the heart and adjacent tissues. It is primarily used in interventional cardiac procedures such as atrial fibrillation radiofrequency ablation, mitral valve repair, left atrial appendage closure, and closure of atrial septal defects and patent foramen ovale. It enables real-time monitoring of catheter position and surgical outcomes, assessment of cardiac structure and function, guidance of surgical procedures, and reduction of surgical risks. The probe 100 has a diameter of approximately 3-10F (1-3.3 mm) and is integrated into the tip of the interventional catheter 200, inserted into the heart chamber via a vascular pathway (such as the femoral vein). The probe 100 typically operates at a frequency of 5-20 MHz, offering extremely high resolution, but with limited penetration depth, covering only local structures within the heart chambers. Given that the heart rate is approximately 60-100 beats per minute and the valve opening and closing cycle is only a few hundred milliseconds, a high imaging frame rate, such as a 4D imaging rate of 50 volumes / s, is required.

[0028] Figure 2 This is a circuit diagram of the ultrasonic chip in an embodiment of the present invention, as shown below. Figure 2As shown, a PMUT transducer array 102 is integrated on the substrate 101. The PMUT transducer array 102 is used to convert received pulse electrical signals into ultrasonic waves and transmit them, or to convert received ultrasonic echoes into echo electrical signals. An ultrasonic control integrated circuit 1017 is formed on the substrate 101. The ultrasonic control integrated circuit 1017 includes a pulse transmitting circuit and an echo receiving circuit. The pulse transmitting circuit includes a transmitting beamformer and a pulse generating unit for transmitting pulse electrical signals to drive the PMUT transducer array 102 to transmit ultrasonic waves. The echo receiving circuit includes a signal amplifier and a receiving beamformer for receiving and processing the echo electrical signals.

[0029] Figure 3 This is a schematic diagram illustrating the principle of beamforming in an embodiment of the present invention, such as... Figure 3 As shown, the transducer array consists of multiple transducer elements, serving both ultrasonic wave transmission and echo reception functions. During the transmission phase, the delay unit applies differentiated delays to the excitation signals of different elements, causing the ultrasonic wavefronts emitted by each element to converge synchronously to a preset focus, achieving electronic focusing without mechanical movement. During the reception phase, it compensates for the time difference in arrival time of the echo signal at the focus point to each element, aligning the echo signals in phase. The superposition and summation module performs in-phase superposition of the delayed multi-element signals, enhancing the signal. The processed ultrasonic signal is finally input into the ultrasonic host for imaging.

[0030] In intracardiac ultrasound (ICE) applications, an analog beamformer is responsible for the primary spatial combination of signals acquired by the transducer array. All transducer elements in the system are divided into multiple subarrays, each containing 12 or 16 transducer elements. The analog beamformer achieves subarray-level beamforming by applying a fixed delay to the signals within each subarray and then averaging them, ultimately generating a single output echo signal for each subarray. This operation effectively reduces the total number of channels.

[0031] Figure 4 This is a circuit diagram of an analog beamformer based on switched capacitors in an embodiment of the present invention, such as... Figure 4 As shown, this simulated beamformer can be used for N channels (labeled CH1...CH). N The echo electrical signal is delayed and superimposed. Within the set target delay range, each channel is sampled through k capacitors. All channels have the same capacitance C. U Each C U All are equipped with a write switch W kN and read / read switch R k Its basic principle is: each channel input is segmented and then processed by each C... U and W kNWhen the required delay time between channels is reached, the read switches for the corresponding segments (1...k) close simultaneously, and capacitor C... U The charges at both ends are averaged at the output node OUT.

[0032] Regarding the bandwidth limitations of analog beamformers, two main effects are involved: 1. the inherent sinc function filtering effect caused by sample-and-hold operation; 2. the infinite impulse response (IIR) filtering effect. The -3dB cutoff frequency of the sinc filter can be approximated as 0.44 × f S ,in f S = 1 / T S That is, the sampling frequency of the analog beamformer. T S The sampling period is [value]. The sinc filter cannot be optimized through design; it can only be compensated for using an equalizer (analog or digital), or by increasing [something]. f S This makes its impact negligible. The IIR filtering effect mainly stems from the characteristic that the previously sampled voltage is stored in the parasitic capacitance of the output node. Therefore, when multiple capacitors are read, their charges will simultaneously affect the current and previous sampled values. This memory effect is essentially equivalent to an IIR filter.

[0033] like Figure 4 As shown, in the simulated beamformer, all channels of the delay unit share the same output node OUT. Each channel delay line has its own parasitic capacitance C. PN , where N is the channel index. C PN Defined as the sum of the capacitances connected to the output terminals of each channel in the delay unit. Assume each read switch has a capacitance C. SWR Then, all channel output terminals in the delay unit are connected to C. SWR A capacitor of ×k.

[0034] Considering there are N channels, all connected to the same node, the total parasitic capacitance at the output is C. PT = N×C P = N×k×C SWR .

[0035] In capacitor C U When the read / write operation is completed, the voltage V at the output terminal... OUT [n] is represented as:

[0036] Therefore, its transfer function in the z-domain can be expressed as:

[0037] Where α is a coefficient, derived from C PT / (C PT + NC U ) is determined, and C PT =N×k×CSWR.

[0038] Where α < 0.18, that is, the total parasitic capacitance at the reading moment is less than the total C. U At 18%, the IIR filtering effect becomes negligible. At this point, the analog beamformer bandwidth is primarily limited by the sinc filter, with a 3dB cutoff frequency of approximately 0.44 × 10⁻⁶. f S This can be achieved by reducing C. PT Or increase C U To achieve this goal, however, considering the limited activity at the subarray level, increasing C... U This may not be feasible. Therefore, C should be minimized through design optimization and meticulous layout. PT .

[0039] from Figure 4 As can be seen, when reading a set of N capacitors (at times 1, 2, ..., k), a large number of additional capacitors are connected to the output node. These capacitors neither perform any function nor increase the total capacitance drop (C). PT For example, when all channel N's readout switch R1 is on, the remaining off switches (R2, R3, ..., R...) k This will generate (N-1)×(k-1)×C through the common output terminal. SWR Additional capacitors. The main purpose of using a common output terminal in this embodiment is to simplify the layout while ensuring that the output signal is always averaged at the same node.

[0040] An alternative to eliminating IIR filter effects is to periodically reset the output node before the start of each summation cycle. However, given C PT For large values, and to ensure the voltage stabilizes to the target value before the next summing cycle begins, the reset operation should be implemented through a node with sufficiently low impedance. Due to the low impedance requirement, the output node is typically reset to ground, which generates a zero-return waveform at the output of the analog beamformer. Therefore, additional resampling circuitry is required to control the zero-return signal.

[0041] The aforementioned alternatives not only require additional circuitry but may also increase power consumption and distortion because the signal source now needs to convert C... U Charge from 0V to V in Therefore, ideally, the reset operation should only be grounded for dual-power systems, and connected to VDD / 2 for single-power systems.

[0042] Simultaneously, analog beamforming rights are also used as analog multiplexers for test design (DfT) of single-component low-noise amplifiers (LNAs). In this case, with one write switch and one read switch closed, the total capacitance connected to the multiplexer input will be greater than C. PT + C U .

[0043] Figure 5 This is a second circuit diagram of an analog beamformer based on switched capacitors in an embodiment of the present invention, as shown below. Figure 5 As shown, the beamformer provided by the present invention includes: a plurality of delay units; each of the delay units includes a first readout switch R and a plurality of delay channels; Each of the aforementioned delay channels includes a sampling capacitor Cu, a write switch W, and a second read switch R; one end of the write switch W is connected to the input terminal of the delay channel, and the other end is connected to one end of the second read switch R; one end of the sampling capacitor Cu is connected between the other end of the write switch W and one end of the second read switch R, and the other end is grounded; The output terminals of multiple delay channels are connected to the common output terminal of the delay unit through the first readout switch R. The first readout switch R is used to isolate the parasitic capacitance of each delay unit, so that each delay unit only connects its own parasitic capacitance to the common output terminal when it is working.

[0044] In this embodiment of the invention, each delay channel in each delay unit is used to connect to a transducer array element to receive echo electrical signals.

[0045] Each of the delay channels writes the echo signal by closing the write switch W and reads the echo signal by closing the second read switch R.

[0046] The echo signal writing time of each delay channel in each delay unit is different, such as being set to write sequentially; the echo signal readout time of each delay channel in each delay unit is the same.

[0047] When the echo signal of one of the delay units is read out, the first readout switch R is closed. The readout time of the echo signal is different for different delay units; the first readout switch R corresponding to the delay unit is closed only when the echo signal of that delay unit is read out.

[0048] In this embodiment of the invention, a series switch is added between each readout switch group of the delay unit and the output terminal of the analog beamformer. The function of the series switch is to isolate the parasitic capacitance C of each readout switch group. P This reduces the total capacitance at the output.

[0049] Although this second circuit requires an additional k switches, it can significantly reduce the total parasitic capacitance C at each read group's read moment. PT .

[0050] As mentioned earlier, the total parasitic capacitance C of the first circuit PT,conv For: C PT,conv = N×k×C SWR And it is always connected to the output terminal.

[0051] However, for the second circuit, C P = (N+1)×C SWR The +1 originates from the additional switches at the read switch group. Furthermore, k additional switches are connected to the output, resulting in the total capacitance of the substitution mode: C. PT,alt = C P + k×C SWR = (N+1)×C SWR + k×C SWR = C SWR ×(N+k+1). This means that the total parasitic capacitance is reduced by C. PT,alt / C PT,conv C PT,alt / C PT,conv = (N+k+1) / (N×k).

[0052] Numerical examples clearly illustrate this reduction effect. Taking a subarray with N=16 and k=14 as an example, the total parasitic capacitance connected to the output can potentially be reduced by more than 7 times. Furthermore, when the analog beamformer is used as an analog multiplexer, the parasitic capacitance connected to the input is reduced by the same magnitude. Achieving such reductions would render the IIR effect negligible.

[0053] The second circuit also supports resetting a single read switch group, wherein the C of the read switch group P The capacitance value has now been significantly reduced. This relaxes the impedance requirements for reset operations and allows the node to be reset to VDD / 2 voltage.

[0054] Figure 7 This is a schematic diagram of the ultrasonic transceiver array element in an embodiment of the present invention, as shown below. Figure 7 As shown, the ultrasonic chip provided by the present invention includes the beamformer and further includes: An ultrasonic circuit array includes multiple ultrasonic circuit sub-arrays, each sub-array comprising a beamformer and multiple ultrasonic transceiver array elements. The ultrasonic transceiver array elements are used to connect to ultrasonic transducer array elements, which are used to convert received pulse electrical signals into ultrasonic waves and transmit them, or to convert received ultrasonic echoes into echo electrical signals. The beamformer is used to beamform the echo electrical signal received by the ultrasonic transceiver array element to enhance the echo electrical signal. In this embodiment of the invention, the ultrasonic transceiver array element includes: A pulse transmitting circuit is used to generate pulsed electrical signals to drive the ultrasonic transducer array elements to emit ultrasonic waves; An echo receiving circuit is used to receive the echo electrical signal generated by the ultrasonic transducer array element; A switching switch is used to switch the connection between the ultrasonic transducer array element and the pulse transmitting circuit or the echo receiving circuit.

[0055] Figure 8 This is a schematic diagram illustrating the control of the write switch and read switch in an embodiment of the present invention, as shown below. Figure 8 As shown, the ultrasonic chip provided by the present invention also includes a write pointer loopback shift register, a read pointer loopback shift register, and a read strobe logic unit; The write pointer loopback shift register is used to output a write strobe signal to control the on / off state of the corresponding write switch W; The read pointer loopback shift register is used to output the read strobe signal; The read gating logic unit is used to receive the read gating signal and convert it into a read gating target signal for controlling the on / off state of the first readout switch R and the second readout switch R.

[0056] Figure 9 This is a timing diagram of the simulated beamformer writing and reading electrical signals in an embodiment of the present invention, as shown below. Figure 9 As shown, a timing reference is provided by a base clock. On the write operation side, the write capacitor signals of different paths are triggered sequentially at adjacent intervals with the initial write offset as the initial delay, forming a stepped delay chain. On the read operation side, the signal is triggered after the initial read offset. By matching the delay of the read and write timing of each channel, the focusing and direction control of the ultrasonic beam are achieved.

[0057] Figure 10 This is a circuit diagram of beamforming resampling in an embodiment of the present invention, as shown below. Figure 10 As shown, the ultrasonic chip provided by the present invention also includes a resampling unit; The signal output terminal of the beamformer is connected to the input terminal of the resampling unit, and is used to transmit the zero-return waveform signal output by the resampling unit to the resampling unit; the resampling unit is used to accurately capture the effective ultrasonic signal in the zero-return waveform output by the beamformer, and restore the discontinuous zero-return waveform into a continuous analog ultrasonic echo signal that is uninterrupted and can be directly transmitted and imaged.

[0058] The resampling unit specifically includes a timing control module, a first sample-and-hold unit, and a second sample-and-hold unit.

[0059] The timing control module is used to generate a non-overlapping first sampling clock and a second sampling clock. The effective window of the first sampling clock is aligned with the effective pulse segment of the return-to-zero waveform, and the effective window of the second sampling clock is aligned with the forced zero-level gap segment of the return-to-zero waveform. At the same time, the timing control module sets a preset dead time between the effective windows of the two clocks to avoid sampling conflicts between the first sample-and-hold unit and the second sample-and-hold unit, thereby ensuring the stability of the circuit operation and the smoothness of the signal output.

[0060] The signal input terminal of the first sample-and-hold unit is electrically connected to the signal output terminal of the beamformer, and its control terminal is electrically connected to the first sampling clock output terminal of the timing control module. The first sample-and-hold unit completes the sampling of the effective ultrasonic echo signal in the effective pulse segment of the zero-return waveform, and continuously maintains and outputs the effective signal level obtained from the sampling in the forced zero-level gap segment.

[0061] The signal input terminal of the second sample-and-hold unit is electrically connected to the signal output terminal of the beamformer, and its control terminal is electrically connected to the second sampling clock output terminal of the timing control module. The second sample-and-hold unit completes the sampling of the effective ultrasonic echo signal in the next effective pulse segment of the zero-return waveform, and continuously maintains and outputs the effective signal level obtained from the sampling in the corresponding forced zero-level gap segment.

[0062] The timing control module uses two non-overlapping clocks to coordinate the alternating operation of the first sample-and-hold unit and the second sample-and-hold unit, enabling seamless splicing of the signals output by the two units, ultimately forming a continuous analog ultrasonic echo signal without forced zero-level gaps.

[0063] The first sample-and-hold unit and the second sample-and-hold unit adopt the same circuit structure, both including a sampling switch, a readout switch and a holding capacitor.

[0064] The control terminal of the sampling switch is connected to the corresponding sampling clock, the input terminal of the sampling switch is connected to the output terminal of the beamformer, and the output terminal of the sampling switch is connected to one end of the holding capacitor and the input terminal of the readout switch respectively. The other end of the holding capacitor is grounded, and the output terminal of the readout switch serves as the signal output terminal of the corresponding sample-and-hold unit. The electrical isolation between the holding capacitor and the output terminal is achieved by switching the readout switch on and off, which effectively prevents the sampling charge in the holding capacitor from being discharged and greatly improves the signal holding accuracy.

[0065] In this embodiment of the invention, by adding a first readout switch R at the output of each delay unit, the parasitic capacitance of each delay unit and delay channel is effectively isolated, significantly reducing the total parasitic capacitance at the common output. Compared to the traditional architecture, the total parasitic capacitance can be reduced by several times (e.g., more than 7 times in the subarray scenario with N=16 and k=14), significantly weakening the IIR filtering effect, so that the beamformer bandwidth is mainly limited by the controllable sinc filter, meeting the core requirements of high bandwidth and low distortion of the ICE system, while avoiding the signal accuracy degradation problem caused by excessive parasitic capacitance; In this embodiment of the invention, the improved architecture can suppress signal interference caused by parasitic capacitance without relying on an additional reset and resampling circuit, solving the problems of complex traditional reset designs, increased power consumption, and signal distortion. Meanwhile, the design of synchronized readout times for each channel within a single delay unit and time-division control of readout times for different delay units ensures phase alignment in beamforming and reduces circuit redundancy through precise timing control of switches. This optimizes chip area utilization while reducing noise interference during signal transmission, achieving a balance between low power consumption and high reliability.

[0066] In this embodiment of the invention, the ultrasound chip integrates an optimized beamformer, an ultrasound transducer array, and control circuitry (write / read pointer loopback shift register, read gating logic unit, etc.). Subarray-level beamforming significantly reduces the total number of channels, improving signal processing efficiency. This design is suitable for miniaturized, high-frame-rate scenarios such as intracardiac ultrasound (e.g., 4D imaging rate of 50 volumes / s). It can be integrated into interventional catheter probes with a diameter of only 1-3.3 mm, enabling real-time, high-precision imaging in cardiac interventional surgery. This effectively guides surgical procedures, monitors surgical outcomes, and reduces surgical risks, while simultaneously meeting the requirements of miniaturization and high performance of the ultrasound chip.

[0067] The various embodiments described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0068] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention.

Claims

1. A beamformer, characterized by, include: Multiple delay units; Each of the aforementioned delay units includes a first readout switch R and multiple delay channels; Each of the aforementioned delay channels includes a sampling capacitor C. u A write switch W and a second read switch R; one end of the write switch W is connected to the input terminal of the delay channel, and the other end is connected to one end of the second read switch R; the sampling capacitor C u One end is connected between the other end of the write switch W and one end of the second read switch R, and the other end is grounded; The output terminals of multiple delay channels are connected to the common output terminal of the delay unit through the first readout switch R. The first readout switch R is used to isolate the parasitic capacitance of each delay unit, so that each delay unit only connects its own parasitic capacitance to the common output terminal when it is working.

2. The beamformer of claim 1, wherein, Each of the delay channels in each of the delay units is used to connect to a transducer array element to receive the echo electrical signal.

3. The beamformer of claim 1, wherein, Each of the aforementioned delay channels has a parasitic capacitance C p .

4. The beamformer of claim 2, wherein, Each of the delay channels writes the echo signal by closing the write switch W and reads the echo signal by closing the second read switch R.

5. The beamformer of claim 4, wherein, The echo electrical signal writing time of each delay channel in each delay unit is different; The echo signal readout time of each delay channel in each delay unit is the same.

6. The beamformer of claim 4, wherein, When the echo signal of one of the delay units is read out, the first readout switch R is closed.

7. The beamformer according to claim 1, characterized in that, The readout time of the echo signal is different for different delay units; The first readout switch R corresponding to the delay unit is closed only when the echo signal of the delay unit is read out.

8. An ultrasonic chip, characterized by The beamformer, comprising any one of claims 1 to 7, further comprises: An ultrasonic circuit array includes multiple ultrasonic circuit sub-arrays, each sub-array comprising a beamformer and multiple ultrasonic transceiver array elements. The ultrasonic transceiver array elements are used to connect to ultrasonic transducer array elements, which are used to convert received pulse electrical signals into ultrasonic waves and transmit them, or to convert received ultrasonic echoes into echo electrical signals. The beamformer is used to beamform the echo electrical signal received by the ultrasonic transceiver array element to enhance the echo electrical signal.

9. The ultrasound chip of claim 8, wherein, The ultrasonic transceiver array element includes: A pulse transmitting circuit is used to generate pulsed electrical signals to drive the ultrasonic transducer array elements to emit ultrasonic waves; An echo receiving circuit is used to receive the echo electrical signal generated by the ultrasonic transducer array element; A switching switch is used to switch the connection between the ultrasonic transducer array element and the pulse transmitting circuit or the echo receiving circuit.

10. The ultrasound chip of claim 8, wherein, It also includes a write pointer loopback shift register, a read pointer loopback shift register, and a read strobe logic unit; The write pointer loopback shift register is used to output a write strobe signal to control the on / off state of the corresponding write switch W; The read pointer loopback shift register is used to output the read strobe signal; The read gating logic unit is used to receive the read gating signal and convert it into a read gating target signal for controlling the on / off state of the first readout switch R and the second readout switch R.

11. The ultrasonic chip according to claim 8, characterized in that, It also includes a resampling unit; The signal output terminal of the beamformer is connected to the input terminal of the resampling unit; the resampling unit is used to capture the effective ultrasonic signal in the zero-return waveform output by the beamformer and restore the discontinuous zero-return waveform to an uninterrupted continuous analog ultrasonic echo signal.

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